1 // SPDX-License-Identifier: GPL-2.0 2 // SPI to CAN driver for the Texas Instruments TCAN4x5x 3 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include "tcan4x5x.h" 6 7 #define TCAN4X5X_EXT_CLK_DEF 40000000 8 9 #define TCAN4X5X_DEV_ID1 0x00 10 #define TCAN4X5X_DEV_ID1_TCAN 0x4e414354 /* ASCII TCAN */ 11 #define TCAN4X5X_DEV_ID2 0x04 12 #define TCAN4X5X_REV 0x08 13 #define TCAN4X5X_STATUS 0x0C 14 #define TCAN4X5X_ERROR_STATUS_MASK 0x10 15 #define TCAN4X5X_CONTROL 0x14 16 17 #define TCAN4X5X_CONFIG 0x800 18 #define TCAN4X5X_TS_PRESCALE 0x804 19 #define TCAN4X5X_TEST_REG 0x808 20 #define TCAN4X5X_INT_FLAGS 0x820 21 #define TCAN4X5X_MCAN_INT_REG 0x824 22 #define TCAN4X5X_INT_EN 0x830 23 24 /* Interrupt bits */ 25 #define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30) 26 #define TCAN4X5X_CANHCANL_INT_EN BIT(29) 27 #define TCAN4X5X_CANHBAT_INT_EN BIT(28) 28 #define TCAN4X5X_CANLGND_INT_EN BIT(27) 29 #define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26) 30 #define TCAN4X5X_CANBUSGND_INT_EN BIT(25) 31 #define TCAN4X5X_CANBUSBAT_INT_EN BIT(24) 32 #define TCAN4X5X_UVSUP_INT_EN BIT(22) 33 #define TCAN4X5X_UVIO_INT_EN BIT(21) 34 #define TCAN4X5X_TSD_INT_EN BIT(19) 35 #define TCAN4X5X_ECCERR_INT_EN BIT(16) 36 #define TCAN4X5X_CANINT_INT_EN BIT(15) 37 #define TCAN4X5X_LWU_INT_EN BIT(14) 38 #define TCAN4X5X_CANSLNT_INT_EN BIT(10) 39 #define TCAN4X5X_CANDOM_INT_EN BIT(8) 40 #define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5) 41 #define TCAN4X5X_BUS_FAULT BIT(4) 42 #define TCAN4X5X_MCAN_INT BIT(1) 43 #define TCAN4X5X_ENABLE_TCAN_INT \ 44 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \ 45 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN) 46 47 /* MCAN Interrupt bits */ 48 #define TCAN4X5X_MCAN_IR_ARA BIT(29) 49 #define TCAN4X5X_MCAN_IR_PED BIT(28) 50 #define TCAN4X5X_MCAN_IR_PEA BIT(27) 51 #define TCAN4X5X_MCAN_IR_WD BIT(26) 52 #define TCAN4X5X_MCAN_IR_BO BIT(25) 53 #define TCAN4X5X_MCAN_IR_EW BIT(24) 54 #define TCAN4X5X_MCAN_IR_EP BIT(23) 55 #define TCAN4X5X_MCAN_IR_ELO BIT(22) 56 #define TCAN4X5X_MCAN_IR_BEU BIT(21) 57 #define TCAN4X5X_MCAN_IR_BEC BIT(20) 58 #define TCAN4X5X_MCAN_IR_DRX BIT(19) 59 #define TCAN4X5X_MCAN_IR_TOO BIT(18) 60 #define TCAN4X5X_MCAN_IR_MRAF BIT(17) 61 #define TCAN4X5X_MCAN_IR_TSW BIT(16) 62 #define TCAN4X5X_MCAN_IR_TEFL BIT(15) 63 #define TCAN4X5X_MCAN_IR_TEFF BIT(14) 64 #define TCAN4X5X_MCAN_IR_TEFW BIT(13) 65 #define TCAN4X5X_MCAN_IR_TEFN BIT(12) 66 #define TCAN4X5X_MCAN_IR_TFE BIT(11) 67 #define TCAN4X5X_MCAN_IR_TCF BIT(10) 68 #define TCAN4X5X_MCAN_IR_TC BIT(9) 69 #define TCAN4X5X_MCAN_IR_HPM BIT(8) 70 #define TCAN4X5X_MCAN_IR_RF1L BIT(7) 71 #define TCAN4X5X_MCAN_IR_RF1F BIT(6) 72 #define TCAN4X5X_MCAN_IR_RF1W BIT(5) 73 #define TCAN4X5X_MCAN_IR_RF1N BIT(4) 74 #define TCAN4X5X_MCAN_IR_RF0L BIT(3) 75 #define TCAN4X5X_MCAN_IR_RF0F BIT(2) 76 #define TCAN4X5X_MCAN_IR_RF0W BIT(1) 77 #define TCAN4X5X_MCAN_IR_RF0N BIT(0) 78 #define TCAN4X5X_ENABLE_MCAN_INT \ 79 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \ 80 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \ 81 TCAN4X5X_MCAN_IR_RF1F) 82 83 #define TCAN4X5X_MRAM_START 0x8000 84 #define TCAN4X5X_MRAM_SIZE 0x800 85 #define TCAN4X5X_MCAN_OFFSET 0x1000 86 87 #define TCAN4X5X_CLEAR_ALL_INT 0xffffffff 88 #define TCAN4X5X_SET_ALL_INT 0xffffffff 89 90 #define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6)) 91 #define TCAN4X5X_MODE_SLEEP 0x00 92 #define TCAN4X5X_MODE_STANDBY BIT(6) 93 #define TCAN4X5X_MODE_NORMAL BIT(7) 94 95 #define TCAN4X5X_NWKRQ_VOLTAGE_VIO BIT(19) 96 97 #define TCAN4X5X_DISABLE_WAKE_MSK (BIT(31) | BIT(30)) 98 #define TCAN4X5X_DISABLE_INH_MSK BIT(9) 99 100 #define TCAN4X5X_SW_RESET BIT(2) 101 102 #define TCAN4X5X_MCAN_CONFIGURED BIT(5) 103 #define TCAN4X5X_WATCHDOG_EN BIT(3) 104 #define TCAN4X5X_WD_60_MS_TIMER 0 105 #define TCAN4X5X_WD_600_MS_TIMER BIT(28) 106 #define TCAN4X5X_WD_3_S_TIMER BIT(29) 107 #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29)) 108 109 struct tcan4x5x_version_info { 110 const char *name; 111 u32 id2_register; 112 113 bool has_wake_pin; 114 bool has_state_pin; 115 }; 116 117 enum { 118 TCAN4552 = 0, 119 TCAN4553, 120 TCAN4X5X, 121 }; 122 123 static const struct tcan4x5x_version_info tcan4x5x_versions[] = { 124 [TCAN4552] = { 125 .name = "4552", 126 .id2_register = 0x32353534, 127 }, 128 [TCAN4553] = { 129 .name = "4553", 130 .id2_register = 0x33353534, 131 }, 132 /* generic version with no id2_register at the end */ 133 [TCAN4X5X] = { 134 .name = "generic", 135 .has_wake_pin = true, 136 .has_state_pin = true, 137 }, 138 }; 139 140 static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev) 141 { 142 return container_of(cdev, struct tcan4x5x_priv, cdev); 143 } 144 145 static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv) 146 { 147 int wake_state = 0; 148 149 if (priv->device_state_gpio) 150 wake_state = gpiod_get_value(priv->device_state_gpio); 151 152 if (priv->device_wake_gpio && wake_state) { 153 gpiod_set_value(priv->device_wake_gpio, 0); 154 usleep_range(5, 50); 155 gpiod_set_value(priv->device_wake_gpio, 1); 156 } 157 } 158 159 static int tcan4x5x_reset(struct tcan4x5x_priv *priv) 160 { 161 int ret = 0; 162 163 if (priv->reset_gpio) { 164 gpiod_set_value(priv->reset_gpio, 1); 165 166 /* tpulse_width minimum 30us */ 167 usleep_range(30, 100); 168 gpiod_set_value(priv->reset_gpio, 0); 169 } else { 170 ret = regmap_write(priv->regmap, TCAN4X5X_CONFIG, 171 TCAN4X5X_SW_RESET); 172 if (ret) 173 return ret; 174 } 175 176 usleep_range(700, 1000); 177 178 return ret; 179 } 180 181 static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) 182 { 183 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 184 u32 val; 185 186 regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val); 187 188 return val; 189 } 190 191 static int tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset, 192 void *val, size_t val_count) 193 { 194 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 195 196 return regmap_bulk_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); 197 } 198 199 static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) 200 { 201 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 202 203 return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val); 204 } 205 206 static int tcan4x5x_write_fifo(struct m_can_classdev *cdev, 207 int addr_offset, const void *val, size_t val_count) 208 { 209 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 210 211 return regmap_bulk_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val, val_count); 212 } 213 214 static int tcan4x5x_power_enable(struct regulator *reg, int enable) 215 { 216 if (IS_ERR_OR_NULL(reg)) 217 return 0; 218 219 if (enable) 220 return regulator_enable(reg); 221 else 222 return regulator_disable(reg); 223 } 224 225 static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev, 226 int reg, int val) 227 { 228 struct tcan4x5x_priv *priv = cdev_to_priv(cdev); 229 230 return regmap_write(priv->regmap, reg, val); 231 } 232 233 static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev) 234 { 235 int ret; 236 237 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS, 238 TCAN4X5X_CLEAR_ALL_INT); 239 if (ret) 240 return ret; 241 242 return tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS, 243 TCAN4X5X_CLEAR_ALL_INT); 244 } 245 246 static int tcan4x5x_init(struct m_can_classdev *cdev) 247 { 248 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 249 int ret; 250 251 tcan4x5x_check_wake(tcan4x5x); 252 253 ret = tcan4x5x_clear_interrupts(cdev); 254 if (ret) 255 return ret; 256 257 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN, 258 TCAN4X5X_ENABLE_TCAN_INT); 259 if (ret) 260 return ret; 261 262 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS_MASK, 263 TCAN4X5X_CLEAR_ALL_INT); 264 if (ret) 265 return ret; 266 267 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 268 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL); 269 if (ret) 270 return ret; 271 272 if (tcan4x5x->nwkrq_voltage_vio) { 273 ret = regmap_set_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 274 TCAN4X5X_NWKRQ_VOLTAGE_VIO); 275 if (ret) 276 return ret; 277 } 278 279 return ret; 280 } 281 282 static int tcan4x5x_deinit(struct m_can_classdev *cdev) 283 { 284 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 285 286 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 287 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_STANDBY); 288 }; 289 290 static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) 291 { 292 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 293 294 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 295 TCAN4X5X_DISABLE_WAKE_MSK, 0x00); 296 } 297 298 static int tcan4x5x_disable_state(struct m_can_classdev *cdev) 299 { 300 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 301 302 return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, 303 TCAN4X5X_DISABLE_INH_MSK, 0x01); 304 } 305 306 static const struct tcan4x5x_version_info 307 *tcan4x5x_find_version(struct tcan4x5x_priv *priv) 308 { 309 u32 val; 310 int ret; 311 312 ret = regmap_read(priv->regmap, TCAN4X5X_DEV_ID1, &val); 313 if (ret) 314 return ERR_PTR(ret); 315 316 if (val != TCAN4X5X_DEV_ID1_TCAN) { 317 dev_err(&priv->spi->dev, "Not a tcan device %x\n", val); 318 return ERR_PTR(-ENODEV); 319 } 320 321 ret = regmap_read(priv->regmap, TCAN4X5X_DEV_ID2, &val); 322 if (ret) 323 return ERR_PTR(ret); 324 325 for (int i = 0; i != ARRAY_SIZE(tcan4x5x_versions); ++i) { 326 const struct tcan4x5x_version_info *vinfo = &tcan4x5x_versions[i]; 327 328 if (!vinfo->id2_register || val == vinfo->id2_register) { 329 dev_info(&priv->spi->dev, "Detected TCAN device version %s\n", 330 vinfo->name); 331 return vinfo; 332 } 333 } 334 335 return &tcan4x5x_versions[TCAN4X5X]; 336 } 337 338 static void tcan4x5x_get_dt_data(struct m_can_classdev *cdev) 339 { 340 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 341 342 tcan4x5x->nwkrq_voltage_vio = 343 of_property_read_bool(cdev->dev->of_node, "ti,nwkrq-voltage-vio"); 344 } 345 346 static int tcan4x5x_get_gpios(struct m_can_classdev *cdev, 347 const struct tcan4x5x_version_info *version_info) 348 { 349 struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); 350 int ret; 351 352 if (version_info->has_wake_pin) { 353 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake", 354 GPIOD_OUT_HIGH); 355 if (IS_ERR(tcan4x5x->device_wake_gpio)) { 356 if (PTR_ERR(tcan4x5x->device_wake_gpio) == -EPROBE_DEFER) 357 return -EPROBE_DEFER; 358 359 tcan4x5x_disable_wake(cdev); 360 } 361 } 362 363 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset", 364 GPIOD_OUT_LOW); 365 if (IS_ERR(tcan4x5x->reset_gpio)) 366 tcan4x5x->reset_gpio = NULL; 367 368 ret = tcan4x5x_reset(tcan4x5x); 369 if (ret) 370 return ret; 371 372 if (version_info->has_state_pin) { 373 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev, 374 "device-state", 375 GPIOD_IN); 376 if (IS_ERR(tcan4x5x->device_state_gpio)) { 377 tcan4x5x->device_state_gpio = NULL; 378 tcan4x5x_disable_state(cdev); 379 } 380 } 381 382 return 0; 383 } 384 385 static const struct m_can_ops tcan4x5x_ops = { 386 .init = tcan4x5x_init, 387 .deinit = tcan4x5x_deinit, 388 .read_reg = tcan4x5x_read_reg, 389 .write_reg = tcan4x5x_write_reg, 390 .write_fifo = tcan4x5x_write_fifo, 391 .read_fifo = tcan4x5x_read_fifo, 392 .clear_interrupts = tcan4x5x_clear_interrupts, 393 }; 394 395 static int tcan4x5x_can_probe(struct spi_device *spi) 396 { 397 const struct tcan4x5x_version_info *version_info; 398 struct tcan4x5x_priv *priv; 399 struct m_can_classdev *mcan_class; 400 int freq, ret; 401 402 mcan_class = m_can_class_allocate_dev(&spi->dev, 403 sizeof(struct tcan4x5x_priv)); 404 if (!mcan_class) 405 return -ENOMEM; 406 407 ret = m_can_check_mram_cfg(mcan_class, TCAN4X5X_MRAM_SIZE); 408 if (ret) 409 goto out_m_can_class_free_dev; 410 411 priv = cdev_to_priv(mcan_class); 412 413 priv->power = devm_regulator_get_optional(&spi->dev, "vsup"); 414 if (PTR_ERR(priv->power) == -EPROBE_DEFER) { 415 ret = -EPROBE_DEFER; 416 goto out_m_can_class_free_dev; 417 } else { 418 priv->power = NULL; 419 } 420 421 mcan_class->cclk = devm_clk_get(mcan_class->dev, "cclk"); 422 if (IS_ERR(mcan_class->cclk)) { 423 dev_err(&spi->dev, "no CAN clock source defined\n"); 424 freq = TCAN4X5X_EXT_CLK_DEF; 425 } else { 426 freq = clk_get_rate(mcan_class->cclk); 427 } 428 429 /* Sanity check */ 430 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF) { 431 dev_err(&spi->dev, "Clock frequency is out of supported range %d\n", 432 freq); 433 ret = -ERANGE; 434 goto out_m_can_class_free_dev; 435 } 436 437 priv->spi = spi; 438 439 mcan_class->pm_clock_support = 0; 440 mcan_class->pm_wake_source = device_property_read_bool(&spi->dev, "wakeup-source"); 441 mcan_class->can.clock.freq = freq; 442 mcan_class->dev = &spi->dev; 443 mcan_class->ops = &tcan4x5x_ops; 444 mcan_class->is_peripheral = true; 445 mcan_class->net->irq = spi->irq; 446 447 spi_set_drvdata(spi, priv); 448 449 /* Configure the SPI bus */ 450 spi->bits_per_word = 8; 451 ret = spi_setup(spi); 452 if (ret) { 453 dev_err(&spi->dev, "SPI setup failed %pe\n", ERR_PTR(ret)); 454 goto out_m_can_class_free_dev; 455 } 456 457 ret = tcan4x5x_regmap_init(priv); 458 if (ret) { 459 dev_err(&spi->dev, "regmap init failed %pe\n", ERR_PTR(ret)); 460 goto out_m_can_class_free_dev; 461 } 462 463 ret = tcan4x5x_power_enable(priv->power, 1); 464 if (ret) { 465 dev_err(&spi->dev, "Enabling regulator failed %pe\n", 466 ERR_PTR(ret)); 467 goto out_m_can_class_free_dev; 468 } 469 470 version_info = tcan4x5x_find_version(priv); 471 if (IS_ERR(version_info)) { 472 ret = PTR_ERR(version_info); 473 goto out_power; 474 } 475 476 ret = tcan4x5x_get_gpios(mcan_class, version_info); 477 if (ret) { 478 dev_err(&spi->dev, "Getting gpios failed %pe\n", ERR_PTR(ret)); 479 goto out_power; 480 } 481 482 tcan4x5x_get_dt_data(mcan_class); 483 484 tcan4x5x_check_wake(priv); 485 486 ret = tcan4x5x_write_tcan_reg(mcan_class, TCAN4X5X_INT_EN, 0); 487 if (ret) { 488 dev_err(&spi->dev, "Disabling interrupts failed %pe\n", ERR_PTR(ret)); 489 goto out_power; 490 } 491 492 ret = tcan4x5x_clear_interrupts(mcan_class); 493 if (ret) { 494 dev_err(&spi->dev, "Clearing interrupts failed %pe\n", ERR_PTR(ret)); 495 goto out_power; 496 } 497 498 if (mcan_class->pm_wake_source) 499 device_init_wakeup(&spi->dev, true); 500 501 ret = m_can_class_register(mcan_class); 502 if (ret) { 503 dev_err(&spi->dev, "Failed registering m_can device %pe\n", 504 ERR_PTR(ret)); 505 goto out_power; 506 } 507 508 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n"); 509 return 0; 510 511 out_power: 512 tcan4x5x_power_enable(priv->power, 0); 513 out_m_can_class_free_dev: 514 m_can_class_free_dev(mcan_class->net); 515 return ret; 516 } 517 518 static void tcan4x5x_can_remove(struct spi_device *spi) 519 { 520 struct tcan4x5x_priv *priv = spi_get_drvdata(spi); 521 522 m_can_class_unregister(&priv->cdev); 523 524 tcan4x5x_power_enable(priv->power, 0); 525 526 m_can_class_free_dev(priv->cdev.net); 527 } 528 529 static int __maybe_unused tcan4x5x_suspend(struct device *dev) 530 { 531 struct m_can_classdev *cdev = dev_get_drvdata(dev); 532 struct spi_device *spi = to_spi_device(dev); 533 534 if (cdev->pm_wake_source) 535 enable_irq_wake(spi->irq); 536 537 return m_can_class_suspend(dev); 538 } 539 540 static int __maybe_unused tcan4x5x_resume(struct device *dev) 541 { 542 struct m_can_classdev *cdev = dev_get_drvdata(dev); 543 struct spi_device *spi = to_spi_device(dev); 544 int ret = m_can_class_resume(dev); 545 546 if (cdev->pm_wake_source) 547 disable_irq_wake(spi->irq); 548 549 return ret; 550 } 551 552 static const struct of_device_id tcan4x5x_of_match[] = { 553 { 554 .compatible = "ti,tcan4x5x", 555 }, { 556 /* sentinel */ 557 }, 558 }; 559 MODULE_DEVICE_TABLE(of, tcan4x5x_of_match); 560 561 static const struct spi_device_id tcan4x5x_id_table[] = { 562 { 563 .name = "tcan4x5x", 564 }, { 565 /* sentinel */ 566 }, 567 }; 568 MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table); 569 570 static const struct dev_pm_ops tcan4x5x_pm_ops = { 571 SET_SYSTEM_SLEEP_PM_OPS(tcan4x5x_suspend, tcan4x5x_resume) 572 }; 573 574 static struct spi_driver tcan4x5x_can_driver = { 575 .driver = { 576 .name = KBUILD_MODNAME, 577 .of_match_table = tcan4x5x_of_match, 578 .pm = &tcan4x5x_pm_ops, 579 }, 580 .id_table = tcan4x5x_id_table, 581 .probe = tcan4x5x_can_probe, 582 .remove = tcan4x5x_can_remove, 583 }; 584 module_spi_driver(tcan4x5x_can_driver); 585 586 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 587 MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver"); 588 MODULE_LICENSE("GPL v2"); 589