1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/can/dev.h> 13 #include <linux/ethtool.h> 14 #include <linux/hrtimer.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/phy/phy.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 27 #include "m_can.h" 28 29 /* registers definition */ 30 enum m_can_reg { 31 M_CAN_CREL = 0x0, 32 M_CAN_ENDN = 0x4, 33 M_CAN_CUST = 0x8, 34 M_CAN_DBTP = 0xc, 35 M_CAN_TEST = 0x10, 36 M_CAN_RWD = 0x14, 37 M_CAN_CCCR = 0x18, 38 M_CAN_NBTP = 0x1c, 39 M_CAN_TSCC = 0x20, 40 M_CAN_TSCV = 0x24, 41 M_CAN_TOCC = 0x28, 42 M_CAN_TOCV = 0x2c, 43 M_CAN_ECR = 0x40, 44 M_CAN_PSR = 0x44, 45 /* TDCR Register only available for version >=3.1.x */ 46 M_CAN_TDCR = 0x48, 47 M_CAN_IR = 0x50, 48 M_CAN_IE = 0x54, 49 M_CAN_ILS = 0x58, 50 M_CAN_ILE = 0x5c, 51 M_CAN_GFC = 0x80, 52 M_CAN_SIDFC = 0x84, 53 M_CAN_XIDFC = 0x88, 54 M_CAN_XIDAM = 0x90, 55 M_CAN_HPMS = 0x94, 56 M_CAN_NDAT1 = 0x98, 57 M_CAN_NDAT2 = 0x9c, 58 M_CAN_RXF0C = 0xa0, 59 M_CAN_RXF0S = 0xa4, 60 M_CAN_RXF0A = 0xa8, 61 M_CAN_RXBC = 0xac, 62 M_CAN_RXF1C = 0xb0, 63 M_CAN_RXF1S = 0xb4, 64 M_CAN_RXF1A = 0xb8, 65 M_CAN_RXESC = 0xbc, 66 M_CAN_TXBC = 0xc0, 67 M_CAN_TXFQS = 0xc4, 68 M_CAN_TXESC = 0xc8, 69 M_CAN_TXBRP = 0xcc, 70 M_CAN_TXBAR = 0xd0, 71 M_CAN_TXBCR = 0xd4, 72 M_CAN_TXBTO = 0xd8, 73 M_CAN_TXBCF = 0xdc, 74 M_CAN_TXBTIE = 0xe0, 75 M_CAN_TXBCIE = 0xe4, 76 M_CAN_TXEFC = 0xf0, 77 M_CAN_TXEFS = 0xf4, 78 M_CAN_TXEFA = 0xf8, 79 }; 80 81 /* message ram configuration data length */ 82 #define MRAM_CFG_LEN 8 83 84 /* Core Release Register (CREL) */ 85 #define CREL_REL_MASK GENMASK(31, 28) 86 #define CREL_STEP_MASK GENMASK(27, 24) 87 #define CREL_SUBSTEP_MASK GENMASK(23, 20) 88 89 /* Data Bit Timing & Prescaler Register (DBTP) */ 90 #define DBTP_TDC BIT(23) 91 #define DBTP_DBRP_MASK GENMASK(20, 16) 92 #define DBTP_DTSEG1_MASK GENMASK(12, 8) 93 #define DBTP_DTSEG2_MASK GENMASK(7, 4) 94 #define DBTP_DSJW_MASK GENMASK(3, 0) 95 96 /* Transmitter Delay Compensation Register (TDCR) */ 97 #define TDCR_TDCO_MASK GENMASK(14, 8) 98 #define TDCR_TDCF_MASK GENMASK(6, 0) 99 100 /* Test Register (TEST) */ 101 #define TEST_LBCK BIT(4) 102 103 /* CC Control Register (CCCR) */ 104 #define CCCR_TXP BIT(14) 105 #define CCCR_TEST BIT(7) 106 #define CCCR_DAR BIT(6) 107 #define CCCR_MON BIT(5) 108 #define CCCR_CSR BIT(4) 109 #define CCCR_CSA BIT(3) 110 #define CCCR_ASM BIT(2) 111 #define CCCR_CCE BIT(1) 112 #define CCCR_INIT BIT(0) 113 /* for version 3.0.x */ 114 #define CCCR_CMR_MASK GENMASK(11, 10) 115 #define CCCR_CMR_CANFD 0x1 116 #define CCCR_CMR_CANFD_BRS 0x2 117 #define CCCR_CMR_CAN 0x3 118 #define CCCR_CME_MASK GENMASK(9, 8) 119 #define CCCR_CME_CAN 0 120 #define CCCR_CME_CANFD 0x1 121 #define CCCR_CME_CANFD_BRS 0x2 122 /* for version >=3.1.x */ 123 #define CCCR_EFBI BIT(13) 124 #define CCCR_PXHD BIT(12) 125 #define CCCR_BRSE BIT(9) 126 #define CCCR_FDOE BIT(8) 127 /* for version >=3.2.x */ 128 #define CCCR_NISO BIT(15) 129 /* for version >=3.3.x */ 130 #define CCCR_WMM BIT(11) 131 #define CCCR_UTSU BIT(10) 132 133 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 134 #define NBTP_NSJW_MASK GENMASK(31, 25) 135 #define NBTP_NBRP_MASK GENMASK(24, 16) 136 #define NBTP_NTSEG1_MASK GENMASK(15, 8) 137 #define NBTP_NTSEG2_MASK GENMASK(6, 0) 138 139 /* Timestamp Counter Configuration Register (TSCC) */ 140 #define TSCC_TCP_MASK GENMASK(19, 16) 141 #define TSCC_TSS_MASK GENMASK(1, 0) 142 #define TSCC_TSS_DISABLE 0x0 143 #define TSCC_TSS_INTERNAL 0x1 144 #define TSCC_TSS_EXTERNAL 0x2 145 146 /* Timestamp Counter Value Register (TSCV) */ 147 #define TSCV_TSC_MASK GENMASK(15, 0) 148 149 /* Error Counter Register (ECR) */ 150 #define ECR_RP BIT(15) 151 #define ECR_REC_MASK GENMASK(14, 8) 152 #define ECR_TEC_MASK GENMASK(7, 0) 153 154 /* Protocol Status Register (PSR) */ 155 #define PSR_BO BIT(7) 156 #define PSR_EW BIT(6) 157 #define PSR_EP BIT(5) 158 #define PSR_LEC_MASK GENMASK(2, 0) 159 #define PSR_DLEC_MASK GENMASK(10, 8) 160 161 /* Interrupt Register (IR) */ 162 #define IR_ALL_INT 0xffffffff 163 164 /* Renamed bits for versions > 3.1.x */ 165 #define IR_ARA BIT(29) 166 #define IR_PED BIT(28) 167 #define IR_PEA BIT(27) 168 169 /* Bits for version 3.0.x */ 170 #define IR_STE BIT(31) 171 #define IR_FOE BIT(30) 172 #define IR_ACKE BIT(29) 173 #define IR_BE BIT(28) 174 #define IR_CRCE BIT(27) 175 #define IR_WDI BIT(26) 176 #define IR_BO BIT(25) 177 #define IR_EW BIT(24) 178 #define IR_EP BIT(23) 179 #define IR_ELO BIT(22) 180 #define IR_BEU BIT(21) 181 #define IR_BEC BIT(20) 182 #define IR_DRX BIT(19) 183 #define IR_TOO BIT(18) 184 #define IR_MRAF BIT(17) 185 #define IR_TSW BIT(16) 186 #define IR_TEFL BIT(15) 187 #define IR_TEFF BIT(14) 188 #define IR_TEFW BIT(13) 189 #define IR_TEFN BIT(12) 190 #define IR_TFE BIT(11) 191 #define IR_TCF BIT(10) 192 #define IR_TC BIT(9) 193 #define IR_HPM BIT(8) 194 #define IR_RF1L BIT(7) 195 #define IR_RF1F BIT(6) 196 #define IR_RF1W BIT(5) 197 #define IR_RF1N BIT(4) 198 #define IR_RF0L BIT(3) 199 #define IR_RF0F BIT(2) 200 #define IR_RF0W BIT(1) 201 #define IR_RF0N BIT(0) 202 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 203 204 /* Interrupts for version 3.0.x */ 205 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 206 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \ 207 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 208 IR_RF0L) 209 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 210 211 /* Interrupts for version >= 3.1.x */ 212 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 213 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \ 214 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 215 IR_RF0L) 216 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 217 218 /* Interrupt Line Select (ILS) */ 219 #define ILS_ALL_INT0 0x0 220 #define ILS_ALL_INT1 0xFFFFFFFF 221 222 /* Interrupt Line Enable (ILE) */ 223 #define ILE_EINT1 BIT(1) 224 #define ILE_EINT0 BIT(0) 225 226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 227 #define RXFC_FWM_MASK GENMASK(30, 24) 228 #define RXFC_FS_MASK GENMASK(22, 16) 229 230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 231 #define RXFS_RFL BIT(25) 232 #define RXFS_FF BIT(24) 233 #define RXFS_FPI_MASK GENMASK(21, 16) 234 #define RXFS_FGI_MASK GENMASK(13, 8) 235 #define RXFS_FFL_MASK GENMASK(6, 0) 236 237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 238 #define RXESC_RBDS_MASK GENMASK(10, 8) 239 #define RXESC_F1DS_MASK GENMASK(6, 4) 240 #define RXESC_F0DS_MASK GENMASK(2, 0) 241 #define RXESC_64B 0x7 242 243 /* Tx Buffer Configuration (TXBC) */ 244 #define TXBC_TFQS_MASK GENMASK(29, 24) 245 #define TXBC_NDTB_MASK GENMASK(21, 16) 246 247 /* Tx FIFO/Queue Status (TXFQS) */ 248 #define TXFQS_TFQF BIT(21) 249 #define TXFQS_TFQPI_MASK GENMASK(20, 16) 250 #define TXFQS_TFGI_MASK GENMASK(12, 8) 251 #define TXFQS_TFFL_MASK GENMASK(5, 0) 252 253 /* Tx Buffer Element Size Configuration (TXESC) */ 254 #define TXESC_TBDS_MASK GENMASK(2, 0) 255 #define TXESC_TBDS_64B 0x7 256 257 /* Tx Event FIFO Configuration (TXEFC) */ 258 #define TXEFC_EFS_MASK GENMASK(21, 16) 259 260 /* Tx Event FIFO Status (TXEFS) */ 261 #define TXEFS_TEFL BIT(25) 262 #define TXEFS_EFF BIT(24) 263 #define TXEFS_EFGI_MASK GENMASK(12, 8) 264 #define TXEFS_EFFL_MASK GENMASK(5, 0) 265 266 /* Tx Event FIFO Acknowledge (TXEFA) */ 267 #define TXEFA_EFAI_MASK GENMASK(4, 0) 268 269 /* Message RAM Configuration (in bytes) */ 270 #define SIDF_ELEMENT_SIZE 4 271 #define XIDF_ELEMENT_SIZE 8 272 #define RXF0_ELEMENT_SIZE 72 273 #define RXF1_ELEMENT_SIZE 72 274 #define RXB_ELEMENT_SIZE 72 275 #define TXE_ELEMENT_SIZE 8 276 #define TXB_ELEMENT_SIZE 72 277 278 /* Message RAM Elements */ 279 #define M_CAN_FIFO_ID 0x0 280 #define M_CAN_FIFO_DLC 0x4 281 #define M_CAN_FIFO_DATA 0x8 282 283 /* Rx Buffer Element */ 284 /* R0 */ 285 #define RX_BUF_ESI BIT(31) 286 #define RX_BUF_XTD BIT(30) 287 #define RX_BUF_RTR BIT(29) 288 /* R1 */ 289 #define RX_BUF_ANMF BIT(31) 290 #define RX_BUF_FDF BIT(21) 291 #define RX_BUF_BRS BIT(20) 292 #define RX_BUF_RXTS_MASK GENMASK(15, 0) 293 294 /* Tx Buffer Element */ 295 /* T0 */ 296 #define TX_BUF_ESI BIT(31) 297 #define TX_BUF_XTD BIT(30) 298 #define TX_BUF_RTR BIT(29) 299 /* T1 */ 300 #define TX_BUF_EFC BIT(23) 301 #define TX_BUF_FDF BIT(21) 302 #define TX_BUF_BRS BIT(20) 303 #define TX_BUF_MM_MASK GENMASK(31, 24) 304 #define TX_BUF_DLC_MASK GENMASK(19, 16) 305 306 /* Tx event FIFO Element */ 307 /* E1 */ 308 #define TX_EVENT_MM_MASK GENMASK(31, 24) 309 #define TX_EVENT_TXTS_MASK GENMASK(15, 0) 310 311 /* Hrtimer polling interval */ 312 #define HRTIMER_POLL_INTERVAL_MS 1 313 314 /* The ID and DLC registers are adjacent in M_CAN FIFO memory, 315 * and we can save a (potentially slow) bus round trip by combining 316 * reads and writes to them. 317 */ 318 struct id_and_dlc { 319 u32 id; 320 u32 dlc; 321 }; 322 323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 324 { 325 return cdev->ops->read_reg(cdev, reg); 326 } 327 328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 329 u32 val) 330 { 331 cdev->ops->write_reg(cdev, reg, val); 332 } 333 334 static int 335 m_can_fifo_read(struct m_can_classdev *cdev, 336 u32 fgi, unsigned int offset, void *val, size_t val_count) 337 { 338 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 339 offset; 340 341 if (val_count == 0) 342 return 0; 343 344 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); 345 } 346 347 static int 348 m_can_fifo_write(struct m_can_classdev *cdev, 349 u32 fpi, unsigned int offset, const void *val, size_t val_count) 350 { 351 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 352 offset; 353 354 if (val_count == 0) 355 return 0; 356 357 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); 358 } 359 360 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, 361 u32 fpi, u32 val) 362 { 363 return cdev->ops->write_fifo(cdev, fpi, &val, 1); 364 } 365 366 static int 367 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) 368 { 369 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 370 offset; 371 372 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); 373 } 374 375 static inline bool _m_can_tx_fifo_full(u32 txfqs) 376 { 377 return !!(txfqs & TXFQS_TFQF); 378 } 379 380 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) 381 { 382 return _m_can_tx_fifo_full(m_can_read(cdev, M_CAN_TXFQS)); 383 } 384 385 static void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) 386 { 387 u32 cccr = m_can_read(cdev, M_CAN_CCCR); 388 u32 timeout = 10; 389 u32 val = 0; 390 391 /* Clear the Clock stop request if it was set */ 392 if (cccr & CCCR_CSR) 393 cccr &= ~CCCR_CSR; 394 395 if (enable) { 396 /* enable m_can configuration */ 397 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT); 398 udelay(5); 399 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */ 400 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE); 401 } else { 402 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE)); 403 } 404 405 /* there's a delay for module initialization */ 406 if (enable) 407 val = CCCR_INIT | CCCR_CCE; 408 409 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) { 410 if (timeout == 0) { 411 netdev_warn(cdev->net, "Failed to init module\n"); 412 return; 413 } 414 timeout--; 415 udelay(1); 416 } 417 } 418 419 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 420 { 421 /* Only interrupt line 0 is used in this driver */ 422 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 423 } 424 425 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 426 { 427 m_can_write(cdev, M_CAN_ILE, 0x0); 428 } 429 430 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit 431 * width. 432 */ 433 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) 434 { 435 u32 tscv; 436 u32 tsc; 437 438 tscv = m_can_read(cdev, M_CAN_TSCV); 439 tsc = FIELD_GET(TSCV_TSC_MASK, tscv); 440 441 return (tsc << 16); 442 } 443 444 static void m_can_clean(struct net_device *net) 445 { 446 struct m_can_classdev *cdev = netdev_priv(net); 447 448 if (cdev->tx_skb) { 449 int putidx = 0; 450 451 net->stats.tx_errors++; 452 if (cdev->version > 30) 453 putidx = FIELD_GET(TXFQS_TFQPI_MASK, 454 m_can_read(cdev, M_CAN_TXFQS)); 455 456 can_free_echo_skb(cdev->net, putidx, NULL); 457 cdev->tx_skb = NULL; 458 } 459 } 460 461 /* For peripherals, pass skb to rx-offload, which will push skb from 462 * napi. For non-peripherals, RX is done in napi already, so push 463 * directly. timestamp is used to ensure good skb ordering in 464 * rx-offload and is ignored for non-peripherals. 465 */ 466 static void m_can_receive_skb(struct m_can_classdev *cdev, 467 struct sk_buff *skb, 468 u32 timestamp) 469 { 470 if (cdev->is_peripheral) { 471 struct net_device_stats *stats = &cdev->net->stats; 472 int err; 473 474 err = can_rx_offload_queue_timestamp(&cdev->offload, skb, 475 timestamp); 476 if (err) 477 stats->rx_fifo_errors++; 478 } else { 479 netif_receive_skb(skb); 480 } 481 } 482 483 static int m_can_read_fifo(struct net_device *dev, u32 fgi) 484 { 485 struct net_device_stats *stats = &dev->stats; 486 struct m_can_classdev *cdev = netdev_priv(dev); 487 struct canfd_frame *cf; 488 struct sk_buff *skb; 489 struct id_and_dlc fifo_header; 490 u32 timestamp = 0; 491 int err; 492 493 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); 494 if (err) 495 goto out_fail; 496 497 if (fifo_header.dlc & RX_BUF_FDF) 498 skb = alloc_canfd_skb(dev, &cf); 499 else 500 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 501 if (!skb) { 502 stats->rx_dropped++; 503 return 0; 504 } 505 506 if (fifo_header.dlc & RX_BUF_FDF) 507 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F); 508 else 509 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F); 510 511 if (fifo_header.id & RX_BUF_XTD) 512 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG; 513 else 514 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK; 515 516 if (fifo_header.id & RX_BUF_ESI) { 517 cf->flags |= CANFD_ESI; 518 netdev_dbg(dev, "ESI Error\n"); 519 } 520 521 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) { 522 cf->can_id |= CAN_RTR_FLAG; 523 } else { 524 if (fifo_header.dlc & RX_BUF_BRS) 525 cf->flags |= CANFD_BRS; 526 527 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, 528 cf->data, DIV_ROUND_UP(cf->len, 4)); 529 if (err) 530 goto out_free_skb; 531 532 stats->rx_bytes += cf->len; 533 } 534 stats->rx_packets++; 535 536 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16; 537 538 m_can_receive_skb(cdev, skb, timestamp); 539 540 return 0; 541 542 out_free_skb: 543 kfree_skb(skb); 544 out_fail: 545 netdev_err(dev, "FIFO read returned %d\n", err); 546 return err; 547 } 548 549 static int m_can_do_rx_poll(struct net_device *dev, int quota) 550 { 551 struct m_can_classdev *cdev = netdev_priv(dev); 552 u32 pkts = 0; 553 u32 rxfs; 554 u32 rx_count; 555 u32 fgi; 556 int ack_fgi = -1; 557 int i; 558 int err = 0; 559 560 rxfs = m_can_read(cdev, M_CAN_RXF0S); 561 if (!(rxfs & RXFS_FFL_MASK)) { 562 netdev_dbg(dev, "no messages in fifo0\n"); 563 return 0; 564 } 565 566 rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs); 567 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs); 568 569 for (i = 0; i < rx_count && quota > 0; ++i) { 570 err = m_can_read_fifo(dev, fgi); 571 if (err) 572 break; 573 574 quota--; 575 pkts++; 576 ack_fgi = fgi; 577 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi); 578 } 579 580 if (ack_fgi != -1) 581 m_can_write(cdev, M_CAN_RXF0A, ack_fgi); 582 583 if (err) 584 return err; 585 586 return pkts; 587 } 588 589 static int m_can_handle_lost_msg(struct net_device *dev) 590 { 591 struct m_can_classdev *cdev = netdev_priv(dev); 592 struct net_device_stats *stats = &dev->stats; 593 struct sk_buff *skb; 594 struct can_frame *frame; 595 u32 timestamp = 0; 596 597 netdev_err(dev, "msg lost in rxf0\n"); 598 599 stats->rx_errors++; 600 stats->rx_over_errors++; 601 602 skb = alloc_can_err_skb(dev, &frame); 603 if (unlikely(!skb)) 604 return 0; 605 606 frame->can_id |= CAN_ERR_CRTL; 607 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 608 609 if (cdev->is_peripheral) 610 timestamp = m_can_get_timestamp(cdev); 611 612 m_can_receive_skb(cdev, skb, timestamp); 613 614 return 1; 615 } 616 617 static int m_can_handle_lec_err(struct net_device *dev, 618 enum m_can_lec_type lec_type) 619 { 620 struct m_can_classdev *cdev = netdev_priv(dev); 621 struct net_device_stats *stats = &dev->stats; 622 struct can_frame *cf; 623 struct sk_buff *skb; 624 u32 timestamp = 0; 625 626 cdev->can.can_stats.bus_error++; 627 stats->rx_errors++; 628 629 /* propagate the error condition to the CAN stack */ 630 skb = alloc_can_err_skb(dev, &cf); 631 if (unlikely(!skb)) 632 return 0; 633 634 /* check for 'last error code' which tells us the 635 * type of the last error to occur on the CAN bus 636 */ 637 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 638 639 switch (lec_type) { 640 case LEC_STUFF_ERROR: 641 netdev_dbg(dev, "stuff error\n"); 642 cf->data[2] |= CAN_ERR_PROT_STUFF; 643 break; 644 case LEC_FORM_ERROR: 645 netdev_dbg(dev, "form error\n"); 646 cf->data[2] |= CAN_ERR_PROT_FORM; 647 break; 648 case LEC_ACK_ERROR: 649 netdev_dbg(dev, "ack error\n"); 650 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 651 break; 652 case LEC_BIT1_ERROR: 653 netdev_dbg(dev, "bit1 error\n"); 654 cf->data[2] |= CAN_ERR_PROT_BIT1; 655 break; 656 case LEC_BIT0_ERROR: 657 netdev_dbg(dev, "bit0 error\n"); 658 cf->data[2] |= CAN_ERR_PROT_BIT0; 659 break; 660 case LEC_CRC_ERROR: 661 netdev_dbg(dev, "CRC error\n"); 662 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 663 break; 664 default: 665 break; 666 } 667 668 if (cdev->is_peripheral) 669 timestamp = m_can_get_timestamp(cdev); 670 671 m_can_receive_skb(cdev, skb, timestamp); 672 673 return 1; 674 } 675 676 static int __m_can_get_berr_counter(const struct net_device *dev, 677 struct can_berr_counter *bec) 678 { 679 struct m_can_classdev *cdev = netdev_priv(dev); 680 unsigned int ecr; 681 682 ecr = m_can_read(cdev, M_CAN_ECR); 683 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr); 684 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr); 685 686 return 0; 687 } 688 689 static int m_can_clk_start(struct m_can_classdev *cdev) 690 { 691 if (cdev->pm_clock_support == 0) 692 return 0; 693 694 return pm_runtime_resume_and_get(cdev->dev); 695 } 696 697 static void m_can_clk_stop(struct m_can_classdev *cdev) 698 { 699 if (cdev->pm_clock_support) 700 pm_runtime_put_sync(cdev->dev); 701 } 702 703 static int m_can_get_berr_counter(const struct net_device *dev, 704 struct can_berr_counter *bec) 705 { 706 struct m_can_classdev *cdev = netdev_priv(dev); 707 int err; 708 709 err = m_can_clk_start(cdev); 710 if (err) 711 return err; 712 713 __m_can_get_berr_counter(dev, bec); 714 715 m_can_clk_stop(cdev); 716 717 return 0; 718 } 719 720 static int m_can_handle_state_change(struct net_device *dev, 721 enum can_state new_state) 722 { 723 struct m_can_classdev *cdev = netdev_priv(dev); 724 struct can_frame *cf; 725 struct sk_buff *skb; 726 struct can_berr_counter bec; 727 unsigned int ecr; 728 u32 timestamp = 0; 729 730 switch (new_state) { 731 case CAN_STATE_ERROR_WARNING: 732 /* error warning state */ 733 cdev->can.can_stats.error_warning++; 734 cdev->can.state = CAN_STATE_ERROR_WARNING; 735 break; 736 case CAN_STATE_ERROR_PASSIVE: 737 /* error passive state */ 738 cdev->can.can_stats.error_passive++; 739 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 740 break; 741 case CAN_STATE_BUS_OFF: 742 /* bus-off state */ 743 cdev->can.state = CAN_STATE_BUS_OFF; 744 m_can_disable_all_interrupts(cdev); 745 cdev->can.can_stats.bus_off++; 746 can_bus_off(dev); 747 break; 748 default: 749 break; 750 } 751 752 /* propagate the error condition to the CAN stack */ 753 skb = alloc_can_err_skb(dev, &cf); 754 if (unlikely(!skb)) 755 return 0; 756 757 __m_can_get_berr_counter(dev, &bec); 758 759 switch (new_state) { 760 case CAN_STATE_ERROR_WARNING: 761 /* error warning state */ 762 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 763 cf->data[1] = (bec.txerr > bec.rxerr) ? 764 CAN_ERR_CRTL_TX_WARNING : 765 CAN_ERR_CRTL_RX_WARNING; 766 cf->data[6] = bec.txerr; 767 cf->data[7] = bec.rxerr; 768 break; 769 case CAN_STATE_ERROR_PASSIVE: 770 /* error passive state */ 771 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 772 ecr = m_can_read(cdev, M_CAN_ECR); 773 if (ecr & ECR_RP) 774 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 775 if (bec.txerr > 127) 776 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 777 cf->data[6] = bec.txerr; 778 cf->data[7] = bec.rxerr; 779 break; 780 case CAN_STATE_BUS_OFF: 781 /* bus-off state */ 782 cf->can_id |= CAN_ERR_BUSOFF; 783 break; 784 default: 785 break; 786 } 787 788 if (cdev->is_peripheral) 789 timestamp = m_can_get_timestamp(cdev); 790 791 m_can_receive_skb(cdev, skb, timestamp); 792 793 return 1; 794 } 795 796 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 797 { 798 struct m_can_classdev *cdev = netdev_priv(dev); 799 int work_done = 0; 800 801 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 802 netdev_dbg(dev, "entered error warning state\n"); 803 work_done += m_can_handle_state_change(dev, 804 CAN_STATE_ERROR_WARNING); 805 } 806 807 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 808 netdev_dbg(dev, "entered error passive state\n"); 809 work_done += m_can_handle_state_change(dev, 810 CAN_STATE_ERROR_PASSIVE); 811 } 812 813 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 814 netdev_dbg(dev, "entered error bus off state\n"); 815 work_done += m_can_handle_state_change(dev, 816 CAN_STATE_BUS_OFF); 817 } 818 819 return work_done; 820 } 821 822 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 823 { 824 if (irqstatus & IR_WDI) 825 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 826 if (irqstatus & IR_BEU) 827 netdev_err(dev, "Bit Error Uncorrected\n"); 828 if (irqstatus & IR_BEC) 829 netdev_err(dev, "Bit Error Corrected\n"); 830 if (irqstatus & IR_TOO) 831 netdev_err(dev, "Timeout reached\n"); 832 if (irqstatus & IR_MRAF) 833 netdev_err(dev, "Message RAM access failure occurred\n"); 834 } 835 836 static inline bool is_lec_err(u8 lec) 837 { 838 return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE; 839 } 840 841 static inline bool m_can_is_protocol_err(u32 irqstatus) 842 { 843 return irqstatus & IR_ERR_LEC_31X; 844 } 845 846 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 847 { 848 struct net_device_stats *stats = &dev->stats; 849 struct m_can_classdev *cdev = netdev_priv(dev); 850 struct can_frame *cf; 851 struct sk_buff *skb; 852 u32 timestamp = 0; 853 854 /* propagate the error condition to the CAN stack */ 855 skb = alloc_can_err_skb(dev, &cf); 856 857 /* update tx error stats since there is protocol error */ 858 stats->tx_errors++; 859 860 /* update arbitration lost status */ 861 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 862 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 863 cdev->can.can_stats.arbitration_lost++; 864 if (skb) { 865 cf->can_id |= CAN_ERR_LOSTARB; 866 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 867 } 868 } 869 870 if (unlikely(!skb)) { 871 netdev_dbg(dev, "allocation of skb failed\n"); 872 return 0; 873 } 874 875 if (cdev->is_peripheral) 876 timestamp = m_can_get_timestamp(cdev); 877 878 m_can_receive_skb(cdev, skb, timestamp); 879 880 return 1; 881 } 882 883 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 884 u32 psr) 885 { 886 struct m_can_classdev *cdev = netdev_priv(dev); 887 int work_done = 0; 888 889 if (irqstatus & IR_RF0L) 890 work_done += m_can_handle_lost_msg(dev); 891 892 /* handle lec errors on the bus */ 893 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 894 u8 lec = FIELD_GET(PSR_LEC_MASK, psr); 895 u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr); 896 897 if (is_lec_err(lec)) { 898 netdev_dbg(dev, "Arbitration phase error detected\n"); 899 work_done += m_can_handle_lec_err(dev, lec); 900 } 901 902 if (is_lec_err(dlec)) { 903 netdev_dbg(dev, "Data phase error detected\n"); 904 work_done += m_can_handle_lec_err(dev, dlec); 905 } 906 } 907 908 /* handle protocol errors in arbitration phase */ 909 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 910 m_can_is_protocol_err(irqstatus)) 911 work_done += m_can_handle_protocol_error(dev, irqstatus); 912 913 /* other unproccessed error interrupts */ 914 m_can_handle_other_err(dev, irqstatus); 915 916 return work_done; 917 } 918 919 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus) 920 { 921 struct m_can_classdev *cdev = netdev_priv(dev); 922 int rx_work_or_err; 923 int work_done = 0; 924 925 if (!irqstatus) 926 goto end; 927 928 /* Errata workaround for issue "Needless activation of MRAF irq" 929 * During frame reception while the MCAN is in Error Passive state 930 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 931 * it may happen that MCAN_IR.MRAF is set although there was no 932 * Message RAM access failure. 933 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 934 * The Message RAM Access Failure interrupt routine needs to check 935 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 936 * In this case, reset MCAN_IR.MRAF. No further action is required. 937 */ 938 if (cdev->version <= 31 && irqstatus & IR_MRAF && 939 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 940 struct can_berr_counter bec; 941 942 __m_can_get_berr_counter(dev, &bec); 943 if (bec.rxerr == 127) { 944 m_can_write(cdev, M_CAN_IR, IR_MRAF); 945 irqstatus &= ~IR_MRAF; 946 } 947 } 948 949 if (irqstatus & IR_ERR_STATE) 950 work_done += m_can_handle_state_errors(dev, 951 m_can_read(cdev, M_CAN_PSR)); 952 953 if (irqstatus & IR_ERR_BUS_30X) 954 work_done += m_can_handle_bus_errors(dev, irqstatus, 955 m_can_read(cdev, M_CAN_PSR)); 956 957 if (irqstatus & IR_RF0N) { 958 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done)); 959 if (rx_work_or_err < 0) 960 return rx_work_or_err; 961 962 work_done += rx_work_or_err; 963 } 964 end: 965 return work_done; 966 } 967 968 static int m_can_rx_peripheral(struct net_device *dev, u32 irqstatus) 969 { 970 struct m_can_classdev *cdev = netdev_priv(dev); 971 int work_done; 972 973 work_done = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, irqstatus); 974 975 /* Don't re-enable interrupts if the driver had a fatal error 976 * (e.g., FIFO read failure). 977 */ 978 if (work_done < 0) 979 m_can_disable_all_interrupts(cdev); 980 981 return work_done; 982 } 983 984 static int m_can_poll(struct napi_struct *napi, int quota) 985 { 986 struct net_device *dev = napi->dev; 987 struct m_can_classdev *cdev = netdev_priv(dev); 988 int work_done; 989 u32 irqstatus; 990 991 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 992 993 work_done = m_can_rx_handler(dev, quota, irqstatus); 994 995 /* Don't re-enable interrupts if the driver had a fatal error 996 * (e.g., FIFO read failure). 997 */ 998 if (work_done >= 0 && work_done < quota) { 999 napi_complete_done(napi, work_done); 1000 m_can_enable_all_interrupts(cdev); 1001 } 1002 1003 return work_done; 1004 } 1005 1006 /* Echo tx skb and update net stats. Peripherals use rx-offload for 1007 * echo. timestamp is used for peripherals to ensure correct ordering 1008 * by rx-offload, and is ignored for non-peripherals. 1009 */ 1010 static void m_can_tx_update_stats(struct m_can_classdev *cdev, 1011 unsigned int msg_mark, 1012 u32 timestamp) 1013 { 1014 struct net_device *dev = cdev->net; 1015 struct net_device_stats *stats = &dev->stats; 1016 1017 if (cdev->is_peripheral) 1018 stats->tx_bytes += 1019 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload, 1020 msg_mark, 1021 timestamp, 1022 NULL); 1023 else 1024 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, NULL); 1025 1026 stats->tx_packets++; 1027 } 1028 1029 static int m_can_echo_tx_event(struct net_device *dev) 1030 { 1031 u32 txe_count = 0; 1032 u32 m_can_txefs; 1033 u32 fgi = 0; 1034 int ack_fgi = -1; 1035 int i = 0; 1036 int err = 0; 1037 unsigned int msg_mark; 1038 1039 struct m_can_classdev *cdev = netdev_priv(dev); 1040 1041 /* read tx event fifo status */ 1042 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 1043 1044 /* Get Tx Event fifo element count */ 1045 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs); 1046 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs); 1047 1048 /* Get and process all sent elements */ 1049 for (i = 0; i < txe_count; i++) { 1050 u32 txe, timestamp = 0; 1051 1052 /* get message marker, timestamp */ 1053 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); 1054 if (err) { 1055 netdev_err(dev, "TXE FIFO read returned %d\n", err); 1056 break; 1057 } 1058 1059 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe); 1060 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16; 1061 1062 ack_fgi = fgi; 1063 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi); 1064 1065 /* update stats */ 1066 m_can_tx_update_stats(cdev, msg_mark, timestamp); 1067 } 1068 1069 if (ack_fgi != -1) 1070 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, 1071 ack_fgi)); 1072 1073 return err; 1074 } 1075 1076 static irqreturn_t m_can_isr(int irq, void *dev_id) 1077 { 1078 struct net_device *dev = (struct net_device *)dev_id; 1079 struct m_can_classdev *cdev = netdev_priv(dev); 1080 u32 ir; 1081 1082 if (pm_runtime_suspended(cdev->dev)) 1083 return IRQ_NONE; 1084 ir = m_can_read(cdev, M_CAN_IR); 1085 if (!ir) 1086 return IRQ_NONE; 1087 1088 /* ACK all irqs */ 1089 m_can_write(cdev, M_CAN_IR, ir); 1090 1091 if (cdev->ops->clear_interrupts) 1092 cdev->ops->clear_interrupts(cdev); 1093 1094 /* schedule NAPI in case of 1095 * - rx IRQ 1096 * - state change IRQ 1097 * - bus error IRQ and bus error reporting 1098 */ 1099 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) { 1100 cdev->irqstatus = ir; 1101 if (!cdev->is_peripheral) { 1102 m_can_disable_all_interrupts(cdev); 1103 napi_schedule(&cdev->napi); 1104 } else if (m_can_rx_peripheral(dev, ir) < 0) { 1105 goto out_fail; 1106 } 1107 } 1108 1109 if (cdev->version == 30) { 1110 if (ir & IR_TC) { 1111 /* Transmission Complete Interrupt*/ 1112 u32 timestamp = 0; 1113 1114 if (cdev->is_peripheral) 1115 timestamp = m_can_get_timestamp(cdev); 1116 m_can_tx_update_stats(cdev, 0, timestamp); 1117 netif_wake_queue(dev); 1118 } 1119 } else { 1120 if (ir & IR_TEFN) { 1121 /* New TX FIFO Element arrived */ 1122 if (m_can_echo_tx_event(dev) != 0) 1123 goto out_fail; 1124 1125 if (netif_queue_stopped(dev) && 1126 !m_can_tx_fifo_full(cdev)) 1127 netif_wake_queue(dev); 1128 } 1129 } 1130 1131 if (cdev->is_peripheral) 1132 can_rx_offload_threaded_irq_finish(&cdev->offload); 1133 1134 return IRQ_HANDLED; 1135 1136 out_fail: 1137 m_can_disable_all_interrupts(cdev); 1138 return IRQ_HANDLED; 1139 } 1140 1141 static const struct can_bittiming_const m_can_bittiming_const_30X = { 1142 .name = KBUILD_MODNAME, 1143 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1144 .tseg1_max = 64, 1145 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1146 .tseg2_max = 16, 1147 .sjw_max = 16, 1148 .brp_min = 1, 1149 .brp_max = 1024, 1150 .brp_inc = 1, 1151 }; 1152 1153 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1154 .name = KBUILD_MODNAME, 1155 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1156 .tseg1_max = 16, 1157 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1158 .tseg2_max = 8, 1159 .sjw_max = 4, 1160 .brp_min = 1, 1161 .brp_max = 32, 1162 .brp_inc = 1, 1163 }; 1164 1165 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1166 .name = KBUILD_MODNAME, 1167 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1168 .tseg1_max = 256, 1169 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1170 .tseg2_max = 128, 1171 .sjw_max = 128, 1172 .brp_min = 1, 1173 .brp_max = 512, 1174 .brp_inc = 1, 1175 }; 1176 1177 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1178 .name = KBUILD_MODNAME, 1179 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1180 .tseg1_max = 32, 1181 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1182 .tseg2_max = 16, 1183 .sjw_max = 16, 1184 .brp_min = 1, 1185 .brp_max = 32, 1186 .brp_inc = 1, 1187 }; 1188 1189 static int m_can_set_bittiming(struct net_device *dev) 1190 { 1191 struct m_can_classdev *cdev = netdev_priv(dev); 1192 const struct can_bittiming *bt = &cdev->can.bittiming; 1193 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1194 u16 brp, sjw, tseg1, tseg2; 1195 u32 reg_btp; 1196 1197 brp = bt->brp - 1; 1198 sjw = bt->sjw - 1; 1199 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1200 tseg2 = bt->phase_seg2 - 1; 1201 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) | 1202 FIELD_PREP(NBTP_NSJW_MASK, sjw) | 1203 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) | 1204 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2); 1205 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1206 1207 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1208 reg_btp = 0; 1209 brp = dbt->brp - 1; 1210 sjw = dbt->sjw - 1; 1211 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1212 tseg2 = dbt->phase_seg2 - 1; 1213 1214 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1215 * This is mentioned in the "Bit Time Requirements for CAN FD" 1216 * paper presented at the International CAN Conference 2013 1217 */ 1218 if (dbt->bitrate > 2500000) { 1219 u32 tdco, ssp; 1220 1221 /* Use the same value of secondary sampling point 1222 * as the data sampling point 1223 */ 1224 ssp = dbt->sample_point; 1225 1226 /* Equation based on Bosch's M_CAN User Manual's 1227 * Transmitter Delay Compensation Section 1228 */ 1229 tdco = (cdev->can.clock.freq / 1000) * 1230 ssp / dbt->bitrate; 1231 1232 /* Max valid TDCO value is 127 */ 1233 if (tdco > 127) { 1234 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1235 tdco); 1236 tdco = 127; 1237 } 1238 1239 reg_btp |= DBTP_TDC; 1240 m_can_write(cdev, M_CAN_TDCR, 1241 FIELD_PREP(TDCR_TDCO_MASK, tdco)); 1242 } 1243 1244 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) | 1245 FIELD_PREP(DBTP_DSJW_MASK, sjw) | 1246 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) | 1247 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2); 1248 1249 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1250 } 1251 1252 return 0; 1253 } 1254 1255 /* Configure M_CAN chip: 1256 * - set rx buffer/fifo element size 1257 * - configure rx fifo 1258 * - accept non-matching frame into fifo 0 1259 * - configure tx buffer 1260 * - >= v3.1.x: TX FIFO is used 1261 * - configure mode 1262 * - setup bittiming 1263 * - configure timestamp generation 1264 */ 1265 static int m_can_chip_config(struct net_device *dev) 1266 { 1267 struct m_can_classdev *cdev = netdev_priv(dev); 1268 u32 interrupts = IR_ALL_INT; 1269 u32 cccr, test; 1270 int err; 1271 1272 err = m_can_init_ram(cdev); 1273 if (err) { 1274 dev_err(cdev->dev, "Message RAM configuration failed\n"); 1275 return err; 1276 } 1277 1278 /* Disable unused interrupts */ 1279 interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TEFW | IR_TFE | 1280 IR_TCF | IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | 1281 IR_RF0F | IR_RF0W); 1282 1283 m_can_config_endisable(cdev, true); 1284 1285 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1286 m_can_write(cdev, M_CAN_RXESC, 1287 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) | 1288 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) | 1289 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B)); 1290 1291 /* Accept Non-matching Frames Into FIFO 0 */ 1292 m_can_write(cdev, M_CAN_GFC, 0x0); 1293 1294 if (cdev->version == 30) { 1295 /* only support one Tx Buffer currently */ 1296 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | 1297 cdev->mcfg[MRAM_TXB].off); 1298 } else { 1299 /* TX FIFO is used for newer IP Core versions */ 1300 m_can_write(cdev, M_CAN_TXBC, 1301 FIELD_PREP(TXBC_TFQS_MASK, 1302 cdev->mcfg[MRAM_TXB].num) | 1303 cdev->mcfg[MRAM_TXB].off); 1304 } 1305 1306 /* support 64 bytes payload */ 1307 m_can_write(cdev, M_CAN_TXESC, 1308 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B)); 1309 1310 /* TX Event FIFO */ 1311 if (cdev->version == 30) { 1312 m_can_write(cdev, M_CAN_TXEFC, 1313 FIELD_PREP(TXEFC_EFS_MASK, 1) | 1314 cdev->mcfg[MRAM_TXE].off); 1315 } else { 1316 /* Full TX Event FIFO is used */ 1317 m_can_write(cdev, M_CAN_TXEFC, 1318 FIELD_PREP(TXEFC_EFS_MASK, 1319 cdev->mcfg[MRAM_TXE].num) | 1320 cdev->mcfg[MRAM_TXE].off); 1321 } 1322 1323 /* rx fifo configuration, blocking mode, fifo size 1 */ 1324 m_can_write(cdev, M_CAN_RXF0C, 1325 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | 1326 cdev->mcfg[MRAM_RXF0].off); 1327 1328 m_can_write(cdev, M_CAN_RXF1C, 1329 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | 1330 cdev->mcfg[MRAM_RXF1].off); 1331 1332 cccr = m_can_read(cdev, M_CAN_CCCR); 1333 test = m_can_read(cdev, M_CAN_TEST); 1334 test &= ~TEST_LBCK; 1335 if (cdev->version == 30) { 1336 /* Version 3.0.x */ 1337 1338 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1339 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) | 1340 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK))); 1341 1342 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1343 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS); 1344 1345 } else { 1346 /* Version 3.1.x or 3.2.x */ 1347 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1348 CCCR_NISO | CCCR_DAR); 1349 1350 /* Only 3.2.x has NISO Bit implemented */ 1351 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1352 cccr |= CCCR_NISO; 1353 1354 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1355 cccr |= (CCCR_BRSE | CCCR_FDOE); 1356 } 1357 1358 /* Loopback Mode */ 1359 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1360 cccr |= CCCR_TEST | CCCR_MON; 1361 test |= TEST_LBCK; 1362 } 1363 1364 /* Enable Monitoring (all versions) */ 1365 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1366 cccr |= CCCR_MON; 1367 1368 /* Disable Auto Retransmission (all versions) */ 1369 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1370 cccr |= CCCR_DAR; 1371 1372 /* Write config */ 1373 m_can_write(cdev, M_CAN_CCCR, cccr); 1374 m_can_write(cdev, M_CAN_TEST, test); 1375 1376 /* Enable interrupts */ 1377 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1378 if (cdev->version == 30) 1379 interrupts &= ~(IR_ERR_LEC_30X); 1380 else 1381 interrupts &= ~(IR_ERR_LEC_31X); 1382 } 1383 m_can_write(cdev, M_CAN_IE, interrupts); 1384 1385 /* route all interrupts to INT0 */ 1386 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1387 1388 /* set bittiming params */ 1389 m_can_set_bittiming(dev); 1390 1391 /* enable internal timestamp generation, with a prescaler of 16. The 1392 * prescaler is applied to the nominal bit timing 1393 */ 1394 m_can_write(cdev, M_CAN_TSCC, 1395 FIELD_PREP(TSCC_TCP_MASK, 0xf) | 1396 FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL)); 1397 1398 m_can_config_endisable(cdev, false); 1399 1400 if (cdev->ops->init) 1401 cdev->ops->init(cdev); 1402 1403 return 0; 1404 } 1405 1406 static int m_can_start(struct net_device *dev) 1407 { 1408 struct m_can_classdev *cdev = netdev_priv(dev); 1409 int ret; 1410 1411 /* basic m_can configuration */ 1412 ret = m_can_chip_config(dev); 1413 if (ret) 1414 return ret; 1415 1416 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1417 1418 m_can_enable_all_interrupts(cdev); 1419 1420 if (!dev->irq) { 1421 dev_dbg(cdev->dev, "Start hrtimer\n"); 1422 hrtimer_start(&cdev->hrtimer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS), 1423 HRTIMER_MODE_REL_PINNED); 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1430 { 1431 switch (mode) { 1432 case CAN_MODE_START: 1433 m_can_clean(dev); 1434 m_can_start(dev); 1435 netif_wake_queue(dev); 1436 break; 1437 default: 1438 return -EOPNOTSUPP; 1439 } 1440 1441 return 0; 1442 } 1443 1444 /* Checks core release number of M_CAN 1445 * returns 0 if an unsupported device is detected 1446 * else it returns the release and step coded as: 1447 * return value = 10 * <release> + 1 * <step> 1448 */ 1449 static int m_can_check_core_release(struct m_can_classdev *cdev) 1450 { 1451 u32 crel_reg; 1452 u8 rel; 1453 u8 step; 1454 int res; 1455 1456 /* Read Core Release Version and split into version number 1457 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1458 */ 1459 crel_reg = m_can_read(cdev, M_CAN_CREL); 1460 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg); 1461 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg); 1462 1463 if (rel == 3) { 1464 /* M_CAN v3.x.y: create return value */ 1465 res = 30 + step; 1466 } else { 1467 /* Unsupported M_CAN version */ 1468 res = 0; 1469 } 1470 1471 return res; 1472 } 1473 1474 /* Selectable Non ISO support only in version 3.2.x 1475 * This function checks if the bit is writable. 1476 */ 1477 static bool m_can_niso_supported(struct m_can_classdev *cdev) 1478 { 1479 u32 cccr_reg, cccr_poll = 0; 1480 int niso_timeout = -ETIMEDOUT; 1481 int i; 1482 1483 m_can_config_endisable(cdev, true); 1484 cccr_reg = m_can_read(cdev, M_CAN_CCCR); 1485 cccr_reg |= CCCR_NISO; 1486 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1487 1488 for (i = 0; i <= 10; i++) { 1489 cccr_poll = m_can_read(cdev, M_CAN_CCCR); 1490 if (cccr_poll == cccr_reg) { 1491 niso_timeout = 0; 1492 break; 1493 } 1494 1495 usleep_range(1, 5); 1496 } 1497 1498 /* Clear NISO */ 1499 cccr_reg &= ~(CCCR_NISO); 1500 m_can_write(cdev, M_CAN_CCCR, cccr_reg); 1501 1502 m_can_config_endisable(cdev, false); 1503 1504 /* return false if time out (-ETIMEDOUT), else return true */ 1505 return !niso_timeout; 1506 } 1507 1508 static int m_can_dev_setup(struct m_can_classdev *cdev) 1509 { 1510 struct net_device *dev = cdev->net; 1511 int m_can_version, err; 1512 1513 m_can_version = m_can_check_core_release(cdev); 1514 /* return if unsupported version */ 1515 if (!m_can_version) { 1516 dev_err(cdev->dev, "Unsupported version number: %2d", 1517 m_can_version); 1518 return -EINVAL; 1519 } 1520 1521 if (!cdev->is_peripheral) 1522 netif_napi_add(dev, &cdev->napi, m_can_poll); 1523 1524 /* Shared properties of all M_CAN versions */ 1525 cdev->version = m_can_version; 1526 cdev->can.do_set_mode = m_can_set_mode; 1527 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1528 1529 /* Set M_CAN supported operations */ 1530 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1531 CAN_CTRLMODE_LISTENONLY | 1532 CAN_CTRLMODE_BERR_REPORTING | 1533 CAN_CTRLMODE_FD | 1534 CAN_CTRLMODE_ONE_SHOT; 1535 1536 /* Set properties depending on M_CAN version */ 1537 switch (cdev->version) { 1538 case 30: 1539 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1540 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1541 if (err) 1542 return err; 1543 cdev->can.bittiming_const = &m_can_bittiming_const_30X; 1544 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; 1545 break; 1546 case 31: 1547 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1548 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1549 if (err) 1550 return err; 1551 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1552 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1553 break; 1554 case 32: 1555 case 33: 1556 /* Support both MCAN version v3.2.x and v3.3.0 */ 1557 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1558 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1559 1560 cdev->can.ctrlmode_supported |= 1561 (m_can_niso_supported(cdev) ? 1562 CAN_CTRLMODE_FD_NON_ISO : 0); 1563 break; 1564 default: 1565 dev_err(cdev->dev, "Unsupported version number: %2d", 1566 cdev->version); 1567 return -EINVAL; 1568 } 1569 1570 if (cdev->ops->init) 1571 cdev->ops->init(cdev); 1572 1573 return 0; 1574 } 1575 1576 static void m_can_stop(struct net_device *dev) 1577 { 1578 struct m_can_classdev *cdev = netdev_priv(dev); 1579 1580 if (!dev->irq) { 1581 dev_dbg(cdev->dev, "Stop hrtimer\n"); 1582 hrtimer_cancel(&cdev->hrtimer); 1583 } 1584 1585 /* disable all interrupts */ 1586 m_can_disable_all_interrupts(cdev); 1587 1588 /* Set init mode to disengage from the network */ 1589 m_can_config_endisable(cdev, true); 1590 1591 /* set the state as STOPPED */ 1592 cdev->can.state = CAN_STATE_STOPPED; 1593 } 1594 1595 static int m_can_close(struct net_device *dev) 1596 { 1597 struct m_can_classdev *cdev = netdev_priv(dev); 1598 1599 netif_stop_queue(dev); 1600 1601 if (!cdev->is_peripheral) 1602 napi_disable(&cdev->napi); 1603 1604 m_can_stop(dev); 1605 m_can_clk_stop(cdev); 1606 free_irq(dev->irq, dev); 1607 1608 if (cdev->is_peripheral) { 1609 cdev->tx_skb = NULL; 1610 destroy_workqueue(cdev->tx_wq); 1611 cdev->tx_wq = NULL; 1612 can_rx_offload_disable(&cdev->offload); 1613 } 1614 1615 close_candev(dev); 1616 1617 phy_power_off(cdev->transceiver); 1618 1619 return 0; 1620 } 1621 1622 static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx) 1623 { 1624 struct m_can_classdev *cdev = netdev_priv(dev); 1625 /*get wrap around for loopback skb index */ 1626 unsigned int wrap = cdev->can.echo_skb_max; 1627 int next_idx; 1628 1629 /* calculate next index */ 1630 next_idx = (++putidx >= wrap ? 0 : putidx); 1631 1632 /* check if occupied */ 1633 return !!cdev->can.echo_skb[next_idx]; 1634 } 1635 1636 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) 1637 { 1638 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data; 1639 struct net_device *dev = cdev->net; 1640 struct sk_buff *skb = cdev->tx_skb; 1641 struct id_and_dlc fifo_header; 1642 u32 cccr, fdflags; 1643 u32 txfqs; 1644 int err; 1645 int putidx; 1646 1647 cdev->tx_skb = NULL; 1648 1649 /* Generate ID field for TX buffer Element */ 1650 /* Common to all supported M_CAN versions */ 1651 if (cf->can_id & CAN_EFF_FLAG) { 1652 fifo_header.id = cf->can_id & CAN_EFF_MASK; 1653 fifo_header.id |= TX_BUF_XTD; 1654 } else { 1655 fifo_header.id = ((cf->can_id & CAN_SFF_MASK) << 18); 1656 } 1657 1658 if (cf->can_id & CAN_RTR_FLAG) 1659 fifo_header.id |= TX_BUF_RTR; 1660 1661 if (cdev->version == 30) { 1662 netif_stop_queue(dev); 1663 1664 fifo_header.dlc = can_fd_len2dlc(cf->len) << 16; 1665 1666 /* Write the frame ID, DLC, and payload to the FIFO element. */ 1667 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_header, 2); 1668 if (err) 1669 goto out_fail; 1670 1671 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, 1672 cf->data, DIV_ROUND_UP(cf->len, 4)); 1673 if (err) 1674 goto out_fail; 1675 1676 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1677 cccr = m_can_read(cdev, M_CAN_CCCR); 1678 cccr &= ~CCCR_CMR_MASK; 1679 if (can_is_canfd_skb(skb)) { 1680 if (cf->flags & CANFD_BRS) 1681 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1682 CCCR_CMR_CANFD_BRS); 1683 else 1684 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1685 CCCR_CMR_CANFD); 1686 } else { 1687 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN); 1688 } 1689 m_can_write(cdev, M_CAN_CCCR, cccr); 1690 } 1691 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1692 1693 can_put_echo_skb(skb, dev, 0, 0); 1694 1695 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1696 /* End of xmit function for version 3.0.x */ 1697 } else { 1698 /* Transmit routine for version >= v3.1.x */ 1699 1700 txfqs = m_can_read(cdev, M_CAN_TXFQS); 1701 1702 /* Check if FIFO full */ 1703 if (_m_can_tx_fifo_full(txfqs)) { 1704 /* This shouldn't happen */ 1705 netif_stop_queue(dev); 1706 netdev_warn(dev, 1707 "TX queue active although FIFO is full."); 1708 1709 if (cdev->is_peripheral) { 1710 kfree_skb(skb); 1711 dev->stats.tx_dropped++; 1712 return NETDEV_TX_OK; 1713 } else { 1714 return NETDEV_TX_BUSY; 1715 } 1716 } 1717 1718 /* get put index for frame */ 1719 putidx = FIELD_GET(TXFQS_TFQPI_MASK, txfqs); 1720 1721 /* Construct DLC Field, with CAN-FD configuration. 1722 * Use the put index of the fifo as the message marker, 1723 * used in the TX interrupt for sending the correct echo frame. 1724 */ 1725 1726 /* get CAN FD configuration of frame */ 1727 fdflags = 0; 1728 if (can_is_canfd_skb(skb)) { 1729 fdflags |= TX_BUF_FDF; 1730 if (cf->flags & CANFD_BRS) 1731 fdflags |= TX_BUF_BRS; 1732 } 1733 1734 fifo_header.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) | 1735 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) | 1736 fdflags | TX_BUF_EFC; 1737 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, &fifo_header, 2); 1738 if (err) 1739 goto out_fail; 1740 1741 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA, 1742 cf->data, DIV_ROUND_UP(cf->len, 4)); 1743 if (err) 1744 goto out_fail; 1745 1746 /* Push loopback echo. 1747 * Will be looped back on TX interrupt based on message marker 1748 */ 1749 can_put_echo_skb(skb, dev, putidx, 0); 1750 1751 /* Enable TX FIFO element to start transfer */ 1752 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx)); 1753 1754 /* stop network queue if fifo full */ 1755 if (m_can_tx_fifo_full(cdev) || 1756 m_can_next_echo_skb_occupied(dev, putidx)) 1757 netif_stop_queue(dev); 1758 } 1759 1760 return NETDEV_TX_OK; 1761 1762 out_fail: 1763 netdev_err(dev, "FIFO write returned %d\n", err); 1764 m_can_disable_all_interrupts(cdev); 1765 return NETDEV_TX_BUSY; 1766 } 1767 1768 static void m_can_tx_work_queue(struct work_struct *ws) 1769 { 1770 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, 1771 tx_work); 1772 1773 m_can_tx_handler(cdev); 1774 } 1775 1776 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1777 struct net_device *dev) 1778 { 1779 struct m_can_classdev *cdev = netdev_priv(dev); 1780 1781 if (can_dev_dropped_skb(dev, skb)) 1782 return NETDEV_TX_OK; 1783 1784 if (cdev->is_peripheral) { 1785 if (cdev->tx_skb) { 1786 netdev_err(dev, "hard_xmit called while tx busy\n"); 1787 return NETDEV_TX_BUSY; 1788 } 1789 1790 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1791 m_can_clean(dev); 1792 } else { 1793 /* Need to stop the queue to avoid numerous requests 1794 * from being sent. Suggested improvement is to create 1795 * a queueing mechanism that will queue the skbs and 1796 * process them in order. 1797 */ 1798 cdev->tx_skb = skb; 1799 netif_stop_queue(cdev->net); 1800 queue_work(cdev->tx_wq, &cdev->tx_work); 1801 } 1802 } else { 1803 cdev->tx_skb = skb; 1804 return m_can_tx_handler(cdev); 1805 } 1806 1807 return NETDEV_TX_OK; 1808 } 1809 1810 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) 1811 { 1812 struct m_can_classdev *cdev = container_of(timer, struct 1813 m_can_classdev, hrtimer); 1814 1815 m_can_isr(0, cdev->net); 1816 1817 hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS)); 1818 1819 return HRTIMER_RESTART; 1820 } 1821 1822 static int m_can_open(struct net_device *dev) 1823 { 1824 struct m_can_classdev *cdev = netdev_priv(dev); 1825 int err; 1826 1827 err = phy_power_on(cdev->transceiver); 1828 if (err) 1829 return err; 1830 1831 err = m_can_clk_start(cdev); 1832 if (err) 1833 goto out_phy_power_off; 1834 1835 /* open the can device */ 1836 err = open_candev(dev); 1837 if (err) { 1838 netdev_err(dev, "failed to open can device\n"); 1839 goto exit_disable_clks; 1840 } 1841 1842 if (cdev->is_peripheral) 1843 can_rx_offload_enable(&cdev->offload); 1844 1845 /* register interrupt handler */ 1846 if (cdev->is_peripheral) { 1847 cdev->tx_skb = NULL; 1848 cdev->tx_wq = alloc_workqueue("mcan_wq", 1849 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0); 1850 if (!cdev->tx_wq) { 1851 err = -ENOMEM; 1852 goto out_wq_fail; 1853 } 1854 1855 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue); 1856 1857 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 1858 IRQF_ONESHOT, 1859 dev->name, dev); 1860 } else if (dev->irq) { 1861 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 1862 dev); 1863 } 1864 1865 if (err < 0) { 1866 netdev_err(dev, "failed to request interrupt\n"); 1867 goto exit_irq_fail; 1868 } 1869 1870 /* start the m_can controller */ 1871 err = m_can_start(dev); 1872 if (err) 1873 goto exit_irq_fail; 1874 1875 if (!cdev->is_peripheral) 1876 napi_enable(&cdev->napi); 1877 1878 netif_start_queue(dev); 1879 1880 return 0; 1881 1882 exit_irq_fail: 1883 if (cdev->is_peripheral) 1884 destroy_workqueue(cdev->tx_wq); 1885 out_wq_fail: 1886 if (cdev->is_peripheral) 1887 can_rx_offload_disable(&cdev->offload); 1888 close_candev(dev); 1889 exit_disable_clks: 1890 m_can_clk_stop(cdev); 1891 out_phy_power_off: 1892 phy_power_off(cdev->transceiver); 1893 return err; 1894 } 1895 1896 static const struct net_device_ops m_can_netdev_ops = { 1897 .ndo_open = m_can_open, 1898 .ndo_stop = m_can_close, 1899 .ndo_start_xmit = m_can_start_xmit, 1900 .ndo_change_mtu = can_change_mtu, 1901 }; 1902 1903 static const struct ethtool_ops m_can_ethtool_ops = { 1904 .get_ts_info = ethtool_op_get_ts_info, 1905 }; 1906 1907 static int register_m_can_dev(struct net_device *dev) 1908 { 1909 dev->flags |= IFF_ECHO; /* we support local echo */ 1910 dev->netdev_ops = &m_can_netdev_ops; 1911 dev->ethtool_ops = &m_can_ethtool_ops; 1912 1913 return register_candev(dev); 1914 } 1915 1916 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size) 1917 { 1918 u32 total_size; 1919 1920 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off + 1921 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1922 if (total_size > mram_max_size) { 1923 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n", 1924 total_size, mram_max_size); 1925 return -EINVAL; 1926 } 1927 1928 return 0; 1929 } 1930 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg); 1931 1932 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 1933 const u32 *mram_config_vals) 1934 { 1935 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 1936 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 1937 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 1938 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 1939 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 1940 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 1941 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 1942 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 1943 FIELD_MAX(RXFC_FS_MASK); 1944 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 1945 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 1946 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 1947 FIELD_MAX(RXFC_FS_MASK); 1948 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 1949 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 1950 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 1951 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 1952 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 1953 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 1954 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 1955 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 1956 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 1957 FIELD_MAX(TXBC_NDTB_MASK); 1958 1959 dev_dbg(cdev->dev, 1960 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 1961 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 1962 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 1963 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 1964 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 1965 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 1966 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 1967 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 1968 } 1969 1970 int m_can_init_ram(struct m_can_classdev *cdev) 1971 { 1972 int end, i, start; 1973 int err = 0; 1974 1975 /* initialize the entire Message RAM in use to avoid possible 1976 * ECC/parity checksum errors when reading an uninitialized buffer 1977 */ 1978 start = cdev->mcfg[MRAM_SIDF].off; 1979 end = cdev->mcfg[MRAM_TXB].off + 1980 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 1981 1982 for (i = start; i < end; i += 4) { 1983 err = m_can_fifo_write_no_off(cdev, i, 0x0); 1984 if (err) 1985 break; 1986 } 1987 1988 return err; 1989 } 1990 EXPORT_SYMBOL_GPL(m_can_init_ram); 1991 1992 int m_can_class_get_clocks(struct m_can_classdev *cdev) 1993 { 1994 int ret = 0; 1995 1996 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 1997 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 1998 1999 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) { 2000 dev_err(cdev->dev, "no clock found\n"); 2001 ret = -ENODEV; 2002 } 2003 2004 return ret; 2005 } 2006 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 2007 2008 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 2009 int sizeof_priv) 2010 { 2011 struct m_can_classdev *class_dev = NULL; 2012 u32 mram_config_vals[MRAM_CFG_LEN]; 2013 struct net_device *net_dev; 2014 u32 tx_fifo_size; 2015 int ret; 2016 2017 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 2018 "bosch,mram-cfg", 2019 mram_config_vals, 2020 sizeof(mram_config_vals) / 4); 2021 if (ret) { 2022 dev_err(dev, "Could not get Message RAM configuration."); 2023 goto out; 2024 } 2025 2026 /* Get TX FIFO size 2027 * Defines the total amount of echo buffers for loopback 2028 */ 2029 tx_fifo_size = mram_config_vals[7]; 2030 2031 /* allocate the m_can device */ 2032 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 2033 if (!net_dev) { 2034 dev_err(dev, "Failed to allocate CAN device"); 2035 goto out; 2036 } 2037 2038 class_dev = netdev_priv(net_dev); 2039 class_dev->net = net_dev; 2040 class_dev->dev = dev; 2041 SET_NETDEV_DEV(net_dev, dev); 2042 2043 m_can_of_parse_mram(class_dev, mram_config_vals); 2044 out: 2045 return class_dev; 2046 } 2047 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 2048 2049 void m_can_class_free_dev(struct net_device *net) 2050 { 2051 free_candev(net); 2052 } 2053 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 2054 2055 int m_can_class_register(struct m_can_classdev *cdev) 2056 { 2057 int ret; 2058 2059 if (cdev->pm_clock_support) { 2060 ret = m_can_clk_start(cdev); 2061 if (ret) 2062 return ret; 2063 } 2064 2065 if (cdev->is_peripheral) { 2066 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, 2067 NAPI_POLL_WEIGHT); 2068 if (ret) 2069 goto clk_disable; 2070 } 2071 2072 if (!cdev->net->irq) 2073 cdev->hrtimer.function = &hrtimer_callback; 2074 2075 ret = m_can_dev_setup(cdev); 2076 if (ret) 2077 goto rx_offload_del; 2078 2079 ret = register_m_can_dev(cdev->net); 2080 if (ret) { 2081 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 2082 cdev->net->name, ret); 2083 goto rx_offload_del; 2084 } 2085 2086 of_can_transceiver(cdev->net); 2087 2088 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 2089 KBUILD_MODNAME, cdev->net->irq, cdev->version); 2090 2091 /* Probe finished 2092 * Stop clocks. They will be reactivated once the M_CAN device is opened 2093 */ 2094 m_can_clk_stop(cdev); 2095 2096 return 0; 2097 2098 rx_offload_del: 2099 if (cdev->is_peripheral) 2100 can_rx_offload_del(&cdev->offload); 2101 clk_disable: 2102 m_can_clk_stop(cdev); 2103 2104 return ret; 2105 } 2106 EXPORT_SYMBOL_GPL(m_can_class_register); 2107 2108 void m_can_class_unregister(struct m_can_classdev *cdev) 2109 { 2110 if (cdev->is_peripheral) 2111 can_rx_offload_del(&cdev->offload); 2112 unregister_candev(cdev->net); 2113 } 2114 EXPORT_SYMBOL_GPL(m_can_class_unregister); 2115 2116 int m_can_class_suspend(struct device *dev) 2117 { 2118 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2119 struct net_device *ndev = cdev->net; 2120 2121 if (netif_running(ndev)) { 2122 netif_stop_queue(ndev); 2123 netif_device_detach(ndev); 2124 m_can_stop(ndev); 2125 m_can_clk_stop(cdev); 2126 } 2127 2128 pinctrl_pm_select_sleep_state(dev); 2129 2130 cdev->can.state = CAN_STATE_SLEEPING; 2131 2132 return 0; 2133 } 2134 EXPORT_SYMBOL_GPL(m_can_class_suspend); 2135 2136 int m_can_class_resume(struct device *dev) 2137 { 2138 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2139 struct net_device *ndev = cdev->net; 2140 2141 pinctrl_pm_select_default_state(dev); 2142 2143 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 2144 2145 if (netif_running(ndev)) { 2146 int ret; 2147 2148 ret = m_can_clk_start(cdev); 2149 if (ret) 2150 return ret; 2151 ret = m_can_start(ndev); 2152 if (ret) { 2153 m_can_clk_stop(cdev); 2154 2155 return ret; 2156 } 2157 2158 netif_device_attach(ndev); 2159 netif_start_queue(ndev); 2160 } 2161 2162 return 0; 2163 } 2164 EXPORT_SYMBOL_GPL(m_can_class_resume); 2165 2166 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 2167 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 2168 MODULE_LICENSE("GPL v2"); 2169 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 2170