xref: /linux/drivers/net/can/m_can/m_can.c (revision e0bf6c5ca2d3281f231c5f0c9bf145e9513644de)
1 /*
2  * CAN bus driver for Bosch M_CAN controller
3  *
4  * Copyright (C) 2014 Freescale Semiconductor, Inc.
5  *	Dong Aisheng <b29396@freescale.com>
6  *
7  * Bosch M_CAN user manual can be obtained from:
8  * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9  * mcan_users_manual_v302.pdf
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2. This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15 
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 
27 #include <linux/can/dev.h>
28 
29 /* napi related */
30 #define M_CAN_NAPI_WEIGHT	64
31 
32 /* message ram configuration data length */
33 #define MRAM_CFG_LEN	8
34 
35 /* registers definition */
36 enum m_can_reg {
37 	M_CAN_CREL	= 0x0,
38 	M_CAN_ENDN	= 0x4,
39 	M_CAN_CUST	= 0x8,
40 	M_CAN_FBTP	= 0xc,
41 	M_CAN_TEST	= 0x10,
42 	M_CAN_RWD	= 0x14,
43 	M_CAN_CCCR	= 0x18,
44 	M_CAN_BTP	= 0x1c,
45 	M_CAN_TSCC	= 0x20,
46 	M_CAN_TSCV	= 0x24,
47 	M_CAN_TOCC	= 0x28,
48 	M_CAN_TOCV	= 0x2c,
49 	M_CAN_ECR	= 0x40,
50 	M_CAN_PSR	= 0x44,
51 	M_CAN_IR	= 0x50,
52 	M_CAN_IE	= 0x54,
53 	M_CAN_ILS	= 0x58,
54 	M_CAN_ILE	= 0x5c,
55 	M_CAN_GFC	= 0x80,
56 	M_CAN_SIDFC	= 0x84,
57 	M_CAN_XIDFC	= 0x88,
58 	M_CAN_XIDAM	= 0x90,
59 	M_CAN_HPMS	= 0x94,
60 	M_CAN_NDAT1	= 0x98,
61 	M_CAN_NDAT2	= 0x9c,
62 	M_CAN_RXF0C	= 0xa0,
63 	M_CAN_RXF0S	= 0xa4,
64 	M_CAN_RXF0A	= 0xa8,
65 	M_CAN_RXBC	= 0xac,
66 	M_CAN_RXF1C	= 0xb0,
67 	M_CAN_RXF1S	= 0xb4,
68 	M_CAN_RXF1A	= 0xb8,
69 	M_CAN_RXESC	= 0xbc,
70 	M_CAN_TXBC	= 0xc0,
71 	M_CAN_TXFQS	= 0xc4,
72 	M_CAN_TXESC	= 0xc8,
73 	M_CAN_TXBRP	= 0xcc,
74 	M_CAN_TXBAR	= 0xd0,
75 	M_CAN_TXBCR	= 0xd4,
76 	M_CAN_TXBTO	= 0xd8,
77 	M_CAN_TXBCF	= 0xdc,
78 	M_CAN_TXBTIE	= 0xe0,
79 	M_CAN_TXBCIE	= 0xe4,
80 	M_CAN_TXEFC	= 0xf0,
81 	M_CAN_TXEFS	= 0xf4,
82 	M_CAN_TXEFA	= 0xf8,
83 };
84 
85 /* m_can lec values */
86 enum m_can_lec_type {
87 	LEC_NO_ERROR = 0,
88 	LEC_STUFF_ERROR,
89 	LEC_FORM_ERROR,
90 	LEC_ACK_ERROR,
91 	LEC_BIT1_ERROR,
92 	LEC_BIT0_ERROR,
93 	LEC_CRC_ERROR,
94 	LEC_UNUSED,
95 };
96 
97 enum m_can_mram_cfg {
98 	MRAM_SIDF = 0,
99 	MRAM_XIDF,
100 	MRAM_RXF0,
101 	MRAM_RXF1,
102 	MRAM_RXB,
103 	MRAM_TXE,
104 	MRAM_TXB,
105 	MRAM_CFG_NUM,
106 };
107 
108 /* Fast Bit Timing & Prescaler Register (FBTP) */
109 #define FBTR_FBRP_MASK		0x1f
110 #define FBTR_FBRP_SHIFT		16
111 #define FBTR_FTSEG1_SHIFT	8
112 #define FBTR_FTSEG1_MASK	(0xf << FBTR_FTSEG1_SHIFT)
113 #define FBTR_FTSEG2_SHIFT	4
114 #define FBTR_FTSEG2_MASK	(0x7 << FBTR_FTSEG2_SHIFT)
115 #define FBTR_FSJW_SHIFT		0
116 #define FBTR_FSJW_MASK		0x3
117 
118 /* Test Register (TEST) */
119 #define TEST_LBCK	BIT(4)
120 
121 /* CC Control Register(CCCR) */
122 #define CCCR_TEST		BIT(7)
123 #define CCCR_CMR_MASK		0x3
124 #define CCCR_CMR_SHIFT		10
125 #define CCCR_CMR_CANFD		0x1
126 #define CCCR_CMR_CANFD_BRS	0x2
127 #define CCCR_CMR_CAN		0x3
128 #define CCCR_CME_MASK		0x3
129 #define CCCR_CME_SHIFT		8
130 #define CCCR_CME_CAN		0
131 #define CCCR_CME_CANFD		0x1
132 #define CCCR_CME_CANFD_BRS	0x2
133 #define CCCR_TEST		BIT(7)
134 #define CCCR_MON		BIT(5)
135 #define CCCR_CCE		BIT(1)
136 #define CCCR_INIT		BIT(0)
137 #define CCCR_CANFD		0x10
138 
139 /* Bit Timing & Prescaler Register (BTP) */
140 #define BTR_BRP_MASK		0x3ff
141 #define BTR_BRP_SHIFT		16
142 #define BTR_TSEG1_SHIFT		8
143 #define BTR_TSEG1_MASK		(0x3f << BTR_TSEG1_SHIFT)
144 #define BTR_TSEG2_SHIFT		4
145 #define BTR_TSEG2_MASK		(0xf << BTR_TSEG2_SHIFT)
146 #define BTR_SJW_SHIFT		0
147 #define BTR_SJW_MASK		0xf
148 
149 /* Error Counter Register(ECR) */
150 #define ECR_RP			BIT(15)
151 #define ECR_REC_SHIFT		8
152 #define ECR_REC_MASK		(0x7f << ECR_REC_SHIFT)
153 #define ECR_TEC_SHIFT		0
154 #define ECR_TEC_MASK		0xff
155 
156 /* Protocol Status Register(PSR) */
157 #define PSR_BO		BIT(7)
158 #define PSR_EW		BIT(6)
159 #define PSR_EP		BIT(5)
160 #define PSR_LEC_MASK	0x7
161 
162 /* Interrupt Register(IR) */
163 #define IR_ALL_INT	0xffffffff
164 #define IR_STE		BIT(31)
165 #define IR_FOE		BIT(30)
166 #define IR_ACKE		BIT(29)
167 #define IR_BE		BIT(28)
168 #define IR_CRCE		BIT(27)
169 #define IR_WDI		BIT(26)
170 #define IR_BO		BIT(25)
171 #define IR_EW		BIT(24)
172 #define IR_EP		BIT(23)
173 #define IR_ELO		BIT(22)
174 #define IR_BEU		BIT(21)
175 #define IR_BEC		BIT(20)
176 #define IR_DRX		BIT(19)
177 #define IR_TOO		BIT(18)
178 #define IR_MRAF		BIT(17)
179 #define IR_TSW		BIT(16)
180 #define IR_TEFL		BIT(15)
181 #define IR_TEFF		BIT(14)
182 #define IR_TEFW		BIT(13)
183 #define IR_TEFN		BIT(12)
184 #define IR_TFE		BIT(11)
185 #define IR_TCF		BIT(10)
186 #define IR_TC		BIT(9)
187 #define IR_HPM		BIT(8)
188 #define IR_RF1L		BIT(7)
189 #define IR_RF1F		BIT(6)
190 #define IR_RF1W		BIT(5)
191 #define IR_RF1N		BIT(4)
192 #define IR_RF0L		BIT(3)
193 #define IR_RF0F		BIT(2)
194 #define IR_RF0W		BIT(1)
195 #define IR_RF0N		BIT(0)
196 #define IR_ERR_STATE	(IR_BO | IR_EW | IR_EP)
197 #define IR_ERR_LEC	(IR_STE	| IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
198 #define IR_ERR_BUS	(IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
199 			 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
200 			 IR_RF1L | IR_RF0L)
201 #define IR_ERR_ALL	(IR_ERR_STATE | IR_ERR_BUS)
202 
203 /* Interrupt Line Select (ILS) */
204 #define ILS_ALL_INT0	0x0
205 #define ILS_ALL_INT1	0xFFFFFFFF
206 
207 /* Interrupt Line Enable (ILE) */
208 #define ILE_EINT0	BIT(0)
209 #define ILE_EINT1	BIT(1)
210 
211 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
212 #define RXFC_FWM_OFF	24
213 #define RXFC_FWM_MASK	0x7f
214 #define RXFC_FWM_1	(1 << RXFC_FWM_OFF)
215 #define RXFC_FS_OFF	16
216 #define RXFC_FS_MASK	0x7f
217 
218 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
219 #define RXFS_RFL	BIT(25)
220 #define RXFS_FF		BIT(24)
221 #define RXFS_FPI_OFF	16
222 #define RXFS_FPI_MASK	0x3f0000
223 #define RXFS_FGI_OFF	8
224 #define RXFS_FGI_MASK	0x3f00
225 #define RXFS_FFL_MASK	0x7f
226 
227 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
228 #define M_CAN_RXESC_8BYTES	0x0
229 #define M_CAN_RXESC_64BYTES	0x777
230 
231 /* Tx Buffer Configuration(TXBC) */
232 #define TXBC_NDTB_OFF		16
233 #define TXBC_NDTB_MASK		0x3f
234 
235 /* Tx Buffer Element Size Configuration(TXESC) */
236 #define TXESC_TBDS_8BYTES	0x0
237 #define TXESC_TBDS_64BYTES	0x7
238 
239 /* Tx Event FIFO Con.guration (TXEFC) */
240 #define TXEFC_EFS_OFF		16
241 #define TXEFC_EFS_MASK		0x3f
242 
243 /* Message RAM Configuration (in bytes) */
244 #define SIDF_ELEMENT_SIZE	4
245 #define XIDF_ELEMENT_SIZE	8
246 #define RXF0_ELEMENT_SIZE	72
247 #define RXF1_ELEMENT_SIZE	72
248 #define RXB_ELEMENT_SIZE	16
249 #define TXE_ELEMENT_SIZE	8
250 #define TXB_ELEMENT_SIZE	72
251 
252 /* Message RAM Elements */
253 #define M_CAN_FIFO_ID		0x0
254 #define M_CAN_FIFO_DLC		0x4
255 #define M_CAN_FIFO_DATA(n)	(0x8 + ((n) << 2))
256 
257 /* Rx Buffer Element */
258 /* R0 */
259 #define RX_BUF_ESI		BIT(31)
260 #define RX_BUF_XTD		BIT(30)
261 #define RX_BUF_RTR		BIT(29)
262 /* R1 */
263 #define RX_BUF_ANMF		BIT(31)
264 #define RX_BUF_EDL		BIT(21)
265 #define RX_BUF_BRS		BIT(20)
266 
267 /* Tx Buffer Element */
268 /* R0 */
269 #define TX_BUF_XTD		BIT(30)
270 #define TX_BUF_RTR		BIT(29)
271 
272 /* address offset and element number for each FIFO/Buffer in the Message RAM */
273 struct mram_cfg {
274 	u16 off;
275 	u8  num;
276 };
277 
278 /* m_can private data structure */
279 struct m_can_priv {
280 	struct can_priv can;	/* must be the first member */
281 	struct napi_struct napi;
282 	struct net_device *dev;
283 	struct device *device;
284 	struct clk *hclk;
285 	struct clk *cclk;
286 	void __iomem *base;
287 	u32 irqstatus;
288 
289 	/* message ram configuration */
290 	void __iomem *mram_base;
291 	struct mram_cfg mcfg[MRAM_CFG_NUM];
292 };
293 
294 static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
295 {
296 	return readl(priv->base + reg);
297 }
298 
299 static inline void m_can_write(const struct m_can_priv *priv,
300 			       enum m_can_reg reg, u32 val)
301 {
302 	writel(val, priv->base + reg);
303 }
304 
305 static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
306 				  u32 fgi, unsigned int offset)
307 {
308 	return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
309 		     fgi * RXF0_ELEMENT_SIZE + offset);
310 }
311 
312 static inline void m_can_fifo_write(const struct m_can_priv *priv,
313 				    u32 fpi, unsigned int offset, u32 val)
314 {
315 	return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
316 		      fpi * TXB_ELEMENT_SIZE + offset);
317 }
318 
319 static inline void m_can_config_endisable(const struct m_can_priv *priv,
320 					  bool enable)
321 {
322 	u32 cccr = m_can_read(priv, M_CAN_CCCR);
323 	u32 timeout = 10;
324 	u32 val = 0;
325 
326 	if (enable) {
327 		/* enable m_can configuration */
328 		m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
329 		udelay(5);
330 		/* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
331 		m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
332 	} else {
333 		m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
334 	}
335 
336 	/* there's a delay for module initialization */
337 	if (enable)
338 		val = CCCR_INIT | CCCR_CCE;
339 
340 	while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
341 		if (timeout == 0) {
342 			netdev_warn(priv->dev, "Failed to init module\n");
343 			return;
344 		}
345 		timeout--;
346 		udelay(1);
347 	}
348 }
349 
350 static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
351 {
352 	m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
353 }
354 
355 static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
356 {
357 	m_can_write(priv, M_CAN_ILE, 0x0);
358 }
359 
360 static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
361 {
362 	struct net_device_stats *stats = &dev->stats;
363 	struct m_can_priv *priv = netdev_priv(dev);
364 	struct canfd_frame *cf;
365 	struct sk_buff *skb;
366 	u32 id, fgi, dlc;
367 	int i;
368 
369 	/* calculate the fifo get index for where to read data */
370 	fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
371 	dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
372 	if (dlc & RX_BUF_EDL)
373 		skb = alloc_canfd_skb(dev, &cf);
374 	else
375 		skb = alloc_can_skb(dev, (struct can_frame **)&cf);
376 	if (!skb) {
377 		stats->rx_dropped++;
378 		return;
379 	}
380 
381 	if (dlc & RX_BUF_EDL)
382 		cf->len = can_dlc2len((dlc >> 16) & 0x0F);
383 	else
384 		cf->len = get_can_dlc((dlc >> 16) & 0x0F);
385 
386 	id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
387 	if (id & RX_BUF_XTD)
388 		cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
389 	else
390 		cf->can_id = (id >> 18) & CAN_SFF_MASK;
391 
392 	if (id & RX_BUF_ESI) {
393 		cf->flags |= CANFD_ESI;
394 		netdev_dbg(dev, "ESI Error\n");
395 	}
396 
397 	if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) {
398 		cf->can_id |= CAN_RTR_FLAG;
399 	} else {
400 		if (dlc & RX_BUF_BRS)
401 			cf->flags |= CANFD_BRS;
402 
403 		for (i = 0; i < cf->len; i += 4)
404 			*(u32 *)(cf->data + i) =
405 				m_can_fifo_read(priv, fgi,
406 						M_CAN_FIFO_DATA(i / 4));
407 	}
408 
409 	/* acknowledge rx fifo 0 */
410 	m_can_write(priv, M_CAN_RXF0A, fgi);
411 
412 	stats->rx_packets++;
413 	stats->rx_bytes += cf->len;
414 
415 	netif_receive_skb(skb);
416 }
417 
418 static int m_can_do_rx_poll(struct net_device *dev, int quota)
419 {
420 	struct m_can_priv *priv = netdev_priv(dev);
421 	u32 pkts = 0;
422 	u32 rxfs;
423 
424 	rxfs = m_can_read(priv, M_CAN_RXF0S);
425 	if (!(rxfs & RXFS_FFL_MASK)) {
426 		netdev_dbg(dev, "no messages in fifo0\n");
427 		return 0;
428 	}
429 
430 	while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
431 		if (rxfs & RXFS_RFL)
432 			netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
433 
434 		m_can_read_fifo(dev, rxfs);
435 
436 		quota--;
437 		pkts++;
438 		rxfs = m_can_read(priv, M_CAN_RXF0S);
439 	}
440 
441 	if (pkts)
442 		can_led_event(dev, CAN_LED_EVENT_RX);
443 
444 	return pkts;
445 }
446 
447 static int m_can_handle_lost_msg(struct net_device *dev)
448 {
449 	struct net_device_stats *stats = &dev->stats;
450 	struct sk_buff *skb;
451 	struct can_frame *frame;
452 
453 	netdev_err(dev, "msg lost in rxf0\n");
454 
455 	stats->rx_errors++;
456 	stats->rx_over_errors++;
457 
458 	skb = alloc_can_err_skb(dev, &frame);
459 	if (unlikely(!skb))
460 		return 0;
461 
462 	frame->can_id |= CAN_ERR_CRTL;
463 	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
464 
465 	netif_receive_skb(skb);
466 
467 	return 1;
468 }
469 
470 static int m_can_handle_lec_err(struct net_device *dev,
471 				enum m_can_lec_type lec_type)
472 {
473 	struct m_can_priv *priv = netdev_priv(dev);
474 	struct net_device_stats *stats = &dev->stats;
475 	struct can_frame *cf;
476 	struct sk_buff *skb;
477 
478 	priv->can.can_stats.bus_error++;
479 	stats->rx_errors++;
480 
481 	/* propagate the error condition to the CAN stack */
482 	skb = alloc_can_err_skb(dev, &cf);
483 	if (unlikely(!skb))
484 		return 0;
485 
486 	/* check for 'last error code' which tells us the
487 	 * type of the last error to occur on the CAN bus
488 	 */
489 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
490 	cf->data[2] |= CAN_ERR_PROT_UNSPEC;
491 
492 	switch (lec_type) {
493 	case LEC_STUFF_ERROR:
494 		netdev_dbg(dev, "stuff error\n");
495 		cf->data[2] |= CAN_ERR_PROT_STUFF;
496 		break;
497 	case LEC_FORM_ERROR:
498 		netdev_dbg(dev, "form error\n");
499 		cf->data[2] |= CAN_ERR_PROT_FORM;
500 		break;
501 	case LEC_ACK_ERROR:
502 		netdev_dbg(dev, "ack error\n");
503 		cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
504 				CAN_ERR_PROT_LOC_ACK_DEL);
505 		break;
506 	case LEC_BIT1_ERROR:
507 		netdev_dbg(dev, "bit1 error\n");
508 		cf->data[2] |= CAN_ERR_PROT_BIT1;
509 		break;
510 	case LEC_BIT0_ERROR:
511 		netdev_dbg(dev, "bit0 error\n");
512 		cf->data[2] |= CAN_ERR_PROT_BIT0;
513 		break;
514 	case LEC_CRC_ERROR:
515 		netdev_dbg(dev, "CRC error\n");
516 		cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
517 				CAN_ERR_PROT_LOC_CRC_DEL);
518 		break;
519 	default:
520 		break;
521 	}
522 
523 	stats->rx_packets++;
524 	stats->rx_bytes += cf->can_dlc;
525 	netif_receive_skb(skb);
526 
527 	return 1;
528 }
529 
530 static int __m_can_get_berr_counter(const struct net_device *dev,
531 				    struct can_berr_counter *bec)
532 {
533 	struct m_can_priv *priv = netdev_priv(dev);
534 	unsigned int ecr;
535 
536 	ecr = m_can_read(priv, M_CAN_ECR);
537 	bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
538 	bec->txerr = ecr & ECR_TEC_MASK;
539 
540 	return 0;
541 }
542 
543 static int m_can_get_berr_counter(const struct net_device *dev,
544 				  struct can_berr_counter *bec)
545 {
546 	struct m_can_priv *priv = netdev_priv(dev);
547 	int err;
548 
549 	err = clk_prepare_enable(priv->hclk);
550 	if (err)
551 		return err;
552 
553 	err = clk_prepare_enable(priv->cclk);
554 	if (err) {
555 		clk_disable_unprepare(priv->hclk);
556 		return err;
557 	}
558 
559 	__m_can_get_berr_counter(dev, bec);
560 
561 	clk_disable_unprepare(priv->cclk);
562 	clk_disable_unprepare(priv->hclk);
563 
564 	return 0;
565 }
566 
567 static int m_can_handle_state_change(struct net_device *dev,
568 				     enum can_state new_state)
569 {
570 	struct m_can_priv *priv = netdev_priv(dev);
571 	struct net_device_stats *stats = &dev->stats;
572 	struct can_frame *cf;
573 	struct sk_buff *skb;
574 	struct can_berr_counter bec;
575 	unsigned int ecr;
576 
577 	switch (new_state) {
578 	case CAN_STATE_ERROR_ACTIVE:
579 		/* error warning state */
580 		priv->can.can_stats.error_warning++;
581 		priv->can.state = CAN_STATE_ERROR_WARNING;
582 		break;
583 	case CAN_STATE_ERROR_PASSIVE:
584 		/* error passive state */
585 		priv->can.can_stats.error_passive++;
586 		priv->can.state = CAN_STATE_ERROR_PASSIVE;
587 		break;
588 	case CAN_STATE_BUS_OFF:
589 		/* bus-off state */
590 		priv->can.state = CAN_STATE_BUS_OFF;
591 		m_can_disable_all_interrupts(priv);
592 		priv->can.can_stats.bus_off++;
593 		can_bus_off(dev);
594 		break;
595 	default:
596 		break;
597 	}
598 
599 	/* propagate the error condition to the CAN stack */
600 	skb = alloc_can_err_skb(dev, &cf);
601 	if (unlikely(!skb))
602 		return 0;
603 
604 	__m_can_get_berr_counter(dev, &bec);
605 
606 	switch (new_state) {
607 	case CAN_STATE_ERROR_ACTIVE:
608 		/* error warning state */
609 		cf->can_id |= CAN_ERR_CRTL;
610 		cf->data[1] = (bec.txerr > bec.rxerr) ?
611 			CAN_ERR_CRTL_TX_WARNING :
612 			CAN_ERR_CRTL_RX_WARNING;
613 		cf->data[6] = bec.txerr;
614 		cf->data[7] = bec.rxerr;
615 		break;
616 	case CAN_STATE_ERROR_PASSIVE:
617 		/* error passive state */
618 		cf->can_id |= CAN_ERR_CRTL;
619 		ecr = m_can_read(priv, M_CAN_ECR);
620 		if (ecr & ECR_RP)
621 			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
622 		if (bec.txerr > 127)
623 			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
624 		cf->data[6] = bec.txerr;
625 		cf->data[7] = bec.rxerr;
626 		break;
627 	case CAN_STATE_BUS_OFF:
628 		/* bus-off state */
629 		cf->can_id |= CAN_ERR_BUSOFF;
630 		break;
631 	default:
632 		break;
633 	}
634 
635 	stats->rx_packets++;
636 	stats->rx_bytes += cf->can_dlc;
637 	netif_receive_skb(skb);
638 
639 	return 1;
640 }
641 
642 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
643 {
644 	struct m_can_priv *priv = netdev_priv(dev);
645 	int work_done = 0;
646 
647 	if ((psr & PSR_EW) &&
648 	    (priv->can.state != CAN_STATE_ERROR_WARNING)) {
649 		netdev_dbg(dev, "entered error warning state\n");
650 		work_done += m_can_handle_state_change(dev,
651 						       CAN_STATE_ERROR_WARNING);
652 	}
653 
654 	if ((psr & PSR_EP) &&
655 	    (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
656 		netdev_dbg(dev, "entered error passive state\n");
657 		work_done += m_can_handle_state_change(dev,
658 						       CAN_STATE_ERROR_PASSIVE);
659 	}
660 
661 	if ((psr & PSR_BO) &&
662 	    (priv->can.state != CAN_STATE_BUS_OFF)) {
663 		netdev_dbg(dev, "entered error bus off state\n");
664 		work_done += m_can_handle_state_change(dev,
665 						       CAN_STATE_BUS_OFF);
666 	}
667 
668 	return work_done;
669 }
670 
671 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
672 {
673 	if (irqstatus & IR_WDI)
674 		netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
675 	if (irqstatus & IR_ELO)
676 		netdev_err(dev, "Error Logging Overflow\n");
677 	if (irqstatus & IR_BEU)
678 		netdev_err(dev, "Bit Error Uncorrected\n");
679 	if (irqstatus & IR_BEC)
680 		netdev_err(dev, "Bit Error Corrected\n");
681 	if (irqstatus & IR_TOO)
682 		netdev_err(dev, "Timeout reached\n");
683 	if (irqstatus & IR_MRAF)
684 		netdev_err(dev, "Message RAM access failure occurred\n");
685 }
686 
687 static inline bool is_lec_err(u32 psr)
688 {
689 	psr &= LEC_UNUSED;
690 
691 	return psr && (psr != LEC_UNUSED);
692 }
693 
694 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
695 				   u32 psr)
696 {
697 	struct m_can_priv *priv = netdev_priv(dev);
698 	int work_done = 0;
699 
700 	if (irqstatus & IR_RF0L)
701 		work_done += m_can_handle_lost_msg(dev);
702 
703 	/* handle lec errors on the bus */
704 	if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
705 	    is_lec_err(psr))
706 		work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
707 
708 	/* other unproccessed error interrupts */
709 	m_can_handle_other_err(dev, irqstatus);
710 
711 	return work_done;
712 }
713 
714 static int m_can_poll(struct napi_struct *napi, int quota)
715 {
716 	struct net_device *dev = napi->dev;
717 	struct m_can_priv *priv = netdev_priv(dev);
718 	int work_done = 0;
719 	u32 irqstatus, psr;
720 
721 	irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
722 	if (!irqstatus)
723 		goto end;
724 
725 	psr = m_can_read(priv, M_CAN_PSR);
726 	if (irqstatus & IR_ERR_STATE)
727 		work_done += m_can_handle_state_errors(dev, psr);
728 
729 	if (irqstatus & IR_ERR_BUS)
730 		work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
731 
732 	if (irqstatus & IR_RF0N)
733 		work_done += m_can_do_rx_poll(dev, (quota - work_done));
734 
735 	if (work_done < quota) {
736 		napi_complete(napi);
737 		m_can_enable_all_interrupts(priv);
738 	}
739 
740 end:
741 	return work_done;
742 }
743 
744 static irqreturn_t m_can_isr(int irq, void *dev_id)
745 {
746 	struct net_device *dev = (struct net_device *)dev_id;
747 	struct m_can_priv *priv = netdev_priv(dev);
748 	struct net_device_stats *stats = &dev->stats;
749 	u32 ir;
750 
751 	ir = m_can_read(priv, M_CAN_IR);
752 	if (!ir)
753 		return IRQ_NONE;
754 
755 	/* ACK all irqs */
756 	if (ir & IR_ALL_INT)
757 		m_can_write(priv, M_CAN_IR, ir);
758 
759 	/* schedule NAPI in case of
760 	 * - rx IRQ
761 	 * - state change IRQ
762 	 * - bus error IRQ and bus error reporting
763 	 */
764 	if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
765 		priv->irqstatus = ir;
766 		m_can_disable_all_interrupts(priv);
767 		napi_schedule(&priv->napi);
768 	}
769 
770 	/* transmission complete interrupt */
771 	if (ir & IR_TC) {
772 		stats->tx_bytes += can_get_echo_skb(dev, 0);
773 		stats->tx_packets++;
774 		can_led_event(dev, CAN_LED_EVENT_TX);
775 		netif_wake_queue(dev);
776 	}
777 
778 	return IRQ_HANDLED;
779 }
780 
781 static const struct can_bittiming_const m_can_bittiming_const = {
782 	.name = KBUILD_MODNAME,
783 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
784 	.tseg1_max = 64,
785 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
786 	.tseg2_max = 16,
787 	.sjw_max = 16,
788 	.brp_min = 1,
789 	.brp_max = 1024,
790 	.brp_inc = 1,
791 };
792 
793 static const struct can_bittiming_const m_can_data_bittiming_const = {
794 	.name = KBUILD_MODNAME,
795 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
796 	.tseg1_max = 16,
797 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
798 	.tseg2_max = 8,
799 	.sjw_max = 4,
800 	.brp_min = 1,
801 	.brp_max = 32,
802 	.brp_inc = 1,
803 };
804 
805 static int m_can_set_bittiming(struct net_device *dev)
806 {
807 	struct m_can_priv *priv = netdev_priv(dev);
808 	const struct can_bittiming *bt = &priv->can.bittiming;
809 	const struct can_bittiming *dbt = &priv->can.data_bittiming;
810 	u16 brp, sjw, tseg1, tseg2;
811 	u32 reg_btp;
812 
813 	brp = bt->brp - 1;
814 	sjw = bt->sjw - 1;
815 	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
816 	tseg2 = bt->phase_seg2 - 1;
817 	reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
818 			(tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
819 	m_can_write(priv, M_CAN_BTP, reg_btp);
820 
821 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
822 		brp = dbt->brp - 1;
823 		sjw = dbt->sjw - 1;
824 		tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
825 		tseg2 = dbt->phase_seg2 - 1;
826 		reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) |
827 				(tseg1 << FBTR_FTSEG1_SHIFT) |
828 				(tseg2 << FBTR_FTSEG2_SHIFT);
829 		m_can_write(priv, M_CAN_FBTP, reg_btp);
830 	}
831 
832 	return 0;
833 }
834 
835 /* Configure M_CAN chip:
836  * - set rx buffer/fifo element size
837  * - configure rx fifo
838  * - accept non-matching frame into fifo 0
839  * - configure tx buffer
840  * - configure mode
841  * - setup bittiming
842  */
843 static void m_can_chip_config(struct net_device *dev)
844 {
845 	struct m_can_priv *priv = netdev_priv(dev);
846 	u32 cccr, test;
847 
848 	m_can_config_endisable(priv, true);
849 
850 	/* RX Buffer/FIFO Element Size 64 bytes data field */
851 	m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
852 
853 	/* Accept Non-matching Frames Into FIFO 0 */
854 	m_can_write(priv, M_CAN_GFC, 0x0);
855 
856 	/* only support one Tx Buffer currently */
857 	m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
858 		    priv->mcfg[MRAM_TXB].off);
859 
860 	/* support 64 bytes payload */
861 	m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
862 
863 	m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
864 		    priv->mcfg[MRAM_TXE].off);
865 
866 	/* rx fifo configuration, blocking mode, fifo size 1 */
867 	m_can_write(priv, M_CAN_RXF0C,
868 		    (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
869 		    RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
870 
871 	m_can_write(priv, M_CAN_RXF1C,
872 		    (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
873 		    RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
874 
875 	cccr = m_can_read(priv, M_CAN_CCCR);
876 	cccr &= ~(CCCR_TEST | CCCR_MON | (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
877 		(CCCR_CME_MASK << CCCR_CME_SHIFT));
878 	test = m_can_read(priv, M_CAN_TEST);
879 	test &= ~TEST_LBCK;
880 
881 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
882 		cccr |= CCCR_MON;
883 
884 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
885 		cccr |= CCCR_TEST;
886 		test |= TEST_LBCK;
887 	}
888 
889 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
890 		cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
891 
892 	m_can_write(priv, M_CAN_CCCR, cccr);
893 	m_can_write(priv, M_CAN_TEST, test);
894 
895 	/* enable interrupts */
896 	m_can_write(priv, M_CAN_IR, IR_ALL_INT);
897 	if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
898 		m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
899 	else
900 		m_can_write(priv, M_CAN_IE, IR_ALL_INT);
901 
902 	/* route all interrupts to INT0 */
903 	m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
904 
905 	/* set bittiming params */
906 	m_can_set_bittiming(dev);
907 
908 	m_can_config_endisable(priv, false);
909 }
910 
911 static void m_can_start(struct net_device *dev)
912 {
913 	struct m_can_priv *priv = netdev_priv(dev);
914 
915 	/* basic m_can configuration */
916 	m_can_chip_config(dev);
917 
918 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
919 
920 	m_can_enable_all_interrupts(priv);
921 }
922 
923 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
924 {
925 	switch (mode) {
926 	case CAN_MODE_START:
927 		m_can_start(dev);
928 		netif_wake_queue(dev);
929 		break;
930 	default:
931 		return -EOPNOTSUPP;
932 	}
933 
934 	return 0;
935 }
936 
937 static void free_m_can_dev(struct net_device *dev)
938 {
939 	free_candev(dev);
940 }
941 
942 static struct net_device *alloc_m_can_dev(void)
943 {
944 	struct net_device *dev;
945 	struct m_can_priv *priv;
946 
947 	dev = alloc_candev(sizeof(*priv), 1);
948 	if (!dev)
949 		return NULL;
950 
951 	priv = netdev_priv(dev);
952 	netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
953 
954 	priv->dev = dev;
955 	priv->can.bittiming_const = &m_can_bittiming_const;
956 	priv->can.data_bittiming_const = &m_can_data_bittiming_const;
957 	priv->can.do_set_mode = m_can_set_mode;
958 	priv->can.do_get_berr_counter = m_can_get_berr_counter;
959 
960 	/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.1 */
961 	priv->can.ctrlmode = CAN_CTRLMODE_FD_NON_ISO;
962 
963 	/* CAN_CTRLMODE_FD_NON_ISO can not be changed with M_CAN IP v3.0.1 */
964 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
965 					CAN_CTRLMODE_LISTENONLY |
966 					CAN_CTRLMODE_BERR_REPORTING |
967 					CAN_CTRLMODE_FD;
968 
969 	return dev;
970 }
971 
972 static int m_can_open(struct net_device *dev)
973 {
974 	struct m_can_priv *priv = netdev_priv(dev);
975 	int err;
976 
977 	err = clk_prepare_enable(priv->hclk);
978 	if (err)
979 		return err;
980 
981 	err = clk_prepare_enable(priv->cclk);
982 	if (err)
983 		goto exit_disable_hclk;
984 
985 	/* open the can device */
986 	err = open_candev(dev);
987 	if (err) {
988 		netdev_err(dev, "failed to open can device\n");
989 		goto exit_disable_cclk;
990 	}
991 
992 	/* register interrupt handler */
993 	err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
994 			  dev);
995 	if (err < 0) {
996 		netdev_err(dev, "failed to request interrupt\n");
997 		goto exit_irq_fail;
998 	}
999 
1000 	/* start the m_can controller */
1001 	m_can_start(dev);
1002 
1003 	can_led_event(dev, CAN_LED_EVENT_OPEN);
1004 	napi_enable(&priv->napi);
1005 	netif_start_queue(dev);
1006 
1007 	return 0;
1008 
1009 exit_irq_fail:
1010 	close_candev(dev);
1011 exit_disable_cclk:
1012 	clk_disable_unprepare(priv->cclk);
1013 exit_disable_hclk:
1014 	clk_disable_unprepare(priv->hclk);
1015 	return err;
1016 }
1017 
1018 static void m_can_stop(struct net_device *dev)
1019 {
1020 	struct m_can_priv *priv = netdev_priv(dev);
1021 
1022 	/* disable all interrupts */
1023 	m_can_disable_all_interrupts(priv);
1024 
1025 	clk_disable_unprepare(priv->hclk);
1026 	clk_disable_unprepare(priv->cclk);
1027 
1028 	/* set the state as STOPPED */
1029 	priv->can.state = CAN_STATE_STOPPED;
1030 }
1031 
1032 static int m_can_close(struct net_device *dev)
1033 {
1034 	struct m_can_priv *priv = netdev_priv(dev);
1035 
1036 	netif_stop_queue(dev);
1037 	napi_disable(&priv->napi);
1038 	m_can_stop(dev);
1039 	free_irq(dev->irq, dev);
1040 	close_candev(dev);
1041 	can_led_event(dev, CAN_LED_EVENT_STOP);
1042 
1043 	return 0;
1044 }
1045 
1046 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1047 				    struct net_device *dev)
1048 {
1049 	struct m_can_priv *priv = netdev_priv(dev);
1050 	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1051 	u32 id, cccr;
1052 	int i;
1053 
1054 	if (can_dropped_invalid_skb(dev, skb))
1055 		return NETDEV_TX_OK;
1056 
1057 	netif_stop_queue(dev);
1058 
1059 	if (cf->can_id & CAN_EFF_FLAG) {
1060 		id = cf->can_id & CAN_EFF_MASK;
1061 		id |= TX_BUF_XTD;
1062 	} else {
1063 		id = ((cf->can_id & CAN_SFF_MASK) << 18);
1064 	}
1065 
1066 	if (cf->can_id & CAN_RTR_FLAG)
1067 		id |= TX_BUF_RTR;
1068 
1069 	/* message ram configuration */
1070 	m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
1071 	m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, can_len2dlc(cf->len) << 16);
1072 
1073 	for (i = 0; i < cf->len; i += 4)
1074 		m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(i / 4),
1075 				 *(u32 *)(cf->data + i));
1076 
1077 	can_put_echo_skb(skb, dev, 0);
1078 
1079 	if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1080 		cccr = m_can_read(priv, M_CAN_CCCR);
1081 		cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1082 		if (can_is_canfd_skb(skb)) {
1083 			if (cf->flags & CANFD_BRS)
1084 				cccr |= CCCR_CMR_CANFD_BRS << CCCR_CMR_SHIFT;
1085 			else
1086 				cccr |= CCCR_CMR_CANFD << CCCR_CMR_SHIFT;
1087 		} else {
1088 			cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1089 		}
1090 		m_can_write(priv, M_CAN_CCCR, cccr);
1091 	}
1092 
1093 	/* enable first TX buffer to start transfer  */
1094 	m_can_write(priv, M_CAN_TXBTIE, 0x1);
1095 	m_can_write(priv, M_CAN_TXBAR, 0x1);
1096 
1097 	return NETDEV_TX_OK;
1098 }
1099 
1100 static const struct net_device_ops m_can_netdev_ops = {
1101 	.ndo_open = m_can_open,
1102 	.ndo_stop = m_can_close,
1103 	.ndo_start_xmit = m_can_start_xmit,
1104 	.ndo_change_mtu = can_change_mtu,
1105 };
1106 
1107 static int register_m_can_dev(struct net_device *dev)
1108 {
1109 	dev->flags |= IFF_ECHO;	/* we support local echo */
1110 	dev->netdev_ops = &m_can_netdev_ops;
1111 
1112 	return register_candev(dev);
1113 }
1114 
1115 static int m_can_of_parse_mram(struct platform_device *pdev,
1116 			       struct m_can_priv *priv)
1117 {
1118 	struct device_node *np = pdev->dev.of_node;
1119 	struct resource *res;
1120 	void __iomem *addr;
1121 	u32 out_val[MRAM_CFG_LEN];
1122 	int i, start, end, ret;
1123 
1124 	/* message ram could be shared */
1125 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
1126 	if (!res)
1127 		return -ENODEV;
1128 
1129 	addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1130 	if (!addr)
1131 		return -ENOMEM;
1132 
1133 	/* get message ram configuration */
1134 	ret = of_property_read_u32_array(np, "bosch,mram-cfg",
1135 					 out_val, sizeof(out_val) / 4);
1136 	if (ret) {
1137 		dev_err(&pdev->dev, "can not get message ram configuration\n");
1138 		return -ENODEV;
1139 	}
1140 
1141 	priv->mram_base = addr;
1142 	priv->mcfg[MRAM_SIDF].off = out_val[0];
1143 	priv->mcfg[MRAM_SIDF].num = out_val[1];
1144 	priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
1145 			priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1146 	priv->mcfg[MRAM_XIDF].num = out_val[2];
1147 	priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
1148 			priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1149 	priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
1150 	priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
1151 			priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1152 	priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
1153 	priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
1154 			priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1155 	priv->mcfg[MRAM_RXB].num = out_val[5];
1156 	priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
1157 			priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1158 	priv->mcfg[MRAM_TXE].num = out_val[6];
1159 	priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
1160 			priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1161 	priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
1162 
1163 	dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1164 		priv->mram_base,
1165 		priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
1166 		priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
1167 		priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
1168 		priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
1169 		priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
1170 		priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
1171 		priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
1172 
1173 	/* initialize the entire Message RAM in use to avoid possible
1174 	 * ECC/parity checksum errors when reading an uninitialized buffer
1175 	 */
1176 	start = priv->mcfg[MRAM_SIDF].off;
1177 	end = priv->mcfg[MRAM_TXB].off +
1178 		priv->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1179 	for (i = start; i < end; i += 4)
1180 		writel(0x0, priv->mram_base + i);
1181 
1182 	return 0;
1183 }
1184 
1185 static int m_can_plat_probe(struct platform_device *pdev)
1186 {
1187 	struct net_device *dev;
1188 	struct m_can_priv *priv;
1189 	struct resource *res;
1190 	void __iomem *addr;
1191 	struct clk *hclk, *cclk;
1192 	int irq, ret;
1193 
1194 	hclk = devm_clk_get(&pdev->dev, "hclk");
1195 	cclk = devm_clk_get(&pdev->dev, "cclk");
1196 	if (IS_ERR(hclk) || IS_ERR(cclk)) {
1197 		dev_err(&pdev->dev, "no clock find\n");
1198 		return -ENODEV;
1199 	}
1200 
1201 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
1202 	addr = devm_ioremap_resource(&pdev->dev, res);
1203 	irq = platform_get_irq_byname(pdev, "int0");
1204 	if (IS_ERR(addr) || irq < 0)
1205 		return -EINVAL;
1206 
1207 	/* allocate the m_can device */
1208 	dev = alloc_m_can_dev();
1209 	if (!dev)
1210 		return -ENOMEM;
1211 
1212 	priv = netdev_priv(dev);
1213 	dev->irq = irq;
1214 	priv->base = addr;
1215 	priv->device = &pdev->dev;
1216 	priv->hclk = hclk;
1217 	priv->cclk = cclk;
1218 	priv->can.clock.freq = clk_get_rate(cclk);
1219 
1220 	ret = m_can_of_parse_mram(pdev, priv);
1221 	if (ret)
1222 		goto failed_free_dev;
1223 
1224 	platform_set_drvdata(pdev, dev);
1225 	SET_NETDEV_DEV(dev, &pdev->dev);
1226 
1227 	ret = register_m_can_dev(dev);
1228 	if (ret) {
1229 		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
1230 			KBUILD_MODNAME, ret);
1231 		goto failed_free_dev;
1232 	}
1233 
1234 	devm_can_led_init(dev);
1235 
1236 	dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
1237 		 KBUILD_MODNAME, priv->base, dev->irq);
1238 
1239 	return 0;
1240 
1241 failed_free_dev:
1242 	free_m_can_dev(dev);
1243 	return ret;
1244 }
1245 
1246 static __maybe_unused int m_can_suspend(struct device *dev)
1247 {
1248 	struct net_device *ndev = dev_get_drvdata(dev);
1249 	struct m_can_priv *priv = netdev_priv(ndev);
1250 
1251 	if (netif_running(ndev)) {
1252 		netif_stop_queue(ndev);
1253 		netif_device_detach(ndev);
1254 	}
1255 
1256 	/* TODO: enter low power */
1257 
1258 	priv->can.state = CAN_STATE_SLEEPING;
1259 
1260 	return 0;
1261 }
1262 
1263 static __maybe_unused int m_can_resume(struct device *dev)
1264 {
1265 	struct net_device *ndev = dev_get_drvdata(dev);
1266 	struct m_can_priv *priv = netdev_priv(ndev);
1267 
1268 	/* TODO: exit low power */
1269 
1270 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1271 
1272 	if (netif_running(ndev)) {
1273 		netif_device_attach(ndev);
1274 		netif_start_queue(ndev);
1275 	}
1276 
1277 	return 0;
1278 }
1279 
1280 static void unregister_m_can_dev(struct net_device *dev)
1281 {
1282 	unregister_candev(dev);
1283 }
1284 
1285 static int m_can_plat_remove(struct platform_device *pdev)
1286 {
1287 	struct net_device *dev = platform_get_drvdata(pdev);
1288 
1289 	unregister_m_can_dev(dev);
1290 	platform_set_drvdata(pdev, NULL);
1291 
1292 	free_m_can_dev(dev);
1293 
1294 	return 0;
1295 }
1296 
1297 static const struct dev_pm_ops m_can_pmops = {
1298 	SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
1299 };
1300 
1301 static const struct of_device_id m_can_of_table[] = {
1302 	{ .compatible = "bosch,m_can", .data = NULL },
1303 	{ /* sentinel */ },
1304 };
1305 MODULE_DEVICE_TABLE(of, m_can_of_table);
1306 
1307 static struct platform_driver m_can_plat_driver = {
1308 	.driver = {
1309 		.name = KBUILD_MODNAME,
1310 		.of_match_table = m_can_of_table,
1311 		.pm     = &m_can_pmops,
1312 	},
1313 	.probe = m_can_plat_probe,
1314 	.remove = m_can_plat_remove,
1315 };
1316 
1317 module_platform_driver(m_can_plat_driver);
1318 
1319 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
1320 MODULE_LICENSE("GPL v2");
1321 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
1322