1 // SPDX-License-Identifier: GPL-2.0 2 // CAN bus driver for Bosch M_CAN controller 3 // Copyright (C) 2014 Freescale Semiconductor, Inc. 4 // Dong Aisheng <b29396@freescale.com> 5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/ 6 7 /* Bosch M_CAN user manual can be obtained from: 8 * https://github.com/linux-can/can-doc/tree/master/m_can 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/can/dev.h> 13 #include <linux/ethtool.h> 14 #include <linux/hrtimer.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/phy/phy.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 27 #include "m_can.h" 28 29 /* registers definition */ 30 enum m_can_reg { 31 M_CAN_CREL = 0x0, 32 M_CAN_ENDN = 0x4, 33 M_CAN_CUST = 0x8, 34 M_CAN_DBTP = 0xc, 35 M_CAN_TEST = 0x10, 36 M_CAN_RWD = 0x14, 37 M_CAN_CCCR = 0x18, 38 M_CAN_NBTP = 0x1c, 39 M_CAN_TSCC = 0x20, 40 M_CAN_TSCV = 0x24, 41 M_CAN_TOCC = 0x28, 42 M_CAN_TOCV = 0x2c, 43 M_CAN_ECR = 0x40, 44 M_CAN_PSR = 0x44, 45 /* TDCR Register only available for version >=3.1.x */ 46 M_CAN_TDCR = 0x48, 47 M_CAN_IR = 0x50, 48 M_CAN_IE = 0x54, 49 M_CAN_ILS = 0x58, 50 M_CAN_ILE = 0x5c, 51 M_CAN_GFC = 0x80, 52 M_CAN_SIDFC = 0x84, 53 M_CAN_XIDFC = 0x88, 54 M_CAN_XIDAM = 0x90, 55 M_CAN_HPMS = 0x94, 56 M_CAN_NDAT1 = 0x98, 57 M_CAN_NDAT2 = 0x9c, 58 M_CAN_RXF0C = 0xa0, 59 M_CAN_RXF0S = 0xa4, 60 M_CAN_RXF0A = 0xa8, 61 M_CAN_RXBC = 0xac, 62 M_CAN_RXF1C = 0xb0, 63 M_CAN_RXF1S = 0xb4, 64 M_CAN_RXF1A = 0xb8, 65 M_CAN_RXESC = 0xbc, 66 M_CAN_TXBC = 0xc0, 67 M_CAN_TXFQS = 0xc4, 68 M_CAN_TXESC = 0xc8, 69 M_CAN_TXBRP = 0xcc, 70 M_CAN_TXBAR = 0xd0, 71 M_CAN_TXBCR = 0xd4, 72 M_CAN_TXBTO = 0xd8, 73 M_CAN_TXBCF = 0xdc, 74 M_CAN_TXBTIE = 0xe0, 75 M_CAN_TXBCIE = 0xe4, 76 M_CAN_TXEFC = 0xf0, 77 M_CAN_TXEFS = 0xf4, 78 M_CAN_TXEFA = 0xf8, 79 }; 80 81 /* message ram configuration data length */ 82 #define MRAM_CFG_LEN 8 83 84 /* Core Release Register (CREL) */ 85 #define CREL_REL_MASK GENMASK(31, 28) 86 #define CREL_STEP_MASK GENMASK(27, 24) 87 #define CREL_SUBSTEP_MASK GENMASK(23, 20) 88 89 /* Data Bit Timing & Prescaler Register (DBTP) */ 90 #define DBTP_TDC BIT(23) 91 #define DBTP_DBRP_MASK GENMASK(20, 16) 92 #define DBTP_DTSEG1_MASK GENMASK(12, 8) 93 #define DBTP_DTSEG2_MASK GENMASK(7, 4) 94 #define DBTP_DSJW_MASK GENMASK(3, 0) 95 96 /* Transmitter Delay Compensation Register (TDCR) */ 97 #define TDCR_TDCO_MASK GENMASK(14, 8) 98 #define TDCR_TDCF_MASK GENMASK(6, 0) 99 100 /* Test Register (TEST) */ 101 #define TEST_LBCK BIT(4) 102 103 /* CC Control Register (CCCR) */ 104 #define CCCR_TXP BIT(14) 105 #define CCCR_TEST BIT(7) 106 #define CCCR_DAR BIT(6) 107 #define CCCR_MON BIT(5) 108 #define CCCR_CSR BIT(4) 109 #define CCCR_CSA BIT(3) 110 #define CCCR_ASM BIT(2) 111 #define CCCR_CCE BIT(1) 112 #define CCCR_INIT BIT(0) 113 /* for version 3.0.x */ 114 #define CCCR_CMR_MASK GENMASK(11, 10) 115 #define CCCR_CMR_CANFD 0x1 116 #define CCCR_CMR_CANFD_BRS 0x2 117 #define CCCR_CMR_CAN 0x3 118 #define CCCR_CME_MASK GENMASK(9, 8) 119 #define CCCR_CME_CAN 0 120 #define CCCR_CME_CANFD 0x1 121 #define CCCR_CME_CANFD_BRS 0x2 122 /* for version >=3.1.x */ 123 #define CCCR_EFBI BIT(13) 124 #define CCCR_PXHD BIT(12) 125 #define CCCR_BRSE BIT(9) 126 #define CCCR_FDOE BIT(8) 127 /* for version >=3.2.x */ 128 #define CCCR_NISO BIT(15) 129 /* for version >=3.3.x */ 130 #define CCCR_WMM BIT(11) 131 #define CCCR_UTSU BIT(10) 132 133 /* Nominal Bit Timing & Prescaler Register (NBTP) */ 134 #define NBTP_NSJW_MASK GENMASK(31, 25) 135 #define NBTP_NBRP_MASK GENMASK(24, 16) 136 #define NBTP_NTSEG1_MASK GENMASK(15, 8) 137 #define NBTP_NTSEG2_MASK GENMASK(6, 0) 138 139 /* Timestamp Counter Configuration Register (TSCC) */ 140 #define TSCC_TCP_MASK GENMASK(19, 16) 141 #define TSCC_TSS_MASK GENMASK(1, 0) 142 #define TSCC_TSS_DISABLE 0x0 143 #define TSCC_TSS_INTERNAL 0x1 144 #define TSCC_TSS_EXTERNAL 0x2 145 146 /* Timestamp Counter Value Register (TSCV) */ 147 #define TSCV_TSC_MASK GENMASK(15, 0) 148 149 /* Error Counter Register (ECR) */ 150 #define ECR_RP BIT(15) 151 #define ECR_REC_MASK GENMASK(14, 8) 152 #define ECR_TEC_MASK GENMASK(7, 0) 153 154 /* Protocol Status Register (PSR) */ 155 #define PSR_BO BIT(7) 156 #define PSR_EW BIT(6) 157 #define PSR_EP BIT(5) 158 #define PSR_LEC_MASK GENMASK(2, 0) 159 #define PSR_DLEC_MASK GENMASK(10, 8) 160 161 /* Interrupt Register (IR) */ 162 #define IR_ALL_INT 0xffffffff 163 164 /* Renamed bits for versions > 3.1.x */ 165 #define IR_ARA BIT(29) 166 #define IR_PED BIT(28) 167 #define IR_PEA BIT(27) 168 169 /* Bits for version 3.0.x */ 170 #define IR_STE BIT(31) 171 #define IR_FOE BIT(30) 172 #define IR_ACKE BIT(29) 173 #define IR_BE BIT(28) 174 #define IR_CRCE BIT(27) 175 #define IR_WDI BIT(26) 176 #define IR_BO BIT(25) 177 #define IR_EW BIT(24) 178 #define IR_EP BIT(23) 179 #define IR_ELO BIT(22) 180 #define IR_BEU BIT(21) 181 #define IR_BEC BIT(20) 182 #define IR_DRX BIT(19) 183 #define IR_TOO BIT(18) 184 #define IR_MRAF BIT(17) 185 #define IR_TSW BIT(16) 186 #define IR_TEFL BIT(15) 187 #define IR_TEFF BIT(14) 188 #define IR_TEFW BIT(13) 189 #define IR_TEFN BIT(12) 190 #define IR_TFE BIT(11) 191 #define IR_TCF BIT(10) 192 #define IR_TC BIT(9) 193 #define IR_HPM BIT(8) 194 #define IR_RF1L BIT(7) 195 #define IR_RF1F BIT(6) 196 #define IR_RF1W BIT(5) 197 #define IR_RF1N BIT(4) 198 #define IR_RF0L BIT(3) 199 #define IR_RF0F BIT(2) 200 #define IR_RF0W BIT(1) 201 #define IR_RF0N BIT(0) 202 #define IR_ERR_STATE (IR_BO | IR_EW | IR_EP) 203 204 /* Interrupts for version 3.0.x */ 205 #define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE) 206 #define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \ 207 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 208 IR_RF0L) 209 #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) 210 211 /* Interrupts for version >= 3.1.x */ 212 #define IR_ERR_LEC_31X (IR_PED | IR_PEA) 213 #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \ 214 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \ 215 IR_RF0L) 216 #define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X) 217 218 /* Interrupt Line Select (ILS) */ 219 #define ILS_ALL_INT0 0x0 220 #define ILS_ALL_INT1 0xFFFFFFFF 221 222 /* Interrupt Line Enable (ILE) */ 223 #define ILE_EINT1 BIT(1) 224 #define ILE_EINT0 BIT(0) 225 226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ 227 #define RXFC_FWM_MASK GENMASK(30, 24) 228 #define RXFC_FS_MASK GENMASK(22, 16) 229 230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ 231 #define RXFS_RFL BIT(25) 232 #define RXFS_FF BIT(24) 233 #define RXFS_FPI_MASK GENMASK(21, 16) 234 #define RXFS_FGI_MASK GENMASK(13, 8) 235 #define RXFS_FFL_MASK GENMASK(6, 0) 236 237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ 238 #define RXESC_RBDS_MASK GENMASK(10, 8) 239 #define RXESC_F1DS_MASK GENMASK(6, 4) 240 #define RXESC_F0DS_MASK GENMASK(2, 0) 241 #define RXESC_64B 0x7 242 243 /* Tx Buffer Configuration (TXBC) */ 244 #define TXBC_TFQS_MASK GENMASK(29, 24) 245 #define TXBC_NDTB_MASK GENMASK(21, 16) 246 247 /* Tx FIFO/Queue Status (TXFQS) */ 248 #define TXFQS_TFQF BIT(21) 249 #define TXFQS_TFQPI_MASK GENMASK(20, 16) 250 #define TXFQS_TFGI_MASK GENMASK(12, 8) 251 #define TXFQS_TFFL_MASK GENMASK(5, 0) 252 253 /* Tx Buffer Element Size Configuration (TXESC) */ 254 #define TXESC_TBDS_MASK GENMASK(2, 0) 255 #define TXESC_TBDS_64B 0x7 256 257 /* Tx Event FIFO Configuration (TXEFC) */ 258 #define TXEFC_EFWM_MASK GENMASK(29, 24) 259 #define TXEFC_EFS_MASK GENMASK(21, 16) 260 261 /* Tx Event FIFO Status (TXEFS) */ 262 #define TXEFS_TEFL BIT(25) 263 #define TXEFS_EFF BIT(24) 264 #define TXEFS_EFGI_MASK GENMASK(12, 8) 265 #define TXEFS_EFFL_MASK GENMASK(5, 0) 266 267 /* Tx Event FIFO Acknowledge (TXEFA) */ 268 #define TXEFA_EFAI_MASK GENMASK(4, 0) 269 270 /* Message RAM Configuration (in bytes) */ 271 #define SIDF_ELEMENT_SIZE 4 272 #define XIDF_ELEMENT_SIZE 8 273 #define RXF0_ELEMENT_SIZE 72 274 #define RXF1_ELEMENT_SIZE 72 275 #define RXB_ELEMENT_SIZE 72 276 #define TXE_ELEMENT_SIZE 8 277 #define TXB_ELEMENT_SIZE 72 278 279 /* Message RAM Elements */ 280 #define M_CAN_FIFO_ID 0x0 281 #define M_CAN_FIFO_DLC 0x4 282 #define M_CAN_FIFO_DATA 0x8 283 284 /* Rx Buffer Element */ 285 /* R0 */ 286 #define RX_BUF_ESI BIT(31) 287 #define RX_BUF_XTD BIT(30) 288 #define RX_BUF_RTR BIT(29) 289 /* R1 */ 290 #define RX_BUF_ANMF BIT(31) 291 #define RX_BUF_FDF BIT(21) 292 #define RX_BUF_BRS BIT(20) 293 #define RX_BUF_RXTS_MASK GENMASK(15, 0) 294 295 /* Tx Buffer Element */ 296 /* T0 */ 297 #define TX_BUF_ESI BIT(31) 298 #define TX_BUF_XTD BIT(30) 299 #define TX_BUF_RTR BIT(29) 300 /* T1 */ 301 #define TX_BUF_EFC BIT(23) 302 #define TX_BUF_FDF BIT(21) 303 #define TX_BUF_BRS BIT(20) 304 #define TX_BUF_MM_MASK GENMASK(31, 24) 305 #define TX_BUF_DLC_MASK GENMASK(19, 16) 306 307 /* Tx event FIFO Element */ 308 /* E1 */ 309 #define TX_EVENT_MM_MASK GENMASK(31, 24) 310 #define TX_EVENT_TXTS_MASK GENMASK(15, 0) 311 312 /* Hrtimer polling interval */ 313 #define HRTIMER_POLL_INTERVAL_MS 1 314 315 /* The ID and DLC registers are adjacent in M_CAN FIFO memory, 316 * and we can save a (potentially slow) bus round trip by combining 317 * reads and writes to them. 318 */ 319 struct id_and_dlc { 320 u32 id; 321 u32 dlc; 322 }; 323 324 struct m_can_fifo_element { 325 u32 id; 326 u32 dlc; 327 u8 data[CANFD_MAX_DLEN]; 328 }; 329 330 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) 331 { 332 return cdev->ops->read_reg(cdev, reg); 333 } 334 335 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, 336 u32 val) 337 { 338 cdev->ops->write_reg(cdev, reg, val); 339 } 340 341 static int 342 m_can_fifo_read(struct m_can_classdev *cdev, 343 u32 fgi, unsigned int offset, void *val, size_t val_count) 344 { 345 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + 346 offset; 347 348 if (val_count == 0) 349 return 0; 350 351 return cdev->ops->read_fifo(cdev, addr_offset, val, val_count); 352 } 353 354 static int 355 m_can_fifo_write(struct m_can_classdev *cdev, 356 u32 fpi, unsigned int offset, const void *val, size_t val_count) 357 { 358 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + 359 offset; 360 361 if (val_count == 0) 362 return 0; 363 364 return cdev->ops->write_fifo(cdev, addr_offset, val, val_count); 365 } 366 367 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev, 368 u32 fpi, u32 val) 369 { 370 return cdev->ops->write_fifo(cdev, fpi, &val, 1); 371 } 372 373 static int 374 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val) 375 { 376 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + 377 offset; 378 379 return cdev->ops->read_fifo(cdev, addr_offset, val, 1); 380 } 381 382 static int m_can_cccr_update_bits(struct m_can_classdev *cdev, u32 mask, u32 val) 383 { 384 u32 val_before = m_can_read(cdev, M_CAN_CCCR); 385 u32 val_after = (val_before & ~mask) | val; 386 size_t tries = 10; 387 388 if (!(mask & CCCR_INIT) && !(val_before & CCCR_INIT)) { 389 dev_err(cdev->dev, 390 "refusing to configure device when in normal mode\n"); 391 return -EBUSY; 392 } 393 394 /* The chip should be in standby mode when changing the CCCR register, 395 * and some chips set the CSR and CSA bits when in standby. Furthermore, 396 * the CSR and CSA bits should be written as zeros, even when they read 397 * ones. 398 */ 399 val_after &= ~(CCCR_CSR | CCCR_CSA); 400 401 while (tries--) { 402 u32 val_read; 403 404 /* Write the desired value in each try, as setting some bits in 405 * the CCCR register require other bits to be set first. E.g. 406 * setting the NISO bit requires setting the CCE bit first. 407 */ 408 m_can_write(cdev, M_CAN_CCCR, val_after); 409 410 val_read = m_can_read(cdev, M_CAN_CCCR) & ~(CCCR_CSR | CCCR_CSA); 411 412 if (val_read == val_after) 413 return 0; 414 415 usleep_range(1, 5); 416 } 417 418 return -ETIMEDOUT; 419 } 420 421 static int m_can_config_enable(struct m_can_classdev *cdev) 422 { 423 int err; 424 425 /* CCCR_INIT must be set in order to set CCCR_CCE, but access to 426 * configuration registers should only be enabled when in standby mode, 427 * where CCCR_INIT is always set. 428 */ 429 err = m_can_cccr_update_bits(cdev, CCCR_CCE, CCCR_CCE); 430 if (err) 431 netdev_err(cdev->net, "failed to enable configuration mode\n"); 432 433 return err; 434 } 435 436 static int m_can_config_disable(struct m_can_classdev *cdev) 437 { 438 int err; 439 440 /* Only clear CCCR_CCE, since CCCR_INIT cannot be cleared while in 441 * standby mode 442 */ 443 err = m_can_cccr_update_bits(cdev, CCCR_CCE, 0); 444 if (err) 445 netdev_err(cdev->net, "failed to disable configuration registers\n"); 446 447 return err; 448 } 449 450 static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts) 451 { 452 if (cdev->active_interrupts == interrupts) 453 return; 454 cdev->ops->write_reg(cdev, M_CAN_IE, interrupts); 455 cdev->active_interrupts = interrupts; 456 } 457 458 static void m_can_coalescing_disable(struct m_can_classdev *cdev) 459 { 460 u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN; 461 462 if (!cdev->net->irq) 463 return; 464 465 hrtimer_cancel(&cdev->hrtimer); 466 m_can_interrupt_enable(cdev, new_interrupts); 467 } 468 469 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev) 470 { 471 if (!cdev->net->irq) { 472 dev_dbg(cdev->dev, "Start hrtimer\n"); 473 hrtimer_start(&cdev->hrtimer, 474 ms_to_ktime(HRTIMER_POLL_INTERVAL_MS), 475 HRTIMER_MODE_REL_PINNED); 476 } 477 478 /* Only interrupt line 0 is used in this driver */ 479 m_can_write(cdev, M_CAN_ILE, ILE_EINT0); 480 } 481 482 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev) 483 { 484 m_can_coalescing_disable(cdev); 485 m_can_write(cdev, M_CAN_ILE, 0x0); 486 487 if (!cdev->net->irq) { 488 dev_dbg(cdev->dev, "Stop hrtimer\n"); 489 hrtimer_try_to_cancel(&cdev->hrtimer); 490 } 491 } 492 493 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit 494 * width. 495 */ 496 static u32 m_can_get_timestamp(struct m_can_classdev *cdev) 497 { 498 u32 tscv; 499 u32 tsc; 500 501 tscv = m_can_read(cdev, M_CAN_TSCV); 502 tsc = FIELD_GET(TSCV_TSC_MASK, tscv); 503 504 return (tsc << 16); 505 } 506 507 static void m_can_clean(struct net_device *net) 508 { 509 struct m_can_classdev *cdev = netdev_priv(net); 510 unsigned long irqflags; 511 512 if (cdev->tx_ops) { 513 for (int i = 0; i != cdev->tx_fifo_size; ++i) { 514 if (!cdev->tx_ops[i].skb) 515 continue; 516 517 net->stats.tx_errors++; 518 cdev->tx_ops[i].skb = NULL; 519 } 520 } 521 522 for (int i = 0; i != cdev->can.echo_skb_max; ++i) 523 can_free_echo_skb(cdev->net, i, NULL); 524 525 netdev_reset_queue(cdev->net); 526 527 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); 528 cdev->tx_fifo_in_flight = 0; 529 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); 530 } 531 532 /* For peripherals, pass skb to rx-offload, which will push skb from 533 * napi. For non-peripherals, RX is done in napi already, so push 534 * directly. timestamp is used to ensure good skb ordering in 535 * rx-offload and is ignored for non-peripherals. 536 */ 537 static void m_can_receive_skb(struct m_can_classdev *cdev, 538 struct sk_buff *skb, 539 u32 timestamp) 540 { 541 if (cdev->is_peripheral) { 542 struct net_device_stats *stats = &cdev->net->stats; 543 int err; 544 545 err = can_rx_offload_queue_timestamp(&cdev->offload, skb, 546 timestamp); 547 if (err) 548 stats->rx_fifo_errors++; 549 } else { 550 netif_receive_skb(skb); 551 } 552 } 553 554 static int m_can_read_fifo(struct net_device *dev, u32 fgi) 555 { 556 struct net_device_stats *stats = &dev->stats; 557 struct m_can_classdev *cdev = netdev_priv(dev); 558 struct canfd_frame *cf; 559 struct sk_buff *skb; 560 struct id_and_dlc fifo_header; 561 u32 timestamp = 0; 562 int err; 563 564 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2); 565 if (err) 566 goto out_fail; 567 568 if (fifo_header.dlc & RX_BUF_FDF) 569 skb = alloc_canfd_skb(dev, &cf); 570 else 571 skb = alloc_can_skb(dev, (struct can_frame **)&cf); 572 if (!skb) { 573 stats->rx_dropped++; 574 return 0; 575 } 576 577 if (fifo_header.dlc & RX_BUF_FDF) 578 cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F); 579 else 580 cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F); 581 582 if (fifo_header.id & RX_BUF_XTD) 583 cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG; 584 else 585 cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK; 586 587 if (fifo_header.id & RX_BUF_ESI) { 588 cf->flags |= CANFD_ESI; 589 netdev_dbg(dev, "ESI Error\n"); 590 } 591 592 if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) { 593 cf->can_id |= CAN_RTR_FLAG; 594 } else { 595 if (fifo_header.dlc & RX_BUF_BRS) 596 cf->flags |= CANFD_BRS; 597 598 err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA, 599 cf->data, DIV_ROUND_UP(cf->len, 4)); 600 if (err) 601 goto out_free_skb; 602 603 stats->rx_bytes += cf->len; 604 } 605 stats->rx_packets++; 606 607 timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16; 608 609 m_can_receive_skb(cdev, skb, timestamp); 610 611 return 0; 612 613 out_free_skb: 614 kfree_skb(skb); 615 out_fail: 616 netdev_err(dev, "FIFO read returned %d\n", err); 617 return err; 618 } 619 620 static int m_can_do_rx_poll(struct net_device *dev, int quota) 621 { 622 struct m_can_classdev *cdev = netdev_priv(dev); 623 u32 pkts = 0; 624 u32 rxfs; 625 u32 rx_count; 626 u32 fgi; 627 int ack_fgi = -1; 628 int i; 629 int err = 0; 630 631 rxfs = m_can_read(cdev, M_CAN_RXF0S); 632 if (!(rxfs & RXFS_FFL_MASK)) { 633 netdev_dbg(dev, "no messages in fifo0\n"); 634 return 0; 635 } 636 637 rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs); 638 fgi = FIELD_GET(RXFS_FGI_MASK, rxfs); 639 640 for (i = 0; i < rx_count && quota > 0; ++i) { 641 err = m_can_read_fifo(dev, fgi); 642 if (err) 643 break; 644 645 quota--; 646 pkts++; 647 ack_fgi = fgi; 648 fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi); 649 } 650 651 if (ack_fgi != -1) 652 m_can_write(cdev, M_CAN_RXF0A, ack_fgi); 653 654 if (err) 655 return err; 656 657 return pkts; 658 } 659 660 static int m_can_handle_lost_msg(struct net_device *dev) 661 { 662 struct m_can_classdev *cdev = netdev_priv(dev); 663 struct net_device_stats *stats = &dev->stats; 664 struct sk_buff *skb; 665 struct can_frame *frame; 666 u32 timestamp = 0; 667 668 netdev_err(dev, "msg lost in rxf0\n"); 669 670 stats->rx_errors++; 671 stats->rx_over_errors++; 672 673 skb = alloc_can_err_skb(dev, &frame); 674 if (unlikely(!skb)) 675 return 0; 676 677 frame->can_id |= CAN_ERR_CRTL; 678 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 679 680 if (cdev->is_peripheral) 681 timestamp = m_can_get_timestamp(cdev); 682 683 m_can_receive_skb(cdev, skb, timestamp); 684 685 return 1; 686 } 687 688 static int m_can_handle_lec_err(struct net_device *dev, 689 enum m_can_lec_type lec_type) 690 { 691 struct m_can_classdev *cdev = netdev_priv(dev); 692 struct net_device_stats *stats = &dev->stats; 693 struct can_frame *cf; 694 struct sk_buff *skb; 695 u32 timestamp = 0; 696 697 cdev->can.can_stats.bus_error++; 698 stats->rx_errors++; 699 700 /* propagate the error condition to the CAN stack */ 701 skb = alloc_can_err_skb(dev, &cf); 702 if (unlikely(!skb)) 703 return 0; 704 705 /* check for 'last error code' which tells us the 706 * type of the last error to occur on the CAN bus 707 */ 708 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 709 710 switch (lec_type) { 711 case LEC_STUFF_ERROR: 712 netdev_dbg(dev, "stuff error\n"); 713 cf->data[2] |= CAN_ERR_PROT_STUFF; 714 break; 715 case LEC_FORM_ERROR: 716 netdev_dbg(dev, "form error\n"); 717 cf->data[2] |= CAN_ERR_PROT_FORM; 718 break; 719 case LEC_ACK_ERROR: 720 netdev_dbg(dev, "ack error\n"); 721 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 722 break; 723 case LEC_BIT1_ERROR: 724 netdev_dbg(dev, "bit1 error\n"); 725 cf->data[2] |= CAN_ERR_PROT_BIT1; 726 break; 727 case LEC_BIT0_ERROR: 728 netdev_dbg(dev, "bit0 error\n"); 729 cf->data[2] |= CAN_ERR_PROT_BIT0; 730 break; 731 case LEC_CRC_ERROR: 732 netdev_dbg(dev, "CRC error\n"); 733 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 734 break; 735 default: 736 break; 737 } 738 739 if (cdev->is_peripheral) 740 timestamp = m_can_get_timestamp(cdev); 741 742 m_can_receive_skb(cdev, skb, timestamp); 743 744 return 1; 745 } 746 747 static int __m_can_get_berr_counter(const struct net_device *dev, 748 struct can_berr_counter *bec) 749 { 750 struct m_can_classdev *cdev = netdev_priv(dev); 751 unsigned int ecr; 752 753 ecr = m_can_read(cdev, M_CAN_ECR); 754 bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr); 755 bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr); 756 757 return 0; 758 } 759 760 static int m_can_clk_start(struct m_can_classdev *cdev) 761 { 762 if (cdev->pm_clock_support == 0) 763 return 0; 764 765 return pm_runtime_resume_and_get(cdev->dev); 766 } 767 768 static void m_can_clk_stop(struct m_can_classdev *cdev) 769 { 770 if (cdev->pm_clock_support) 771 pm_runtime_put_sync(cdev->dev); 772 } 773 774 static int m_can_get_berr_counter(const struct net_device *dev, 775 struct can_berr_counter *bec) 776 { 777 struct m_can_classdev *cdev = netdev_priv(dev); 778 int err; 779 780 err = m_can_clk_start(cdev); 781 if (err) 782 return err; 783 784 __m_can_get_berr_counter(dev, bec); 785 786 m_can_clk_stop(cdev); 787 788 return 0; 789 } 790 791 static int m_can_handle_state_change(struct net_device *dev, 792 enum can_state new_state) 793 { 794 struct m_can_classdev *cdev = netdev_priv(dev); 795 struct can_frame *cf; 796 struct sk_buff *skb; 797 struct can_berr_counter bec; 798 unsigned int ecr; 799 u32 timestamp = 0; 800 801 switch (new_state) { 802 case CAN_STATE_ERROR_WARNING: 803 /* error warning state */ 804 cdev->can.can_stats.error_warning++; 805 cdev->can.state = CAN_STATE_ERROR_WARNING; 806 break; 807 case CAN_STATE_ERROR_PASSIVE: 808 /* error passive state */ 809 cdev->can.can_stats.error_passive++; 810 cdev->can.state = CAN_STATE_ERROR_PASSIVE; 811 break; 812 case CAN_STATE_BUS_OFF: 813 /* bus-off state */ 814 cdev->can.state = CAN_STATE_BUS_OFF; 815 m_can_disable_all_interrupts(cdev); 816 cdev->can.can_stats.bus_off++; 817 can_bus_off(dev); 818 break; 819 default: 820 break; 821 } 822 823 /* propagate the error condition to the CAN stack */ 824 skb = alloc_can_err_skb(dev, &cf); 825 if (unlikely(!skb)) 826 return 0; 827 828 __m_can_get_berr_counter(dev, &bec); 829 830 switch (new_state) { 831 case CAN_STATE_ERROR_WARNING: 832 /* error warning state */ 833 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 834 cf->data[1] = (bec.txerr > bec.rxerr) ? 835 CAN_ERR_CRTL_TX_WARNING : 836 CAN_ERR_CRTL_RX_WARNING; 837 cf->data[6] = bec.txerr; 838 cf->data[7] = bec.rxerr; 839 break; 840 case CAN_STATE_ERROR_PASSIVE: 841 /* error passive state */ 842 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT; 843 ecr = m_can_read(cdev, M_CAN_ECR); 844 if (ecr & ECR_RP) 845 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 846 if (bec.txerr > 127) 847 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 848 cf->data[6] = bec.txerr; 849 cf->data[7] = bec.rxerr; 850 break; 851 case CAN_STATE_BUS_OFF: 852 /* bus-off state */ 853 cf->can_id |= CAN_ERR_BUSOFF; 854 break; 855 default: 856 break; 857 } 858 859 if (cdev->is_peripheral) 860 timestamp = m_can_get_timestamp(cdev); 861 862 m_can_receive_skb(cdev, skb, timestamp); 863 864 return 1; 865 } 866 867 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) 868 { 869 struct m_can_classdev *cdev = netdev_priv(dev); 870 int work_done = 0; 871 872 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) { 873 netdev_dbg(dev, "entered error warning state\n"); 874 work_done += m_can_handle_state_change(dev, 875 CAN_STATE_ERROR_WARNING); 876 } 877 878 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) { 879 netdev_dbg(dev, "entered error passive state\n"); 880 work_done += m_can_handle_state_change(dev, 881 CAN_STATE_ERROR_PASSIVE); 882 } 883 884 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) { 885 netdev_dbg(dev, "entered error bus off state\n"); 886 work_done += m_can_handle_state_change(dev, 887 CAN_STATE_BUS_OFF); 888 } 889 890 return work_done; 891 } 892 893 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus) 894 { 895 if (irqstatus & IR_WDI) 896 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n"); 897 if (irqstatus & IR_BEU) 898 netdev_err(dev, "Bit Error Uncorrected\n"); 899 if (irqstatus & IR_BEC) 900 netdev_err(dev, "Bit Error Corrected\n"); 901 if (irqstatus & IR_TOO) 902 netdev_err(dev, "Timeout reached\n"); 903 if (irqstatus & IR_MRAF) 904 netdev_err(dev, "Message RAM access failure occurred\n"); 905 } 906 907 static inline bool is_lec_err(u8 lec) 908 { 909 return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE; 910 } 911 912 static inline bool m_can_is_protocol_err(u32 irqstatus) 913 { 914 return irqstatus & IR_ERR_LEC_31X; 915 } 916 917 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus) 918 { 919 struct net_device_stats *stats = &dev->stats; 920 struct m_can_classdev *cdev = netdev_priv(dev); 921 struct can_frame *cf; 922 struct sk_buff *skb; 923 u32 timestamp = 0; 924 925 /* propagate the error condition to the CAN stack */ 926 skb = alloc_can_err_skb(dev, &cf); 927 928 /* update tx error stats since there is protocol error */ 929 stats->tx_errors++; 930 931 /* update arbitration lost status */ 932 if (cdev->version >= 31 && (irqstatus & IR_PEA)) { 933 netdev_dbg(dev, "Protocol error in Arbitration fail\n"); 934 cdev->can.can_stats.arbitration_lost++; 935 if (skb) { 936 cf->can_id |= CAN_ERR_LOSTARB; 937 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC; 938 } 939 } 940 941 if (unlikely(!skb)) { 942 netdev_dbg(dev, "allocation of skb failed\n"); 943 return 0; 944 } 945 946 if (cdev->is_peripheral) 947 timestamp = m_can_get_timestamp(cdev); 948 949 m_can_receive_skb(cdev, skb, timestamp); 950 951 return 1; 952 } 953 954 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, 955 u32 psr) 956 { 957 struct m_can_classdev *cdev = netdev_priv(dev); 958 int work_done = 0; 959 960 if (irqstatus & IR_RF0L) 961 work_done += m_can_handle_lost_msg(dev); 962 963 /* handle lec errors on the bus */ 964 if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 965 u8 lec = FIELD_GET(PSR_LEC_MASK, psr); 966 u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr); 967 968 if (is_lec_err(lec)) { 969 netdev_dbg(dev, "Arbitration phase error detected\n"); 970 work_done += m_can_handle_lec_err(dev, lec); 971 } 972 973 if (is_lec_err(dlec)) { 974 netdev_dbg(dev, "Data phase error detected\n"); 975 work_done += m_can_handle_lec_err(dev, dlec); 976 } 977 } 978 979 /* handle protocol errors in arbitration phase */ 980 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 981 m_can_is_protocol_err(irqstatus)) 982 work_done += m_can_handle_protocol_error(dev, irqstatus); 983 984 /* other unproccessed error interrupts */ 985 m_can_handle_other_err(dev, irqstatus); 986 987 return work_done; 988 } 989 990 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus) 991 { 992 struct m_can_classdev *cdev = netdev_priv(dev); 993 int rx_work_or_err; 994 int work_done = 0; 995 996 if (!irqstatus) 997 goto end; 998 999 /* Errata workaround for issue "Needless activation of MRAF irq" 1000 * During frame reception while the MCAN is in Error Passive state 1001 * and the Receive Error Counter has the value MCAN_ECR.REC = 127, 1002 * it may happen that MCAN_IR.MRAF is set although there was no 1003 * Message RAM access failure. 1004 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated 1005 * The Message RAM Access Failure interrupt routine needs to check 1006 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. 1007 * In this case, reset MCAN_IR.MRAF. No further action is required. 1008 */ 1009 if (cdev->version <= 31 && irqstatus & IR_MRAF && 1010 m_can_read(cdev, M_CAN_ECR) & ECR_RP) { 1011 struct can_berr_counter bec; 1012 1013 __m_can_get_berr_counter(dev, &bec); 1014 if (bec.rxerr == 127) { 1015 m_can_write(cdev, M_CAN_IR, IR_MRAF); 1016 irqstatus &= ~IR_MRAF; 1017 } 1018 } 1019 1020 if (irqstatus & IR_ERR_STATE) 1021 work_done += m_can_handle_state_errors(dev, 1022 m_can_read(cdev, M_CAN_PSR)); 1023 1024 if (irqstatus & IR_ERR_BUS_30X) 1025 work_done += m_can_handle_bus_errors(dev, irqstatus, 1026 m_can_read(cdev, M_CAN_PSR)); 1027 1028 if (irqstatus & IR_RF0N) { 1029 rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done)); 1030 if (rx_work_or_err < 0) 1031 return rx_work_or_err; 1032 1033 work_done += rx_work_or_err; 1034 } 1035 end: 1036 return work_done; 1037 } 1038 1039 static int m_can_poll(struct napi_struct *napi, int quota) 1040 { 1041 struct net_device *dev = napi->dev; 1042 struct m_can_classdev *cdev = netdev_priv(dev); 1043 int work_done; 1044 u32 irqstatus; 1045 1046 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR); 1047 1048 work_done = m_can_rx_handler(dev, quota, irqstatus); 1049 1050 /* Don't re-enable interrupts if the driver had a fatal error 1051 * (e.g., FIFO read failure). 1052 */ 1053 if (work_done >= 0 && work_done < quota) { 1054 napi_complete_done(napi, work_done); 1055 m_can_enable_all_interrupts(cdev); 1056 } 1057 1058 return work_done; 1059 } 1060 1061 /* Echo tx skb and update net stats. Peripherals use rx-offload for 1062 * echo. timestamp is used for peripherals to ensure correct ordering 1063 * by rx-offload, and is ignored for non-peripherals. 1064 */ 1065 static unsigned int m_can_tx_update_stats(struct m_can_classdev *cdev, 1066 unsigned int msg_mark, u32 timestamp) 1067 { 1068 struct net_device *dev = cdev->net; 1069 struct net_device_stats *stats = &dev->stats; 1070 unsigned int frame_len; 1071 1072 if (cdev->is_peripheral) 1073 stats->tx_bytes += 1074 can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload, 1075 msg_mark, 1076 timestamp, 1077 &frame_len); 1078 else 1079 stats->tx_bytes += can_get_echo_skb(dev, msg_mark, &frame_len); 1080 1081 stats->tx_packets++; 1082 1083 return frame_len; 1084 } 1085 1086 static void m_can_finish_tx(struct m_can_classdev *cdev, int transmitted, 1087 unsigned int transmitted_frame_len) 1088 { 1089 unsigned long irqflags; 1090 1091 netdev_completed_queue(cdev->net, transmitted, transmitted_frame_len); 1092 1093 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); 1094 if (cdev->tx_fifo_in_flight >= cdev->tx_fifo_size && transmitted > 0) 1095 netif_wake_queue(cdev->net); 1096 cdev->tx_fifo_in_flight -= transmitted; 1097 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); 1098 } 1099 1100 static netdev_tx_t m_can_start_tx(struct m_can_classdev *cdev) 1101 { 1102 unsigned long irqflags; 1103 int tx_fifo_in_flight; 1104 1105 spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags); 1106 tx_fifo_in_flight = cdev->tx_fifo_in_flight + 1; 1107 if (tx_fifo_in_flight >= cdev->tx_fifo_size) { 1108 netif_stop_queue(cdev->net); 1109 if (tx_fifo_in_flight > cdev->tx_fifo_size) { 1110 netdev_err_once(cdev->net, "hard_xmit called while TX FIFO full\n"); 1111 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); 1112 return NETDEV_TX_BUSY; 1113 } 1114 } 1115 cdev->tx_fifo_in_flight = tx_fifo_in_flight; 1116 spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags); 1117 1118 return NETDEV_TX_OK; 1119 } 1120 1121 static int m_can_echo_tx_event(struct net_device *dev) 1122 { 1123 u32 txe_count = 0; 1124 u32 m_can_txefs; 1125 u32 fgi = 0; 1126 int ack_fgi = -1; 1127 int i = 0; 1128 int err = 0; 1129 unsigned int msg_mark; 1130 int processed = 0; 1131 unsigned int processed_frame_len = 0; 1132 1133 struct m_can_classdev *cdev = netdev_priv(dev); 1134 1135 /* read tx event fifo status */ 1136 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); 1137 1138 /* Get Tx Event fifo element count */ 1139 txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs); 1140 fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs); 1141 1142 /* Get and process all sent elements */ 1143 for (i = 0; i < txe_count; i++) { 1144 u32 txe, timestamp = 0; 1145 1146 /* get message marker, timestamp */ 1147 err = m_can_txe_fifo_read(cdev, fgi, 4, &txe); 1148 if (err) { 1149 netdev_err(dev, "TXE FIFO read returned %d\n", err); 1150 break; 1151 } 1152 1153 msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe); 1154 timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16; 1155 1156 ack_fgi = fgi; 1157 fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi); 1158 1159 /* update stats */ 1160 processed_frame_len += m_can_tx_update_stats(cdev, msg_mark, 1161 timestamp); 1162 1163 ++processed; 1164 } 1165 1166 if (ack_fgi != -1) 1167 m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, 1168 ack_fgi)); 1169 1170 m_can_finish_tx(cdev, processed, processed_frame_len); 1171 1172 return err; 1173 } 1174 1175 static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir) 1176 { 1177 u32 new_interrupts = cdev->active_interrupts; 1178 bool enable_rx_timer = false; 1179 bool enable_tx_timer = false; 1180 1181 if (!cdev->net->irq) 1182 return; 1183 1184 if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) { 1185 enable_rx_timer = true; 1186 new_interrupts &= ~IR_RF0N; 1187 } 1188 if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) { 1189 enable_tx_timer = true; 1190 new_interrupts &= ~IR_TEFN; 1191 } 1192 if (!enable_rx_timer && !hrtimer_active(&cdev->hrtimer)) 1193 new_interrupts |= IR_RF0N; 1194 if (!enable_tx_timer && !hrtimer_active(&cdev->hrtimer)) 1195 new_interrupts |= IR_TEFN; 1196 1197 m_can_interrupt_enable(cdev, new_interrupts); 1198 if (enable_rx_timer | enable_tx_timer) 1199 hrtimer_start(&cdev->hrtimer, cdev->irq_timer_wait, 1200 HRTIMER_MODE_REL); 1201 } 1202 1203 /* This interrupt handler is called either from the interrupt thread or a 1204 * hrtimer. This has implications like cancelling a timer won't be possible 1205 * blocking. 1206 */ 1207 static int m_can_interrupt_handler(struct m_can_classdev *cdev) 1208 { 1209 struct net_device *dev = cdev->net; 1210 u32 ir; 1211 int ret; 1212 1213 if (pm_runtime_suspended(cdev->dev)) 1214 return IRQ_NONE; 1215 1216 ir = m_can_read(cdev, M_CAN_IR); 1217 m_can_coalescing_update(cdev, ir); 1218 if (!ir) 1219 return IRQ_NONE; 1220 1221 /* ACK all irqs */ 1222 m_can_write(cdev, M_CAN_IR, ir); 1223 1224 if (cdev->ops->clear_interrupts) 1225 cdev->ops->clear_interrupts(cdev); 1226 1227 /* schedule NAPI in case of 1228 * - rx IRQ 1229 * - state change IRQ 1230 * - bus error IRQ and bus error reporting 1231 */ 1232 if (ir & (IR_RF0N | IR_RF0W | IR_ERR_ALL_30X)) { 1233 cdev->irqstatus = ir; 1234 if (!cdev->is_peripheral) { 1235 m_can_disable_all_interrupts(cdev); 1236 napi_schedule(&cdev->napi); 1237 } else { 1238 ret = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, ir); 1239 if (ret < 0) 1240 return ret; 1241 } 1242 } 1243 1244 if (cdev->version == 30) { 1245 if (ir & IR_TC) { 1246 /* Transmission Complete Interrupt*/ 1247 u32 timestamp = 0; 1248 unsigned int frame_len; 1249 1250 if (cdev->is_peripheral) 1251 timestamp = m_can_get_timestamp(cdev); 1252 frame_len = m_can_tx_update_stats(cdev, 0, timestamp); 1253 m_can_finish_tx(cdev, 1, frame_len); 1254 } 1255 } else { 1256 if (ir & (IR_TEFN | IR_TEFW)) { 1257 /* New TX FIFO Element arrived */ 1258 ret = m_can_echo_tx_event(dev); 1259 if (ret != 0) 1260 return ret; 1261 } 1262 } 1263 1264 if (cdev->is_peripheral) 1265 can_rx_offload_threaded_irq_finish(&cdev->offload); 1266 1267 return IRQ_HANDLED; 1268 } 1269 1270 static irqreturn_t m_can_isr(int irq, void *dev_id) 1271 { 1272 struct net_device *dev = (struct net_device *)dev_id; 1273 struct m_can_classdev *cdev = netdev_priv(dev); 1274 int ret; 1275 1276 ret = m_can_interrupt_handler(cdev); 1277 if (ret < 0) { 1278 m_can_disable_all_interrupts(cdev); 1279 return IRQ_HANDLED; 1280 } 1281 1282 return ret; 1283 } 1284 1285 static enum hrtimer_restart m_can_coalescing_timer(struct hrtimer *timer) 1286 { 1287 struct m_can_classdev *cdev = container_of(timer, struct m_can_classdev, hrtimer); 1288 1289 if (cdev->can.state == CAN_STATE_BUS_OFF || 1290 cdev->can.state == CAN_STATE_STOPPED) 1291 return HRTIMER_NORESTART; 1292 1293 irq_wake_thread(cdev->net->irq, cdev->net); 1294 1295 return HRTIMER_NORESTART; 1296 } 1297 1298 static const struct can_bittiming_const m_can_bittiming_const_30X = { 1299 .name = KBUILD_MODNAME, 1300 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1301 .tseg1_max = 64, 1302 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1303 .tseg2_max = 16, 1304 .sjw_max = 16, 1305 .brp_min = 1, 1306 .brp_max = 1024, 1307 .brp_inc = 1, 1308 }; 1309 1310 static const struct can_bittiming_const m_can_data_bittiming_const_30X = { 1311 .name = KBUILD_MODNAME, 1312 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1313 .tseg1_max = 16, 1314 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1315 .tseg2_max = 8, 1316 .sjw_max = 4, 1317 .brp_min = 1, 1318 .brp_max = 32, 1319 .brp_inc = 1, 1320 }; 1321 1322 static const struct can_bittiming_const m_can_bittiming_const_31X = { 1323 .name = KBUILD_MODNAME, 1324 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 1325 .tseg1_max = 256, 1326 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */ 1327 .tseg2_max = 128, 1328 .sjw_max = 128, 1329 .brp_min = 1, 1330 .brp_max = 512, 1331 .brp_inc = 1, 1332 }; 1333 1334 static const struct can_bittiming_const m_can_data_bittiming_const_31X = { 1335 .name = KBUILD_MODNAME, 1336 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */ 1337 .tseg1_max = 32, 1338 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 1339 .tseg2_max = 16, 1340 .sjw_max = 16, 1341 .brp_min = 1, 1342 .brp_max = 32, 1343 .brp_inc = 1, 1344 }; 1345 1346 static int m_can_set_bittiming(struct net_device *dev) 1347 { 1348 struct m_can_classdev *cdev = netdev_priv(dev); 1349 const struct can_bittiming *bt = &cdev->can.bittiming; 1350 const struct can_bittiming *dbt = &cdev->can.data_bittiming; 1351 u16 brp, sjw, tseg1, tseg2; 1352 u32 reg_btp; 1353 1354 brp = bt->brp - 1; 1355 sjw = bt->sjw - 1; 1356 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 1357 tseg2 = bt->phase_seg2 - 1; 1358 reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) | 1359 FIELD_PREP(NBTP_NSJW_MASK, sjw) | 1360 FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) | 1361 FIELD_PREP(NBTP_NTSEG2_MASK, tseg2); 1362 m_can_write(cdev, M_CAN_NBTP, reg_btp); 1363 1364 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1365 reg_btp = 0; 1366 brp = dbt->brp - 1; 1367 sjw = dbt->sjw - 1; 1368 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1; 1369 tseg2 = dbt->phase_seg2 - 1; 1370 1371 /* TDC is only needed for bitrates beyond 2.5 MBit/s. 1372 * This is mentioned in the "Bit Time Requirements for CAN FD" 1373 * paper presented at the International CAN Conference 2013 1374 */ 1375 if (dbt->bitrate > 2500000) { 1376 u32 tdco, ssp; 1377 1378 /* Use the same value of secondary sampling point 1379 * as the data sampling point 1380 */ 1381 ssp = dbt->sample_point; 1382 1383 /* Equation based on Bosch's M_CAN User Manual's 1384 * Transmitter Delay Compensation Section 1385 */ 1386 tdco = (cdev->can.clock.freq / 1000) * 1387 ssp / dbt->bitrate; 1388 1389 /* Max valid TDCO value is 127 */ 1390 if (tdco > 127) { 1391 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n", 1392 tdco); 1393 tdco = 127; 1394 } 1395 1396 reg_btp |= DBTP_TDC; 1397 m_can_write(cdev, M_CAN_TDCR, 1398 FIELD_PREP(TDCR_TDCO_MASK, tdco)); 1399 } 1400 1401 reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) | 1402 FIELD_PREP(DBTP_DSJW_MASK, sjw) | 1403 FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) | 1404 FIELD_PREP(DBTP_DTSEG2_MASK, tseg2); 1405 1406 m_can_write(cdev, M_CAN_DBTP, reg_btp); 1407 } 1408 1409 return 0; 1410 } 1411 1412 /* Configure M_CAN chip: 1413 * - set rx buffer/fifo element size 1414 * - configure rx fifo 1415 * - accept non-matching frame into fifo 0 1416 * - configure tx buffer 1417 * - >= v3.1.x: TX FIFO is used 1418 * - configure mode 1419 * - setup bittiming 1420 * - configure timestamp generation 1421 */ 1422 static int m_can_chip_config(struct net_device *dev) 1423 { 1424 struct m_can_classdev *cdev = netdev_priv(dev); 1425 u32 interrupts = IR_ALL_INT; 1426 u32 cccr, test; 1427 int err; 1428 1429 err = m_can_init_ram(cdev); 1430 if (err) { 1431 dev_err(cdev->dev, "Message RAM configuration failed\n"); 1432 return err; 1433 } 1434 1435 /* Disable unused interrupts */ 1436 interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TFE | IR_TCF | 1437 IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | IR_RF0F | 1438 IR_TSW); 1439 1440 err = m_can_config_enable(cdev); 1441 if (err) 1442 return err; 1443 1444 /* RX Buffer/FIFO Element Size 64 bytes data field */ 1445 m_can_write(cdev, M_CAN_RXESC, 1446 FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) | 1447 FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) | 1448 FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B)); 1449 1450 /* Accept Non-matching Frames Into FIFO 0 */ 1451 m_can_write(cdev, M_CAN_GFC, 0x0); 1452 1453 if (cdev->version == 30) { 1454 /* only support one Tx Buffer currently */ 1455 m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | 1456 cdev->mcfg[MRAM_TXB].off); 1457 } else { 1458 /* TX FIFO is used for newer IP Core versions */ 1459 m_can_write(cdev, M_CAN_TXBC, 1460 FIELD_PREP(TXBC_TFQS_MASK, 1461 cdev->mcfg[MRAM_TXB].num) | 1462 cdev->mcfg[MRAM_TXB].off); 1463 } 1464 1465 /* support 64 bytes payload */ 1466 m_can_write(cdev, M_CAN_TXESC, 1467 FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B)); 1468 1469 /* TX Event FIFO */ 1470 if (cdev->version == 30) { 1471 m_can_write(cdev, M_CAN_TXEFC, 1472 FIELD_PREP(TXEFC_EFS_MASK, 1) | 1473 cdev->mcfg[MRAM_TXE].off); 1474 } else { 1475 /* Full TX Event FIFO is used */ 1476 m_can_write(cdev, M_CAN_TXEFC, 1477 FIELD_PREP(TXEFC_EFWM_MASK, 1478 cdev->tx_max_coalesced_frames_irq) | 1479 FIELD_PREP(TXEFC_EFS_MASK, 1480 cdev->mcfg[MRAM_TXE].num) | 1481 cdev->mcfg[MRAM_TXE].off); 1482 } 1483 1484 /* rx fifo configuration, blocking mode, fifo size 1 */ 1485 m_can_write(cdev, M_CAN_RXF0C, 1486 FIELD_PREP(RXFC_FWM_MASK, cdev->rx_max_coalesced_frames_irq) | 1487 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | 1488 cdev->mcfg[MRAM_RXF0].off); 1489 1490 m_can_write(cdev, M_CAN_RXF1C, 1491 FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | 1492 cdev->mcfg[MRAM_RXF1].off); 1493 1494 cccr = m_can_read(cdev, M_CAN_CCCR); 1495 test = m_can_read(cdev, M_CAN_TEST); 1496 test &= ~TEST_LBCK; 1497 if (cdev->version == 30) { 1498 /* Version 3.0.x */ 1499 1500 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | 1501 FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) | 1502 FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK))); 1503 1504 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1505 cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS); 1506 1507 } else { 1508 /* Version 3.1.x or 3.2.x */ 1509 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | 1510 CCCR_NISO | CCCR_DAR); 1511 1512 /* Only 3.2.x has NISO Bit implemented */ 1513 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO) 1514 cccr |= CCCR_NISO; 1515 1516 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) 1517 cccr |= (CCCR_BRSE | CCCR_FDOE); 1518 } 1519 1520 /* Loopback Mode */ 1521 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1522 cccr |= CCCR_TEST | CCCR_MON; 1523 test |= TEST_LBCK; 1524 } 1525 1526 /* Enable Monitoring (all versions) */ 1527 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1528 cccr |= CCCR_MON; 1529 1530 /* Disable Auto Retransmission (all versions) */ 1531 if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 1532 cccr |= CCCR_DAR; 1533 1534 /* Write config */ 1535 m_can_write(cdev, M_CAN_CCCR, cccr); 1536 m_can_write(cdev, M_CAN_TEST, test); 1537 1538 /* Enable interrupts */ 1539 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1540 if (cdev->version == 30) 1541 interrupts &= ~(IR_ERR_LEC_30X); 1542 else 1543 interrupts &= ~(IR_ERR_LEC_31X); 1544 } 1545 cdev->active_interrupts = 0; 1546 m_can_interrupt_enable(cdev, interrupts); 1547 1548 /* route all interrupts to INT0 */ 1549 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0); 1550 1551 /* set bittiming params */ 1552 m_can_set_bittiming(dev); 1553 1554 /* enable internal timestamp generation, with a prescaler of 16. The 1555 * prescaler is applied to the nominal bit timing 1556 */ 1557 m_can_write(cdev, M_CAN_TSCC, 1558 FIELD_PREP(TSCC_TCP_MASK, 0xf) | 1559 FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL)); 1560 1561 err = m_can_config_disable(cdev); 1562 if (err) 1563 return err; 1564 1565 if (cdev->ops->init) 1566 cdev->ops->init(cdev); 1567 1568 return 0; 1569 } 1570 1571 static int m_can_start(struct net_device *dev) 1572 { 1573 struct m_can_classdev *cdev = netdev_priv(dev); 1574 int ret; 1575 1576 /* basic m_can configuration */ 1577 ret = m_can_chip_config(dev); 1578 if (ret) 1579 return ret; 1580 1581 netdev_queue_set_dql_min_limit(netdev_get_tx_queue(cdev->net, 0), 1582 cdev->tx_max_coalesced_frames); 1583 1584 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 1585 1586 m_can_enable_all_interrupts(cdev); 1587 1588 if (cdev->version > 30) 1589 cdev->tx_fifo_putidx = FIELD_GET(TXFQS_TFQPI_MASK, 1590 m_can_read(cdev, M_CAN_TXFQS)); 1591 1592 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, 0); 1593 if (ret) 1594 netdev_err(dev, "failed to enter normal mode\n"); 1595 1596 return ret; 1597 } 1598 1599 static int m_can_set_mode(struct net_device *dev, enum can_mode mode) 1600 { 1601 switch (mode) { 1602 case CAN_MODE_START: 1603 m_can_clean(dev); 1604 m_can_start(dev); 1605 netif_wake_queue(dev); 1606 break; 1607 default: 1608 return -EOPNOTSUPP; 1609 } 1610 1611 return 0; 1612 } 1613 1614 /* Checks core release number of M_CAN 1615 * returns 0 if an unsupported device is detected 1616 * else it returns the release and step coded as: 1617 * return value = 10 * <release> + 1 * <step> 1618 */ 1619 static int m_can_check_core_release(struct m_can_classdev *cdev) 1620 { 1621 u32 crel_reg; 1622 u8 rel; 1623 u8 step; 1624 int res; 1625 1626 /* Read Core Release Version and split into version number 1627 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; 1628 */ 1629 crel_reg = m_can_read(cdev, M_CAN_CREL); 1630 rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg); 1631 step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg); 1632 1633 if (rel == 3) { 1634 /* M_CAN v3.x.y: create return value */ 1635 res = 30 + step; 1636 } else { 1637 /* Unsupported M_CAN version */ 1638 res = 0; 1639 } 1640 1641 return res; 1642 } 1643 1644 /* Selectable Non ISO support only in version 3.2.x 1645 * Return 1 if the bit is writable, 0 if it is not, or negative on error. 1646 */ 1647 static int m_can_niso_supported(struct m_can_classdev *cdev) 1648 { 1649 int ret, niso; 1650 1651 ret = m_can_config_enable(cdev); 1652 if (ret) 1653 return ret; 1654 1655 /* First try to set the NISO bit. */ 1656 niso = m_can_cccr_update_bits(cdev, CCCR_NISO, CCCR_NISO); 1657 1658 /* Then clear the it again. */ 1659 ret = m_can_cccr_update_bits(cdev, CCCR_NISO, 0); 1660 if (ret) { 1661 dev_err(cdev->dev, "failed to revert the NON-ISO bit in CCCR\n"); 1662 return ret; 1663 } 1664 1665 ret = m_can_config_disable(cdev); 1666 if (ret) 1667 return ret; 1668 1669 return niso == 0; 1670 } 1671 1672 static int m_can_dev_setup(struct m_can_classdev *cdev) 1673 { 1674 struct net_device *dev = cdev->net; 1675 int m_can_version, err, niso; 1676 1677 m_can_version = m_can_check_core_release(cdev); 1678 /* return if unsupported version */ 1679 if (!m_can_version) { 1680 dev_err(cdev->dev, "Unsupported version number: %2d", 1681 m_can_version); 1682 return -EINVAL; 1683 } 1684 1685 if (!cdev->is_peripheral) 1686 netif_napi_add(dev, &cdev->napi, m_can_poll); 1687 1688 /* Shared properties of all M_CAN versions */ 1689 cdev->version = m_can_version; 1690 cdev->can.do_set_mode = m_can_set_mode; 1691 cdev->can.do_get_berr_counter = m_can_get_berr_counter; 1692 1693 /* Set M_CAN supported operations */ 1694 cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1695 CAN_CTRLMODE_LISTENONLY | 1696 CAN_CTRLMODE_BERR_REPORTING | 1697 CAN_CTRLMODE_FD | 1698 CAN_CTRLMODE_ONE_SHOT; 1699 1700 /* Set properties depending on M_CAN version */ 1701 switch (cdev->version) { 1702 case 30: 1703 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */ 1704 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1705 if (err) 1706 return err; 1707 cdev->can.bittiming_const = &m_can_bittiming_const_30X; 1708 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X; 1709 break; 1710 case 31: 1711 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ 1712 err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO); 1713 if (err) 1714 return err; 1715 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1716 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1717 break; 1718 case 32: 1719 case 33: 1720 /* Support both MCAN version v3.2.x and v3.3.0 */ 1721 cdev->can.bittiming_const = &m_can_bittiming_const_31X; 1722 cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X; 1723 1724 niso = m_can_niso_supported(cdev); 1725 if (niso < 0) 1726 return niso; 1727 if (niso) 1728 cdev->can.ctrlmode_supported |= CAN_CTRLMODE_FD_NON_ISO; 1729 break; 1730 default: 1731 dev_err(cdev->dev, "Unsupported version number: %2d", 1732 cdev->version); 1733 return -EINVAL; 1734 } 1735 1736 /* Forcing standby mode should be redundant, as the chip should be in 1737 * standby after a reset. Write the INIT bit anyways, should the chip 1738 * be configured by previous stage. 1739 */ 1740 return m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT); 1741 } 1742 1743 static void m_can_stop(struct net_device *dev) 1744 { 1745 struct m_can_classdev *cdev = netdev_priv(dev); 1746 int ret; 1747 1748 /* disable all interrupts */ 1749 m_can_disable_all_interrupts(cdev); 1750 1751 /* Set init mode to disengage from the network */ 1752 ret = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT); 1753 if (ret) 1754 netdev_err(dev, "failed to enter standby mode: %pe\n", 1755 ERR_PTR(ret)); 1756 1757 /* set the state as STOPPED */ 1758 cdev->can.state = CAN_STATE_STOPPED; 1759 } 1760 1761 static int m_can_close(struct net_device *dev) 1762 { 1763 struct m_can_classdev *cdev = netdev_priv(dev); 1764 1765 netif_stop_queue(dev); 1766 1767 m_can_stop(dev); 1768 free_irq(dev->irq, dev); 1769 1770 m_can_clean(dev); 1771 1772 if (cdev->is_peripheral) { 1773 destroy_workqueue(cdev->tx_wq); 1774 cdev->tx_wq = NULL; 1775 can_rx_offload_disable(&cdev->offload); 1776 } else { 1777 napi_disable(&cdev->napi); 1778 } 1779 1780 close_candev(dev); 1781 1782 m_can_clk_stop(cdev); 1783 phy_power_off(cdev->transceiver); 1784 1785 return 0; 1786 } 1787 1788 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev, 1789 struct sk_buff *skb) 1790 { 1791 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 1792 u8 len_padded = DIV_ROUND_UP(cf->len, 4); 1793 struct m_can_fifo_element fifo_element; 1794 struct net_device *dev = cdev->net; 1795 u32 cccr, fdflags; 1796 int err; 1797 u32 putidx; 1798 unsigned int frame_len = can_skb_get_frame_len(skb); 1799 1800 /* Generate ID field for TX buffer Element */ 1801 /* Common to all supported M_CAN versions */ 1802 if (cf->can_id & CAN_EFF_FLAG) { 1803 fifo_element.id = cf->can_id & CAN_EFF_MASK; 1804 fifo_element.id |= TX_BUF_XTD; 1805 } else { 1806 fifo_element.id = ((cf->can_id & CAN_SFF_MASK) << 18); 1807 } 1808 1809 if (cf->can_id & CAN_RTR_FLAG) 1810 fifo_element.id |= TX_BUF_RTR; 1811 1812 if (cdev->version == 30) { 1813 netif_stop_queue(dev); 1814 1815 fifo_element.dlc = can_fd_len2dlc(cf->len) << 16; 1816 1817 /* Write the frame ID, DLC, and payload to the FIFO element. */ 1818 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_element, 2); 1819 if (err) 1820 goto out_fail; 1821 1822 err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA, 1823 cf->data, len_padded); 1824 if (err) 1825 goto out_fail; 1826 1827 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { 1828 cccr = m_can_read(cdev, M_CAN_CCCR); 1829 cccr &= ~CCCR_CMR_MASK; 1830 if (can_is_canfd_skb(skb)) { 1831 if (cf->flags & CANFD_BRS) 1832 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1833 CCCR_CMR_CANFD_BRS); 1834 else 1835 cccr |= FIELD_PREP(CCCR_CMR_MASK, 1836 CCCR_CMR_CANFD); 1837 } else { 1838 cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN); 1839 } 1840 m_can_write(cdev, M_CAN_CCCR, cccr); 1841 } 1842 m_can_write(cdev, M_CAN_TXBTIE, 0x1); 1843 1844 can_put_echo_skb(skb, dev, 0, frame_len); 1845 1846 m_can_write(cdev, M_CAN_TXBAR, 0x1); 1847 /* End of xmit function for version 3.0.x */ 1848 } else { 1849 /* Transmit routine for version >= v3.1.x */ 1850 1851 /* get put index for frame */ 1852 putidx = cdev->tx_fifo_putidx; 1853 1854 /* Construct DLC Field, with CAN-FD configuration. 1855 * Use the put index of the fifo as the message marker, 1856 * used in the TX interrupt for sending the correct echo frame. 1857 */ 1858 1859 /* get CAN FD configuration of frame */ 1860 fdflags = 0; 1861 if (can_is_canfd_skb(skb)) { 1862 fdflags |= TX_BUF_FDF; 1863 if (cf->flags & CANFD_BRS) 1864 fdflags |= TX_BUF_BRS; 1865 } 1866 1867 fifo_element.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) | 1868 FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) | 1869 fdflags | TX_BUF_EFC; 1870 1871 memcpy_and_pad(fifo_element.data, CANFD_MAX_DLEN, &cf->data, 1872 cf->len, 0); 1873 1874 err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, 1875 &fifo_element, 2 + len_padded); 1876 if (err) 1877 goto out_fail; 1878 1879 /* Push loopback echo. 1880 * Will be looped back on TX interrupt based on message marker 1881 */ 1882 can_put_echo_skb(skb, dev, putidx, frame_len); 1883 1884 if (cdev->is_peripheral) { 1885 /* Delay enabling TX FIFO element */ 1886 cdev->tx_peripheral_submit |= BIT(putidx); 1887 } else { 1888 /* Enable TX FIFO element to start transfer */ 1889 m_can_write(cdev, M_CAN_TXBAR, BIT(putidx)); 1890 } 1891 cdev->tx_fifo_putidx = (++cdev->tx_fifo_putidx >= cdev->can.echo_skb_max ? 1892 0 : cdev->tx_fifo_putidx); 1893 } 1894 1895 return NETDEV_TX_OK; 1896 1897 out_fail: 1898 netdev_err(dev, "FIFO write returned %d\n", err); 1899 m_can_disable_all_interrupts(cdev); 1900 return NETDEV_TX_BUSY; 1901 } 1902 1903 static void m_can_tx_submit(struct m_can_classdev *cdev) 1904 { 1905 if (cdev->version == 30) 1906 return; 1907 if (!cdev->is_peripheral) 1908 return; 1909 1910 m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit); 1911 cdev->tx_peripheral_submit = 0; 1912 } 1913 1914 static void m_can_tx_work_queue(struct work_struct *ws) 1915 { 1916 struct m_can_tx_op *op = container_of(ws, struct m_can_tx_op, work); 1917 struct m_can_classdev *cdev = op->cdev; 1918 struct sk_buff *skb = op->skb; 1919 1920 op->skb = NULL; 1921 m_can_tx_handler(cdev, skb); 1922 if (op->submit) 1923 m_can_tx_submit(cdev); 1924 } 1925 1926 static void m_can_tx_queue_skb(struct m_can_classdev *cdev, struct sk_buff *skb, 1927 bool submit) 1928 { 1929 cdev->tx_ops[cdev->next_tx_op].skb = skb; 1930 cdev->tx_ops[cdev->next_tx_op].submit = submit; 1931 queue_work(cdev->tx_wq, &cdev->tx_ops[cdev->next_tx_op].work); 1932 1933 ++cdev->next_tx_op; 1934 if (cdev->next_tx_op >= cdev->tx_fifo_size) 1935 cdev->next_tx_op = 0; 1936 } 1937 1938 static netdev_tx_t m_can_start_peripheral_xmit(struct m_can_classdev *cdev, 1939 struct sk_buff *skb) 1940 { 1941 bool submit; 1942 1943 ++cdev->nr_txs_without_submit; 1944 if (cdev->nr_txs_without_submit >= cdev->tx_max_coalesced_frames || 1945 !netdev_xmit_more()) { 1946 cdev->nr_txs_without_submit = 0; 1947 submit = true; 1948 } else { 1949 submit = false; 1950 } 1951 m_can_tx_queue_skb(cdev, skb, submit); 1952 1953 return NETDEV_TX_OK; 1954 } 1955 1956 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb, 1957 struct net_device *dev) 1958 { 1959 struct m_can_classdev *cdev = netdev_priv(dev); 1960 unsigned int frame_len; 1961 netdev_tx_t ret; 1962 1963 if (can_dev_dropped_skb(dev, skb)) 1964 return NETDEV_TX_OK; 1965 1966 frame_len = can_skb_get_frame_len(skb); 1967 1968 if (cdev->can.state == CAN_STATE_BUS_OFF) { 1969 m_can_clean(cdev->net); 1970 return NETDEV_TX_OK; 1971 } 1972 1973 ret = m_can_start_tx(cdev); 1974 if (ret != NETDEV_TX_OK) 1975 return ret; 1976 1977 netdev_sent_queue(dev, frame_len); 1978 1979 if (cdev->is_peripheral) 1980 ret = m_can_start_peripheral_xmit(cdev, skb); 1981 else 1982 ret = m_can_tx_handler(cdev, skb); 1983 1984 if (ret != NETDEV_TX_OK) 1985 netdev_completed_queue(dev, 1, frame_len); 1986 1987 return ret; 1988 } 1989 1990 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) 1991 { 1992 struct m_can_classdev *cdev = container_of(timer, struct 1993 m_can_classdev, hrtimer); 1994 int ret; 1995 1996 if (cdev->can.state == CAN_STATE_BUS_OFF || 1997 cdev->can.state == CAN_STATE_STOPPED) 1998 return HRTIMER_NORESTART; 1999 2000 ret = m_can_interrupt_handler(cdev); 2001 2002 /* On error or if napi is scheduled to read, stop the timer */ 2003 if (ret < 0 || napi_is_scheduled(&cdev->napi)) 2004 return HRTIMER_NORESTART; 2005 2006 hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS)); 2007 2008 return HRTIMER_RESTART; 2009 } 2010 2011 static int m_can_open(struct net_device *dev) 2012 { 2013 struct m_can_classdev *cdev = netdev_priv(dev); 2014 int err; 2015 2016 err = phy_power_on(cdev->transceiver); 2017 if (err) 2018 return err; 2019 2020 err = m_can_clk_start(cdev); 2021 if (err) 2022 goto out_phy_power_off; 2023 2024 /* open the can device */ 2025 err = open_candev(dev); 2026 if (err) { 2027 netdev_err(dev, "failed to open can device\n"); 2028 goto exit_disable_clks; 2029 } 2030 2031 if (cdev->is_peripheral) 2032 can_rx_offload_enable(&cdev->offload); 2033 else 2034 napi_enable(&cdev->napi); 2035 2036 /* register interrupt handler */ 2037 if (cdev->is_peripheral) { 2038 cdev->tx_wq = alloc_ordered_workqueue("mcan_wq", 2039 WQ_FREEZABLE | WQ_MEM_RECLAIM); 2040 if (!cdev->tx_wq) { 2041 err = -ENOMEM; 2042 goto out_wq_fail; 2043 } 2044 2045 for (int i = 0; i != cdev->tx_fifo_size; ++i) { 2046 cdev->tx_ops[i].cdev = cdev; 2047 INIT_WORK(&cdev->tx_ops[i].work, m_can_tx_work_queue); 2048 } 2049 2050 err = request_threaded_irq(dev->irq, NULL, m_can_isr, 2051 IRQF_ONESHOT, 2052 dev->name, dev); 2053 } else if (dev->irq) { 2054 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name, 2055 dev); 2056 } 2057 2058 if (err < 0) { 2059 netdev_err(dev, "failed to request interrupt\n"); 2060 goto exit_irq_fail; 2061 } 2062 2063 /* start the m_can controller */ 2064 err = m_can_start(dev); 2065 if (err) 2066 goto exit_start_fail; 2067 2068 netif_start_queue(dev); 2069 2070 return 0; 2071 2072 exit_start_fail: 2073 if (cdev->is_peripheral || dev->irq) 2074 free_irq(dev->irq, dev); 2075 exit_irq_fail: 2076 if (cdev->is_peripheral) 2077 destroy_workqueue(cdev->tx_wq); 2078 out_wq_fail: 2079 if (cdev->is_peripheral) 2080 can_rx_offload_disable(&cdev->offload); 2081 else 2082 napi_disable(&cdev->napi); 2083 close_candev(dev); 2084 exit_disable_clks: 2085 m_can_clk_stop(cdev); 2086 out_phy_power_off: 2087 phy_power_off(cdev->transceiver); 2088 return err; 2089 } 2090 2091 static const struct net_device_ops m_can_netdev_ops = { 2092 .ndo_open = m_can_open, 2093 .ndo_stop = m_can_close, 2094 .ndo_start_xmit = m_can_start_xmit, 2095 .ndo_change_mtu = can_change_mtu, 2096 }; 2097 2098 static int m_can_get_coalesce(struct net_device *dev, 2099 struct ethtool_coalesce *ec, 2100 struct kernel_ethtool_coalesce *kec, 2101 struct netlink_ext_ack *ext_ack) 2102 { 2103 struct m_can_classdev *cdev = netdev_priv(dev); 2104 2105 ec->rx_max_coalesced_frames_irq = cdev->rx_max_coalesced_frames_irq; 2106 ec->rx_coalesce_usecs_irq = cdev->rx_coalesce_usecs_irq; 2107 ec->tx_max_coalesced_frames = cdev->tx_max_coalesced_frames; 2108 ec->tx_max_coalesced_frames_irq = cdev->tx_max_coalesced_frames_irq; 2109 ec->tx_coalesce_usecs_irq = cdev->tx_coalesce_usecs_irq; 2110 2111 return 0; 2112 } 2113 2114 static int m_can_set_coalesce(struct net_device *dev, 2115 struct ethtool_coalesce *ec, 2116 struct kernel_ethtool_coalesce *kec, 2117 struct netlink_ext_ack *ext_ack) 2118 { 2119 struct m_can_classdev *cdev = netdev_priv(dev); 2120 2121 if (cdev->can.state != CAN_STATE_STOPPED) { 2122 netdev_err(dev, "Device is in use, please shut it down first\n"); 2123 return -EBUSY; 2124 } 2125 2126 if (ec->rx_max_coalesced_frames_irq > cdev->mcfg[MRAM_RXF0].num) { 2127 netdev_err(dev, "rx-frames-irq %u greater than the RX FIFO %u\n", 2128 ec->rx_max_coalesced_frames_irq, 2129 cdev->mcfg[MRAM_RXF0].num); 2130 return -EINVAL; 2131 } 2132 if ((ec->rx_max_coalesced_frames_irq == 0) != (ec->rx_coalesce_usecs_irq == 0)) { 2133 netdev_err(dev, "rx-frames-irq and rx-usecs-irq can only be set together\n"); 2134 return -EINVAL; 2135 } 2136 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXE].num) { 2137 netdev_err(dev, "tx-frames-irq %u greater than the TX event FIFO %u\n", 2138 ec->tx_max_coalesced_frames_irq, 2139 cdev->mcfg[MRAM_TXE].num); 2140 return -EINVAL; 2141 } 2142 if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXB].num) { 2143 netdev_err(dev, "tx-frames-irq %u greater than the TX FIFO %u\n", 2144 ec->tx_max_coalesced_frames_irq, 2145 cdev->mcfg[MRAM_TXB].num); 2146 return -EINVAL; 2147 } 2148 if ((ec->tx_max_coalesced_frames_irq == 0) != (ec->tx_coalesce_usecs_irq == 0)) { 2149 netdev_err(dev, "tx-frames-irq and tx-usecs-irq can only be set together\n"); 2150 return -EINVAL; 2151 } 2152 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXE].num) { 2153 netdev_err(dev, "tx-frames %u greater than the TX event FIFO %u\n", 2154 ec->tx_max_coalesced_frames, 2155 cdev->mcfg[MRAM_TXE].num); 2156 return -EINVAL; 2157 } 2158 if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXB].num) { 2159 netdev_err(dev, "tx-frames %u greater than the TX FIFO %u\n", 2160 ec->tx_max_coalesced_frames, 2161 cdev->mcfg[MRAM_TXB].num); 2162 return -EINVAL; 2163 } 2164 if (ec->rx_coalesce_usecs_irq != 0 && ec->tx_coalesce_usecs_irq != 0 && 2165 ec->rx_coalesce_usecs_irq != ec->tx_coalesce_usecs_irq) { 2166 netdev_err(dev, "rx-usecs-irq %u needs to be equal to tx-usecs-irq %u if both are enabled\n", 2167 ec->rx_coalesce_usecs_irq, 2168 ec->tx_coalesce_usecs_irq); 2169 return -EINVAL; 2170 } 2171 2172 cdev->rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; 2173 cdev->rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; 2174 cdev->tx_max_coalesced_frames = ec->tx_max_coalesced_frames; 2175 cdev->tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; 2176 cdev->tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; 2177 2178 if (cdev->rx_coalesce_usecs_irq) 2179 cdev->irq_timer_wait = 2180 ns_to_ktime(cdev->rx_coalesce_usecs_irq * NSEC_PER_USEC); 2181 else 2182 cdev->irq_timer_wait = 2183 ns_to_ktime(cdev->tx_coalesce_usecs_irq * NSEC_PER_USEC); 2184 2185 return 0; 2186 } 2187 2188 static const struct ethtool_ops m_can_ethtool_ops_coalescing = { 2189 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS_IRQ | 2190 ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ | 2191 ETHTOOL_COALESCE_TX_USECS_IRQ | 2192 ETHTOOL_COALESCE_TX_MAX_FRAMES | 2193 ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ, 2194 .get_ts_info = ethtool_op_get_ts_info, 2195 .get_coalesce = m_can_get_coalesce, 2196 .set_coalesce = m_can_set_coalesce, 2197 }; 2198 2199 static const struct ethtool_ops m_can_ethtool_ops = { 2200 .get_ts_info = ethtool_op_get_ts_info, 2201 }; 2202 2203 static int register_m_can_dev(struct m_can_classdev *cdev) 2204 { 2205 struct net_device *dev = cdev->net; 2206 2207 dev->flags |= IFF_ECHO; /* we support local echo */ 2208 dev->netdev_ops = &m_can_netdev_ops; 2209 if (dev->irq && cdev->is_peripheral) 2210 dev->ethtool_ops = &m_can_ethtool_ops_coalescing; 2211 else 2212 dev->ethtool_ops = &m_can_ethtool_ops; 2213 2214 return register_candev(dev); 2215 } 2216 2217 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size) 2218 { 2219 u32 total_size; 2220 2221 total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off + 2222 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 2223 if (total_size > mram_max_size) { 2224 dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n", 2225 total_size, mram_max_size); 2226 return -EINVAL; 2227 } 2228 2229 return 0; 2230 } 2231 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg); 2232 2233 static void m_can_of_parse_mram(struct m_can_classdev *cdev, 2234 const u32 *mram_config_vals) 2235 { 2236 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; 2237 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; 2238 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + 2239 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; 2240 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; 2241 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + 2242 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; 2243 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & 2244 FIELD_MAX(RXFC_FS_MASK); 2245 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + 2246 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; 2247 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & 2248 FIELD_MAX(RXFC_FS_MASK); 2249 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + 2250 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; 2251 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; 2252 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + 2253 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; 2254 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; 2255 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + 2256 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; 2257 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & 2258 FIELD_MAX(TXBC_NDTB_MASK); 2259 2260 dev_dbg(cdev->dev, 2261 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", 2262 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num, 2263 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num, 2264 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num, 2265 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num, 2266 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num, 2267 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num, 2268 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num); 2269 } 2270 2271 int m_can_init_ram(struct m_can_classdev *cdev) 2272 { 2273 int end, i, start; 2274 int err = 0; 2275 2276 /* initialize the entire Message RAM in use to avoid possible 2277 * ECC/parity checksum errors when reading an uninitialized buffer 2278 */ 2279 start = cdev->mcfg[MRAM_SIDF].off; 2280 end = cdev->mcfg[MRAM_TXB].off + 2281 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE; 2282 2283 for (i = start; i < end; i += 4) { 2284 err = m_can_fifo_write_no_off(cdev, i, 0x0); 2285 if (err) 2286 break; 2287 } 2288 2289 return err; 2290 } 2291 EXPORT_SYMBOL_GPL(m_can_init_ram); 2292 2293 int m_can_class_get_clocks(struct m_can_classdev *cdev) 2294 { 2295 int ret = 0; 2296 2297 cdev->hclk = devm_clk_get(cdev->dev, "hclk"); 2298 cdev->cclk = devm_clk_get(cdev->dev, "cclk"); 2299 2300 if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) { 2301 dev_err(cdev->dev, "no clock found\n"); 2302 ret = -ENODEV; 2303 } 2304 2305 return ret; 2306 } 2307 EXPORT_SYMBOL_GPL(m_can_class_get_clocks); 2308 2309 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, 2310 int sizeof_priv) 2311 { 2312 struct m_can_classdev *class_dev = NULL; 2313 u32 mram_config_vals[MRAM_CFG_LEN]; 2314 struct net_device *net_dev; 2315 u32 tx_fifo_size; 2316 int ret; 2317 2318 ret = fwnode_property_read_u32_array(dev_fwnode(dev), 2319 "bosch,mram-cfg", 2320 mram_config_vals, 2321 sizeof(mram_config_vals) / 4); 2322 if (ret) { 2323 dev_err(dev, "Could not get Message RAM configuration."); 2324 goto out; 2325 } 2326 2327 /* Get TX FIFO size 2328 * Defines the total amount of echo buffers for loopback 2329 */ 2330 tx_fifo_size = mram_config_vals[7]; 2331 2332 /* allocate the m_can device */ 2333 net_dev = alloc_candev(sizeof_priv, tx_fifo_size); 2334 if (!net_dev) { 2335 dev_err(dev, "Failed to allocate CAN device"); 2336 goto out; 2337 } 2338 2339 class_dev = netdev_priv(net_dev); 2340 class_dev->net = net_dev; 2341 class_dev->dev = dev; 2342 SET_NETDEV_DEV(net_dev, dev); 2343 2344 m_can_of_parse_mram(class_dev, mram_config_vals); 2345 out: 2346 return class_dev; 2347 } 2348 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev); 2349 2350 void m_can_class_free_dev(struct net_device *net) 2351 { 2352 free_candev(net); 2353 } 2354 EXPORT_SYMBOL_GPL(m_can_class_free_dev); 2355 2356 int m_can_class_register(struct m_can_classdev *cdev) 2357 { 2358 int ret; 2359 2360 cdev->tx_fifo_size = max(1, min(cdev->mcfg[MRAM_TXB].num, 2361 cdev->mcfg[MRAM_TXE].num)); 2362 if (cdev->is_peripheral) { 2363 cdev->tx_ops = 2364 devm_kzalloc(cdev->dev, 2365 cdev->tx_fifo_size * sizeof(*cdev->tx_ops), 2366 GFP_KERNEL); 2367 if (!cdev->tx_ops) { 2368 dev_err(cdev->dev, "Failed to allocate tx_ops for workqueue\n"); 2369 return -ENOMEM; 2370 } 2371 } 2372 2373 ret = m_can_clk_start(cdev); 2374 if (ret) 2375 return ret; 2376 2377 if (cdev->is_peripheral) { 2378 ret = can_rx_offload_add_manual(cdev->net, &cdev->offload, 2379 NAPI_POLL_WEIGHT); 2380 if (ret) 2381 goto clk_disable; 2382 } 2383 2384 if (!cdev->net->irq) { 2385 dev_dbg(cdev->dev, "Polling enabled, initialize hrtimer"); 2386 hrtimer_init(&cdev->hrtimer, CLOCK_MONOTONIC, 2387 HRTIMER_MODE_REL_PINNED); 2388 cdev->hrtimer.function = &hrtimer_callback; 2389 } else { 2390 hrtimer_init(&cdev->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2391 cdev->hrtimer.function = m_can_coalescing_timer; 2392 } 2393 2394 ret = m_can_dev_setup(cdev); 2395 if (ret) 2396 goto rx_offload_del; 2397 2398 ret = register_m_can_dev(cdev); 2399 if (ret) { 2400 dev_err(cdev->dev, "registering %s failed (err=%d)\n", 2401 cdev->net->name, ret); 2402 goto rx_offload_del; 2403 } 2404 2405 of_can_transceiver(cdev->net); 2406 2407 dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n", 2408 KBUILD_MODNAME, cdev->net->irq, cdev->version); 2409 2410 /* Probe finished 2411 * Stop clocks. They will be reactivated once the M_CAN device is opened 2412 */ 2413 m_can_clk_stop(cdev); 2414 2415 return 0; 2416 2417 rx_offload_del: 2418 if (cdev->is_peripheral) 2419 can_rx_offload_del(&cdev->offload); 2420 clk_disable: 2421 m_can_clk_stop(cdev); 2422 2423 return ret; 2424 } 2425 EXPORT_SYMBOL_GPL(m_can_class_register); 2426 2427 void m_can_class_unregister(struct m_can_classdev *cdev) 2428 { 2429 if (cdev->is_peripheral) 2430 can_rx_offload_del(&cdev->offload); 2431 unregister_candev(cdev->net); 2432 } 2433 EXPORT_SYMBOL_GPL(m_can_class_unregister); 2434 2435 int m_can_class_suspend(struct device *dev) 2436 { 2437 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2438 struct net_device *ndev = cdev->net; 2439 2440 if (netif_running(ndev)) { 2441 netif_stop_queue(ndev); 2442 netif_device_detach(ndev); 2443 2444 /* leave the chip running with rx interrupt enabled if it is 2445 * used as a wake-up source. Coalescing needs to be reset then, 2446 * the timer is cancelled here, interrupts are done in resume. 2447 */ 2448 if (cdev->pm_wake_source) { 2449 hrtimer_cancel(&cdev->hrtimer); 2450 m_can_write(cdev, M_CAN_IE, IR_RF0N); 2451 } else { 2452 m_can_stop(ndev); 2453 } 2454 2455 m_can_clk_stop(cdev); 2456 } 2457 2458 pinctrl_pm_select_sleep_state(dev); 2459 2460 cdev->can.state = CAN_STATE_SLEEPING; 2461 2462 return 0; 2463 } 2464 EXPORT_SYMBOL_GPL(m_can_class_suspend); 2465 2466 int m_can_class_resume(struct device *dev) 2467 { 2468 struct m_can_classdev *cdev = dev_get_drvdata(dev); 2469 struct net_device *ndev = cdev->net; 2470 2471 pinctrl_pm_select_default_state(dev); 2472 2473 cdev->can.state = CAN_STATE_ERROR_ACTIVE; 2474 2475 if (netif_running(ndev)) { 2476 int ret; 2477 2478 ret = m_can_clk_start(cdev); 2479 if (ret) 2480 return ret; 2481 2482 if (cdev->pm_wake_source) { 2483 /* Restore active interrupts but disable coalescing as 2484 * we may have missed important waterlevel interrupts 2485 * between suspend and resume. Timers are already 2486 * stopped in suspend. Here we enable all interrupts 2487 * again. 2488 */ 2489 cdev->active_interrupts |= IR_RF0N | IR_TEFN; 2490 m_can_write(cdev, M_CAN_IE, cdev->active_interrupts); 2491 } else { 2492 ret = m_can_start(ndev); 2493 if (ret) { 2494 m_can_clk_stop(cdev); 2495 return ret; 2496 } 2497 } 2498 2499 netif_device_attach(ndev); 2500 netif_start_queue(ndev); 2501 } 2502 2503 return 0; 2504 } 2505 EXPORT_SYMBOL_GPL(m_can_class_resume); 2506 2507 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>"); 2508 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 2509 MODULE_LICENSE("GPL v2"); 2510 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller"); 2511