xref: /linux/drivers/net/can/grcan.c (revision e3fc2fd77c63cd2e37ebd33a336602a68650f22b)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
4  *
5  * 2012 (c) Aeroflex Gaisler AB
6  *
7  * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
8  * VHDL IP core library.
9  *
10  * Full documentation of the GRCAN core can be found here:
11  * http://www.gaisler.com/products/grlib/grip.pdf
12  *
13  * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
14  * open firmware properties.
15  *
16  * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
17  * sysfs interface.
18  *
19  * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module
20  * parameters.
21  *
22  * Contributors: Andreas Larsson <andreas@gaisler.com>
23  */
24 
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/netdevice.h>
29 #include <linux/delay.h>
30 #include <linux/ethtool.h>
31 #include <linux/io.h>
32 #include <linux/can/dev.h>
33 #include <linux/platform_device.h>
34 #include <linux/spinlock.h>
35 #include <linux/of.h>
36 #include <linux/of_irq.h>
37 
38 #include <linux/dma-mapping.h>
39 
40 #define DRV_NAME	"grcan"
41 
42 #define GRCAN_NAPI_WEIGHT	32
43 
44 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
45 
46 struct grcan_registers {
47 	u32 conf;	/* 0x00 */
48 	u32 stat;	/* 0x04 */
49 	u32 ctrl;	/* 0x08 */
50 	u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
51 	u32 smask;	/* 0x18 - CanMASK */
52 	u32 scode;	/* 0x1c - CanCODE */
53 	u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
54 	u32 pimsr;	/* 0x100 */
55 	u32 pimr;	/* 0x104 */
56 	u32 pisr;	/* 0x108 */
57 	u32 pir;	/* 0x10C */
58 	u32 imr;	/* 0x110 */
59 	u32 picr;	/* 0x114 */
60 	u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
61 	u32 txctrl;	/* 0x200 */
62 	u32 txaddr;	/* 0x204 */
63 	u32 txsize;	/* 0x208 */
64 	u32 txwr;	/* 0x20C */
65 	u32 txrd;	/* 0x210 */
66 	u32 txirq;	/* 0x214 */
67 	u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
68 	u32 rxctrl;	/* 0x300 */
69 	u32 rxaddr;	/* 0x304 */
70 	u32 rxsize;	/* 0x308 */
71 	u32 rxwr;	/* 0x30C */
72 	u32 rxrd;	/* 0x310 */
73 	u32 rxirq;	/* 0x314 */
74 	u32 rxmask;	/* 0x318 */
75 	u32 rxcode;	/* 0x31C */
76 };
77 
78 #define GRCAN_CONF_ABORT	0x00000001
79 #define GRCAN_CONF_ENABLE0	0x00000002
80 #define GRCAN_CONF_ENABLE1	0x00000004
81 #define GRCAN_CONF_SELECT	0x00000008
82 #define GRCAN_CONF_SILENT	0x00000010
83 #define GRCAN_CONF_SAM		0x00000020 /* Available in some hardware */
84 #define GRCAN_CONF_BPR		0x00000300 /* Note: not BRP */
85 #define GRCAN_CONF_RSJ		0x00007000
86 #define GRCAN_CONF_PS1		0x00f00000
87 #define GRCAN_CONF_PS2		0x000f0000
88 #define GRCAN_CONF_SCALER	0xff000000
89 #define GRCAN_CONF_OPERATION						\
90 	(GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1	\
91 	 | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
92 #define GRCAN_CONF_TIMING						\
93 	(GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1		\
94 	 | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
95 
96 #define GRCAN_CONF_RSJ_MIN	1
97 #define GRCAN_CONF_RSJ_MAX	4
98 #define GRCAN_CONF_PS1_MIN	1
99 #define GRCAN_CONF_PS1_MAX	15
100 #define GRCAN_CONF_PS2_MIN	2
101 #define GRCAN_CONF_PS2_MAX	8
102 #define GRCAN_CONF_SCALER_MIN	0
103 #define GRCAN_CONF_SCALER_MAX	255
104 #define GRCAN_CONF_SCALER_INC	1
105 
106 #define GRCAN_CONF_BPR_BIT	8
107 #define GRCAN_CONF_RSJ_BIT	12
108 #define GRCAN_CONF_PS1_BIT	20
109 #define GRCAN_CONF_PS2_BIT	16
110 #define GRCAN_CONF_SCALER_BIT	24
111 
112 #define GRCAN_STAT_PASS		0x000001
113 #define GRCAN_STAT_OFF		0x000002
114 #define GRCAN_STAT_OR		0x000004
115 #define GRCAN_STAT_AHBERR	0x000008
116 #define GRCAN_STAT_ACTIVE	0x000010
117 #define GRCAN_STAT_RXERRCNT	0x00ff00
118 #define GRCAN_STAT_TXERRCNT	0xff0000
119 
120 #define GRCAN_STAT_ERRCTR_RELATED	(GRCAN_STAT_PASS | GRCAN_STAT_OFF)
121 
122 #define GRCAN_STAT_RXERRCNT_BIT	8
123 #define GRCAN_STAT_TXERRCNT_BIT	16
124 
125 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT	96
126 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT	127
127 
128 #define GRCAN_CTRL_RESET	0x2
129 #define GRCAN_CTRL_ENABLE	0x1
130 
131 #define GRCAN_TXCTRL_ENABLE	0x1
132 #define GRCAN_TXCTRL_ONGOING	0x2
133 #define GRCAN_TXCTRL_SINGLE	0x4
134 
135 #define GRCAN_RXCTRL_ENABLE	0x1
136 #define GRCAN_RXCTRL_ONGOING	0x2
137 
138 /* Relative offset of IRQ sources to AMBA Plug&Play */
139 #define GRCAN_IRQIX_IRQ		0
140 #define GRCAN_IRQIX_TXSYNC	1
141 #define GRCAN_IRQIX_RXSYNC	2
142 
143 #define GRCAN_IRQ_PASS		0x00001
144 #define GRCAN_IRQ_OFF		0x00002
145 #define GRCAN_IRQ_OR		0x00004
146 #define GRCAN_IRQ_RXAHBERR	0x00008
147 #define GRCAN_IRQ_TXAHBERR	0x00010
148 #define GRCAN_IRQ_RXIRQ		0x00020
149 #define GRCAN_IRQ_TXIRQ		0x00040
150 #define GRCAN_IRQ_RXFULL	0x00080
151 #define GRCAN_IRQ_TXEMPTY	0x00100
152 #define GRCAN_IRQ_RX		0x00200
153 #define GRCAN_IRQ_TX		0x00400
154 #define GRCAN_IRQ_RXSYNC	0x00800
155 #define GRCAN_IRQ_TXSYNC	0x01000
156 #define GRCAN_IRQ_RXERRCTR	0x02000
157 #define GRCAN_IRQ_TXERRCTR	0x04000
158 #define GRCAN_IRQ_RXMISS	0x08000
159 #define GRCAN_IRQ_TXLOSS	0x10000
160 
161 #define GRCAN_IRQ_NONE	0
162 #define GRCAN_IRQ_ALL							\
163 	(GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR			\
164 	 | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR			\
165 	 | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ				\
166 	 | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY				\
167 	 | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC		\
168 	 | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR			\
169 	 | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS			\
170 	 | GRCAN_IRQ_TXLOSS)
171 
172 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
173 				  | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
174 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR	\
175 			  | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR	\
176 			  | GRCAN_IRQ_TXLOSS)
177 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
178 
179 #define GRCAN_MSG_SIZE		16
180 
181 #define GRCAN_MSG_IDE		0x80000000
182 #define GRCAN_MSG_RTR		0x40000000
183 #define GRCAN_MSG_BID		0x1ffc0000
184 #define GRCAN_MSG_EID		0x1fffffff
185 #define GRCAN_MSG_IDE_BIT	31
186 #define GRCAN_MSG_RTR_BIT	30
187 #define GRCAN_MSG_BID_BIT	18
188 #define GRCAN_MSG_EID_BIT	0
189 
190 #define GRCAN_MSG_DLC		0xf0000000
191 #define GRCAN_MSG_TXERRC	0x00ff0000
192 #define GRCAN_MSG_RXERRC	0x0000ff00
193 #define GRCAN_MSG_DLC_BIT	28
194 #define GRCAN_MSG_TXERRC_BIT	16
195 #define GRCAN_MSG_RXERRC_BIT	8
196 #define GRCAN_MSG_AHBERR	0x00000008
197 #define GRCAN_MSG_OR		0x00000004
198 #define GRCAN_MSG_OFF		0x00000002
199 #define GRCAN_MSG_PASS		0x00000001
200 
201 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
202 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
203 
204 #define GRCAN_BUFFER_ALIGNMENT		1024
205 #define GRCAN_DEFAULT_BUFFER_SIZE	1024
206 #define GRCAN_VALID_TR_SIZE_MASK	0x001fffc0
207 
208 #define GRCAN_INVALID_BUFFER_SIZE(s)			\
209 	((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
210 
211 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
212 #error "Invalid default buffer size"
213 #endif
214 
215 struct grcan_dma_buffer {
216 	size_t size;
217 	void *buf;
218 	dma_addr_t handle;
219 };
220 
221 struct grcan_dma {
222 	size_t base_size;
223 	void *base_buf;
224 	dma_addr_t base_handle;
225 	struct grcan_dma_buffer tx;
226 	struct grcan_dma_buffer rx;
227 };
228 
229 /* GRCAN configuration parameters */
230 struct grcan_device_config {
231 	unsigned short enable0;
232 	unsigned short enable1;
233 	unsigned short select;
234 	unsigned int txsize;
235 	unsigned int rxsize;
236 };
237 
238 #define GRCAN_DEFAULT_DEVICE_CONFIG {				\
239 		.enable0	= 0,				\
240 		.enable1	= 0,				\
241 		.select		= 0,				\
242 		.txsize		= GRCAN_DEFAULT_BUFFER_SIZE,	\
243 		.rxsize		= GRCAN_DEFAULT_BUFFER_SIZE,	\
244 		}
245 
246 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION	4100
247 #define GRLIB_VERSION_MASK		0xffff
248 
249 /* GRCAN private data structure */
250 struct grcan_priv {
251 	struct can_priv can;	/* must be the first member */
252 	struct net_device *dev;
253 	struct device *ofdev_dev;
254 	struct napi_struct napi;
255 
256 	struct grcan_registers __iomem *regs;	/* ioremap'ed registers */
257 	struct grcan_device_config config;
258 	struct grcan_dma dma;
259 
260 	struct sk_buff **echo_skb;	/* We allocate this on our own */
261 
262 	/* The echo skb pointer, pointing into echo_skb and indicating which
263 	 * frames can be echoed back. See the "Notes on the tx cyclic buffer
264 	 * handling"-comment for grcan_start_xmit for more details.
265 	 */
266 	u32 eskbp;
267 
268 	/* Lock for controlling changes to the netif tx queue state, accesses to
269 	 * the echo_skb pointer eskbp and for making sure that a running reset
270 	 * and/or a close of the interface is done without interference from
271 	 * other parts of the code.
272 	 *
273 	 * The echo_skb pointer, eskbp, should only be accessed under this lock
274 	 * as it can be changed in several places and together with decisions on
275 	 * whether to wake up the tx queue.
276 	 *
277 	 * The tx queue must never be woken up if there is a running reset or
278 	 * close in progress.
279 	 *
280 	 * A running reset (see below on need_txbug_workaround) should never be
281 	 * done if the interface is closing down and several running resets
282 	 * should never be scheduled simultaneously.
283 	 */
284 	spinlock_t lock;
285 
286 	/* Whether a workaround is needed due to a bug in older hardware. In
287 	 * this case, the driver both tries to prevent the bug from being
288 	 * triggered and recovers, if the bug nevertheless happens, by doing a
289 	 * running reset. A running reset, resets the device and continues from
290 	 * where it were without being noticeable from outside the driver (apart
291 	 * from slight delays).
292 	 */
293 	bool need_txbug_workaround;
294 
295 	/* To trigger initization of running reset and to trigger running reset
296 	 * respectively in the case of a hanged device due to a txbug.
297 	 */
298 	struct timer_list hang_timer;
299 	struct timer_list rr_timer;
300 
301 	/* To avoid waking up the netif queue and restarting timers
302 	 * when a reset is scheduled or when closing of the device is
303 	 * undergoing
304 	 */
305 	bool resetting;
306 	bool closing;
307 };
308 
309 /* Wait time for a short wait for ongoing to clear */
310 #define GRCAN_SHORTWAIT_USECS	10
311 
312 /* Limit on the number of transmitted bits of an eff frame according to the CAN
313  * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
314  * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
315  * bits end of frame
316  */
317 #define GRCAN_EFF_FRAME_MAX_BITS	(1+32+6+8*8+16+2+7)
318 
319 #if defined(__BIG_ENDIAN)
320 static inline u32 grcan_read_reg(u32 __iomem *reg)
321 {
322 	return ioread32be(reg);
323 }
324 
325 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
326 {
327 	iowrite32be(val, reg);
328 }
329 #else
330 static inline u32 grcan_read_reg(u32 __iomem *reg)
331 {
332 	return ioread32(reg);
333 }
334 
335 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
336 {
337 	iowrite32(val, reg);
338 }
339 #endif
340 
341 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
342 {
343 	grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
344 }
345 
346 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
347 {
348 	grcan_write_reg(reg, grcan_read_reg(reg) | mask);
349 }
350 
351 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
352 {
353 	return grcan_read_reg(reg) & mask;
354 }
355 
356 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
357 {
358 	u32 old = grcan_read_reg(reg);
359 
360 	grcan_write_reg(reg, (old & ~mask) | (value & mask));
361 }
362 
363 /* a and b should both be in [0,size] and a == b == size should not hold */
364 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
365 {
366 	u32 sum = a + b;
367 
368 	if (sum < size)
369 		return sum;
370 	else
371 		return sum - size;
372 }
373 
374 /* a and b should both be in [0,size) */
375 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
376 {
377 	return grcan_ring_add(a, size - b, size);
378 }
379 
380 /* Available slots for new transmissions */
381 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
382 {
383 	u32 slots = txsize / GRCAN_MSG_SIZE - 1;
384 	u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
385 
386 	return slots - used;
387 }
388 
389 /* Configuration parameters that can be set via module parameters */
390 static struct grcan_device_config grcan_module_config =
391 	GRCAN_DEFAULT_DEVICE_CONFIG;
392 
393 static const struct can_bittiming_const grcan_bittiming_const = {
394 	.name		= DRV_NAME,
395 	.tseg1_min	= GRCAN_CONF_PS1_MIN + 1,
396 	.tseg1_max	= GRCAN_CONF_PS1_MAX + 1,
397 	.tseg2_min	= GRCAN_CONF_PS2_MIN,
398 	.tseg2_max	= GRCAN_CONF_PS2_MAX,
399 	.sjw_max	= GRCAN_CONF_RSJ_MAX,
400 	.brp_min	= GRCAN_CONF_SCALER_MIN + 1,
401 	.brp_max	= GRCAN_CONF_SCALER_MAX + 1,
402 	.brp_inc	= GRCAN_CONF_SCALER_INC,
403 };
404 
405 static int grcan_set_bittiming(struct net_device *dev)
406 {
407 	struct grcan_priv *priv = netdev_priv(dev);
408 	struct grcan_registers __iomem *regs = priv->regs;
409 	struct can_bittiming *bt = &priv->can.bittiming;
410 	u32 timing = 0;
411 	int bpr, rsj, ps1, ps2, scaler;
412 
413 	/* Should never happen - function will not be called when
414 	 * device is up
415 	 */
416 	if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
417 		return -EBUSY;
418 
419 	bpr = 0; /* Note bpr and brp are different concepts */
420 	rsj = bt->sjw;
421 	ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
422 	ps2 = bt->phase_seg2;
423 	scaler = (bt->brp - 1);
424 	netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
425 		   bpr, rsj, ps1, ps2, scaler);
426 	if (!(ps1 > ps2)) {
427 		netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
428 			   ps1, ps2);
429 		return -EINVAL;
430 	}
431 	if (!(ps2 >= rsj)) {
432 		netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
433 			   ps2, rsj);
434 		return -EINVAL;
435 	}
436 
437 	timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
438 	timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
439 	timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
440 	timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
441 	timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
442 	netdev_info(dev, "setting timing=0x%x\n", timing);
443 	grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
444 
445 	return 0;
446 }
447 
448 static int grcan_get_berr_counter(const struct net_device *dev,
449 				  struct can_berr_counter *bec)
450 {
451 	struct grcan_priv *priv = netdev_priv(dev);
452 	struct grcan_registers __iomem *regs = priv->regs;
453 	u32 status = grcan_read_reg(&regs->stat);
454 
455 	bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
456 	bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
457 	return 0;
458 }
459 
460 static int grcan_poll(struct napi_struct *napi, int budget);
461 
462 /* Reset device, but keep configuration information */
463 static void grcan_reset(struct net_device *dev)
464 {
465 	struct grcan_priv *priv = netdev_priv(dev);
466 	struct grcan_registers __iomem *regs = priv->regs;
467 	u32 config = grcan_read_reg(&regs->conf);
468 
469 	grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
470 	grcan_write_reg(&regs->conf, config);
471 
472 	priv->eskbp = grcan_read_reg(&regs->txrd);
473 	priv->can.state = CAN_STATE_STOPPED;
474 
475 	/* Turn off hardware filtering - regs->rxcode set to 0 by reset */
476 	grcan_write_reg(&regs->rxmask, 0);
477 }
478 
479 /* stop device without changing any configurations */
480 static void grcan_stop_hardware(struct net_device *dev)
481 {
482 	struct grcan_priv *priv = netdev_priv(dev);
483 	struct grcan_registers __iomem *regs = priv->regs;
484 
485 	grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
486 	grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
487 	grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
488 	grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
489 }
490 
491 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
492  * is true and free them otherwise.
493  *
494  * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
495  * continue until priv->eskbp catches up to regs->txrd.
496  *
497  * priv->lock *must* be held when calling this function
498  */
499 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
500 {
501 	struct grcan_priv *priv = netdev_priv(dev);
502 	struct grcan_registers __iomem *regs = priv->regs;
503 	struct grcan_dma *dma = &priv->dma;
504 	struct net_device_stats *stats = &dev->stats;
505 	int i, work_done;
506 
507 	/* Updates to priv->eskbp and wake-ups of the queue needs to
508 	 * be atomic towards the reads of priv->eskbp and shut-downs
509 	 * of the queue in grcan_start_xmit.
510 	 */
511 	u32 txrd = grcan_read_reg(&regs->txrd);
512 
513 	for (work_done = 0; work_done < budget || budget < 0; work_done++) {
514 		if (priv->eskbp == txrd)
515 			break;
516 		i = priv->eskbp / GRCAN_MSG_SIZE;
517 		if (echo) {
518 			/* Normal echo of messages */
519 			stats->tx_packets++;
520 			stats->tx_bytes += can_get_echo_skb(dev, i, NULL);
521 		} else {
522 			/* For cleanup of untransmitted messages */
523 			can_free_echo_skb(dev, i, NULL);
524 		}
525 
526 		priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
527 					     dma->tx.size);
528 		txrd = grcan_read_reg(&regs->txrd);
529 	}
530 	return work_done;
531 }
532 
533 static void grcan_lost_one_shot_frame(struct net_device *dev)
534 {
535 	struct grcan_priv *priv = netdev_priv(dev);
536 	struct grcan_registers __iomem *regs = priv->regs;
537 	struct grcan_dma *dma = &priv->dma;
538 	u32 txrd;
539 	unsigned long flags;
540 
541 	spin_lock_irqsave(&priv->lock, flags);
542 
543 	catch_up_echo_skb(dev, -1, true);
544 
545 	if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
546 		/* Should never happen */
547 		netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
548 	} else {
549 		/* By the time an GRCAN_IRQ_TXLOSS is generated in
550 		 * one-shot mode there is no problem in writing
551 		 * to TXRD even in versions of the hardware in
552 		 * which GRCAN_TXCTRL_ONGOING is not cleared properly
553 		 * in one-shot mode.
554 		 */
555 
556 		/* Skip message and discard echo-skb */
557 		txrd = grcan_read_reg(&regs->txrd);
558 		txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
559 		grcan_write_reg(&regs->txrd, txrd);
560 		catch_up_echo_skb(dev, -1, false);
561 
562 		if (!priv->resetting && !priv->closing &&
563 		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
564 			netif_wake_queue(dev);
565 			grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
566 		}
567 	}
568 
569 	spin_unlock_irqrestore(&priv->lock, flags);
570 }
571 
572 static void grcan_err(struct net_device *dev, u32 sources, u32 status)
573 {
574 	struct grcan_priv *priv = netdev_priv(dev);
575 	struct grcan_registers __iomem *regs = priv->regs;
576 	struct grcan_dma *dma = &priv->dma;
577 	struct net_device_stats *stats = &dev->stats;
578 	struct can_frame cf;
579 
580 	/* Zero potential error_frame */
581 	memset(&cf, 0, sizeof(cf));
582 
583 	/* Message lost interrupt. This might be due to arbitration error, but
584 	 * is also triggered when there is no one else on the can bus or when
585 	 * there is a problem with the hardware interface or the bus itself. As
586 	 * arbitration errors can not be singled out, no error frames are
587 	 * generated reporting this event as an arbitration error.
588 	 */
589 	if (sources & GRCAN_IRQ_TXLOSS) {
590 		/* Take care of failed one-shot transmit */
591 		if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
592 			grcan_lost_one_shot_frame(dev);
593 
594 		/* Stop printing as soon as error passive or bus off is in
595 		 * effect to limit the amount of txloss debug printouts.
596 		 */
597 		if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
598 			netdev_dbg(dev, "tx message lost\n");
599 			stats->tx_errors++;
600 		}
601 	}
602 
603 	/* Conditions dealing with the error counters. There is no interrupt for
604 	 * error warning, but there are interrupts for increases of the error
605 	 * counters.
606 	 */
607 	if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
608 	    (status & GRCAN_STAT_ERRCTR_RELATED)) {
609 		enum can_state state = priv->can.state;
610 		enum can_state oldstate = state;
611 		u32 txerr = (status & GRCAN_STAT_TXERRCNT)
612 			>> GRCAN_STAT_TXERRCNT_BIT;
613 		u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
614 			>> GRCAN_STAT_RXERRCNT_BIT;
615 
616 		/* Figure out current state */
617 		if (status & GRCAN_STAT_OFF) {
618 			state = CAN_STATE_BUS_OFF;
619 		} else if (status & GRCAN_STAT_PASS) {
620 			state = CAN_STATE_ERROR_PASSIVE;
621 		} else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
622 			   rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
623 			state = CAN_STATE_ERROR_WARNING;
624 		} else {
625 			state = CAN_STATE_ERROR_ACTIVE;
626 		}
627 
628 		/* Handle and report state changes */
629 		if (state != oldstate) {
630 			switch (state) {
631 			case CAN_STATE_BUS_OFF:
632 				netdev_dbg(dev, "bus-off\n");
633 				netif_carrier_off(dev);
634 				priv->can.can_stats.bus_off++;
635 
636 				/* Prevent the hardware from recovering from bus
637 				 * off on its own if restart is disabled.
638 				 */
639 				if (!priv->can.restart_ms)
640 					grcan_stop_hardware(dev);
641 
642 				cf.can_id |= CAN_ERR_BUSOFF;
643 				break;
644 
645 			case CAN_STATE_ERROR_PASSIVE:
646 				netdev_dbg(dev, "Error passive condition\n");
647 				priv->can.can_stats.error_passive++;
648 
649 				cf.can_id |= CAN_ERR_CRTL;
650 				if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
651 					cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
652 				if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
653 					cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
654 				break;
655 
656 			case CAN_STATE_ERROR_WARNING:
657 				netdev_dbg(dev, "Error warning condition\n");
658 				priv->can.can_stats.error_warning++;
659 
660 				cf.can_id |= CAN_ERR_CRTL;
661 				if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
662 					cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
663 				if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
664 					cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
665 				break;
666 
667 			case CAN_STATE_ERROR_ACTIVE:
668 				netdev_dbg(dev, "Error active condition\n");
669 				cf.can_id |= CAN_ERR_CRTL;
670 				break;
671 
672 			default:
673 				/* There are no others at this point */
674 				break;
675 			}
676 			cf.can_id |= CAN_ERR_CNT;
677 			cf.data[6] = txerr;
678 			cf.data[7] = rxerr;
679 			priv->can.state = state;
680 		}
681 
682 		/* Report automatic restarts */
683 		if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
684 			unsigned long flags;
685 
686 			cf.can_id |= CAN_ERR_RESTARTED;
687 			netdev_dbg(dev, "restarted\n");
688 			priv->can.can_stats.restarts++;
689 			netif_carrier_on(dev);
690 
691 			spin_lock_irqsave(&priv->lock, flags);
692 
693 			if (!priv->resetting && !priv->closing) {
694 				u32 txwr = grcan_read_reg(&regs->txwr);
695 
696 				if (grcan_txspace(dma->tx.size, txwr,
697 						  priv->eskbp))
698 					netif_wake_queue(dev);
699 			}
700 
701 			spin_unlock_irqrestore(&priv->lock, flags);
702 		}
703 	}
704 
705 	/* Data overrun interrupt */
706 	if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
707 		netdev_dbg(dev, "got data overrun interrupt\n");
708 		stats->rx_over_errors++;
709 		stats->rx_errors++;
710 
711 		cf.can_id |= CAN_ERR_CRTL;
712 		cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
713 	}
714 
715 	/* AHB bus error interrupts (not CAN bus errors) - shut down the
716 	 * device.
717 	 */
718 	if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
719 	    (status & GRCAN_STAT_AHBERR)) {
720 		char *txrx = "";
721 		unsigned long flags;
722 
723 		if (sources & GRCAN_IRQ_TXAHBERR) {
724 			txrx = "on tx ";
725 			stats->tx_errors++;
726 		} else if (sources & GRCAN_IRQ_RXAHBERR) {
727 			txrx = "on rx ";
728 			stats->rx_errors++;
729 		}
730 		netdev_err(dev, "Fatal AHB bus error %s- halting device\n",
731 			   txrx);
732 
733 		spin_lock_irqsave(&priv->lock, flags);
734 
735 		/* Prevent anything to be enabled again and halt device */
736 		priv->closing = true;
737 		netif_stop_queue(dev);
738 		grcan_stop_hardware(dev);
739 		priv->can.state = CAN_STATE_STOPPED;
740 
741 		spin_unlock_irqrestore(&priv->lock, flags);
742 	}
743 
744 	/* Pass on error frame if something to report,
745 	 * i.e. id contains some information
746 	 */
747 	if (cf.can_id) {
748 		struct can_frame *skb_cf;
749 		struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
750 
751 		if (skb == NULL) {
752 			netdev_dbg(dev, "could not allocate error frame\n");
753 			return;
754 		}
755 		skb_cf->can_id |= cf.can_id;
756 		memcpy(skb_cf->data, cf.data, sizeof(cf.data));
757 
758 		netif_rx(skb);
759 	}
760 }
761 
762 static irqreturn_t grcan_interrupt(int irq, void *dev_id)
763 {
764 	struct net_device *dev = dev_id;
765 	struct grcan_priv *priv = netdev_priv(dev);
766 	struct grcan_registers __iomem *regs = priv->regs;
767 	u32 sources, status;
768 
769 	/* Find out the source */
770 	sources = grcan_read_reg(&regs->pimsr);
771 	if (!sources)
772 		return IRQ_NONE;
773 	grcan_write_reg(&regs->picr, sources);
774 	status = grcan_read_reg(&regs->stat);
775 
776 	/* If we got TX progress, the device has not hanged,
777 	 * so disable the hang timer
778 	 */
779 	if (priv->need_txbug_workaround &&
780 	    (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
781 		del_timer(&priv->hang_timer);
782 	}
783 
784 	/* Frame(s) received or transmitted */
785 	if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
786 		/* Disable tx/rx interrupts and schedule poll(). No need for
787 		 * locking as interference from a running reset at worst leads
788 		 * to an extra interrupt.
789 		 */
790 		grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
791 		napi_schedule(&priv->napi);
792 	}
793 
794 	/* (Potential) error conditions to take care of */
795 	if (sources & GRCAN_IRQ_ERRORS)
796 		grcan_err(dev, sources, status);
797 
798 	return IRQ_HANDLED;
799 }
800 
801 /* Reset device and restart operations from where they were.
802  *
803  * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
804  * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
805  * for single shot)
806  */
807 static void grcan_running_reset(struct timer_list *t)
808 {
809 	struct grcan_priv *priv = from_timer(priv, t, rr_timer);
810 	struct net_device *dev = priv->dev;
811 	struct grcan_registers __iomem *regs = priv->regs;
812 	unsigned long flags;
813 
814 	/* This temporarily messes with eskbp, so we need to lock
815 	 * priv->lock
816 	 */
817 	spin_lock_irqsave(&priv->lock, flags);
818 
819 	priv->resetting = false;
820 	del_timer(&priv->hang_timer);
821 	del_timer(&priv->rr_timer);
822 
823 	if (!priv->closing) {
824 		/* Save and reset - config register preserved by grcan_reset */
825 		u32 imr = grcan_read_reg(&regs->imr);
826 
827 		u32 txaddr = grcan_read_reg(&regs->txaddr);
828 		u32 txsize = grcan_read_reg(&regs->txsize);
829 		u32 txwr = grcan_read_reg(&regs->txwr);
830 		u32 txrd = grcan_read_reg(&regs->txrd);
831 		u32 eskbp = priv->eskbp;
832 
833 		u32 rxaddr = grcan_read_reg(&regs->rxaddr);
834 		u32 rxsize = grcan_read_reg(&regs->rxsize);
835 		u32 rxwr = grcan_read_reg(&regs->rxwr);
836 		u32 rxrd = grcan_read_reg(&regs->rxrd);
837 
838 		grcan_reset(dev);
839 
840 		/* Restore */
841 		grcan_write_reg(&regs->txaddr, txaddr);
842 		grcan_write_reg(&regs->txsize, txsize);
843 		grcan_write_reg(&regs->txwr, txwr);
844 		grcan_write_reg(&regs->txrd, txrd);
845 		priv->eskbp = eskbp;
846 
847 		grcan_write_reg(&regs->rxaddr, rxaddr);
848 		grcan_write_reg(&regs->rxsize, rxsize);
849 		grcan_write_reg(&regs->rxwr, rxwr);
850 		grcan_write_reg(&regs->rxrd, rxrd);
851 
852 		/* Turn on device again */
853 		grcan_write_reg(&regs->imr, imr);
854 		priv->can.state = CAN_STATE_ERROR_ACTIVE;
855 		grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
856 				| (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
857 				   ? GRCAN_TXCTRL_SINGLE : 0));
858 		grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
859 		grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
860 
861 		/* Start queue if there is size and listen-onle mode is not
862 		 * enabled
863 		 */
864 		if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
865 		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
866 			netif_wake_queue(dev);
867 	}
868 
869 	spin_unlock_irqrestore(&priv->lock, flags);
870 
871 	netdev_err(dev, "Device reset and restored\n");
872 }
873 
874 /* Waiting time in usecs corresponding to the transmission of three maximum
875  * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
876  * of time makes sure that the can controller have time to finish sending or
877  * receiving a frame with a good margin.
878  *
879  * usecs/sec * number of frames * bits/frame / bits/sec
880  */
881 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
882 {
883 	return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
884 }
885 
886 /* Set timer so that it will not fire until after a period in which the can
887  * controller have a good margin to finish transmitting a frame unless it has
888  * hanged
889  */
890 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
891 {
892 	u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
893 
894 	mod_timer(timer, jiffies + wait_jiffies);
895 }
896 
897 /* Disable channels and schedule a running reset */
898 static void grcan_initiate_running_reset(struct timer_list *t)
899 {
900 	struct grcan_priv *priv = from_timer(priv, t, hang_timer);
901 	struct net_device *dev = priv->dev;
902 	struct grcan_registers __iomem *regs = priv->regs;
903 	unsigned long flags;
904 
905 	netdev_err(dev, "Device seems hanged - reset scheduled\n");
906 
907 	spin_lock_irqsave(&priv->lock, flags);
908 
909 	/* The main body of this function must never be executed again
910 	 * until after an execution of grcan_running_reset
911 	 */
912 	if (!priv->resetting && !priv->closing) {
913 		priv->resetting = true;
914 		netif_stop_queue(dev);
915 		grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
916 		grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
917 		grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
918 	}
919 
920 	spin_unlock_irqrestore(&priv->lock, flags);
921 }
922 
923 static void grcan_free_dma_buffers(struct net_device *dev)
924 {
925 	struct grcan_priv *priv = netdev_priv(dev);
926 	struct grcan_dma *dma = &priv->dma;
927 
928 	dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf,
929 			  dma->base_handle);
930 	memset(dma, 0, sizeof(*dma));
931 }
932 
933 static int grcan_allocate_dma_buffers(struct net_device *dev,
934 				      size_t tsize, size_t rsize)
935 {
936 	struct grcan_priv *priv = netdev_priv(dev);
937 	struct grcan_dma *dma = &priv->dma;
938 	struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
939 	struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
940 	size_t shift;
941 
942 	/* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
943 	 * i.e. first buffer
944 	 */
945 	size_t maxs = max(tsize, rsize);
946 	size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
947 
948 	/* Put the small buffer after that */
949 	size_t ssize = min(tsize, rsize);
950 
951 	/* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
952 	dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
953 	dma->base_buf = dma_alloc_coherent(priv->ofdev_dev,
954 					   dma->base_size,
955 					   &dma->base_handle,
956 					   GFP_KERNEL);
957 
958 	if (!dma->base_buf)
959 		return -ENOMEM;
960 
961 	dma->tx.size = tsize;
962 	dma->rx.size = rsize;
963 
964 	large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
965 	small->handle = large->handle + lsize;
966 	shift = large->handle - dma->base_handle;
967 
968 	large->buf = dma->base_buf + shift;
969 	small->buf = large->buf + lsize;
970 
971 	return 0;
972 }
973 
974 /* priv->lock *must* be held when calling this function */
975 static int grcan_start(struct net_device *dev)
976 {
977 	struct grcan_priv *priv = netdev_priv(dev);
978 	struct grcan_registers __iomem *regs = priv->regs;
979 	u32 confop, txctrl;
980 
981 	grcan_reset(dev);
982 
983 	grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
984 	grcan_write_reg(&regs->txsize, priv->dma.tx.size);
985 	/* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
986 
987 	grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
988 	grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
989 	/* regs->rxwr and regs->rxrd already set to 0 by reset */
990 
991 	/* Enable interrupts */
992 	grcan_read_reg(&regs->pir);
993 	grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
994 
995 	/* Enable interfaces, channels and device */
996 	confop = GRCAN_CONF_ABORT
997 		| (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
998 		| (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
999 		| (priv->config.select ? GRCAN_CONF_SELECT : 0)
1000 		| (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1001 		   GRCAN_CONF_SILENT : 0)
1002 		| (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1003 		   GRCAN_CONF_SAM : 0);
1004 	grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1005 	txctrl = GRCAN_TXCTRL_ENABLE
1006 		| (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1007 		   ? GRCAN_TXCTRL_SINGLE : 0);
1008 	grcan_write_reg(&regs->txctrl, txctrl);
1009 	grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1010 	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1011 
1012 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1013 
1014 	return 0;
1015 }
1016 
1017 static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1018 {
1019 	struct grcan_priv *priv = netdev_priv(dev);
1020 	unsigned long flags;
1021 	int err = 0;
1022 
1023 	if (mode == CAN_MODE_START) {
1024 		/* This might be called to restart the device to recover from
1025 		 * bus off errors
1026 		 */
1027 		spin_lock_irqsave(&priv->lock, flags);
1028 		if (priv->closing || priv->resetting) {
1029 			err = -EBUSY;
1030 		} else {
1031 			netdev_info(dev, "Restarting device\n");
1032 			grcan_start(dev);
1033 			if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1034 				netif_wake_queue(dev);
1035 		}
1036 		spin_unlock_irqrestore(&priv->lock, flags);
1037 		return err;
1038 	}
1039 	return -EOPNOTSUPP;
1040 }
1041 
1042 static int grcan_open(struct net_device *dev)
1043 {
1044 	struct grcan_priv *priv = netdev_priv(dev);
1045 	struct grcan_dma *dma = &priv->dma;
1046 	unsigned long flags;
1047 	int err;
1048 
1049 	/* Allocate memory */
1050 	err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1051 					 priv->config.rxsize);
1052 	if (err) {
1053 		netdev_err(dev, "could not allocate DMA buffers\n");
1054 		return err;
1055 	}
1056 
1057 	priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb),
1058 				 GFP_KERNEL);
1059 	if (!priv->echo_skb) {
1060 		err = -ENOMEM;
1061 		goto exit_free_dma_buffers;
1062 	}
1063 	priv->can.echo_skb_max = dma->tx.size;
1064 	priv->can.echo_skb = priv->echo_skb;
1065 
1066 	/* Get can device up */
1067 	err = open_candev(dev);
1068 	if (err)
1069 		goto exit_free_echo_skb;
1070 
1071 	err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1072 			  dev->name, dev);
1073 	if (err)
1074 		goto exit_close_candev;
1075 
1076 	spin_lock_irqsave(&priv->lock, flags);
1077 
1078 	napi_enable(&priv->napi);
1079 	grcan_start(dev);
1080 	if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1081 		netif_start_queue(dev);
1082 	priv->resetting = false;
1083 	priv->closing = false;
1084 
1085 	spin_unlock_irqrestore(&priv->lock, flags);
1086 
1087 	return 0;
1088 
1089 exit_close_candev:
1090 	close_candev(dev);
1091 exit_free_echo_skb:
1092 	kfree(priv->echo_skb);
1093 exit_free_dma_buffers:
1094 	grcan_free_dma_buffers(dev);
1095 	return err;
1096 }
1097 
1098 static int grcan_close(struct net_device *dev)
1099 {
1100 	struct grcan_priv *priv = netdev_priv(dev);
1101 	unsigned long flags;
1102 
1103 	napi_disable(&priv->napi);
1104 
1105 	spin_lock_irqsave(&priv->lock, flags);
1106 
1107 	priv->closing = true;
1108 	if (priv->need_txbug_workaround) {
1109 		spin_unlock_irqrestore(&priv->lock, flags);
1110 		del_timer_sync(&priv->hang_timer);
1111 		del_timer_sync(&priv->rr_timer);
1112 		spin_lock_irqsave(&priv->lock, flags);
1113 	}
1114 	netif_stop_queue(dev);
1115 	grcan_stop_hardware(dev);
1116 	priv->can.state = CAN_STATE_STOPPED;
1117 
1118 	spin_unlock_irqrestore(&priv->lock, flags);
1119 
1120 	free_irq(dev->irq, dev);
1121 	close_candev(dev);
1122 
1123 	grcan_free_dma_buffers(dev);
1124 	priv->can.echo_skb_max = 0;
1125 	priv->can.echo_skb = NULL;
1126 	kfree(priv->echo_skb);
1127 
1128 	return 0;
1129 }
1130 
1131 static void grcan_transmit_catch_up(struct net_device *dev)
1132 {
1133 	struct grcan_priv *priv = netdev_priv(dev);
1134 	unsigned long flags;
1135 	int work_done;
1136 
1137 	spin_lock_irqsave(&priv->lock, flags);
1138 
1139 	work_done = catch_up_echo_skb(dev, -1, true);
1140 	if (work_done) {
1141 		if (!priv->resetting && !priv->closing &&
1142 		    !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1143 			netif_wake_queue(dev);
1144 
1145 		/* With napi we don't get TX interrupts for a while,
1146 		 * so prevent a running reset while catching up
1147 		 */
1148 		if (priv->need_txbug_workaround)
1149 			del_timer(&priv->hang_timer);
1150 	}
1151 
1152 	spin_unlock_irqrestore(&priv->lock, flags);
1153 }
1154 
1155 static int grcan_receive(struct net_device *dev, int budget)
1156 {
1157 	struct grcan_priv *priv = netdev_priv(dev);
1158 	struct grcan_registers __iomem *regs = priv->regs;
1159 	struct grcan_dma *dma = &priv->dma;
1160 	struct net_device_stats *stats = &dev->stats;
1161 	struct can_frame *cf;
1162 	struct sk_buff *skb;
1163 	u32 wr, rd, startrd;
1164 	u32 *slot;
1165 	u32 i, rtr, eff, j, shift;
1166 	int work_done = 0;
1167 
1168 	rd = grcan_read_reg(&regs->rxrd);
1169 	startrd = rd;
1170 	for (work_done = 0; work_done < budget; work_done++) {
1171 		/* Check for packet to receive */
1172 		wr = grcan_read_reg(&regs->rxwr);
1173 		if (rd == wr)
1174 			break;
1175 
1176 		/* Take care of packet */
1177 		skb = alloc_can_skb(dev, &cf);
1178 		if (skb == NULL) {
1179 			netdev_err(dev,
1180 				   "dropping frame: skb allocation failed\n");
1181 			stats->rx_dropped++;
1182 			continue;
1183 		}
1184 
1185 		slot = dma->rx.buf + rd;
1186 		eff = slot[0] & GRCAN_MSG_IDE;
1187 		rtr = slot[0] & GRCAN_MSG_RTR;
1188 		if (eff) {
1189 			cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1190 				      >> GRCAN_MSG_EID_BIT);
1191 			cf->can_id |= CAN_EFF_FLAG;
1192 		} else {
1193 			cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1194 				      >> GRCAN_MSG_BID_BIT);
1195 		}
1196 		cf->len = can_cc_dlc2len((slot[1] & GRCAN_MSG_DLC)
1197 					  >> GRCAN_MSG_DLC_BIT);
1198 		if (rtr) {
1199 			cf->can_id |= CAN_RTR_FLAG;
1200 		} else {
1201 			for (i = 0; i < cf->len; i++) {
1202 				j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1203 				shift = GRCAN_MSG_DATA_SHIFT(i);
1204 				cf->data[i] = (u8)(slot[j] >> shift);
1205 			}
1206 
1207 			stats->rx_bytes += cf->len;
1208 		}
1209 		stats->rx_packets++;
1210 
1211 		netif_receive_skb(skb);
1212 
1213 		rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1214 	}
1215 
1216 	/* Make sure everything is read before allowing hardware to
1217 	 * use the memory
1218 	 */
1219 	mb();
1220 
1221 	/* Update read pointer - no need to check for ongoing */
1222 	if (likely(rd != startrd))
1223 		grcan_write_reg(&regs->rxrd, rd);
1224 
1225 	return work_done;
1226 }
1227 
1228 static int grcan_poll(struct napi_struct *napi, int budget)
1229 {
1230 	struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1231 	struct net_device *dev = priv->dev;
1232 	struct grcan_registers __iomem *regs = priv->regs;
1233 	unsigned long flags;
1234 	int work_done;
1235 
1236 	work_done = grcan_receive(dev, budget);
1237 
1238 	grcan_transmit_catch_up(dev);
1239 
1240 	if (work_done < budget) {
1241 		napi_complete(napi);
1242 
1243 		/* Guarantee no interference with a running reset that otherwise
1244 		 * could turn off interrupts.
1245 		 */
1246 		spin_lock_irqsave(&priv->lock, flags);
1247 
1248 		/* Enable tx and rx interrupts again. No need to check
1249 		 * priv->closing as napi_disable in grcan_close is waiting for
1250 		 * scheduled napi calls to finish.
1251 		 */
1252 		grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1253 
1254 		spin_unlock_irqrestore(&priv->lock, flags);
1255 	}
1256 
1257 	return work_done;
1258 }
1259 
1260 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
1261  * drop a frame in one-shot mode or indicate a busy device otherwise.
1262  *
1263  * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1264  * value that should be returned by grcan_start_xmit when aborting the xmit.
1265  */
1266 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1267 				  u32 txwr, u32 oneshotmode,
1268 				  netdev_tx_t *netdev_tx_status)
1269 {
1270 	struct grcan_priv *priv = netdev_priv(dev);
1271 	struct grcan_registers __iomem *regs = priv->regs;
1272 	struct grcan_dma *dma = &priv->dma;
1273 	int i;
1274 	unsigned long flags;
1275 
1276 	/* Wait a while for ongoing to be cleared or read pointer to catch up to
1277 	 * write pointer. The latter is needed due to a bug in older versions of
1278 	 * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1279 	 * transmission fails.
1280 	 */
1281 	for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1282 		udelay(1);
1283 		if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1284 		    grcan_read_reg(&regs->txrd) == txwr) {
1285 			return 0;
1286 		}
1287 	}
1288 
1289 	/* Clean up, in case the situation was not resolved */
1290 	spin_lock_irqsave(&priv->lock, flags);
1291 	if (!priv->resetting && !priv->closing) {
1292 		/* Queue might have been stopped earlier in grcan_start_xmit */
1293 		if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1294 			netif_wake_queue(dev);
1295 		/* Set a timer to resolve a hanged tx controller */
1296 		if (!timer_pending(&priv->hang_timer))
1297 			grcan_reset_timer(&priv->hang_timer,
1298 					  priv->can.bittiming.bitrate);
1299 	}
1300 	spin_unlock_irqrestore(&priv->lock, flags);
1301 
1302 	if (oneshotmode) {
1303 		/* In one-shot mode we should never end up here because
1304 		 * then the interrupt handler increases txrd on TXLOSS,
1305 		 * but it is consistent with one-shot mode to drop the
1306 		 * frame in this case.
1307 		 */
1308 		kfree_skb(skb);
1309 		*netdev_tx_status = NETDEV_TX_OK;
1310 	} else {
1311 		/* In normal mode the socket-can transmission queue get
1312 		 * to keep the frame so that it can be retransmitted
1313 		 * later
1314 		 */
1315 		*netdev_tx_status = NETDEV_TX_BUSY;
1316 	}
1317 	return -EBUSY;
1318 }
1319 
1320 /* Notes on the tx cyclic buffer handling:
1321  *
1322  * regs->txwr	- the next slot for the driver to put data to be sent
1323  * regs->txrd	- the next slot for the device to read data
1324  * priv->eskbp	- the next slot for the driver to call can_put_echo_skb for
1325  *
1326  * grcan_start_xmit can enter more messages as long as regs->txwr does
1327  * not reach priv->eskbp (within 1 message gap)
1328  *
1329  * The device sends messages until regs->txrd reaches regs->txwr
1330  *
1331  * The interrupt calls handler calls can_put_echo_skb until
1332  * priv->eskbp reaches regs->txrd
1333  */
1334 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1335 				    struct net_device *dev)
1336 {
1337 	struct grcan_priv *priv = netdev_priv(dev);
1338 	struct grcan_registers __iomem *regs = priv->regs;
1339 	struct grcan_dma *dma = &priv->dma;
1340 	struct can_frame *cf = (struct can_frame *)skb->data;
1341 	u32 id, txwr, txrd, space, txctrl;
1342 	int slotindex;
1343 	u32 *slot;
1344 	u32 i, rtr, eff, dlc, tmp, err;
1345 	int j, shift;
1346 	unsigned long flags;
1347 	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1348 
1349 	if (can_dev_dropped_skb(dev, skb))
1350 		return NETDEV_TX_OK;
1351 
1352 	/* Trying to transmit in silent mode will generate error interrupts, but
1353 	 * this should never happen - the queue should not have been started.
1354 	 */
1355 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1356 		return NETDEV_TX_BUSY;
1357 
1358 	/* Reads of priv->eskbp and shut-downs of the queue needs to
1359 	 * be atomic towards the updates to priv->eskbp and wake-ups
1360 	 * of the queue in the interrupt handler.
1361 	 */
1362 	spin_lock_irqsave(&priv->lock, flags);
1363 
1364 	txwr = grcan_read_reg(&regs->txwr);
1365 	space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1366 
1367 	slotindex = txwr / GRCAN_MSG_SIZE;
1368 	slot = dma->tx.buf + txwr;
1369 
1370 	if (unlikely(space == 1))
1371 		netif_stop_queue(dev);
1372 
1373 	spin_unlock_irqrestore(&priv->lock, flags);
1374 	/* End of critical section*/
1375 
1376 	/* This should never happen. If circular buffer is full, the
1377 	 * netif_stop_queue should have been stopped already.
1378 	 */
1379 	if (unlikely(!space)) {
1380 		netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1381 		return NETDEV_TX_BUSY;
1382 	}
1383 
1384 	/* Convert and write CAN message to DMA buffer */
1385 	eff = cf->can_id & CAN_EFF_FLAG;
1386 	rtr = cf->can_id & CAN_RTR_FLAG;
1387 	id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1388 	dlc = cf->len;
1389 	if (eff)
1390 		tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1391 	else
1392 		tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1393 	slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1394 
1395 	slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1396 	slot[2] = 0;
1397 	slot[3] = 0;
1398 	for (i = 0; i < dlc; i++) {
1399 		j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1400 		shift = GRCAN_MSG_DATA_SHIFT(i);
1401 		slot[j] |= cf->data[i] << shift;
1402 	}
1403 
1404 	/* Checking that channel has not been disabled. These cases
1405 	 * should never happen
1406 	 */
1407 	txctrl = grcan_read_reg(&regs->txctrl);
1408 	if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1409 		netdev_err(dev, "tx channel spuriously disabled\n");
1410 
1411 	if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1412 		netdev_err(dev, "one-shot mode spuriously disabled\n");
1413 
1414 	/* Bug workaround for old version of grcan where updating txwr
1415 	 * in the same clock cycle as the controller updates txrd to
1416 	 * the current txwr could hang the can controller
1417 	 */
1418 	if (priv->need_txbug_workaround) {
1419 		txrd = grcan_read_reg(&regs->txrd);
1420 		if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1421 			netdev_tx_t txstatus;
1422 
1423 			err = grcan_txbug_workaround(dev, skb, txwr,
1424 						     oneshotmode, &txstatus);
1425 			if (err)
1426 				return txstatus;
1427 		}
1428 	}
1429 
1430 	/* Prepare skb for echoing. This must be after the bug workaround above
1431 	 * as ownership of the skb is passed on by calling can_put_echo_skb.
1432 	 * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1433 	 * can_put_echo_skb would be an error unless other measures are
1434 	 * taken.
1435 	 */
1436 	can_put_echo_skb(skb, dev, slotindex, 0);
1437 
1438 	/* Make sure everything is written before allowing hardware to
1439 	 * read from the memory
1440 	 */
1441 	wmb();
1442 
1443 	/* Update write pointer to start transmission */
1444 	grcan_write_reg(&regs->txwr,
1445 			grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1446 
1447 	return NETDEV_TX_OK;
1448 }
1449 
1450 /* ========== Setting up sysfs interface and module parameters ========== */
1451 
1452 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1453 
1454 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)		\
1455 	static void grcan_sanitize_##name(struct platform_device *pd)	\
1456 	{								\
1457 		struct grcan_device_config grcan_default_config		\
1458 			= GRCAN_DEFAULT_DEVICE_CONFIG;			\
1459 		if (valcheckf(grcan_module_config.name)) {		\
1460 			dev_err(&pd->dev,				\
1461 				"Invalid module parameter value for "	\
1462 				#name " - setting default\n");		\
1463 			grcan_module_config.name =			\
1464 				grcan_default_config.name;		\
1465 		}							\
1466 	}								\
1467 	module_param_named(name, grcan_module_config.name,		\
1468 			   mtype, 0444);				\
1469 	MODULE_PARM_DESC(name, desc)
1470 
1471 #define GRCAN_CONFIG_ATTR(name, desc)					\
1472 	static ssize_t grcan_store_##name(struct device *sdev,		\
1473 					  struct device_attribute *att,	\
1474 					  const char *buf,		\
1475 					  size_t count)			\
1476 	{								\
1477 		struct net_device *dev = to_net_dev(sdev);		\
1478 		struct grcan_priv *priv = netdev_priv(dev);		\
1479 		u8 val;							\
1480 		int ret;						\
1481 		if (dev->flags & IFF_UP)				\
1482 			return -EBUSY;					\
1483 		ret = kstrtou8(buf, 0, &val);				\
1484 		if (ret < 0 || val > 1)					\
1485 			return -EINVAL;					\
1486 		priv->config.name = val;				\
1487 		return count;						\
1488 	}								\
1489 	static ssize_t grcan_show_##name(struct device *sdev,		\
1490 					 struct device_attribute *att,	\
1491 					 char *buf)			\
1492 	{								\
1493 		struct net_device *dev = to_net_dev(sdev);		\
1494 		struct grcan_priv *priv = netdev_priv(dev);		\
1495 		return sprintf(buf, "%d\n", priv->config.name);		\
1496 	}								\
1497 	static DEVICE_ATTR(name, 0644,					\
1498 			   grcan_show_##name,				\
1499 			   grcan_store_##name);				\
1500 	GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1501 
1502 /* The following configuration options are made available both via module
1503  * parameters and writable sysfs files. See the chapter about GRCAN in the
1504  * documentation for the GRLIB VHDL library for further details.
1505  */
1506 GRCAN_CONFIG_ATTR(enable0,
1507 		  "Configuration of physical interface 0. Determines\n"	\
1508 		  "the \"Enable 0\" bit of the configuration register.\n" \
1509 		  "Format: 0 | 1\nDefault: 0\n");
1510 
1511 GRCAN_CONFIG_ATTR(enable1,
1512 		  "Configuration of physical interface 1. Determines\n"	\
1513 		  "the \"Enable 1\" bit of the configuration register.\n" \
1514 		  "Format: 0 | 1\nDefault: 0\n");
1515 
1516 GRCAN_CONFIG_ATTR(select,
1517 		  "Select which physical interface to use.\n"	\
1518 		  "Format: 0 | 1\nDefault: 0\n");
1519 
1520 /* The tx and rx buffer size configuration options are only available via module
1521  * parameters.
1522  */
1523 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1524 		   "Sets the size of the tx buffer.\n"			\
1525 		   "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1526 		   "Default: 1024\n");
1527 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1528 		   "Sets the size of the rx buffer.\n"			\
1529 		   "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1530 		   "Default: 1024\n");
1531 
1532 /* Function that makes sure that configuration done using
1533  * module parameters are set to valid values
1534  */
1535 static void grcan_sanitize_module_config(struct platform_device *ofdev)
1536 {
1537 	grcan_sanitize_enable0(ofdev);
1538 	grcan_sanitize_enable1(ofdev);
1539 	grcan_sanitize_select(ofdev);
1540 	grcan_sanitize_txsize(ofdev);
1541 	grcan_sanitize_rxsize(ofdev);
1542 }
1543 
1544 static const struct attribute *const sysfs_grcan_attrs[] = {
1545 	/* Config attrs */
1546 	&dev_attr_enable0.attr,
1547 	&dev_attr_enable1.attr,
1548 	&dev_attr_select.attr,
1549 	NULL,
1550 };
1551 
1552 static const struct attribute_group sysfs_grcan_group = {
1553 	.name	= "grcan",
1554 	.attrs	= (struct attribute **)sysfs_grcan_attrs,
1555 };
1556 
1557 /* ========== Setting up the driver ========== */
1558 
1559 static const struct net_device_ops grcan_netdev_ops = {
1560 	.ndo_open	= grcan_open,
1561 	.ndo_stop	= grcan_close,
1562 	.ndo_start_xmit	= grcan_start_xmit,
1563 	.ndo_change_mtu = can_change_mtu,
1564 };
1565 
1566 static const struct ethtool_ops grcan_ethtool_ops = {
1567 	.get_ts_info = ethtool_op_get_ts_info,
1568 };
1569 
1570 static int grcan_setup_netdev(struct platform_device *ofdev,
1571 			      void __iomem *base,
1572 			      int irq, u32 ambafreq, bool txbug)
1573 {
1574 	struct net_device *dev;
1575 	struct grcan_priv *priv;
1576 	struct grcan_registers __iomem *regs;
1577 	int err;
1578 
1579 	dev = alloc_candev(sizeof(struct grcan_priv), 0);
1580 	if (!dev)
1581 		return -ENOMEM;
1582 
1583 	dev->irq = irq;
1584 	dev->flags |= IFF_ECHO;
1585 	dev->netdev_ops = &grcan_netdev_ops;
1586 	dev->ethtool_ops = &grcan_ethtool_ops;
1587 	dev->sysfs_groups[0] = &sysfs_grcan_group;
1588 
1589 	priv = netdev_priv(dev);
1590 	memcpy(&priv->config, &grcan_module_config,
1591 	       sizeof(struct grcan_device_config));
1592 	priv->dev = dev;
1593 	priv->ofdev_dev = &ofdev->dev;
1594 	priv->regs = base;
1595 	priv->can.bittiming_const = &grcan_bittiming_const;
1596 	priv->can.do_set_bittiming = grcan_set_bittiming;
1597 	priv->can.do_set_mode = grcan_set_mode;
1598 	priv->can.do_get_berr_counter = grcan_get_berr_counter;
1599 	priv->can.clock.freq = ambafreq;
1600 	priv->can.ctrlmode_supported =
1601 		CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1602 	priv->need_txbug_workaround = txbug;
1603 
1604 	/* Discover if triple sampling is supported by hardware */
1605 	regs = priv->regs;
1606 	grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1607 	grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1608 	if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1609 		priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1610 		dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1611 	}
1612 
1613 	spin_lock_init(&priv->lock);
1614 
1615 	if (priv->need_txbug_workaround) {
1616 		timer_setup(&priv->rr_timer, grcan_running_reset, 0);
1617 		timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0);
1618 	}
1619 
1620 	netif_napi_add_weight(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1621 
1622 	SET_NETDEV_DEV(dev, &ofdev->dev);
1623 	dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1624 		 priv->regs, dev->irq, priv->can.clock.freq);
1625 
1626 	err = register_candev(dev);
1627 	if (err)
1628 		goto exit_free_candev;
1629 
1630 	platform_set_drvdata(ofdev, dev);
1631 
1632 	/* Reset device to allow bit-timing to be set. No need to call
1633 	 * grcan_reset at this stage. That is done in grcan_open.
1634 	 */
1635 	grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1636 
1637 	return 0;
1638 exit_free_candev:
1639 	free_candev(dev);
1640 	return err;
1641 }
1642 
1643 static int grcan_probe(struct platform_device *ofdev)
1644 {
1645 	struct device_node *np = ofdev->dev.of_node;
1646 	struct device_node *sysid_parent;
1647 	u32 sysid, ambafreq;
1648 	int irq, err;
1649 	void __iomem *base;
1650 	bool txbug = true;
1651 
1652 	/* Compare GRLIB version number with the first that does not
1653 	 * have the tx bug (see start_xmit)
1654 	 */
1655 	sysid_parent = of_find_node_by_path("/ambapp0");
1656 	if (sysid_parent) {
1657 		err = of_property_read_u32(sysid_parent, "systemid", &sysid);
1658 		if (!err && ((sysid & GRLIB_VERSION_MASK) >=
1659 			     GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1660 			txbug = false;
1661 		of_node_put(sysid_parent);
1662 	}
1663 
1664 	err = of_property_read_u32(np, "freq", &ambafreq);
1665 	if (err) {
1666 		dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1667 		goto exit_error;
1668 	}
1669 
1670 	base = devm_platform_ioremap_resource(ofdev, 0);
1671 	if (IS_ERR(base)) {
1672 		err = PTR_ERR(base);
1673 		goto exit_error;
1674 	}
1675 
1676 	irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1677 	if (!irq) {
1678 		dev_err(&ofdev->dev, "no irq found\n");
1679 		err = -ENODEV;
1680 		goto exit_error;
1681 	}
1682 
1683 	grcan_sanitize_module_config(ofdev);
1684 
1685 	err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1686 	if (err)
1687 		goto exit_dispose_irq;
1688 
1689 	return 0;
1690 
1691 exit_dispose_irq:
1692 	irq_dispose_mapping(irq);
1693 exit_error:
1694 	dev_err(&ofdev->dev,
1695 		"%s socket CAN driver initialization failed with error %d\n",
1696 		DRV_NAME, err);
1697 	return err;
1698 }
1699 
1700 static void grcan_remove(struct platform_device *ofdev)
1701 {
1702 	struct net_device *dev = platform_get_drvdata(ofdev);
1703 	struct grcan_priv *priv = netdev_priv(dev);
1704 
1705 	unregister_candev(dev); /* Will in turn call grcan_close */
1706 
1707 	irq_dispose_mapping(dev->irq);
1708 	netif_napi_del(&priv->napi);
1709 	free_candev(dev);
1710 }
1711 
1712 static const struct of_device_id grcan_match[] = {
1713 	{.name = "GAISLER_GRCAN"},
1714 	{.name = "01_03d"},
1715 	{.name = "GAISLER_GRHCAN"},
1716 	{.name = "01_034"},
1717 	{},
1718 };
1719 
1720 MODULE_DEVICE_TABLE(of, grcan_match);
1721 
1722 static struct platform_driver grcan_driver = {
1723 	.driver = {
1724 		.name = DRV_NAME,
1725 		.of_match_table = grcan_match,
1726 	},
1727 	.probe = grcan_probe,
1728 	.remove = grcan_remove,
1729 };
1730 
1731 module_platform_driver(grcan_driver);
1732 
1733 MODULE_AUTHOR("Aeroflex Gaisler AB.");
1734 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1735 MODULE_LICENSE("GPL");
1736