1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN. 4 * 5 * 2012 (c) Aeroflex Gaisler AB 6 * 7 * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB 8 * VHDL IP core library. 9 * 10 * Full documentation of the GRCAN core can be found here: 11 * http://www.gaisler.com/products/grlib/grip.pdf 12 * 13 * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on 14 * open firmware properties. 15 * 16 * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the 17 * sysfs interface. 18 * 19 * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module 20 * parameters. 21 * 22 * Contributors: Andreas Larsson <andreas@gaisler.com> 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/interrupt.h> 28 #include <linux/netdevice.h> 29 #include <linux/delay.h> 30 #include <linux/io.h> 31 #include <linux/can/dev.h> 32 #include <linux/spinlock.h> 33 #include <linux/of_platform.h> 34 #include <linux/of_irq.h> 35 36 #include <linux/dma-mapping.h> 37 38 #define DRV_NAME "grcan" 39 40 #define GRCAN_NAPI_WEIGHT 32 41 42 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1) 43 44 struct grcan_registers { 45 u32 conf; /* 0x00 */ 46 u32 stat; /* 0x04 */ 47 u32 ctrl; /* 0x08 */ 48 u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)]; 49 u32 smask; /* 0x18 - CanMASK */ 50 u32 scode; /* 0x1c - CanCODE */ 51 u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)]; 52 u32 pimsr; /* 0x100 */ 53 u32 pimr; /* 0x104 */ 54 u32 pisr; /* 0x108 */ 55 u32 pir; /* 0x10C */ 56 u32 imr; /* 0x110 */ 57 u32 picr; /* 0x114 */ 58 u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)]; 59 u32 txctrl; /* 0x200 */ 60 u32 txaddr; /* 0x204 */ 61 u32 txsize; /* 0x208 */ 62 u32 txwr; /* 0x20C */ 63 u32 txrd; /* 0x210 */ 64 u32 txirq; /* 0x214 */ 65 u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)]; 66 u32 rxctrl; /* 0x300 */ 67 u32 rxaddr; /* 0x304 */ 68 u32 rxsize; /* 0x308 */ 69 u32 rxwr; /* 0x30C */ 70 u32 rxrd; /* 0x310 */ 71 u32 rxirq; /* 0x314 */ 72 u32 rxmask; /* 0x318 */ 73 u32 rxcode; /* 0x31C */ 74 }; 75 76 #define GRCAN_CONF_ABORT 0x00000001 77 #define GRCAN_CONF_ENABLE0 0x00000002 78 #define GRCAN_CONF_ENABLE1 0x00000004 79 #define GRCAN_CONF_SELECT 0x00000008 80 #define GRCAN_CONF_SILENT 0x00000010 81 #define GRCAN_CONF_SAM 0x00000020 /* Available in some hardware */ 82 #define GRCAN_CONF_BPR 0x00000300 /* Note: not BRP */ 83 #define GRCAN_CONF_RSJ 0x00007000 84 #define GRCAN_CONF_PS1 0x00f00000 85 #define GRCAN_CONF_PS2 0x000f0000 86 #define GRCAN_CONF_SCALER 0xff000000 87 #define GRCAN_CONF_OPERATION \ 88 (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1 \ 89 | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM) 90 #define GRCAN_CONF_TIMING \ 91 (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1 \ 92 | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER) 93 94 #define GRCAN_CONF_RSJ_MIN 1 95 #define GRCAN_CONF_RSJ_MAX 4 96 #define GRCAN_CONF_PS1_MIN 1 97 #define GRCAN_CONF_PS1_MAX 15 98 #define GRCAN_CONF_PS2_MIN 2 99 #define GRCAN_CONF_PS2_MAX 8 100 #define GRCAN_CONF_SCALER_MIN 0 101 #define GRCAN_CONF_SCALER_MAX 255 102 #define GRCAN_CONF_SCALER_INC 1 103 104 #define GRCAN_CONF_BPR_BIT 8 105 #define GRCAN_CONF_RSJ_BIT 12 106 #define GRCAN_CONF_PS1_BIT 20 107 #define GRCAN_CONF_PS2_BIT 16 108 #define GRCAN_CONF_SCALER_BIT 24 109 110 #define GRCAN_STAT_PASS 0x000001 111 #define GRCAN_STAT_OFF 0x000002 112 #define GRCAN_STAT_OR 0x000004 113 #define GRCAN_STAT_AHBERR 0x000008 114 #define GRCAN_STAT_ACTIVE 0x000010 115 #define GRCAN_STAT_RXERRCNT 0x00ff00 116 #define GRCAN_STAT_TXERRCNT 0xff0000 117 118 #define GRCAN_STAT_ERRCTR_RELATED (GRCAN_STAT_PASS | GRCAN_STAT_OFF) 119 120 #define GRCAN_STAT_RXERRCNT_BIT 8 121 #define GRCAN_STAT_TXERRCNT_BIT 16 122 123 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96 124 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127 125 126 #define GRCAN_CTRL_RESET 0x2 127 #define GRCAN_CTRL_ENABLE 0x1 128 129 #define GRCAN_TXCTRL_ENABLE 0x1 130 #define GRCAN_TXCTRL_ONGOING 0x2 131 #define GRCAN_TXCTRL_SINGLE 0x4 132 133 #define GRCAN_RXCTRL_ENABLE 0x1 134 #define GRCAN_RXCTRL_ONGOING 0x2 135 136 /* Relative offset of IRQ sources to AMBA Plug&Play */ 137 #define GRCAN_IRQIX_IRQ 0 138 #define GRCAN_IRQIX_TXSYNC 1 139 #define GRCAN_IRQIX_RXSYNC 2 140 141 #define GRCAN_IRQ_PASS 0x00001 142 #define GRCAN_IRQ_OFF 0x00002 143 #define GRCAN_IRQ_OR 0x00004 144 #define GRCAN_IRQ_RXAHBERR 0x00008 145 #define GRCAN_IRQ_TXAHBERR 0x00010 146 #define GRCAN_IRQ_RXIRQ 0x00020 147 #define GRCAN_IRQ_TXIRQ 0x00040 148 #define GRCAN_IRQ_RXFULL 0x00080 149 #define GRCAN_IRQ_TXEMPTY 0x00100 150 #define GRCAN_IRQ_RX 0x00200 151 #define GRCAN_IRQ_TX 0x00400 152 #define GRCAN_IRQ_RXSYNC 0x00800 153 #define GRCAN_IRQ_TXSYNC 0x01000 154 #define GRCAN_IRQ_RXERRCTR 0x02000 155 #define GRCAN_IRQ_TXERRCTR 0x04000 156 #define GRCAN_IRQ_RXMISS 0x08000 157 #define GRCAN_IRQ_TXLOSS 0x10000 158 159 #define GRCAN_IRQ_NONE 0 160 #define GRCAN_IRQ_ALL \ 161 (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR \ 162 | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR \ 163 | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ \ 164 | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY \ 165 | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC \ 166 | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR \ 167 | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS \ 168 | GRCAN_IRQ_TXLOSS) 169 170 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \ 171 | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF) 172 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR \ 173 | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR \ 174 | GRCAN_IRQ_TXLOSS) 175 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS) 176 177 #define GRCAN_MSG_SIZE 16 178 179 #define GRCAN_MSG_IDE 0x80000000 180 #define GRCAN_MSG_RTR 0x40000000 181 #define GRCAN_MSG_BID 0x1ffc0000 182 #define GRCAN_MSG_EID 0x1fffffff 183 #define GRCAN_MSG_IDE_BIT 31 184 #define GRCAN_MSG_RTR_BIT 30 185 #define GRCAN_MSG_BID_BIT 18 186 #define GRCAN_MSG_EID_BIT 0 187 188 #define GRCAN_MSG_DLC 0xf0000000 189 #define GRCAN_MSG_TXERRC 0x00ff0000 190 #define GRCAN_MSG_RXERRC 0x0000ff00 191 #define GRCAN_MSG_DLC_BIT 28 192 #define GRCAN_MSG_TXERRC_BIT 16 193 #define GRCAN_MSG_RXERRC_BIT 8 194 #define GRCAN_MSG_AHBERR 0x00000008 195 #define GRCAN_MSG_OR 0x00000004 196 #define GRCAN_MSG_OFF 0x00000002 197 #define GRCAN_MSG_PASS 0x00000001 198 199 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4) 200 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8) 201 202 #define GRCAN_BUFFER_ALIGNMENT 1024 203 #define GRCAN_DEFAULT_BUFFER_SIZE 1024 204 #define GRCAN_VALID_TR_SIZE_MASK 0x001fffc0 205 206 #define GRCAN_INVALID_BUFFER_SIZE(s) \ 207 ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK)) 208 209 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE) 210 #error "Invalid default buffer size" 211 #endif 212 213 struct grcan_dma_buffer { 214 size_t size; 215 void *buf; 216 dma_addr_t handle; 217 }; 218 219 struct grcan_dma { 220 size_t base_size; 221 void *base_buf; 222 dma_addr_t base_handle; 223 struct grcan_dma_buffer tx; 224 struct grcan_dma_buffer rx; 225 }; 226 227 /* GRCAN configuration parameters */ 228 struct grcan_device_config { 229 unsigned short enable0; 230 unsigned short enable1; 231 unsigned short select; 232 unsigned int txsize; 233 unsigned int rxsize; 234 }; 235 236 #define GRCAN_DEFAULT_DEVICE_CONFIG { \ 237 .enable0 = 0, \ 238 .enable1 = 0, \ 239 .select = 0, \ 240 .txsize = GRCAN_DEFAULT_BUFFER_SIZE, \ 241 .rxsize = GRCAN_DEFAULT_BUFFER_SIZE, \ 242 } 243 244 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION 4100 245 #define GRLIB_VERSION_MASK 0xffff 246 247 /* GRCAN private data structure */ 248 struct grcan_priv { 249 struct can_priv can; /* must be the first member */ 250 struct net_device *dev; 251 struct device *ofdev_dev; 252 struct napi_struct napi; 253 254 struct grcan_registers __iomem *regs; /* ioremap'ed registers */ 255 struct grcan_device_config config; 256 struct grcan_dma dma; 257 258 struct sk_buff **echo_skb; /* We allocate this on our own */ 259 260 /* The echo skb pointer, pointing into echo_skb and indicating which 261 * frames can be echoed back. See the "Notes on the tx cyclic buffer 262 * handling"-comment for grcan_start_xmit for more details. 263 */ 264 u32 eskbp; 265 266 /* Lock for controlling changes to the netif tx queue state, accesses to 267 * the echo_skb pointer eskbp and for making sure that a running reset 268 * and/or a close of the interface is done without interference from 269 * other parts of the code. 270 * 271 * The echo_skb pointer, eskbp, should only be accessed under this lock 272 * as it can be changed in several places and together with decisions on 273 * whether to wake up the tx queue. 274 * 275 * The tx queue must never be woken up if there is a running reset or 276 * close in progress. 277 * 278 * A running reset (see below on need_txbug_workaround) should never be 279 * done if the interface is closing down and several running resets 280 * should never be scheduled simultaneously. 281 */ 282 spinlock_t lock; 283 284 /* Whether a workaround is needed due to a bug in older hardware. In 285 * this case, the driver both tries to prevent the bug from being 286 * triggered and recovers, if the bug nevertheless happens, by doing a 287 * running reset. A running reset, resets the device and continues from 288 * where it were without being noticeable from outside the driver (apart 289 * from slight delays). 290 */ 291 bool need_txbug_workaround; 292 293 /* To trigger initization of running reset and to trigger running reset 294 * respectively in the case of a hanged device due to a txbug. 295 */ 296 struct timer_list hang_timer; 297 struct timer_list rr_timer; 298 299 /* To avoid waking up the netif queue and restarting timers 300 * when a reset is scheduled or when closing of the device is 301 * undergoing 302 */ 303 bool resetting; 304 bool closing; 305 }; 306 307 /* Wait time for a short wait for ongoing to clear */ 308 #define GRCAN_SHORTWAIT_USECS 10 309 310 /* Limit on the number of transmitted bits of an eff frame according to the CAN 311 * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits 312 * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7 313 * bits end of frame 314 */ 315 #define GRCAN_EFF_FRAME_MAX_BITS (1+32+6+8*8+16+2+7) 316 317 #if defined(__BIG_ENDIAN) 318 static inline u32 grcan_read_reg(u32 __iomem *reg) 319 { 320 return ioread32be(reg); 321 } 322 323 static inline void grcan_write_reg(u32 __iomem *reg, u32 val) 324 { 325 iowrite32be(val, reg); 326 } 327 #else 328 static inline u32 grcan_read_reg(u32 __iomem *reg) 329 { 330 return ioread32(reg); 331 } 332 333 static inline void grcan_write_reg(u32 __iomem *reg, u32 val) 334 { 335 iowrite32(val, reg); 336 } 337 #endif 338 339 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask) 340 { 341 grcan_write_reg(reg, grcan_read_reg(reg) & ~mask); 342 } 343 344 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask) 345 { 346 grcan_write_reg(reg, grcan_read_reg(reg) | mask); 347 } 348 349 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask) 350 { 351 return grcan_read_reg(reg) & mask; 352 } 353 354 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask) 355 { 356 u32 old = grcan_read_reg(reg); 357 358 grcan_write_reg(reg, (old & ~mask) | (value & mask)); 359 } 360 361 /* a and b should both be in [0,size] and a == b == size should not hold */ 362 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size) 363 { 364 u32 sum = a + b; 365 366 if (sum < size) 367 return sum; 368 else 369 return sum - size; 370 } 371 372 /* a and b should both be in [0,size) */ 373 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size) 374 { 375 return grcan_ring_add(a, size - b, size); 376 } 377 378 /* Available slots for new transmissions */ 379 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp) 380 { 381 u32 slots = txsize / GRCAN_MSG_SIZE - 1; 382 u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE; 383 384 return slots - used; 385 } 386 387 /* Configuration parameters that can be set via module parameters */ 388 static struct grcan_device_config grcan_module_config = 389 GRCAN_DEFAULT_DEVICE_CONFIG; 390 391 static const struct can_bittiming_const grcan_bittiming_const = { 392 .name = DRV_NAME, 393 .tseg1_min = GRCAN_CONF_PS1_MIN + 1, 394 .tseg1_max = GRCAN_CONF_PS1_MAX + 1, 395 .tseg2_min = GRCAN_CONF_PS2_MIN, 396 .tseg2_max = GRCAN_CONF_PS2_MAX, 397 .sjw_max = GRCAN_CONF_RSJ_MAX, 398 .brp_min = GRCAN_CONF_SCALER_MIN + 1, 399 .brp_max = GRCAN_CONF_SCALER_MAX + 1, 400 .brp_inc = GRCAN_CONF_SCALER_INC, 401 }; 402 403 static int grcan_set_bittiming(struct net_device *dev) 404 { 405 struct grcan_priv *priv = netdev_priv(dev); 406 struct grcan_registers __iomem *regs = priv->regs; 407 struct can_bittiming *bt = &priv->can.bittiming; 408 u32 timing = 0; 409 int bpr, rsj, ps1, ps2, scaler; 410 411 /* Should never happen - function will not be called when 412 * device is up 413 */ 414 if (grcan_read_bits(®s->ctrl, GRCAN_CTRL_ENABLE)) 415 return -EBUSY; 416 417 bpr = 0; /* Note bpr and brp are different concepts */ 418 rsj = bt->sjw; 419 ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */ 420 ps2 = bt->phase_seg2; 421 scaler = (bt->brp - 1); 422 netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d", 423 bpr, rsj, ps1, ps2, scaler); 424 if (!(ps1 > ps2)) { 425 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n", 426 ps1, ps2); 427 return -EINVAL; 428 } 429 if (!(ps2 >= rsj)) { 430 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n", 431 ps2, rsj); 432 return -EINVAL; 433 } 434 435 timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR; 436 timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ; 437 timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1; 438 timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2; 439 timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER; 440 netdev_info(dev, "setting timing=0x%x\n", timing); 441 grcan_write_bits(®s->conf, timing, GRCAN_CONF_TIMING); 442 443 return 0; 444 } 445 446 static int grcan_get_berr_counter(const struct net_device *dev, 447 struct can_berr_counter *bec) 448 { 449 struct grcan_priv *priv = netdev_priv(dev); 450 struct grcan_registers __iomem *regs = priv->regs; 451 u32 status = grcan_read_reg(®s->stat); 452 453 bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT; 454 bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT; 455 return 0; 456 } 457 458 static int grcan_poll(struct napi_struct *napi, int budget); 459 460 /* Reset device, but keep configuration information */ 461 static void grcan_reset(struct net_device *dev) 462 { 463 struct grcan_priv *priv = netdev_priv(dev); 464 struct grcan_registers __iomem *regs = priv->regs; 465 u32 config = grcan_read_reg(®s->conf); 466 467 grcan_set_bits(®s->ctrl, GRCAN_CTRL_RESET); 468 grcan_write_reg(®s->conf, config); 469 470 priv->eskbp = grcan_read_reg(®s->txrd); 471 priv->can.state = CAN_STATE_STOPPED; 472 473 /* Turn off hardware filtering - regs->rxcode set to 0 by reset */ 474 grcan_write_reg(®s->rxmask, 0); 475 } 476 477 /* stop device without changing any configurations */ 478 static void grcan_stop_hardware(struct net_device *dev) 479 { 480 struct grcan_priv *priv = netdev_priv(dev); 481 struct grcan_registers __iomem *regs = priv->regs; 482 483 grcan_write_reg(®s->imr, GRCAN_IRQ_NONE); 484 grcan_clear_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 485 grcan_clear_bits(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 486 grcan_clear_bits(®s->ctrl, GRCAN_CTRL_ENABLE); 487 } 488 489 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo 490 * is true and free them otherwise. 491 * 492 * If budget is >= 0, stop after handling at most budget skbs. Otherwise, 493 * continue until priv->eskbp catches up to regs->txrd. 494 * 495 * priv->lock *must* be held when calling this function 496 */ 497 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo) 498 { 499 struct grcan_priv *priv = netdev_priv(dev); 500 struct grcan_registers __iomem *regs = priv->regs; 501 struct grcan_dma *dma = &priv->dma; 502 struct net_device_stats *stats = &dev->stats; 503 int i, work_done; 504 505 /* Updates to priv->eskbp and wake-ups of the queue needs to 506 * be atomic towards the reads of priv->eskbp and shut-downs 507 * of the queue in grcan_start_xmit. 508 */ 509 u32 txrd = grcan_read_reg(®s->txrd); 510 511 for (work_done = 0; work_done < budget || budget < 0; work_done++) { 512 if (priv->eskbp == txrd) 513 break; 514 i = priv->eskbp / GRCAN_MSG_SIZE; 515 if (echo) { 516 /* Normal echo of messages */ 517 stats->tx_packets++; 518 stats->tx_bytes += can_get_echo_skb(dev, i, NULL); 519 } else { 520 /* For cleanup of untransmitted messages */ 521 can_free_echo_skb(dev, i, NULL); 522 } 523 524 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE, 525 dma->tx.size); 526 txrd = grcan_read_reg(®s->txrd); 527 } 528 return work_done; 529 } 530 531 static void grcan_lost_one_shot_frame(struct net_device *dev) 532 { 533 struct grcan_priv *priv = netdev_priv(dev); 534 struct grcan_registers __iomem *regs = priv->regs; 535 struct grcan_dma *dma = &priv->dma; 536 u32 txrd; 537 unsigned long flags; 538 539 spin_lock_irqsave(&priv->lock, flags); 540 541 catch_up_echo_skb(dev, -1, true); 542 543 if (unlikely(grcan_read_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE))) { 544 /* Should never happen */ 545 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n"); 546 } else { 547 /* By the time an GRCAN_IRQ_TXLOSS is generated in 548 * one-shot mode there is no problem in writing 549 * to TXRD even in versions of the hardware in 550 * which GRCAN_TXCTRL_ONGOING is not cleared properly 551 * in one-shot mode. 552 */ 553 554 /* Skip message and discard echo-skb */ 555 txrd = grcan_read_reg(®s->txrd); 556 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size); 557 grcan_write_reg(®s->txrd, txrd); 558 catch_up_echo_skb(dev, -1, false); 559 560 if (!priv->resetting && !priv->closing && 561 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) { 562 netif_wake_queue(dev); 563 grcan_set_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 564 } 565 } 566 567 spin_unlock_irqrestore(&priv->lock, flags); 568 } 569 570 static void grcan_err(struct net_device *dev, u32 sources, u32 status) 571 { 572 struct grcan_priv *priv = netdev_priv(dev); 573 struct grcan_registers __iomem *regs = priv->regs; 574 struct grcan_dma *dma = &priv->dma; 575 struct net_device_stats *stats = &dev->stats; 576 struct can_frame cf; 577 578 /* Zero potential error_frame */ 579 memset(&cf, 0, sizeof(cf)); 580 581 /* Message lost interrupt. This might be due to arbitration error, but 582 * is also triggered when there is no one else on the can bus or when 583 * there is a problem with the hardware interface or the bus itself. As 584 * arbitration errors can not be singled out, no error frames are 585 * generated reporting this event as an arbitration error. 586 */ 587 if (sources & GRCAN_IRQ_TXLOSS) { 588 /* Take care of failed one-shot transmit */ 589 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 590 grcan_lost_one_shot_frame(dev); 591 592 /* Stop printing as soon as error passive or bus off is in 593 * effect to limit the amount of txloss debug printouts. 594 */ 595 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) { 596 netdev_dbg(dev, "tx message lost\n"); 597 stats->tx_errors++; 598 } 599 } 600 601 /* Conditions dealing with the error counters. There is no interrupt for 602 * error warning, but there are interrupts for increases of the error 603 * counters. 604 */ 605 if ((sources & GRCAN_IRQ_ERRCTR_RELATED) || 606 (status & GRCAN_STAT_ERRCTR_RELATED)) { 607 enum can_state state = priv->can.state; 608 enum can_state oldstate = state; 609 u32 txerr = (status & GRCAN_STAT_TXERRCNT) 610 >> GRCAN_STAT_TXERRCNT_BIT; 611 u32 rxerr = (status & GRCAN_STAT_RXERRCNT) 612 >> GRCAN_STAT_RXERRCNT_BIT; 613 614 /* Figure out current state */ 615 if (status & GRCAN_STAT_OFF) { 616 state = CAN_STATE_BUS_OFF; 617 } else if (status & GRCAN_STAT_PASS) { 618 state = CAN_STATE_ERROR_PASSIVE; 619 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT || 620 rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) { 621 state = CAN_STATE_ERROR_WARNING; 622 } else { 623 state = CAN_STATE_ERROR_ACTIVE; 624 } 625 626 /* Handle and report state changes */ 627 if (state != oldstate) { 628 switch (state) { 629 case CAN_STATE_BUS_OFF: 630 netdev_dbg(dev, "bus-off\n"); 631 netif_carrier_off(dev); 632 priv->can.can_stats.bus_off++; 633 634 /* Prevent the hardware from recovering from bus 635 * off on its own if restart is disabled. 636 */ 637 if (!priv->can.restart_ms) 638 grcan_stop_hardware(dev); 639 640 cf.can_id |= CAN_ERR_BUSOFF; 641 break; 642 643 case CAN_STATE_ERROR_PASSIVE: 644 netdev_dbg(dev, "Error passive condition\n"); 645 priv->can.can_stats.error_passive++; 646 647 cf.can_id |= CAN_ERR_CRTL; 648 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT) 649 cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 650 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT) 651 cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 652 break; 653 654 case CAN_STATE_ERROR_WARNING: 655 netdev_dbg(dev, "Error warning condition\n"); 656 priv->can.can_stats.error_warning++; 657 658 cf.can_id |= CAN_ERR_CRTL; 659 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) 660 cf.data[1] |= CAN_ERR_CRTL_TX_WARNING; 661 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) 662 cf.data[1] |= CAN_ERR_CRTL_RX_WARNING; 663 break; 664 665 case CAN_STATE_ERROR_ACTIVE: 666 netdev_dbg(dev, "Error active condition\n"); 667 cf.can_id |= CAN_ERR_CRTL; 668 break; 669 670 default: 671 /* There are no others at this point */ 672 break; 673 } 674 cf.data[6] = txerr; 675 cf.data[7] = rxerr; 676 priv->can.state = state; 677 } 678 679 /* Report automatic restarts */ 680 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) { 681 unsigned long flags; 682 683 cf.can_id |= CAN_ERR_RESTARTED; 684 netdev_dbg(dev, "restarted\n"); 685 priv->can.can_stats.restarts++; 686 netif_carrier_on(dev); 687 688 spin_lock_irqsave(&priv->lock, flags); 689 690 if (!priv->resetting && !priv->closing) { 691 u32 txwr = grcan_read_reg(®s->txwr); 692 693 if (grcan_txspace(dma->tx.size, txwr, 694 priv->eskbp)) 695 netif_wake_queue(dev); 696 } 697 698 spin_unlock_irqrestore(&priv->lock, flags); 699 } 700 } 701 702 /* Data overrun interrupt */ 703 if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) { 704 netdev_dbg(dev, "got data overrun interrupt\n"); 705 stats->rx_over_errors++; 706 stats->rx_errors++; 707 708 cf.can_id |= CAN_ERR_CRTL; 709 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 710 } 711 712 /* AHB bus error interrupts (not CAN bus errors) - shut down the 713 * device. 714 */ 715 if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) || 716 (status & GRCAN_STAT_AHBERR)) { 717 char *txrx = ""; 718 unsigned long flags; 719 720 if (sources & GRCAN_IRQ_TXAHBERR) { 721 txrx = "on tx "; 722 stats->tx_errors++; 723 } else if (sources & GRCAN_IRQ_RXAHBERR) { 724 txrx = "on rx "; 725 stats->rx_errors++; 726 } 727 netdev_err(dev, "Fatal AHB bus error %s- halting device\n", 728 txrx); 729 730 spin_lock_irqsave(&priv->lock, flags); 731 732 /* Prevent anything to be enabled again and halt device */ 733 priv->closing = true; 734 netif_stop_queue(dev); 735 grcan_stop_hardware(dev); 736 priv->can.state = CAN_STATE_STOPPED; 737 738 spin_unlock_irqrestore(&priv->lock, flags); 739 } 740 741 /* Pass on error frame if something to report, 742 * i.e. id contains some information 743 */ 744 if (cf.can_id) { 745 struct can_frame *skb_cf; 746 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf); 747 748 if (skb == NULL) { 749 netdev_dbg(dev, "could not allocate error frame\n"); 750 return; 751 } 752 skb_cf->can_id |= cf.can_id; 753 memcpy(skb_cf->data, cf.data, sizeof(cf.data)); 754 755 netif_rx(skb); 756 } 757 } 758 759 static irqreturn_t grcan_interrupt(int irq, void *dev_id) 760 { 761 struct net_device *dev = dev_id; 762 struct grcan_priv *priv = netdev_priv(dev); 763 struct grcan_registers __iomem *regs = priv->regs; 764 u32 sources, status; 765 766 /* Find out the source */ 767 sources = grcan_read_reg(®s->pimsr); 768 if (!sources) 769 return IRQ_NONE; 770 grcan_write_reg(®s->picr, sources); 771 status = grcan_read_reg(®s->stat); 772 773 /* If we got TX progress, the device has not hanged, 774 * so disable the hang timer 775 */ 776 if (priv->need_txbug_workaround && 777 (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) { 778 del_timer(&priv->hang_timer); 779 } 780 781 /* Frame(s) received or transmitted */ 782 if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) { 783 /* Disable tx/rx interrupts and schedule poll(). No need for 784 * locking as interference from a running reset at worst leads 785 * to an extra interrupt. 786 */ 787 grcan_clear_bits(®s->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX); 788 napi_schedule(&priv->napi); 789 } 790 791 /* (Potential) error conditions to take care of */ 792 if (sources & GRCAN_IRQ_ERRORS) 793 grcan_err(dev, sources, status); 794 795 return IRQ_HANDLED; 796 } 797 798 /* Reset device and restart operations from where they were. 799 * 800 * This assumes that RXCTRL & RXCTRL is properly disabled and that RX 801 * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug 802 * for single shot) 803 */ 804 static void grcan_running_reset(struct timer_list *t) 805 { 806 struct grcan_priv *priv = from_timer(priv, t, rr_timer); 807 struct net_device *dev = priv->dev; 808 struct grcan_registers __iomem *regs = priv->regs; 809 unsigned long flags; 810 811 /* This temporarily messes with eskbp, so we need to lock 812 * priv->lock 813 */ 814 spin_lock_irqsave(&priv->lock, flags); 815 816 priv->resetting = false; 817 del_timer(&priv->hang_timer); 818 del_timer(&priv->rr_timer); 819 820 if (!priv->closing) { 821 /* Save and reset - config register preserved by grcan_reset */ 822 u32 imr = grcan_read_reg(®s->imr); 823 824 u32 txaddr = grcan_read_reg(®s->txaddr); 825 u32 txsize = grcan_read_reg(®s->txsize); 826 u32 txwr = grcan_read_reg(®s->txwr); 827 u32 txrd = grcan_read_reg(®s->txrd); 828 u32 eskbp = priv->eskbp; 829 830 u32 rxaddr = grcan_read_reg(®s->rxaddr); 831 u32 rxsize = grcan_read_reg(®s->rxsize); 832 u32 rxwr = grcan_read_reg(®s->rxwr); 833 u32 rxrd = grcan_read_reg(®s->rxrd); 834 835 grcan_reset(dev); 836 837 /* Restore */ 838 grcan_write_reg(®s->txaddr, txaddr); 839 grcan_write_reg(®s->txsize, txsize); 840 grcan_write_reg(®s->txwr, txwr); 841 grcan_write_reg(®s->txrd, txrd); 842 priv->eskbp = eskbp; 843 844 grcan_write_reg(®s->rxaddr, rxaddr); 845 grcan_write_reg(®s->rxsize, rxsize); 846 grcan_write_reg(®s->rxwr, rxwr); 847 grcan_write_reg(®s->rxrd, rxrd); 848 849 /* Turn on device again */ 850 grcan_write_reg(®s->imr, imr); 851 priv->can.state = CAN_STATE_ERROR_ACTIVE; 852 grcan_write_reg(®s->txctrl, GRCAN_TXCTRL_ENABLE 853 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT 854 ? GRCAN_TXCTRL_SINGLE : 0)); 855 grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 856 grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE); 857 858 /* Start queue if there is size and listen-onle mode is not 859 * enabled 860 */ 861 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) && 862 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 863 netif_wake_queue(dev); 864 } 865 866 spin_unlock_irqrestore(&priv->lock, flags); 867 868 netdev_err(dev, "Device reset and restored\n"); 869 } 870 871 /* Waiting time in usecs corresponding to the transmission of three maximum 872 * sized can frames in the given bitrate (in bits/sec). Waiting for this amount 873 * of time makes sure that the can controller have time to finish sending or 874 * receiving a frame with a good margin. 875 * 876 * usecs/sec * number of frames * bits/frame / bits/sec 877 */ 878 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate) 879 { 880 return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate; 881 } 882 883 /* Set timer so that it will not fire until after a period in which the can 884 * controller have a good margin to finish transmitting a frame unless it has 885 * hanged 886 */ 887 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate) 888 { 889 u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate)); 890 891 mod_timer(timer, jiffies + wait_jiffies); 892 } 893 894 /* Disable channels and schedule a running reset */ 895 static void grcan_initiate_running_reset(struct timer_list *t) 896 { 897 struct grcan_priv *priv = from_timer(priv, t, hang_timer); 898 struct net_device *dev = priv->dev; 899 struct grcan_registers __iomem *regs = priv->regs; 900 unsigned long flags; 901 902 netdev_err(dev, "Device seems hanged - reset scheduled\n"); 903 904 spin_lock_irqsave(&priv->lock, flags); 905 906 /* The main body of this function must never be executed again 907 * until after an execution of grcan_running_reset 908 */ 909 if (!priv->resetting && !priv->closing) { 910 priv->resetting = true; 911 netif_stop_queue(dev); 912 grcan_clear_bits(®s->txctrl, GRCAN_TXCTRL_ENABLE); 913 grcan_clear_bits(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 914 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate); 915 } 916 917 spin_unlock_irqrestore(&priv->lock, flags); 918 } 919 920 static void grcan_free_dma_buffers(struct net_device *dev) 921 { 922 struct grcan_priv *priv = netdev_priv(dev); 923 struct grcan_dma *dma = &priv->dma; 924 925 dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf, 926 dma->base_handle); 927 memset(dma, 0, sizeof(*dma)); 928 } 929 930 static int grcan_allocate_dma_buffers(struct net_device *dev, 931 size_t tsize, size_t rsize) 932 { 933 struct grcan_priv *priv = netdev_priv(dev); 934 struct grcan_dma *dma = &priv->dma; 935 struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx; 936 struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx; 937 size_t shift; 938 939 /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large, 940 * i.e. first buffer 941 */ 942 size_t maxs = max(tsize, rsize); 943 size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT); 944 945 /* Put the small buffer after that */ 946 size_t ssize = min(tsize, rsize); 947 948 /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */ 949 dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT; 950 dma->base_buf = dma_alloc_coherent(priv->ofdev_dev, 951 dma->base_size, 952 &dma->base_handle, 953 GFP_KERNEL); 954 955 if (!dma->base_buf) 956 return -ENOMEM; 957 958 dma->tx.size = tsize; 959 dma->rx.size = rsize; 960 961 large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT); 962 small->handle = large->handle + lsize; 963 shift = large->handle - dma->base_handle; 964 965 large->buf = dma->base_buf + shift; 966 small->buf = large->buf + lsize; 967 968 return 0; 969 } 970 971 /* priv->lock *must* be held when calling this function */ 972 static int grcan_start(struct net_device *dev) 973 { 974 struct grcan_priv *priv = netdev_priv(dev); 975 struct grcan_registers __iomem *regs = priv->regs; 976 u32 confop, txctrl; 977 978 grcan_reset(dev); 979 980 grcan_write_reg(®s->txaddr, priv->dma.tx.handle); 981 grcan_write_reg(®s->txsize, priv->dma.tx.size); 982 /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */ 983 984 grcan_write_reg(®s->rxaddr, priv->dma.rx.handle); 985 grcan_write_reg(®s->rxsize, priv->dma.rx.size); 986 /* regs->rxwr and regs->rxrd already set to 0 by reset */ 987 988 /* Enable interrupts */ 989 grcan_read_reg(®s->pir); 990 grcan_write_reg(®s->imr, GRCAN_IRQ_DEFAULT); 991 992 /* Enable interfaces, channels and device */ 993 confop = GRCAN_CONF_ABORT 994 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0) 995 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0) 996 | (priv->config.select ? GRCAN_CONF_SELECT : 0) 997 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ? 998 GRCAN_CONF_SILENT : 0) 999 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? 1000 GRCAN_CONF_SAM : 0); 1001 grcan_write_bits(®s->conf, confop, GRCAN_CONF_OPERATION); 1002 txctrl = GRCAN_TXCTRL_ENABLE 1003 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT 1004 ? GRCAN_TXCTRL_SINGLE : 0); 1005 grcan_write_reg(®s->txctrl, txctrl); 1006 grcan_write_reg(®s->rxctrl, GRCAN_RXCTRL_ENABLE); 1007 grcan_write_reg(®s->ctrl, GRCAN_CTRL_ENABLE); 1008 1009 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1010 1011 return 0; 1012 } 1013 1014 static int grcan_set_mode(struct net_device *dev, enum can_mode mode) 1015 { 1016 struct grcan_priv *priv = netdev_priv(dev); 1017 unsigned long flags; 1018 int err = 0; 1019 1020 if (mode == CAN_MODE_START) { 1021 /* This might be called to restart the device to recover from 1022 * bus off errors 1023 */ 1024 spin_lock_irqsave(&priv->lock, flags); 1025 if (priv->closing || priv->resetting) { 1026 err = -EBUSY; 1027 } else { 1028 netdev_info(dev, "Restarting device\n"); 1029 grcan_start(dev); 1030 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1031 netif_wake_queue(dev); 1032 } 1033 spin_unlock_irqrestore(&priv->lock, flags); 1034 return err; 1035 } 1036 return -EOPNOTSUPP; 1037 } 1038 1039 static int grcan_open(struct net_device *dev) 1040 { 1041 struct grcan_priv *priv = netdev_priv(dev); 1042 struct grcan_dma *dma = &priv->dma; 1043 unsigned long flags; 1044 int err; 1045 1046 /* Allocate memory */ 1047 err = grcan_allocate_dma_buffers(dev, priv->config.txsize, 1048 priv->config.rxsize); 1049 if (err) { 1050 netdev_err(dev, "could not allocate DMA buffers\n"); 1051 return err; 1052 } 1053 1054 priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb), 1055 GFP_KERNEL); 1056 if (!priv->echo_skb) { 1057 err = -ENOMEM; 1058 goto exit_free_dma_buffers; 1059 } 1060 priv->can.echo_skb_max = dma->tx.size; 1061 priv->can.echo_skb = priv->echo_skb; 1062 1063 /* Get can device up */ 1064 err = open_candev(dev); 1065 if (err) 1066 goto exit_free_echo_skb; 1067 1068 err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED, 1069 dev->name, dev); 1070 if (err) 1071 goto exit_close_candev; 1072 1073 spin_lock_irqsave(&priv->lock, flags); 1074 1075 napi_enable(&priv->napi); 1076 grcan_start(dev); 1077 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1078 netif_start_queue(dev); 1079 priv->resetting = false; 1080 priv->closing = false; 1081 1082 spin_unlock_irqrestore(&priv->lock, flags); 1083 1084 return 0; 1085 1086 exit_close_candev: 1087 close_candev(dev); 1088 exit_free_echo_skb: 1089 kfree(priv->echo_skb); 1090 exit_free_dma_buffers: 1091 grcan_free_dma_buffers(dev); 1092 return err; 1093 } 1094 1095 static int grcan_close(struct net_device *dev) 1096 { 1097 struct grcan_priv *priv = netdev_priv(dev); 1098 unsigned long flags; 1099 1100 napi_disable(&priv->napi); 1101 1102 spin_lock_irqsave(&priv->lock, flags); 1103 1104 priv->closing = true; 1105 if (priv->need_txbug_workaround) { 1106 spin_unlock_irqrestore(&priv->lock, flags); 1107 del_timer_sync(&priv->hang_timer); 1108 del_timer_sync(&priv->rr_timer); 1109 spin_lock_irqsave(&priv->lock, flags); 1110 } 1111 netif_stop_queue(dev); 1112 grcan_stop_hardware(dev); 1113 priv->can.state = CAN_STATE_STOPPED; 1114 1115 spin_unlock_irqrestore(&priv->lock, flags); 1116 1117 free_irq(dev->irq, dev); 1118 close_candev(dev); 1119 1120 grcan_free_dma_buffers(dev); 1121 priv->can.echo_skb_max = 0; 1122 priv->can.echo_skb = NULL; 1123 kfree(priv->echo_skb); 1124 1125 return 0; 1126 } 1127 1128 static void grcan_transmit_catch_up(struct net_device *dev) 1129 { 1130 struct grcan_priv *priv = netdev_priv(dev); 1131 unsigned long flags; 1132 int work_done; 1133 1134 spin_lock_irqsave(&priv->lock, flags); 1135 1136 work_done = catch_up_echo_skb(dev, -1, true); 1137 if (work_done) { 1138 if (!priv->resetting && !priv->closing && 1139 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) 1140 netif_wake_queue(dev); 1141 1142 /* With napi we don't get TX interrupts for a while, 1143 * so prevent a running reset while catching up 1144 */ 1145 if (priv->need_txbug_workaround) 1146 del_timer(&priv->hang_timer); 1147 } 1148 1149 spin_unlock_irqrestore(&priv->lock, flags); 1150 } 1151 1152 static int grcan_receive(struct net_device *dev, int budget) 1153 { 1154 struct grcan_priv *priv = netdev_priv(dev); 1155 struct grcan_registers __iomem *regs = priv->regs; 1156 struct grcan_dma *dma = &priv->dma; 1157 struct net_device_stats *stats = &dev->stats; 1158 struct can_frame *cf; 1159 struct sk_buff *skb; 1160 u32 wr, rd, startrd; 1161 u32 *slot; 1162 u32 i, rtr, eff, j, shift; 1163 int work_done = 0; 1164 1165 rd = grcan_read_reg(®s->rxrd); 1166 startrd = rd; 1167 for (work_done = 0; work_done < budget; work_done++) { 1168 /* Check for packet to receive */ 1169 wr = grcan_read_reg(®s->rxwr); 1170 if (rd == wr) 1171 break; 1172 1173 /* Take care of packet */ 1174 skb = alloc_can_skb(dev, &cf); 1175 if (skb == NULL) { 1176 netdev_err(dev, 1177 "dropping frame: skb allocation failed\n"); 1178 stats->rx_dropped++; 1179 continue; 1180 } 1181 1182 slot = dma->rx.buf + rd; 1183 eff = slot[0] & GRCAN_MSG_IDE; 1184 rtr = slot[0] & GRCAN_MSG_RTR; 1185 if (eff) { 1186 cf->can_id = ((slot[0] & GRCAN_MSG_EID) 1187 >> GRCAN_MSG_EID_BIT); 1188 cf->can_id |= CAN_EFF_FLAG; 1189 } else { 1190 cf->can_id = ((slot[0] & GRCAN_MSG_BID) 1191 >> GRCAN_MSG_BID_BIT); 1192 } 1193 cf->len = can_cc_dlc2len((slot[1] & GRCAN_MSG_DLC) 1194 >> GRCAN_MSG_DLC_BIT); 1195 if (rtr) { 1196 cf->can_id |= CAN_RTR_FLAG; 1197 } else { 1198 for (i = 0; i < cf->len; i++) { 1199 j = GRCAN_MSG_DATA_SLOT_INDEX(i); 1200 shift = GRCAN_MSG_DATA_SHIFT(i); 1201 cf->data[i] = (u8)(slot[j] >> shift); 1202 } 1203 1204 stats->rx_bytes += cf->len; 1205 } 1206 stats->rx_packets++; 1207 1208 netif_receive_skb(skb); 1209 1210 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size); 1211 } 1212 1213 /* Make sure everything is read before allowing hardware to 1214 * use the memory 1215 */ 1216 mb(); 1217 1218 /* Update read pointer - no need to check for ongoing */ 1219 if (likely(rd != startrd)) 1220 grcan_write_reg(®s->rxrd, rd); 1221 1222 return work_done; 1223 } 1224 1225 static int grcan_poll(struct napi_struct *napi, int budget) 1226 { 1227 struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi); 1228 struct net_device *dev = priv->dev; 1229 struct grcan_registers __iomem *regs = priv->regs; 1230 unsigned long flags; 1231 int work_done; 1232 1233 work_done = grcan_receive(dev, budget); 1234 1235 grcan_transmit_catch_up(dev); 1236 1237 if (work_done < budget) { 1238 napi_complete(napi); 1239 1240 /* Guarantee no interference with a running reset that otherwise 1241 * could turn off interrupts. 1242 */ 1243 spin_lock_irqsave(&priv->lock, flags); 1244 1245 /* Enable tx and rx interrupts again. No need to check 1246 * priv->closing as napi_disable in grcan_close is waiting for 1247 * scheduled napi calls to finish. 1248 */ 1249 grcan_set_bits(®s->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX); 1250 1251 spin_unlock_irqrestore(&priv->lock, flags); 1252 } 1253 1254 return work_done; 1255 } 1256 1257 /* Work tx bug by waiting while for the risky situation to clear. If that fails, 1258 * drop a frame in one-shot mode or indicate a busy device otherwise. 1259 * 1260 * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the 1261 * value that should be returned by grcan_start_xmit when aborting the xmit. 1262 */ 1263 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb, 1264 u32 txwr, u32 oneshotmode, 1265 netdev_tx_t *netdev_tx_status) 1266 { 1267 struct grcan_priv *priv = netdev_priv(dev); 1268 struct grcan_registers __iomem *regs = priv->regs; 1269 struct grcan_dma *dma = &priv->dma; 1270 int i; 1271 unsigned long flags; 1272 1273 /* Wait a while for ongoing to be cleared or read pointer to catch up to 1274 * write pointer. The latter is needed due to a bug in older versions of 1275 * GRCAN in which ONGOING is not cleared properly one-shot mode when a 1276 * transmission fails. 1277 */ 1278 for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) { 1279 udelay(1); 1280 if (!grcan_read_bits(®s->txctrl, GRCAN_TXCTRL_ONGOING) || 1281 grcan_read_reg(®s->txrd) == txwr) { 1282 return 0; 1283 } 1284 } 1285 1286 /* Clean up, in case the situation was not resolved */ 1287 spin_lock_irqsave(&priv->lock, flags); 1288 if (!priv->resetting && !priv->closing) { 1289 /* Queue might have been stopped earlier in grcan_start_xmit */ 1290 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp)) 1291 netif_wake_queue(dev); 1292 /* Set a timer to resolve a hanged tx controller */ 1293 if (!timer_pending(&priv->hang_timer)) 1294 grcan_reset_timer(&priv->hang_timer, 1295 priv->can.bittiming.bitrate); 1296 } 1297 spin_unlock_irqrestore(&priv->lock, flags); 1298 1299 if (oneshotmode) { 1300 /* In one-shot mode we should never end up here because 1301 * then the interrupt handler increases txrd on TXLOSS, 1302 * but it is consistent with one-shot mode to drop the 1303 * frame in this case. 1304 */ 1305 kfree_skb(skb); 1306 *netdev_tx_status = NETDEV_TX_OK; 1307 } else { 1308 /* In normal mode the socket-can transmission queue get 1309 * to keep the frame so that it can be retransmitted 1310 * later 1311 */ 1312 *netdev_tx_status = NETDEV_TX_BUSY; 1313 } 1314 return -EBUSY; 1315 } 1316 1317 /* Notes on the tx cyclic buffer handling: 1318 * 1319 * regs->txwr - the next slot for the driver to put data to be sent 1320 * regs->txrd - the next slot for the device to read data 1321 * priv->eskbp - the next slot for the driver to call can_put_echo_skb for 1322 * 1323 * grcan_start_xmit can enter more messages as long as regs->txwr does 1324 * not reach priv->eskbp (within 1 message gap) 1325 * 1326 * The device sends messages until regs->txrd reaches regs->txwr 1327 * 1328 * The interrupt calls handler calls can_put_echo_skb until 1329 * priv->eskbp reaches regs->txrd 1330 */ 1331 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb, 1332 struct net_device *dev) 1333 { 1334 struct grcan_priv *priv = netdev_priv(dev); 1335 struct grcan_registers __iomem *regs = priv->regs; 1336 struct grcan_dma *dma = &priv->dma; 1337 struct can_frame *cf = (struct can_frame *)skb->data; 1338 u32 id, txwr, txrd, space, txctrl; 1339 int slotindex; 1340 u32 *slot; 1341 u32 i, rtr, eff, dlc, tmp, err; 1342 int j, shift; 1343 unsigned long flags; 1344 u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT; 1345 1346 if (can_dropped_invalid_skb(dev, skb)) 1347 return NETDEV_TX_OK; 1348 1349 /* Trying to transmit in silent mode will generate error interrupts, but 1350 * this should never happen - the queue should not have been started. 1351 */ 1352 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1353 return NETDEV_TX_BUSY; 1354 1355 /* Reads of priv->eskbp and shut-downs of the queue needs to 1356 * be atomic towards the updates to priv->eskbp and wake-ups 1357 * of the queue in the interrupt handler. 1358 */ 1359 spin_lock_irqsave(&priv->lock, flags); 1360 1361 txwr = grcan_read_reg(®s->txwr); 1362 space = grcan_txspace(dma->tx.size, txwr, priv->eskbp); 1363 1364 slotindex = txwr / GRCAN_MSG_SIZE; 1365 slot = dma->tx.buf + txwr; 1366 1367 if (unlikely(space == 1)) 1368 netif_stop_queue(dev); 1369 1370 spin_unlock_irqrestore(&priv->lock, flags); 1371 /* End of critical section*/ 1372 1373 /* This should never happen. If circular buffer is full, the 1374 * netif_stop_queue should have been stopped already. 1375 */ 1376 if (unlikely(!space)) { 1377 netdev_err(dev, "No buffer space, but queue is non-stopped.\n"); 1378 return NETDEV_TX_BUSY; 1379 } 1380 1381 /* Convert and write CAN message to DMA buffer */ 1382 eff = cf->can_id & CAN_EFF_FLAG; 1383 rtr = cf->can_id & CAN_RTR_FLAG; 1384 id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK); 1385 dlc = cf->len; 1386 if (eff) 1387 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID; 1388 else 1389 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID; 1390 slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp; 1391 1392 slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC); 1393 slot[2] = 0; 1394 slot[3] = 0; 1395 for (i = 0; i < dlc; i++) { 1396 j = GRCAN_MSG_DATA_SLOT_INDEX(i); 1397 shift = GRCAN_MSG_DATA_SHIFT(i); 1398 slot[j] |= cf->data[i] << shift; 1399 } 1400 1401 /* Checking that channel has not been disabled. These cases 1402 * should never happen 1403 */ 1404 txctrl = grcan_read_reg(®s->txctrl); 1405 if (!(txctrl & GRCAN_TXCTRL_ENABLE)) 1406 netdev_err(dev, "tx channel spuriously disabled\n"); 1407 1408 if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE)) 1409 netdev_err(dev, "one-shot mode spuriously disabled\n"); 1410 1411 /* Bug workaround for old version of grcan where updating txwr 1412 * in the same clock cycle as the controller updates txrd to 1413 * the current txwr could hang the can controller 1414 */ 1415 if (priv->need_txbug_workaround) { 1416 txrd = grcan_read_reg(®s->txrd); 1417 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) { 1418 netdev_tx_t txstatus; 1419 1420 err = grcan_txbug_workaround(dev, skb, txwr, 1421 oneshotmode, &txstatus); 1422 if (err) 1423 return txstatus; 1424 } 1425 } 1426 1427 /* Prepare skb for echoing. This must be after the bug workaround above 1428 * as ownership of the skb is passed on by calling can_put_echo_skb. 1429 * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to 1430 * can_put_echo_skb would be an error unless other measures are 1431 * taken. 1432 */ 1433 can_put_echo_skb(skb, dev, slotindex, 0); 1434 1435 /* Make sure everything is written before allowing hardware to 1436 * read from the memory 1437 */ 1438 wmb(); 1439 1440 /* Update write pointer to start transmission */ 1441 grcan_write_reg(®s->txwr, 1442 grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size)); 1443 1444 return NETDEV_TX_OK; 1445 } 1446 1447 /* ========== Setting up sysfs interface and module parameters ========== */ 1448 1449 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1) 1450 1451 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc) \ 1452 static void grcan_sanitize_##name(struct platform_device *pd) \ 1453 { \ 1454 struct grcan_device_config grcan_default_config \ 1455 = GRCAN_DEFAULT_DEVICE_CONFIG; \ 1456 if (valcheckf(grcan_module_config.name)) { \ 1457 dev_err(&pd->dev, \ 1458 "Invalid module parameter value for " \ 1459 #name " - setting default\n"); \ 1460 grcan_module_config.name = \ 1461 grcan_default_config.name; \ 1462 } \ 1463 } \ 1464 module_param_named(name, grcan_module_config.name, \ 1465 mtype, 0444); \ 1466 MODULE_PARM_DESC(name, desc) 1467 1468 #define GRCAN_CONFIG_ATTR(name, desc) \ 1469 static ssize_t grcan_store_##name(struct device *sdev, \ 1470 struct device_attribute *att, \ 1471 const char *buf, \ 1472 size_t count) \ 1473 { \ 1474 struct net_device *dev = to_net_dev(sdev); \ 1475 struct grcan_priv *priv = netdev_priv(dev); \ 1476 u8 val; \ 1477 int ret; \ 1478 if (dev->flags & IFF_UP) \ 1479 return -EBUSY; \ 1480 ret = kstrtou8(buf, 0, &val); \ 1481 if (ret < 0 || val > 1) \ 1482 return -EINVAL; \ 1483 priv->config.name = val; \ 1484 return count; \ 1485 } \ 1486 static ssize_t grcan_show_##name(struct device *sdev, \ 1487 struct device_attribute *att, \ 1488 char *buf) \ 1489 { \ 1490 struct net_device *dev = to_net_dev(sdev); \ 1491 struct grcan_priv *priv = netdev_priv(dev); \ 1492 return sprintf(buf, "%d\n", priv->config.name); \ 1493 } \ 1494 static DEVICE_ATTR(name, 0644, \ 1495 grcan_show_##name, \ 1496 grcan_store_##name); \ 1497 GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc) 1498 1499 /* The following configuration options are made available both via module 1500 * parameters and writable sysfs files. See the chapter about GRCAN in the 1501 * documentation for the GRLIB VHDL library for further details. 1502 */ 1503 GRCAN_CONFIG_ATTR(enable0, 1504 "Configuration of physical interface 0. Determines\n" \ 1505 "the \"Enable 0\" bit of the configuration register.\n" \ 1506 "Format: 0 | 1\nDefault: 0\n"); 1507 1508 GRCAN_CONFIG_ATTR(enable1, 1509 "Configuration of physical interface 1. Determines\n" \ 1510 "the \"Enable 1\" bit of the configuration register.\n" \ 1511 "Format: 0 | 1\nDefault: 0\n"); 1512 1513 GRCAN_CONFIG_ATTR(select, 1514 "Select which physical interface to use.\n" \ 1515 "Format: 0 | 1\nDefault: 0\n"); 1516 1517 /* The tx and rx buffer size configuration options are only available via module 1518 * parameters. 1519 */ 1520 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE, 1521 "Sets the size of the tx buffer.\n" \ 1522 "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \ 1523 "Default: 1024\n"); 1524 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE, 1525 "Sets the size of the rx buffer.\n" \ 1526 "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \ 1527 "Default: 1024\n"); 1528 1529 /* Function that makes sure that configuration done using 1530 * module parameters are set to valid values 1531 */ 1532 static void grcan_sanitize_module_config(struct platform_device *ofdev) 1533 { 1534 grcan_sanitize_enable0(ofdev); 1535 grcan_sanitize_enable1(ofdev); 1536 grcan_sanitize_select(ofdev); 1537 grcan_sanitize_txsize(ofdev); 1538 grcan_sanitize_rxsize(ofdev); 1539 } 1540 1541 static const struct attribute *const sysfs_grcan_attrs[] = { 1542 /* Config attrs */ 1543 &dev_attr_enable0.attr, 1544 &dev_attr_enable1.attr, 1545 &dev_attr_select.attr, 1546 NULL, 1547 }; 1548 1549 static const struct attribute_group sysfs_grcan_group = { 1550 .name = "grcan", 1551 .attrs = (struct attribute **)sysfs_grcan_attrs, 1552 }; 1553 1554 /* ========== Setting up the driver ========== */ 1555 1556 static const struct net_device_ops grcan_netdev_ops = { 1557 .ndo_open = grcan_open, 1558 .ndo_stop = grcan_close, 1559 .ndo_start_xmit = grcan_start_xmit, 1560 .ndo_change_mtu = can_change_mtu, 1561 }; 1562 1563 static int grcan_setup_netdev(struct platform_device *ofdev, 1564 void __iomem *base, 1565 int irq, u32 ambafreq, bool txbug) 1566 { 1567 struct net_device *dev; 1568 struct grcan_priv *priv; 1569 struct grcan_registers __iomem *regs; 1570 int err; 1571 1572 dev = alloc_candev(sizeof(struct grcan_priv), 0); 1573 if (!dev) 1574 return -ENOMEM; 1575 1576 dev->irq = irq; 1577 dev->flags |= IFF_ECHO; 1578 dev->netdev_ops = &grcan_netdev_ops; 1579 dev->sysfs_groups[0] = &sysfs_grcan_group; 1580 1581 priv = netdev_priv(dev); 1582 memcpy(&priv->config, &grcan_module_config, 1583 sizeof(struct grcan_device_config)); 1584 priv->dev = dev; 1585 priv->ofdev_dev = &ofdev->dev; 1586 priv->regs = base; 1587 priv->can.bittiming_const = &grcan_bittiming_const; 1588 priv->can.do_set_bittiming = grcan_set_bittiming; 1589 priv->can.do_set_mode = grcan_set_mode; 1590 priv->can.do_get_berr_counter = grcan_get_berr_counter; 1591 priv->can.clock.freq = ambafreq; 1592 priv->can.ctrlmode_supported = 1593 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT; 1594 priv->need_txbug_workaround = txbug; 1595 1596 /* Discover if triple sampling is supported by hardware */ 1597 regs = priv->regs; 1598 grcan_set_bits(®s->ctrl, GRCAN_CTRL_RESET); 1599 grcan_set_bits(®s->conf, GRCAN_CONF_SAM); 1600 if (grcan_read_bits(®s->conf, GRCAN_CONF_SAM)) { 1601 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES; 1602 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n"); 1603 } 1604 1605 spin_lock_init(&priv->lock); 1606 1607 if (priv->need_txbug_workaround) { 1608 timer_setup(&priv->rr_timer, grcan_running_reset, 0); 1609 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0); 1610 } 1611 1612 netif_napi_add_weight(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT); 1613 1614 SET_NETDEV_DEV(dev, &ofdev->dev); 1615 dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n", 1616 priv->regs, dev->irq, priv->can.clock.freq); 1617 1618 err = register_candev(dev); 1619 if (err) 1620 goto exit_free_candev; 1621 1622 platform_set_drvdata(ofdev, dev); 1623 1624 /* Reset device to allow bit-timing to be set. No need to call 1625 * grcan_reset at this stage. That is done in grcan_open. 1626 */ 1627 grcan_write_reg(®s->ctrl, GRCAN_CTRL_RESET); 1628 1629 return 0; 1630 exit_free_candev: 1631 free_candev(dev); 1632 return err; 1633 } 1634 1635 static int grcan_probe(struct platform_device *ofdev) 1636 { 1637 struct device_node *np = ofdev->dev.of_node; 1638 struct device_node *sysid_parent; 1639 u32 sysid, ambafreq; 1640 int irq, err; 1641 void __iomem *base; 1642 bool txbug = true; 1643 1644 /* Compare GRLIB version number with the first that does not 1645 * have the tx bug (see start_xmit) 1646 */ 1647 sysid_parent = of_find_node_by_path("/ambapp0"); 1648 if (sysid_parent) { 1649 of_node_get(sysid_parent); 1650 err = of_property_read_u32(sysid_parent, "systemid", &sysid); 1651 if (!err && ((sysid & GRLIB_VERSION_MASK) >= 1652 GRCAN_TXBUG_SAFE_GRLIB_VERSION)) 1653 txbug = false; 1654 of_node_put(sysid_parent); 1655 } 1656 1657 err = of_property_read_u32(np, "freq", &ambafreq); 1658 if (err) { 1659 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n"); 1660 goto exit_error; 1661 } 1662 1663 base = devm_platform_ioremap_resource(ofdev, 0); 1664 if (IS_ERR(base)) { 1665 err = PTR_ERR(base); 1666 goto exit_error; 1667 } 1668 1669 irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ); 1670 if (!irq) { 1671 dev_err(&ofdev->dev, "no irq found\n"); 1672 err = -ENODEV; 1673 goto exit_error; 1674 } 1675 1676 grcan_sanitize_module_config(ofdev); 1677 1678 err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug); 1679 if (err) 1680 goto exit_dispose_irq; 1681 1682 return 0; 1683 1684 exit_dispose_irq: 1685 irq_dispose_mapping(irq); 1686 exit_error: 1687 dev_err(&ofdev->dev, 1688 "%s socket CAN driver initialization failed with error %d\n", 1689 DRV_NAME, err); 1690 return err; 1691 } 1692 1693 static int grcan_remove(struct platform_device *ofdev) 1694 { 1695 struct net_device *dev = platform_get_drvdata(ofdev); 1696 struct grcan_priv *priv = netdev_priv(dev); 1697 1698 unregister_candev(dev); /* Will in turn call grcan_close */ 1699 1700 irq_dispose_mapping(dev->irq); 1701 netif_napi_del(&priv->napi); 1702 free_candev(dev); 1703 1704 return 0; 1705 } 1706 1707 static const struct of_device_id grcan_match[] = { 1708 {.name = "GAISLER_GRCAN"}, 1709 {.name = "01_03d"}, 1710 {.name = "GAISLER_GRHCAN"}, 1711 {.name = "01_034"}, 1712 {}, 1713 }; 1714 1715 MODULE_DEVICE_TABLE(of, grcan_match); 1716 1717 static struct platform_driver grcan_driver = { 1718 .driver = { 1719 .name = DRV_NAME, 1720 .of_match_table = grcan_match, 1721 }, 1722 .probe = grcan_probe, 1723 .remove = grcan_remove, 1724 }; 1725 1726 module_platform_driver(grcan_driver); 1727 1728 MODULE_AUTHOR("Aeroflex Gaisler AB."); 1729 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN"); 1730 MODULE_LICENSE("GPL"); 1731