1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /******************************************************************************* 3 * 4 * CTU CAN FD IP Core 5 * 6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU 7 * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded 8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU 9 * Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded 10 * 11 * Project advisors: 12 * Jiri Novak <jnovak@fel.cvut.cz> 13 * Pavel Pisa <pisa@cmp.felk.cvut.cz> 14 * 15 * Department of Measurement (http://meas.fel.cvut.cz/) 16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz) 17 * Czech Technical University (http://www.cvut.cz/) 18 ******************************************************************************/ 19 20 /* This file is autogenerated, DO NOT EDIT! */ 21 22 #ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__ 23 #define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__ 24 25 #include <linux/bits.h> 26 27 /* CAN_Frame_format memory map */ 28 enum ctu_can_fd_can_frame_format { 29 CTUCANFD_FRAME_FORMAT_W = 0x0, 30 CTUCANFD_IDENTIFIER_W = 0x4, 31 CTUCANFD_TIMESTAMP_L_W = 0x8, 32 CTUCANFD_TIMESTAMP_U_W = 0xc, 33 CTUCANFD_DATA_1_4_W = 0x10, 34 CTUCANFD_DATA_5_8_W = 0x14, 35 CTUCANFD_DATA_61_64_W = 0x4c, 36 }; 37 38 /* CAN_FD_Frame_format memory region */ 39 40 /* FRAME_FORMAT_W registers */ 41 #define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0) 42 #define REG_FRAME_FORMAT_W_RTR BIT(5) 43 #define REG_FRAME_FORMAT_W_IDE BIT(6) 44 #define REG_FRAME_FORMAT_W_FDF BIT(7) 45 #define REG_FRAME_FORMAT_W_BRS BIT(9) 46 #define REG_FRAME_FORMAT_W_ESI_RSV BIT(10) 47 #define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11) 48 49 /* IDENTIFIER_W registers */ 50 #define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0) 51 #define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18) 52 53 /* TIMESTAMP_L_W registers */ 54 #define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0) 55 56 /* TIMESTAMP_U_W registers */ 57 #define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0) 58 59 /* DATA_1_4_W registers */ 60 #define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0) 61 #define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8) 62 #define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16) 63 #define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24) 64 65 /* DATA_5_8_W registers */ 66 #define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0) 67 #define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8) 68 #define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16) 69 #define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24) 70 71 /* DATA_61_64_W registers */ 72 #define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0) 73 #define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8) 74 #define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16) 75 #define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24) 76 77 #endif 78