1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /******************************************************************************* 3 * 4 * CTU CAN FD IP Core 5 * 6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU 7 * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded 8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU 9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded 10 * 11 * Project advisors: 12 * Jiri Novak <jnovak@fel.cvut.cz> 13 * Pavel Pisa <pisa@cmp.felk.cvut.cz> 14 * 15 * Department of Measurement (http://meas.fel.cvut.cz/) 16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz) 17 * Czech Technical University (http://www.cvut.cz/) 18 ******************************************************************************/ 19 20 #include <linux/clk.h> 21 #include <linux/errno.h> 22 #include <linux/init.h> 23 #include <linux/bitfield.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/skbuff.h> 29 #include <linux/string.h> 30 #include <linux/types.h> 31 #include <linux/can/error.h> 32 #include <linux/pm_runtime.h> 33 34 #include "ctucanfd.h" 35 #include "ctucanfd_kregs.h" 36 #include "ctucanfd_kframe.h" 37 38 #ifdef DEBUG 39 #define ctucan_netdev_dbg(ndev, args...) \ 40 netdev_dbg(ndev, args) 41 #else 42 #define ctucan_netdev_dbg(...) do { } while (0) 43 #endif 44 45 #define CTUCANFD_ID 0xCAFD 46 47 /* TX buffer rotation: 48 * - when a buffer transitions to empty state, rotate order and priorities 49 * - if more buffers seem to transition at the same time, rotate by the number of buffers 50 * - it may be assumed that buffers transition to empty state in FIFO order (because we manage 51 * priorities that way) 52 * - at frame filling, do not rotate anything, just increment buffer modulo counter 53 */ 54 55 #define CTUCANFD_FLAG_RX_FFW_BUFFERED 1 56 57 #define CTUCAN_STATE_TO_TEXT_ENTRY(st) \ 58 [st] = #st 59 60 enum ctucan_txtb_status { 61 TXT_NOT_EXIST = 0x0, 62 TXT_RDY = 0x1, 63 TXT_TRAN = 0x2, 64 TXT_ABTP = 0x3, 65 TXT_TOK = 0x4, 66 TXT_ERR = 0x6, 67 TXT_ABT = 0x7, 68 TXT_ETY = 0x8, 69 }; 70 71 enum ctucan_txtb_command { 72 TXT_CMD_SET_EMPTY = 0x01, 73 TXT_CMD_SET_READY = 0x02, 74 TXT_CMD_SET_ABORT = 0x04 75 }; 76 77 static const struct can_bittiming_const ctu_can_fd_bit_timing_max = { 78 .name = "ctu_can_fd", 79 .tseg1_min = 2, 80 .tseg1_max = 190, 81 .tseg2_min = 1, 82 .tseg2_max = 63, 83 .sjw_max = 31, 84 .brp_min = 1, 85 .brp_max = 8, 86 .brp_inc = 1, 87 }; 88 89 static const struct can_bittiming_const ctu_can_fd_bit_timing_data_max = { 90 .name = "ctu_can_fd", 91 .tseg1_min = 2, 92 .tseg1_max = 94, 93 .tseg2_min = 1, 94 .tseg2_max = 31, 95 .sjw_max = 31, 96 .brp_min = 1, 97 .brp_max = 2, 98 .brp_inc = 1, 99 }; 100 101 static const char * const ctucan_state_strings[CAN_STATE_MAX] = { 102 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_ACTIVE), 103 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_WARNING), 104 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_PASSIVE), 105 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_BUS_OFF), 106 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_STOPPED), 107 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_SLEEPING) 108 }; 109 110 static void ctucan_write32_le(struct ctucan_priv *priv, 111 enum ctu_can_fd_can_registers reg, u32 val) 112 { 113 iowrite32(val, priv->mem_base + reg); 114 } 115 116 static void ctucan_write32_be(struct ctucan_priv *priv, 117 enum ctu_can_fd_can_registers reg, u32 val) 118 { 119 iowrite32be(val, priv->mem_base + reg); 120 } 121 122 static u32 ctucan_read32_le(struct ctucan_priv *priv, 123 enum ctu_can_fd_can_registers reg) 124 { 125 return ioread32(priv->mem_base + reg); 126 } 127 128 static u32 ctucan_read32_be(struct ctucan_priv *priv, 129 enum ctu_can_fd_can_registers reg) 130 { 131 return ioread32be(priv->mem_base + reg); 132 } 133 134 static void ctucan_write32(struct ctucan_priv *priv, enum ctu_can_fd_can_registers reg, u32 val) 135 { 136 priv->write_reg(priv, reg, val); 137 } 138 139 static u32 ctucan_read32(struct ctucan_priv *priv, enum ctu_can_fd_can_registers reg) 140 { 141 return priv->read_reg(priv, reg); 142 } 143 144 static void ctucan_write_txt_buf(struct ctucan_priv *priv, enum ctu_can_fd_can_registers buf_base, 145 u32 offset, u32 val) 146 { 147 priv->write_reg(priv, buf_base + offset, val); 148 } 149 150 #define CTU_CAN_FD_TXTNF(priv) (!!FIELD_GET(REG_STATUS_TXNF, ctucan_read32(priv, CTUCANFD_STATUS))) 151 #define CTU_CAN_FD_ENABLED(priv) (!!FIELD_GET(REG_MODE_ENA, ctucan_read32(priv, CTUCANFD_MODE))) 152 153 /** 154 * ctucan_state_to_str() - Converts CAN controller state code to corresponding text 155 * @state: CAN controller state code 156 * 157 * Return: Pointer to string representation of the error state 158 */ 159 static const char *ctucan_state_to_str(enum can_state state) 160 { 161 const char *txt = NULL; 162 163 if (state >= 0 && state < CAN_STATE_MAX) 164 txt = ctucan_state_strings[state]; 165 return txt ? txt : "UNKNOWN"; 166 } 167 168 /** 169 * ctucan_reset() - Issues software reset request to CTU CAN FD 170 * @ndev: Pointer to net_device structure 171 * 172 * Return: 0 for success, -%ETIMEDOUT if CAN controller does not leave reset 173 */ 174 static int ctucan_reset(struct net_device *ndev) 175 { 176 struct ctucan_priv *priv = netdev_priv(ndev); 177 int i = 100; 178 179 ctucan_write32(priv, CTUCANFD_MODE, REG_MODE_RST); 180 clear_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 181 182 do { 183 u16 device_id = FIELD_GET(REG_DEVICE_ID_DEVICE_ID, 184 ctucan_read32(priv, CTUCANFD_DEVICE_ID)); 185 186 if (device_id == 0xCAFD) 187 return 0; 188 if (!i--) { 189 netdev_warn(ndev, "device did not leave reset\n"); 190 return -ETIMEDOUT; 191 } 192 usleep_range(100, 200); 193 } while (1); 194 } 195 196 /** 197 * ctucan_set_btr() - Sets CAN bus bit timing in CTU CAN FD 198 * @ndev: Pointer to net_device structure 199 * @bt: Pointer to Bit timing structure 200 * @nominal: True - Nominal bit timing, False - Data bit timing 201 * 202 * Return: 0 - OK, -%EPERM if controller is enabled 203 */ 204 static int ctucan_set_btr(struct net_device *ndev, struct can_bittiming *bt, bool nominal) 205 { 206 struct ctucan_priv *priv = netdev_priv(ndev); 207 int max_ph1_len = 31; 208 u32 btr = 0; 209 u32 prop_seg = bt->prop_seg; 210 u32 phase_seg1 = bt->phase_seg1; 211 212 if (CTU_CAN_FD_ENABLED(priv)) { 213 netdev_err(ndev, "BUG! Cannot set bittiming - CAN is enabled\n"); 214 return -EPERM; 215 } 216 217 if (nominal) 218 max_ph1_len = 63; 219 220 /* The timing calculation functions have only constraints on tseg1, which is prop_seg + 221 * phase1_seg combined. tseg1 is then split in half and stored into prog_seg and phase_seg1. 222 * In CTU CAN FD, PROP is 6/7 bits wide but PH1 only 6/5, so we must re-distribute the 223 * values here. 224 */ 225 if (phase_seg1 > max_ph1_len) { 226 prop_seg += phase_seg1 - max_ph1_len; 227 phase_seg1 = max_ph1_len; 228 bt->prop_seg = prop_seg; 229 bt->phase_seg1 = phase_seg1; 230 } 231 232 if (nominal) { 233 btr = FIELD_PREP(REG_BTR_PROP, prop_seg); 234 btr |= FIELD_PREP(REG_BTR_PH1, phase_seg1); 235 btr |= FIELD_PREP(REG_BTR_PH2, bt->phase_seg2); 236 btr |= FIELD_PREP(REG_BTR_BRP, bt->brp); 237 btr |= FIELD_PREP(REG_BTR_SJW, bt->sjw); 238 239 ctucan_write32(priv, CTUCANFD_BTR, btr); 240 } else { 241 btr = FIELD_PREP(REG_BTR_FD_PROP_FD, prop_seg); 242 btr |= FIELD_PREP(REG_BTR_FD_PH1_FD, phase_seg1); 243 btr |= FIELD_PREP(REG_BTR_FD_PH2_FD, bt->phase_seg2); 244 btr |= FIELD_PREP(REG_BTR_FD_BRP_FD, bt->brp); 245 btr |= FIELD_PREP(REG_BTR_FD_SJW_FD, bt->sjw); 246 247 ctucan_write32(priv, CTUCANFD_BTR_FD, btr); 248 } 249 250 return 0; 251 } 252 253 /** 254 * ctucan_set_bittiming() - CAN set nominal bit timing routine 255 * @ndev: Pointer to net_device structure 256 * 257 * Return: 0 on success, -%EPERM on error 258 */ 259 static int ctucan_set_bittiming(struct net_device *ndev) 260 { 261 struct ctucan_priv *priv = netdev_priv(ndev); 262 struct can_bittiming *bt = &priv->can.bittiming; 263 264 /* Note that bt may be modified here */ 265 return ctucan_set_btr(ndev, bt, true); 266 } 267 268 /** 269 * ctucan_set_data_bittiming() - CAN set data bit timing routine 270 * @ndev: Pointer to net_device structure 271 * 272 * Return: 0 on success, -%EPERM on error 273 */ 274 static int ctucan_set_data_bittiming(struct net_device *ndev) 275 { 276 struct ctucan_priv *priv = netdev_priv(ndev); 277 struct can_bittiming *dbt = &priv->can.data_bittiming; 278 279 /* Note that dbt may be modified here */ 280 return ctucan_set_btr(ndev, dbt, false); 281 } 282 283 /** 284 * ctucan_set_secondary_sample_point() - Sets secondary sample point in CTU CAN FD 285 * @ndev: Pointer to net_device structure 286 * 287 * Return: 0 on success, -%EPERM if controller is enabled 288 */ 289 static int ctucan_set_secondary_sample_point(struct net_device *ndev) 290 { 291 struct ctucan_priv *priv = netdev_priv(ndev); 292 struct can_bittiming *dbt = &priv->can.data_bittiming; 293 int ssp_offset = 0; 294 u32 ssp_cfg = 0; /* No SSP by default */ 295 296 if (CTU_CAN_FD_ENABLED(priv)) { 297 netdev_err(ndev, "BUG! Cannot set SSP - CAN is enabled\n"); 298 return -EPERM; 299 } 300 301 /* Use SSP for bit-rates above 1 Mbits/s */ 302 if (dbt->bitrate > 1000000) { 303 /* Calculate SSP in minimal time quanta */ 304 ssp_offset = (priv->can.clock.freq / 1000) * dbt->sample_point / dbt->bitrate; 305 306 if (ssp_offset > 127) { 307 netdev_warn(ndev, "SSP offset saturated to 127\n"); 308 ssp_offset = 127; 309 } 310 311 ssp_cfg = FIELD_PREP(REG_TRV_DELAY_SSP_OFFSET, ssp_offset); 312 ssp_cfg |= FIELD_PREP(REG_TRV_DELAY_SSP_SRC, 0x1); 313 } 314 315 ctucan_write32(priv, CTUCANFD_TRV_DELAY, ssp_cfg); 316 317 return 0; 318 } 319 320 /** 321 * ctucan_set_mode() - Sets CTU CAN FDs mode 322 * @priv: Pointer to private data 323 * @mode: Pointer to controller modes to be set 324 */ 325 static void ctucan_set_mode(struct ctucan_priv *priv, const struct can_ctrlmode *mode) 326 { 327 u32 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); 328 329 mode_reg = (mode->flags & CAN_CTRLMODE_LOOPBACK) ? 330 (mode_reg | REG_MODE_ILBP) : 331 (mode_reg & ~REG_MODE_ILBP); 332 333 mode_reg = (mode->flags & CAN_CTRLMODE_LISTENONLY) ? 334 (mode_reg | REG_MODE_BMM) : 335 (mode_reg & ~REG_MODE_BMM); 336 337 mode_reg = (mode->flags & CAN_CTRLMODE_FD) ? 338 (mode_reg | REG_MODE_FDE) : 339 (mode_reg & ~REG_MODE_FDE); 340 341 mode_reg = (mode->flags & CAN_CTRLMODE_PRESUME_ACK) ? 342 (mode_reg | REG_MODE_ACF) : 343 (mode_reg & ~REG_MODE_ACF); 344 345 mode_reg = (mode->flags & CAN_CTRLMODE_FD_NON_ISO) ? 346 (mode_reg | REG_MODE_NISOFD) : 347 (mode_reg & ~REG_MODE_NISOFD); 348 349 /* One shot mode supported indirectly via Retransmit limit */ 350 mode_reg &= ~FIELD_PREP(REG_MODE_RTRTH, 0xF); 351 mode_reg = (mode->flags & CAN_CTRLMODE_ONE_SHOT) ? 352 (mode_reg | REG_MODE_RTRLE) : 353 (mode_reg & ~REG_MODE_RTRLE); 354 355 /* Some bits fixed: 356 * TSTM - Off, User shall not be able to change REC/TEC by hand during operation 357 */ 358 mode_reg &= ~REG_MODE_TSTM; 359 360 ctucan_write32(priv, CTUCANFD_MODE, mode_reg); 361 } 362 363 /** 364 * ctucan_chip_start() - This routine starts the driver 365 * @ndev: Pointer to net_device structure 366 * 367 * Routine expects that chip is in reset state. It setups initial 368 * Tx buffers for FIFO priorities, sets bittiming, enables interrupts, 369 * switches core to operational mode and changes controller 370 * state to %CAN_STATE_STOPPED. 371 * 372 * Return: 0 on success and failure value on error 373 */ 374 static int ctucan_chip_start(struct net_device *ndev) 375 { 376 struct ctucan_priv *priv = netdev_priv(ndev); 377 u32 int_ena, int_msk; 378 u32 mode_reg; 379 int err; 380 struct can_ctrlmode mode; 381 382 priv->txb_prio = 0x01234567; 383 priv->txb_head = 0; 384 priv->txb_tail = 0; 385 ctucan_write32(priv, CTUCANFD_TX_PRIORITY, priv->txb_prio); 386 387 /* Configure bit-rates and ssp */ 388 err = ctucan_set_bittiming(ndev); 389 if (err < 0) 390 return err; 391 392 err = ctucan_set_data_bittiming(ndev); 393 if (err < 0) 394 return err; 395 396 err = ctucan_set_secondary_sample_point(ndev); 397 if (err < 0) 398 return err; 399 400 /* Configure modes */ 401 mode.flags = priv->can.ctrlmode; 402 mode.mask = 0xFFFFFFFF; 403 ctucan_set_mode(priv, &mode); 404 405 /* Configure interrupts */ 406 int_ena = REG_INT_STAT_RBNEI | 407 REG_INT_STAT_TXBHCI | 408 REG_INT_STAT_EWLI | 409 REG_INT_STAT_FCSI; 410 411 /* Bus error reporting -> Allow Error/Arb.lost interrupts */ 412 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 413 int_ena |= REG_INT_STAT_ALI | 414 REG_INT_STAT_BEI; 415 } 416 417 int_msk = ~int_ena; /* Mask all disabled interrupts */ 418 419 /* It's after reset, so there is no need to clear anything */ 420 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, int_msk); 421 ctucan_write32(priv, CTUCANFD_INT_ENA_SET, int_ena); 422 423 /* Controller enters ERROR_ACTIVE on initial FCSI */ 424 priv->can.state = CAN_STATE_STOPPED; 425 426 /* Enable the controller */ 427 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); 428 mode_reg |= REG_MODE_ENA; 429 ctucan_write32(priv, CTUCANFD_MODE, mode_reg); 430 431 return 0; 432 } 433 434 /** 435 * ctucan_do_set_mode() - Sets mode of the driver 436 * @ndev: Pointer to net_device structure 437 * @mode: Tells the mode of the driver 438 * 439 * This check the drivers state and calls the corresponding modes to set. 440 * 441 * Return: 0 on success and failure value on error 442 */ 443 static int ctucan_do_set_mode(struct net_device *ndev, enum can_mode mode) 444 { 445 int ret; 446 447 switch (mode) { 448 case CAN_MODE_START: 449 ret = ctucan_reset(ndev); 450 if (ret < 0) 451 return ret; 452 ret = ctucan_chip_start(ndev); 453 if (ret < 0) { 454 netdev_err(ndev, "ctucan_chip_start failed!\n"); 455 return ret; 456 } 457 netif_wake_queue(ndev); 458 break; 459 default: 460 ret = -EOPNOTSUPP; 461 break; 462 } 463 464 return ret; 465 } 466 467 /** 468 * ctucan_get_tx_status() - Gets status of TXT buffer 469 * @priv: Pointer to private data 470 * @buf: Buffer index (0-based) 471 * 472 * Return: Status of TXT buffer 473 */ 474 static enum ctucan_txtb_status ctucan_get_tx_status(struct ctucan_priv *priv, u8 buf) 475 { 476 u32 tx_status = ctucan_read32(priv, CTUCANFD_TX_STATUS); 477 enum ctucan_txtb_status status = (tx_status >> (buf * 4)) & 0x7; 478 479 return status; 480 } 481 482 /** 483 * ctucan_is_txt_buf_writable() - Checks if frame can be inserted to TXT Buffer 484 * @priv: Pointer to private data 485 * @buf: Buffer index (0-based) 486 * 487 * Return: True - Frame can be inserted to TXT Buffer, False - If attempted, frame will not be 488 * inserted to TXT Buffer 489 */ 490 static bool ctucan_is_txt_buf_writable(struct ctucan_priv *priv, u8 buf) 491 { 492 enum ctucan_txtb_status buf_status; 493 494 buf_status = ctucan_get_tx_status(priv, buf); 495 if (buf_status == TXT_RDY || buf_status == TXT_TRAN || buf_status == TXT_ABTP) 496 return false; 497 498 return true; 499 } 500 501 /** 502 * ctucan_insert_frame() - Inserts frame to TXT buffer 503 * @priv: Pointer to private data 504 * @cf: Pointer to CAN frame to be inserted 505 * @buf: TXT Buffer index to which frame is inserted (0-based) 506 * @isfdf: True - CAN FD Frame, False - CAN 2.0 Frame 507 * 508 * Return: True - Frame inserted successfully 509 * False - Frame was not inserted due to one of: 510 * 1. TXT Buffer is not writable (it is in wrong state) 511 * 2. Invalid TXT buffer index 512 * 3. Invalid frame length 513 */ 514 static bool ctucan_insert_frame(struct ctucan_priv *priv, const struct canfd_frame *cf, u8 buf, 515 bool isfdf) 516 { 517 u32 buf_base; 518 u32 ffw = 0; 519 u32 idw = 0; 520 unsigned int i; 521 522 if (buf >= priv->ntxbufs) 523 return false; 524 525 if (!ctucan_is_txt_buf_writable(priv, buf)) 526 return false; 527 528 if (cf->len > CANFD_MAX_DLEN) 529 return false; 530 531 /* Prepare Frame format */ 532 if (cf->can_id & CAN_RTR_FLAG) 533 ffw |= REG_FRAME_FORMAT_W_RTR; 534 535 if (cf->can_id & CAN_EFF_FLAG) 536 ffw |= REG_FRAME_FORMAT_W_IDE; 537 538 if (isfdf) { 539 ffw |= REG_FRAME_FORMAT_W_FDF; 540 if (cf->flags & CANFD_BRS) 541 ffw |= REG_FRAME_FORMAT_W_BRS; 542 } 543 544 ffw |= FIELD_PREP(REG_FRAME_FORMAT_W_DLC, can_fd_len2dlc(cf->len)); 545 546 /* Prepare identifier */ 547 if (cf->can_id & CAN_EFF_FLAG) 548 idw = cf->can_id & CAN_EFF_MASK; 549 else 550 idw = FIELD_PREP(REG_IDENTIFIER_W_IDENTIFIER_BASE, cf->can_id & CAN_SFF_MASK); 551 552 /* Write ID, Frame format, Don't write timestamp -> Time triggered transmission disabled */ 553 buf_base = (buf + 1) * 0x100; 554 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_FRAME_FORMAT_W, ffw); 555 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_IDENTIFIER_W, idw); 556 557 /* Write Data payload */ 558 if (!(cf->can_id & CAN_RTR_FLAG)) { 559 for (i = 0; i < cf->len; i += 4) { 560 u32 data = le32_to_cpu(*(__le32 *)(cf->data + i)); 561 562 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_DATA_1_4_W + i, data); 563 } 564 } 565 566 return true; 567 } 568 569 /** 570 * ctucan_give_txtb_cmd() - Applies command on TXT buffer 571 * @priv: Pointer to private data 572 * @cmd: Command to give 573 * @buf: Buffer index (0-based) 574 */ 575 static void ctucan_give_txtb_cmd(struct ctucan_priv *priv, enum ctucan_txtb_command cmd, u8 buf) 576 { 577 u32 tx_cmd = cmd; 578 579 tx_cmd |= 1 << (buf + 8); 580 ctucan_write32(priv, CTUCANFD_TX_COMMAND, tx_cmd); 581 } 582 583 /** 584 * ctucan_start_xmit() - Starts the transmission 585 * @skb: sk_buff pointer that contains data to be Txed 586 * @ndev: Pointer to net_device structure 587 * 588 * Invoked from upper layers to initiate transmission. Uses the next available free TXT Buffer and 589 * populates its fields to start the transmission. 590 * 591 * Return: %NETDEV_TX_OK on success, %NETDEV_TX_BUSY when no free TXT buffer is available, 592 * negative return values reserved for error cases 593 */ 594 static netdev_tx_t ctucan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 595 { 596 struct ctucan_priv *priv = netdev_priv(ndev); 597 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 598 u32 txtb_id; 599 bool ok; 600 unsigned long flags; 601 602 if (can_dropped_invalid_skb(ndev, skb)) 603 return NETDEV_TX_OK; 604 605 if (unlikely(!CTU_CAN_FD_TXTNF(priv))) { 606 netif_stop_queue(ndev); 607 netdev_err(ndev, "BUG!, no TXB free when queue awake!\n"); 608 return NETDEV_TX_BUSY; 609 } 610 611 txtb_id = priv->txb_head % priv->ntxbufs; 612 ctucan_netdev_dbg(ndev, "%s: using TXB#%u\n", __func__, txtb_id); 613 ok = ctucan_insert_frame(priv, cf, txtb_id, can_is_canfd_skb(skb)); 614 615 if (!ok) { 616 netdev_err(ndev, "BUG! TXNF set but cannot insert frame into TXTB! HW Bug?"); 617 kfree_skb(skb); 618 ndev->stats.tx_dropped++; 619 return NETDEV_TX_OK; 620 } 621 622 can_put_echo_skb(skb, ndev, txtb_id, 0); 623 624 spin_lock_irqsave(&priv->tx_lock, flags); 625 ctucan_give_txtb_cmd(priv, TXT_CMD_SET_READY, txtb_id); 626 priv->txb_head++; 627 628 /* Check if all TX buffers are full */ 629 if (!CTU_CAN_FD_TXTNF(priv)) 630 netif_stop_queue(ndev); 631 632 spin_unlock_irqrestore(&priv->tx_lock, flags); 633 634 return NETDEV_TX_OK; 635 } 636 637 /** 638 * ctucan_read_rx_frame() - Reads frame from RX FIFO 639 * @priv: Pointer to CTU CAN FD's private data 640 * @cf: Pointer to CAN frame struct 641 * @ffw: Previously read frame format word 642 * 643 * Note: Frame format word must be read separately and provided in 'ffw'. 644 */ 645 static void ctucan_read_rx_frame(struct ctucan_priv *priv, struct canfd_frame *cf, u32 ffw) 646 { 647 u32 idw; 648 unsigned int i; 649 unsigned int wc; 650 unsigned int len; 651 652 idw = ctucan_read32(priv, CTUCANFD_RX_DATA); 653 if (FIELD_GET(REG_FRAME_FORMAT_W_IDE, ffw)) 654 cf->can_id = (idw & CAN_EFF_MASK) | CAN_EFF_FLAG; 655 else 656 cf->can_id = (idw >> 18) & CAN_SFF_MASK; 657 658 /* BRS, ESI, RTR Flags */ 659 cf->flags = 0; 660 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) { 661 if (FIELD_GET(REG_FRAME_FORMAT_W_BRS, ffw)) 662 cf->flags |= CANFD_BRS; 663 if (FIELD_GET(REG_FRAME_FORMAT_W_ESI_RSV, ffw)) 664 cf->flags |= CANFD_ESI; 665 } else if (FIELD_GET(REG_FRAME_FORMAT_W_RTR, ffw)) { 666 cf->can_id |= CAN_RTR_FLAG; 667 } 668 669 wc = FIELD_GET(REG_FRAME_FORMAT_W_RWCNT, ffw) - 3; 670 671 /* DLC */ 672 if (FIELD_GET(REG_FRAME_FORMAT_W_DLC, ffw) <= 8) { 673 len = FIELD_GET(REG_FRAME_FORMAT_W_DLC, ffw); 674 } else { 675 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) 676 len = wc << 2; 677 else 678 len = 8; 679 } 680 cf->len = len; 681 if (unlikely(len > wc * 4)) 682 len = wc * 4; 683 684 /* Timestamp - Read and throw away */ 685 ctucan_read32(priv, CTUCANFD_RX_DATA); 686 ctucan_read32(priv, CTUCANFD_RX_DATA); 687 688 /* Data */ 689 for (i = 0; i < len; i += 4) { 690 u32 data = ctucan_read32(priv, CTUCANFD_RX_DATA); 691 *(__le32 *)(cf->data + i) = cpu_to_le32(data); 692 } 693 while (unlikely(i < wc * 4)) { 694 ctucan_read32(priv, CTUCANFD_RX_DATA); 695 i += 4; 696 } 697 } 698 699 /** 700 * ctucan_rx() - Called from CAN ISR to complete the received frame processing 701 * @ndev: Pointer to net_device structure 702 * 703 * This function is invoked from the CAN isr(poll) to process the Rx frames. It does minimal 704 * processing and invokes "netif_receive_skb" to complete further processing. 705 * Return: 1 when frame is passed to the network layer, 0 when the first frame word is read but 706 * system is out of free SKBs temporally and left code to resolve SKB allocation later, 707 * -%EAGAIN in a case of empty Rx FIFO. 708 */ 709 static int ctucan_rx(struct net_device *ndev) 710 { 711 struct ctucan_priv *priv = netdev_priv(ndev); 712 struct net_device_stats *stats = &ndev->stats; 713 struct canfd_frame *cf; 714 struct sk_buff *skb; 715 u32 ffw; 716 717 if (test_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags)) { 718 ffw = priv->rxfrm_first_word; 719 clear_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 720 } else { 721 ffw = ctucan_read32(priv, CTUCANFD_RX_DATA); 722 } 723 724 if (!FIELD_GET(REG_FRAME_FORMAT_W_RWCNT, ffw)) 725 return -EAGAIN; 726 727 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) 728 skb = alloc_canfd_skb(ndev, &cf); 729 else 730 skb = alloc_can_skb(ndev, (struct can_frame **)&cf); 731 732 if (unlikely(!skb)) { 733 priv->rxfrm_first_word = ffw; 734 set_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 735 return 0; 736 } 737 738 ctucan_read_rx_frame(priv, cf, ffw); 739 740 stats->rx_bytes += cf->len; 741 stats->rx_packets++; 742 netif_receive_skb(skb); 743 744 return 1; 745 } 746 747 /** 748 * ctucan_read_fault_state() - Reads CTU CAN FDs fault confinement state. 749 * @priv: Pointer to private data 750 * 751 * Returns: Fault confinement state of controller 752 */ 753 static enum can_state ctucan_read_fault_state(struct ctucan_priv *priv) 754 { 755 u32 fs; 756 u32 rec_tec; 757 u32 ewl; 758 759 fs = ctucan_read32(priv, CTUCANFD_EWL); 760 rec_tec = ctucan_read32(priv, CTUCANFD_REC); 761 ewl = FIELD_GET(REG_EWL_EW_LIMIT, fs); 762 763 if (FIELD_GET(REG_EWL_ERA, fs)) { 764 if (ewl > FIELD_GET(REG_REC_REC_VAL, rec_tec) && 765 ewl > FIELD_GET(REG_REC_TEC_VAL, rec_tec)) 766 return CAN_STATE_ERROR_ACTIVE; 767 else 768 return CAN_STATE_ERROR_WARNING; 769 } else if (FIELD_GET(REG_EWL_ERP, fs)) { 770 return CAN_STATE_ERROR_PASSIVE; 771 } else if (FIELD_GET(REG_EWL_BOF, fs)) { 772 return CAN_STATE_BUS_OFF; 773 } 774 775 WARN(true, "Invalid error state"); 776 return CAN_STATE_ERROR_PASSIVE; 777 } 778 779 /** 780 * ctucan_get_rec_tec() - Reads REC/TEC counter values from controller 781 * @priv: Pointer to private data 782 * @bec: Pointer to Error counter structure 783 */ 784 static void ctucan_get_rec_tec(struct ctucan_priv *priv, struct can_berr_counter *bec) 785 { 786 u32 err_ctrs = ctucan_read32(priv, CTUCANFD_REC); 787 788 bec->rxerr = FIELD_GET(REG_REC_REC_VAL, err_ctrs); 789 bec->txerr = FIELD_GET(REG_REC_TEC_VAL, err_ctrs); 790 } 791 792 /** 793 * ctucan_err_interrupt() - Error frame ISR 794 * @ndev: net_device pointer 795 * @isr: interrupt status register value 796 * 797 * This is the CAN error interrupt and it will check the type of error and forward the error 798 * frame to upper layers. 799 */ 800 static void ctucan_err_interrupt(struct net_device *ndev, u32 isr) 801 { 802 struct ctucan_priv *priv = netdev_priv(ndev); 803 struct net_device_stats *stats = &ndev->stats; 804 struct can_frame *cf; 805 struct sk_buff *skb; 806 enum can_state state; 807 struct can_berr_counter bec; 808 u32 err_capt_alc; 809 int dologerr = net_ratelimit(); 810 811 ctucan_get_rec_tec(priv, &bec); 812 state = ctucan_read_fault_state(priv); 813 err_capt_alc = ctucan_read32(priv, CTUCANFD_ERR_CAPT); 814 815 if (dologerr) 816 netdev_info(ndev, "%s: ISR = 0x%08x, rxerr %d, txerr %d, error type %lu, pos %lu, ALC id_field %lu, bit %lu\n", 817 __func__, isr, bec.rxerr, bec.txerr, 818 FIELD_GET(REG_ERR_CAPT_ERR_TYPE, err_capt_alc), 819 FIELD_GET(REG_ERR_CAPT_ERR_POS, err_capt_alc), 820 FIELD_GET(REG_ERR_CAPT_ALC_ID_FIELD, err_capt_alc), 821 FIELD_GET(REG_ERR_CAPT_ALC_BIT, err_capt_alc)); 822 823 skb = alloc_can_err_skb(ndev, &cf); 824 825 /* EWLI: error warning limit condition met 826 * FCSI: fault confinement state changed 827 * ALI: arbitration lost (just informative) 828 * BEI: bus error interrupt 829 */ 830 if (FIELD_GET(REG_INT_STAT_FCSI, isr) || FIELD_GET(REG_INT_STAT_EWLI, isr)) { 831 netdev_info(ndev, "state changes from %s to %s\n", 832 ctucan_state_to_str(priv->can.state), 833 ctucan_state_to_str(state)); 834 835 if (priv->can.state == state) 836 netdev_warn(ndev, 837 "current and previous state is the same! (missed interrupt?)\n"); 838 839 priv->can.state = state; 840 switch (state) { 841 case CAN_STATE_BUS_OFF: 842 priv->can.can_stats.bus_off++; 843 can_bus_off(ndev); 844 if (skb) 845 cf->can_id |= CAN_ERR_BUSOFF; 846 break; 847 case CAN_STATE_ERROR_PASSIVE: 848 priv->can.can_stats.error_passive++; 849 if (skb) { 850 cf->can_id |= CAN_ERR_CRTL; 851 cf->data[1] = (bec.rxerr > 127) ? 852 CAN_ERR_CRTL_RX_PASSIVE : 853 CAN_ERR_CRTL_TX_PASSIVE; 854 cf->data[6] = bec.txerr; 855 cf->data[7] = bec.rxerr; 856 } 857 break; 858 case CAN_STATE_ERROR_WARNING: 859 priv->can.can_stats.error_warning++; 860 if (skb) { 861 cf->can_id |= CAN_ERR_CRTL; 862 cf->data[1] |= (bec.txerr > bec.rxerr) ? 863 CAN_ERR_CRTL_TX_WARNING : 864 CAN_ERR_CRTL_RX_WARNING; 865 cf->data[6] = bec.txerr; 866 cf->data[7] = bec.rxerr; 867 } 868 break; 869 case CAN_STATE_ERROR_ACTIVE: 870 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 871 cf->data[6] = bec.txerr; 872 cf->data[7] = bec.rxerr; 873 break; 874 default: 875 netdev_warn(ndev, "unhandled error state (%d:%s)!\n", 876 state, ctucan_state_to_str(state)); 877 break; 878 } 879 } 880 881 /* Check for Arbitration Lost interrupt */ 882 if (FIELD_GET(REG_INT_STAT_ALI, isr)) { 883 if (dologerr) 884 netdev_info(ndev, "arbitration lost\n"); 885 priv->can.can_stats.arbitration_lost++; 886 if (skb) { 887 cf->can_id |= CAN_ERR_LOSTARB; 888 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; 889 } 890 } 891 892 /* Check for Bus Error interrupt */ 893 if (FIELD_GET(REG_INT_STAT_BEI, isr)) { 894 netdev_info(ndev, "bus error\n"); 895 priv->can.can_stats.bus_error++; 896 stats->rx_errors++; 897 if (skb) { 898 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 899 cf->data[2] = CAN_ERR_PROT_UNSPEC; 900 cf->data[3] = CAN_ERR_PROT_LOC_UNSPEC; 901 } 902 } 903 904 if (skb) { 905 stats->rx_packets++; 906 stats->rx_bytes += cf->can_dlc; 907 netif_rx(skb); 908 } 909 } 910 911 /** 912 * ctucan_rx_poll() - Poll routine for rx packets (NAPI) 913 * @napi: NAPI structure pointer 914 * @quota: Max number of rx packets to be processed. 915 * 916 * This is the poll routine for rx part. It will process the packets maximux quota value. 917 * 918 * Return: Number of packets received 919 */ 920 static int ctucan_rx_poll(struct napi_struct *napi, int quota) 921 { 922 struct net_device *ndev = napi->dev; 923 struct ctucan_priv *priv = netdev_priv(ndev); 924 int work_done = 0; 925 u32 status; 926 u32 framecnt; 927 int res = 1; 928 929 framecnt = FIELD_GET(REG_RX_STATUS_RXFRC, ctucan_read32(priv, CTUCANFD_RX_STATUS)); 930 while (framecnt && work_done < quota && res > 0) { 931 res = ctucan_rx(ndev); 932 work_done++; 933 framecnt = FIELD_GET(REG_RX_STATUS_RXFRC, ctucan_read32(priv, CTUCANFD_RX_STATUS)); 934 } 935 936 /* Check for RX FIFO Overflow */ 937 status = ctucan_read32(priv, CTUCANFD_STATUS); 938 if (FIELD_GET(REG_STATUS_DOR, status)) { 939 struct net_device_stats *stats = &ndev->stats; 940 struct can_frame *cf; 941 struct sk_buff *skb; 942 943 netdev_info(ndev, "rx_poll: rx fifo overflow\n"); 944 stats->rx_over_errors++; 945 stats->rx_errors++; 946 skb = alloc_can_err_skb(ndev, &cf); 947 if (skb) { 948 cf->can_id |= CAN_ERR_CRTL; 949 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 950 stats->rx_packets++; 951 stats->rx_bytes += cf->can_dlc; 952 netif_rx(skb); 953 } 954 955 /* Clear Data Overrun */ 956 ctucan_write32(priv, CTUCANFD_COMMAND, REG_COMMAND_CDO); 957 } 958 959 if (!framecnt && res != 0) { 960 if (napi_complete_done(napi, work_done)) { 961 /* Clear and enable RBNEI. It is level-triggered, so 962 * there is no race condition. 963 */ 964 ctucan_write32(priv, CTUCANFD_INT_STAT, REG_INT_STAT_RBNEI); 965 ctucan_write32(priv, CTUCANFD_INT_MASK_CLR, REG_INT_STAT_RBNEI); 966 } 967 } 968 969 return work_done; 970 } 971 972 /** 973 * ctucan_rotate_txb_prio() - Rotates priorities of TXT Buffers 974 * @ndev: net_device pointer 975 */ 976 static void ctucan_rotate_txb_prio(struct net_device *ndev) 977 { 978 struct ctucan_priv *priv = netdev_priv(ndev); 979 u32 prio = priv->txb_prio; 980 981 prio = (prio << 4) | ((prio >> ((priv->ntxbufs - 1) * 4)) & 0xF); 982 ctucan_netdev_dbg(ndev, "%s: from 0x%08x to 0x%08x\n", __func__, priv->txb_prio, prio); 983 priv->txb_prio = prio; 984 ctucan_write32(priv, CTUCANFD_TX_PRIORITY, prio); 985 } 986 987 /** 988 * ctucan_tx_interrupt() - Tx done Isr 989 * @ndev: net_device pointer 990 */ 991 static void ctucan_tx_interrupt(struct net_device *ndev) 992 { 993 struct ctucan_priv *priv = netdev_priv(ndev); 994 struct net_device_stats *stats = &ndev->stats; 995 bool first = true; 996 bool some_buffers_processed; 997 unsigned long flags; 998 enum ctucan_txtb_status txtb_status; 999 u32 txtb_id; 1000 1001 /* read tx_status 1002 * if txb[n].finished (bit 2) 1003 * if ok -> echo 1004 * if error / aborted -> ?? (find how to handle oneshot mode) 1005 * txb_tail++ 1006 */ 1007 do { 1008 spin_lock_irqsave(&priv->tx_lock, flags); 1009 1010 some_buffers_processed = false; 1011 while ((int)(priv->txb_head - priv->txb_tail) > 0) { 1012 txtb_id = priv->txb_tail % priv->ntxbufs; 1013 txtb_status = ctucan_get_tx_status(priv, txtb_id); 1014 1015 ctucan_netdev_dbg(ndev, "TXI: TXB#%u: status 0x%x\n", txtb_id, txtb_status); 1016 1017 switch (txtb_status) { 1018 case TXT_TOK: 1019 ctucan_netdev_dbg(ndev, "TXT_OK\n"); 1020 stats->tx_bytes += can_get_echo_skb(ndev, txtb_id, NULL); 1021 stats->tx_packets++; 1022 break; 1023 case TXT_ERR: 1024 /* This indicated that retransmit limit has been reached. Obviously 1025 * we should not echo the frame, but also not indicate any kind of 1026 * error. If desired, it was already reported (possible multiple 1027 * times) on each arbitration lost. 1028 */ 1029 netdev_warn(ndev, "TXB in Error state\n"); 1030 can_free_echo_skb(ndev, txtb_id, NULL); 1031 stats->tx_dropped++; 1032 break; 1033 case TXT_ABT: 1034 /* Same as for TXT_ERR, only with different cause. We *could* 1035 * re-queue the frame, but multiqueue/abort is not supported yet 1036 * anyway. 1037 */ 1038 netdev_warn(ndev, "TXB in Aborted state\n"); 1039 can_free_echo_skb(ndev, txtb_id, NULL); 1040 stats->tx_dropped++; 1041 break; 1042 default: 1043 /* Bug only if the first buffer is not finished, otherwise it is 1044 * pretty much expected. 1045 */ 1046 if (first) { 1047 netdev_err(ndev, 1048 "BUG: TXB#%u not in a finished state (0x%x)!\n", 1049 txtb_id, txtb_status); 1050 spin_unlock_irqrestore(&priv->tx_lock, flags); 1051 /* do not clear nor wake */ 1052 return; 1053 } 1054 goto clear; 1055 } 1056 priv->txb_tail++; 1057 first = false; 1058 some_buffers_processed = true; 1059 /* Adjust priorities *before* marking the buffer as empty. */ 1060 ctucan_rotate_txb_prio(ndev); 1061 ctucan_give_txtb_cmd(priv, TXT_CMD_SET_EMPTY, txtb_id); 1062 } 1063 clear: 1064 spin_unlock_irqrestore(&priv->tx_lock, flags); 1065 1066 /* If no buffers were processed this time, we cannot clear - that would introduce 1067 * a race condition. 1068 */ 1069 if (some_buffers_processed) { 1070 /* Clear the interrupt again. We do not want to receive again interrupt for 1071 * the buffer already handled. If it is the last finished one then it would 1072 * cause log of spurious interrupt. 1073 */ 1074 ctucan_write32(priv, CTUCANFD_INT_STAT, REG_INT_STAT_TXBHCI); 1075 } 1076 } while (some_buffers_processed); 1077 1078 spin_lock_irqsave(&priv->tx_lock, flags); 1079 1080 /* Check if at least one TX buffer is free */ 1081 if (CTU_CAN_FD_TXTNF(priv)) 1082 netif_wake_queue(ndev); 1083 1084 spin_unlock_irqrestore(&priv->tx_lock, flags); 1085 } 1086 1087 /** 1088 * ctucan_interrupt() - CAN Isr 1089 * @irq: irq number 1090 * @dev_id: device id poniter 1091 * 1092 * This is the CTU CAN FD ISR. It checks for the type of interrupt 1093 * and invokes the corresponding ISR. 1094 * 1095 * Return: 1096 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 1097 */ 1098 static irqreturn_t ctucan_interrupt(int irq, void *dev_id) 1099 { 1100 struct net_device *ndev = (struct net_device *)dev_id; 1101 struct ctucan_priv *priv = netdev_priv(ndev); 1102 u32 isr, icr; 1103 u32 imask; 1104 int irq_loops; 1105 1106 for (irq_loops = 0; irq_loops < 10000; irq_loops++) { 1107 /* Get the interrupt status */ 1108 isr = ctucan_read32(priv, CTUCANFD_INT_STAT); 1109 1110 if (!isr) 1111 return irq_loops ? IRQ_HANDLED : IRQ_NONE; 1112 1113 /* Receive Buffer Not Empty Interrupt */ 1114 if (FIELD_GET(REG_INT_STAT_RBNEI, isr)) { 1115 ctucan_netdev_dbg(ndev, "RXBNEI\n"); 1116 /* Mask RXBNEI the first, then clear interrupt and schedule NAPI. Even if 1117 * another IRQ fires, RBNEI will always be 0 (masked). 1118 */ 1119 icr = REG_INT_STAT_RBNEI; 1120 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, icr); 1121 ctucan_write32(priv, CTUCANFD_INT_STAT, icr); 1122 napi_schedule(&priv->napi); 1123 } 1124 1125 /* TXT Buffer HW Command Interrupt */ 1126 if (FIELD_GET(REG_INT_STAT_TXBHCI, isr)) { 1127 ctucan_netdev_dbg(ndev, "TXBHCI\n"); 1128 /* Cleared inside */ 1129 ctucan_tx_interrupt(ndev); 1130 } 1131 1132 /* Error interrupts */ 1133 if (FIELD_GET(REG_INT_STAT_EWLI, isr) || 1134 FIELD_GET(REG_INT_STAT_FCSI, isr) || 1135 FIELD_GET(REG_INT_STAT_ALI, isr)) { 1136 icr = isr & (REG_INT_STAT_EWLI | REG_INT_STAT_FCSI | REG_INT_STAT_ALI); 1137 1138 ctucan_netdev_dbg(ndev, "some ERR interrupt: clearing 0x%08x\n", icr); 1139 ctucan_write32(priv, CTUCANFD_INT_STAT, icr); 1140 ctucan_err_interrupt(ndev, isr); 1141 } 1142 /* Ignore RI, TI, LFI, RFI, BSI */ 1143 } 1144 1145 netdev_err(ndev, "%s: stuck interrupt (isr=0x%08x), stopping\n", __func__, isr); 1146 1147 if (FIELD_GET(REG_INT_STAT_TXBHCI, isr)) { 1148 int i; 1149 1150 netdev_err(ndev, "txb_head=0x%08x txb_tail=0x%08x\n", 1151 priv->txb_head, priv->txb_tail); 1152 for (i = 0; i < priv->ntxbufs; i++) { 1153 u32 status = ctucan_get_tx_status(priv, i); 1154 1155 netdev_err(ndev, "txb[%d] txb status=0x%08x\n", i, status); 1156 } 1157 } 1158 1159 imask = 0xffffffff; 1160 ctucan_write32(priv, CTUCANFD_INT_ENA_CLR, imask); 1161 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, imask); 1162 1163 return IRQ_HANDLED; 1164 } 1165 1166 /** 1167 * ctucan_chip_stop() - Driver stop routine 1168 * @ndev: Pointer to net_device structure 1169 * 1170 * This is the drivers stop routine. It will disable the 1171 * interrupts and disable the controller. 1172 */ 1173 static void ctucan_chip_stop(struct net_device *ndev) 1174 { 1175 struct ctucan_priv *priv = netdev_priv(ndev); 1176 u32 mask = 0xffffffff; 1177 u32 mode; 1178 1179 /* Disable interrupts and disable CAN */ 1180 ctucan_write32(priv, CTUCANFD_INT_ENA_CLR, mask); 1181 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, mask); 1182 mode = ctucan_read32(priv, CTUCANFD_MODE); 1183 mode &= ~REG_MODE_ENA; 1184 ctucan_write32(priv, CTUCANFD_MODE, mode); 1185 1186 priv->can.state = CAN_STATE_STOPPED; 1187 } 1188 1189 /** 1190 * ctucan_open() - Driver open routine 1191 * @ndev: Pointer to net_device structure 1192 * 1193 * This is the driver open routine. 1194 * Return: 0 on success and failure value on error 1195 */ 1196 static int ctucan_open(struct net_device *ndev) 1197 { 1198 struct ctucan_priv *priv = netdev_priv(ndev); 1199 int ret; 1200 1201 ret = pm_runtime_get_sync(priv->dev); 1202 if (ret < 0) { 1203 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1204 __func__, ret); 1205 pm_runtime_put_noidle(priv->dev); 1206 return ret; 1207 } 1208 1209 ret = ctucan_reset(ndev); 1210 if (ret < 0) 1211 goto err_reset; 1212 1213 /* Common open */ 1214 ret = open_candev(ndev); 1215 if (ret) { 1216 netdev_warn(ndev, "open_candev failed!\n"); 1217 goto err_open; 1218 } 1219 1220 ret = request_irq(ndev->irq, ctucan_interrupt, priv->irq_flags, ndev->name, ndev); 1221 if (ret < 0) { 1222 netdev_err(ndev, "irq allocation for CAN failed\n"); 1223 goto err_irq; 1224 } 1225 1226 ret = ctucan_chip_start(ndev); 1227 if (ret < 0) { 1228 netdev_err(ndev, "ctucan_chip_start failed!\n"); 1229 goto err_chip_start; 1230 } 1231 1232 netdev_info(ndev, "ctu_can_fd device registered\n"); 1233 napi_enable(&priv->napi); 1234 netif_start_queue(ndev); 1235 1236 return 0; 1237 1238 err_chip_start: 1239 free_irq(ndev->irq, ndev); 1240 err_irq: 1241 close_candev(ndev); 1242 err_open: 1243 err_reset: 1244 pm_runtime_put(priv->dev); 1245 1246 return ret; 1247 } 1248 1249 /** 1250 * ctucan_close() - Driver close routine 1251 * @ndev: Pointer to net_device structure 1252 * 1253 * Return: 0 always 1254 */ 1255 static int ctucan_close(struct net_device *ndev) 1256 { 1257 struct ctucan_priv *priv = netdev_priv(ndev); 1258 1259 netif_stop_queue(ndev); 1260 napi_disable(&priv->napi); 1261 ctucan_chip_stop(ndev); 1262 free_irq(ndev->irq, ndev); 1263 close_candev(ndev); 1264 1265 pm_runtime_put(priv->dev); 1266 1267 return 0; 1268 } 1269 1270 /** 1271 * ctucan_get_berr_counter() - error counter routine 1272 * @ndev: Pointer to net_device structure 1273 * @bec: Pointer to can_berr_counter structure 1274 * 1275 * This is the driver error counter routine. 1276 * Return: 0 on success and failure value on error 1277 */ 1278 static int ctucan_get_berr_counter(const struct net_device *ndev, struct can_berr_counter *bec) 1279 { 1280 struct ctucan_priv *priv = netdev_priv(ndev); 1281 int ret; 1282 1283 ret = pm_runtime_get_sync(priv->dev); 1284 if (ret < 0) { 1285 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", __func__, ret); 1286 pm_runtime_put_noidle(priv->dev); 1287 return ret; 1288 } 1289 1290 ctucan_get_rec_tec(priv, bec); 1291 pm_runtime_put(priv->dev); 1292 1293 return 0; 1294 } 1295 1296 static const struct net_device_ops ctucan_netdev_ops = { 1297 .ndo_open = ctucan_open, 1298 .ndo_stop = ctucan_close, 1299 .ndo_start_xmit = ctucan_start_xmit, 1300 .ndo_change_mtu = can_change_mtu, 1301 }; 1302 1303 int ctucan_suspend(struct device *dev) 1304 { 1305 struct net_device *ndev = dev_get_drvdata(dev); 1306 struct ctucan_priv *priv = netdev_priv(ndev); 1307 1308 if (netif_running(ndev)) { 1309 netif_stop_queue(ndev); 1310 netif_device_detach(ndev); 1311 } 1312 1313 priv->can.state = CAN_STATE_SLEEPING; 1314 1315 return 0; 1316 } 1317 EXPORT_SYMBOL(ctucan_suspend); 1318 1319 int ctucan_resume(struct device *dev) 1320 { 1321 struct net_device *ndev = dev_get_drvdata(dev); 1322 struct ctucan_priv *priv = netdev_priv(ndev); 1323 1324 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1325 1326 if (netif_running(ndev)) { 1327 netif_device_attach(ndev); 1328 netif_start_queue(ndev); 1329 } 1330 1331 return 0; 1332 } 1333 EXPORT_SYMBOL(ctucan_resume); 1334 1335 int ctucan_probe_common(struct device *dev, void __iomem *addr, int irq, unsigned int ntxbufs, 1336 unsigned long can_clk_rate, int pm_enable_call, 1337 void (*set_drvdata_fnc)(struct device *dev, struct net_device *ndev)) 1338 { 1339 struct ctucan_priv *priv; 1340 struct net_device *ndev; 1341 int ret; 1342 1343 /* Create a CAN device instance */ 1344 ndev = alloc_candev(sizeof(struct ctucan_priv), ntxbufs); 1345 if (!ndev) 1346 return -ENOMEM; 1347 1348 priv = netdev_priv(ndev); 1349 spin_lock_init(&priv->tx_lock); 1350 INIT_LIST_HEAD(&priv->peers_on_pdev); 1351 priv->ntxbufs = ntxbufs; 1352 priv->dev = dev; 1353 priv->can.bittiming_const = &ctu_can_fd_bit_timing_max; 1354 priv->can.data_bittiming_const = &ctu_can_fd_bit_timing_data_max; 1355 priv->can.do_set_mode = ctucan_do_set_mode; 1356 1357 /* Needed for timing adjustment to be performed as soon as possible */ 1358 priv->can.do_set_bittiming = ctucan_set_bittiming; 1359 priv->can.do_set_data_bittiming = ctucan_set_data_bittiming; 1360 1361 priv->can.do_get_berr_counter = ctucan_get_berr_counter; 1362 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK 1363 | CAN_CTRLMODE_LISTENONLY 1364 | CAN_CTRLMODE_FD 1365 | CAN_CTRLMODE_PRESUME_ACK 1366 | CAN_CTRLMODE_BERR_REPORTING 1367 | CAN_CTRLMODE_FD_NON_ISO 1368 | CAN_CTRLMODE_ONE_SHOT; 1369 priv->mem_base = addr; 1370 1371 /* Get IRQ for the device */ 1372 ndev->irq = irq; 1373 ndev->flags |= IFF_ECHO; /* We support local echo */ 1374 1375 if (set_drvdata_fnc) 1376 set_drvdata_fnc(dev, ndev); 1377 SET_NETDEV_DEV(ndev, dev); 1378 ndev->netdev_ops = &ctucan_netdev_ops; 1379 1380 /* Getting the can_clk info */ 1381 if (!can_clk_rate) { 1382 priv->can_clk = devm_clk_get(dev, NULL); 1383 if (IS_ERR(priv->can_clk)) { 1384 dev_err(dev, "Device clock not found.\n"); 1385 ret = PTR_ERR(priv->can_clk); 1386 goto err_free; 1387 } 1388 can_clk_rate = clk_get_rate(priv->can_clk); 1389 } 1390 1391 priv->write_reg = ctucan_write32_le; 1392 priv->read_reg = ctucan_read32_le; 1393 1394 if (pm_enable_call) 1395 pm_runtime_enable(dev); 1396 ret = pm_runtime_get_sync(dev); 1397 if (ret < 0) { 1398 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1399 __func__, ret); 1400 pm_runtime_put_noidle(priv->dev); 1401 goto err_pmdisable; 1402 } 1403 1404 /* Check for big-endianity and set according IO-accessors */ 1405 if ((ctucan_read32(priv, CTUCANFD_DEVICE_ID) & 0xFFFF) != CTUCANFD_ID) { 1406 priv->write_reg = ctucan_write32_be; 1407 priv->read_reg = ctucan_read32_be; 1408 if ((ctucan_read32(priv, CTUCANFD_DEVICE_ID) & 0xFFFF) != CTUCANFD_ID) { 1409 netdev_err(ndev, "CTU_CAN_FD signature not found\n"); 1410 ret = -ENODEV; 1411 goto err_deviceoff; 1412 } 1413 } 1414 1415 ret = ctucan_reset(ndev); 1416 if (ret < 0) 1417 goto err_deviceoff; 1418 1419 priv->can.clock.freq = can_clk_rate; 1420 1421 netif_napi_add(ndev, &priv->napi, ctucan_rx_poll, NAPI_POLL_WEIGHT); 1422 1423 ret = register_candev(ndev); 1424 if (ret) { 1425 dev_err(dev, "fail to register failed (err=%d)\n", ret); 1426 goto err_deviceoff; 1427 } 1428 1429 pm_runtime_put(dev); 1430 1431 netdev_dbg(ndev, "mem_base=0x%p irq=%d clock=%d, no. of txt buffers:%d\n", 1432 priv->mem_base, ndev->irq, priv->can.clock.freq, priv->ntxbufs); 1433 1434 return 0; 1435 1436 err_deviceoff: 1437 pm_runtime_put(priv->dev); 1438 err_pmdisable: 1439 if (pm_enable_call) 1440 pm_runtime_disable(dev); 1441 err_free: 1442 list_del_init(&priv->peers_on_pdev); 1443 free_candev(ndev); 1444 return ret; 1445 } 1446 EXPORT_SYMBOL(ctucan_probe_common); 1447 1448 MODULE_LICENSE("GPL"); 1449 MODULE_AUTHOR("Martin Jerabek <martin.jerabek01@gmail.com>"); 1450 MODULE_AUTHOR("Pavel Pisa <pisa@cmp.felk.cvut.cz>"); 1451 MODULE_AUTHOR("Ondrej Ille <ondrej.ille@gmail.com>"); 1452 MODULE_DESCRIPTION("CTU CAN FD interface"); 1453