1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /******************************************************************************* 3 * 4 * CTU CAN FD IP Core 5 * 6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU 7 * Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded 8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU 9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded 10 * 11 * Project advisors: 12 * Jiri Novak <jnovak@fel.cvut.cz> 13 * Pavel Pisa <pisa@cmp.felk.cvut.cz> 14 * 15 * Department of Measurement (http://meas.fel.cvut.cz/) 16 * Faculty of Electrical Engineering (http://www.fel.cvut.cz) 17 * Czech Technical University (http://www.cvut.cz/) 18 ******************************************************************************/ 19 20 #include <linux/clk.h> 21 #include <linux/errno.h> 22 #include <linux/init.h> 23 #include <linux/bitfield.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/skbuff.h> 29 #include <linux/string.h> 30 #include <linux/types.h> 31 #include <linux/can/error.h> 32 #include <linux/can/led.h> 33 #include <linux/pm_runtime.h> 34 35 #include "ctucanfd.h" 36 #include "ctucanfd_kregs.h" 37 #include "ctucanfd_kframe.h" 38 39 #ifdef DEBUG 40 #define ctucan_netdev_dbg(ndev, args...) \ 41 netdev_dbg(ndev, args) 42 #else 43 #define ctucan_netdev_dbg(...) do { } while (0) 44 #endif 45 46 #define CTUCANFD_ID 0xCAFD 47 48 /* TX buffer rotation: 49 * - when a buffer transitions to empty state, rotate order and priorities 50 * - if more buffers seem to transition at the same time, rotate by the number of buffers 51 * - it may be assumed that buffers transition to empty state in FIFO order (because we manage 52 * priorities that way) 53 * - at frame filling, do not rotate anything, just increment buffer modulo counter 54 */ 55 56 #define CTUCANFD_FLAG_RX_FFW_BUFFERED 1 57 58 #define CTUCAN_STATE_TO_TEXT_ENTRY(st) \ 59 [st] = #st 60 61 enum ctucan_txtb_status { 62 TXT_NOT_EXIST = 0x0, 63 TXT_RDY = 0x1, 64 TXT_TRAN = 0x2, 65 TXT_ABTP = 0x3, 66 TXT_TOK = 0x4, 67 TXT_ERR = 0x6, 68 TXT_ABT = 0x7, 69 TXT_ETY = 0x8, 70 }; 71 72 enum ctucan_txtb_command { 73 TXT_CMD_SET_EMPTY = 0x01, 74 TXT_CMD_SET_READY = 0x02, 75 TXT_CMD_SET_ABORT = 0x04 76 }; 77 78 static const struct can_bittiming_const ctu_can_fd_bit_timing_max = { 79 .name = "ctu_can_fd", 80 .tseg1_min = 2, 81 .tseg1_max = 190, 82 .tseg2_min = 1, 83 .tseg2_max = 63, 84 .sjw_max = 31, 85 .brp_min = 1, 86 .brp_max = 8, 87 .brp_inc = 1, 88 }; 89 90 static const struct can_bittiming_const ctu_can_fd_bit_timing_data_max = { 91 .name = "ctu_can_fd", 92 .tseg1_min = 2, 93 .tseg1_max = 94, 94 .tseg2_min = 1, 95 .tseg2_max = 31, 96 .sjw_max = 31, 97 .brp_min = 1, 98 .brp_max = 2, 99 .brp_inc = 1, 100 }; 101 102 static const char * const ctucan_state_strings[CAN_STATE_MAX] = { 103 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_ACTIVE), 104 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_WARNING), 105 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_ERROR_PASSIVE), 106 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_BUS_OFF), 107 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_STOPPED), 108 CTUCAN_STATE_TO_TEXT_ENTRY(CAN_STATE_SLEEPING) 109 }; 110 111 static void ctucan_write32_le(struct ctucan_priv *priv, 112 enum ctu_can_fd_can_registers reg, u32 val) 113 { 114 iowrite32(val, priv->mem_base + reg); 115 } 116 117 static void ctucan_write32_be(struct ctucan_priv *priv, 118 enum ctu_can_fd_can_registers reg, u32 val) 119 { 120 iowrite32be(val, priv->mem_base + reg); 121 } 122 123 static u32 ctucan_read32_le(struct ctucan_priv *priv, 124 enum ctu_can_fd_can_registers reg) 125 { 126 return ioread32(priv->mem_base + reg); 127 } 128 129 static u32 ctucan_read32_be(struct ctucan_priv *priv, 130 enum ctu_can_fd_can_registers reg) 131 { 132 return ioread32be(priv->mem_base + reg); 133 } 134 135 static inline void ctucan_write32(struct ctucan_priv *priv, enum ctu_can_fd_can_registers reg, 136 u32 val) 137 { 138 priv->write_reg(priv, reg, val); 139 } 140 141 static inline u32 ctucan_read32(struct ctucan_priv *priv, enum ctu_can_fd_can_registers reg) 142 { 143 return priv->read_reg(priv, reg); 144 } 145 146 static void ctucan_write_txt_buf(struct ctucan_priv *priv, enum ctu_can_fd_can_registers buf_base, 147 u32 offset, u32 val) 148 { 149 priv->write_reg(priv, buf_base + offset, val); 150 } 151 152 #define CTU_CAN_FD_TXTNF(priv) (!!FIELD_GET(REG_STATUS_TXNF, ctucan_read32(priv, CTUCANFD_STATUS))) 153 #define CTU_CAN_FD_ENABLED(priv) (!!FIELD_GET(REG_MODE_ENA, ctucan_read32(priv, CTUCANFD_MODE))) 154 155 /** 156 * ctucan_state_to_str() - Converts CAN controller state code to corresponding text 157 * @state: CAN controller state code 158 * 159 * Return: Pointer to string representation of the error state 160 */ 161 static const char *ctucan_state_to_str(enum can_state state) 162 { 163 const char *txt = NULL; 164 165 if (state >= 0 && state < CAN_STATE_MAX) 166 txt = ctucan_state_strings[state]; 167 return txt ? txt : "UNKNOWN"; 168 } 169 170 /** 171 * ctucan_reset() - Issues software reset request to CTU CAN FD 172 * @ndev: Pointer to net_device structure 173 * 174 * Return: 0 for success, -%ETIMEDOUT if CAN controller does not leave reset 175 */ 176 static int ctucan_reset(struct net_device *ndev) 177 { 178 struct ctucan_priv *priv = netdev_priv(ndev); 179 int i = 100; 180 181 ctucan_netdev_dbg(ndev, "%s\n", __func__); 182 183 ctucan_write32(priv, CTUCANFD_MODE, REG_MODE_RST); 184 clear_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 185 186 do { 187 u16 device_id = FIELD_GET(REG_DEVICE_ID_DEVICE_ID, 188 ctucan_read32(priv, CTUCANFD_DEVICE_ID)); 189 190 if (device_id == 0xCAFD) 191 return 0; 192 if (!i--) { 193 netdev_warn(ndev, "device did not leave reset\n"); 194 return -ETIMEDOUT; 195 } 196 usleep_range(100, 200); 197 } while (1); 198 } 199 200 /** 201 * ctucan_set_btr() - Sets CAN bus bit timing in CTU CAN FD 202 * @ndev: Pointer to net_device structure 203 * @bt: Pointer to Bit timing structure 204 * @nominal: True - Nominal bit timing, False - Data bit timing 205 * 206 * Return: 0 - OK, -%EPERM if controller is enabled 207 */ 208 static int ctucan_set_btr(struct net_device *ndev, struct can_bittiming *bt, bool nominal) 209 { 210 struct ctucan_priv *priv = netdev_priv(ndev); 211 int max_ph1_len = 31; 212 u32 btr = 0; 213 u32 prop_seg = bt->prop_seg; 214 u32 phase_seg1 = bt->phase_seg1; 215 216 if (CTU_CAN_FD_ENABLED(priv)) { 217 netdev_err(ndev, "BUG! Cannot set bittiming - CAN is enabled\n"); 218 return -EPERM; 219 } 220 221 if (nominal) 222 max_ph1_len = 63; 223 224 /* The timing calculation functions have only constraints on tseg1, which is prop_seg + 225 * phase1_seg combined. tseg1 is then split in half and stored into prog_seg and phase_seg1. 226 * In CTU CAN FD, PROP is 6/7 bits wide but PH1 only 6/5, so we must re-distribute the 227 * values here. 228 */ 229 if (phase_seg1 > max_ph1_len) { 230 prop_seg += phase_seg1 - max_ph1_len; 231 phase_seg1 = max_ph1_len; 232 bt->prop_seg = prop_seg; 233 bt->phase_seg1 = phase_seg1; 234 } 235 236 if (nominal) { 237 btr = FIELD_PREP(REG_BTR_PROP, prop_seg); 238 btr |= FIELD_PREP(REG_BTR_PH1, phase_seg1); 239 btr |= FIELD_PREP(REG_BTR_PH2, bt->phase_seg2); 240 btr |= FIELD_PREP(REG_BTR_BRP, bt->brp); 241 btr |= FIELD_PREP(REG_BTR_SJW, bt->sjw); 242 243 ctucan_write32(priv, CTUCANFD_BTR, btr); 244 } else { 245 btr = FIELD_PREP(REG_BTR_FD_PROP_FD, prop_seg); 246 btr |= FIELD_PREP(REG_BTR_FD_PH1_FD, phase_seg1); 247 btr |= FIELD_PREP(REG_BTR_FD_PH2_FD, bt->phase_seg2); 248 btr |= FIELD_PREP(REG_BTR_FD_BRP_FD, bt->brp); 249 btr |= FIELD_PREP(REG_BTR_FD_SJW_FD, bt->sjw); 250 251 ctucan_write32(priv, CTUCANFD_BTR_FD, btr); 252 } 253 254 return 0; 255 } 256 257 /** 258 * ctucan_set_bittiming() - CAN set nominal bit timing routine 259 * @ndev: Pointer to net_device structure 260 * 261 * Return: 0 on success, -%EPERM on error 262 */ 263 static int ctucan_set_bittiming(struct net_device *ndev) 264 { 265 struct ctucan_priv *priv = netdev_priv(ndev); 266 struct can_bittiming *bt = &priv->can.bittiming; 267 268 ctucan_netdev_dbg(ndev, "%s\n", __func__); 269 270 /* Note that bt may be modified here */ 271 return ctucan_set_btr(ndev, bt, true); 272 } 273 274 /** 275 * ctucan_set_data_bittiming() - CAN set data bit timing routine 276 * @ndev: Pointer to net_device structure 277 * 278 * Return: 0 on success, -%EPERM on error 279 */ 280 static int ctucan_set_data_bittiming(struct net_device *ndev) 281 { 282 struct ctucan_priv *priv = netdev_priv(ndev); 283 struct can_bittiming *dbt = &priv->can.data_bittiming; 284 285 ctucan_netdev_dbg(ndev, "%s\n", __func__); 286 287 /* Note that dbt may be modified here */ 288 return ctucan_set_btr(ndev, dbt, false); 289 } 290 291 /** 292 * ctucan_set_secondary_sample_point() - Sets secondary sample point in CTU CAN FD 293 * @ndev: Pointer to net_device structure 294 * 295 * Return: 0 on success, -%EPERM if controller is enabled 296 */ 297 static int ctucan_set_secondary_sample_point(struct net_device *ndev) 298 { 299 struct ctucan_priv *priv = netdev_priv(ndev); 300 struct can_bittiming *dbt = &priv->can.data_bittiming; 301 int ssp_offset = 0; 302 u32 ssp_cfg = 0; /* No SSP by default */ 303 304 ctucan_netdev_dbg(ndev, "%s\n", __func__); 305 306 if (CTU_CAN_FD_ENABLED(priv)) { 307 netdev_err(ndev, "BUG! Cannot set SSP - CAN is enabled\n"); 308 return -EPERM; 309 } 310 311 /* Use SSP for bit-rates above 1 Mbits/s */ 312 if (dbt->bitrate > 1000000) { 313 /* Calculate SSP in minimal time quanta */ 314 ssp_offset = (priv->can.clock.freq / 1000) * dbt->sample_point / dbt->bitrate; 315 316 if (ssp_offset > 127) { 317 netdev_warn(ndev, "SSP offset saturated to 127\n"); 318 ssp_offset = 127; 319 } 320 321 ssp_cfg = FIELD_PREP(REG_TRV_DELAY_SSP_OFFSET, ssp_offset); 322 ssp_cfg |= FIELD_PREP(REG_TRV_DELAY_SSP_SRC, 0x1); 323 } 324 325 ctucan_write32(priv, CTUCANFD_TRV_DELAY, ssp_cfg); 326 327 return 0; 328 } 329 330 /** 331 * ctucan_set_mode() - Sets CTU CAN FDs mode 332 * @priv: Pointer to private data 333 * @mode: Pointer to controller modes to be set 334 */ 335 static void ctucan_set_mode(struct ctucan_priv *priv, const struct can_ctrlmode *mode) 336 { 337 u32 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); 338 339 mode_reg = (mode->flags & CAN_CTRLMODE_LOOPBACK) ? 340 (mode_reg | REG_MODE_ILBP) : 341 (mode_reg & ~REG_MODE_ILBP); 342 343 mode_reg = (mode->flags & CAN_CTRLMODE_LISTENONLY) ? 344 (mode_reg | REG_MODE_BMM) : 345 (mode_reg & ~REG_MODE_BMM); 346 347 mode_reg = (mode->flags & CAN_CTRLMODE_FD) ? 348 (mode_reg | REG_MODE_FDE) : 349 (mode_reg & ~REG_MODE_FDE); 350 351 mode_reg = (mode->flags & CAN_CTRLMODE_PRESUME_ACK) ? 352 (mode_reg | REG_MODE_ACF) : 353 (mode_reg & ~REG_MODE_ACF); 354 355 mode_reg = (mode->flags & CAN_CTRLMODE_FD_NON_ISO) ? 356 (mode_reg | REG_MODE_NISOFD) : 357 (mode_reg & ~REG_MODE_NISOFD); 358 359 /* One shot mode supported indirectly via Retransmit limit */ 360 mode_reg &= ~FIELD_PREP(REG_MODE_RTRTH, 0xF); 361 mode_reg = (mode->flags & CAN_CTRLMODE_ONE_SHOT) ? 362 (mode_reg | REG_MODE_RTRLE) : 363 (mode_reg & ~REG_MODE_RTRLE); 364 365 /* Some bits fixed: 366 * TSTM - Off, User shall not be able to change REC/TEC by hand during operation 367 */ 368 mode_reg &= ~REG_MODE_TSTM; 369 370 ctucan_write32(priv, CTUCANFD_MODE, mode_reg); 371 } 372 373 /** 374 * ctucan_chip_start() - This routine starts the driver 375 * @ndev: Pointer to net_device structure 376 * 377 * Routine expects that chip is in reset state. It setups initial 378 * Tx buffers for FIFO priorities, sets bittiming, enables interrupts, 379 * switches core to operational mode and changes controller 380 * state to %CAN_STATE_STOPPED. 381 * 382 * Return: 0 on success and failure value on error 383 */ 384 static int ctucan_chip_start(struct net_device *ndev) 385 { 386 struct ctucan_priv *priv = netdev_priv(ndev); 387 u32 int_ena, int_msk; 388 u32 mode_reg; 389 int err; 390 struct can_ctrlmode mode; 391 392 ctucan_netdev_dbg(ndev, "%s\n", __func__); 393 394 priv->txb_prio = 0x01234567; 395 priv->txb_head = 0; 396 priv->txb_tail = 0; 397 ctucan_write32(priv, CTUCANFD_TX_PRIORITY, priv->txb_prio); 398 399 /* Configure bit-rates and ssp */ 400 err = ctucan_set_bittiming(ndev); 401 if (err < 0) 402 return err; 403 404 err = ctucan_set_data_bittiming(ndev); 405 if (err < 0) 406 return err; 407 408 err = ctucan_set_secondary_sample_point(ndev); 409 if (err < 0) 410 return err; 411 412 /* Configure modes */ 413 mode.flags = priv->can.ctrlmode; 414 mode.mask = 0xFFFFFFFF; 415 ctucan_set_mode(priv, &mode); 416 417 /* Configure interrupts */ 418 int_ena = REG_INT_STAT_RBNEI | 419 REG_INT_STAT_TXBHCI | 420 REG_INT_STAT_EWLI | 421 REG_INT_STAT_FCSI; 422 423 /* Bus error reporting -> Allow Error/Arb.lost interrupts */ 424 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { 425 int_ena |= REG_INT_STAT_ALI | 426 REG_INT_STAT_BEI; 427 } 428 429 int_msk = ~int_ena; /* Mask all disabled interrupts */ 430 431 /* It's after reset, so there is no need to clear anything */ 432 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, int_msk); 433 ctucan_write32(priv, CTUCANFD_INT_ENA_SET, int_ena); 434 435 /* Controller enters ERROR_ACTIVE on initial FCSI */ 436 priv->can.state = CAN_STATE_STOPPED; 437 438 /* Enable the controller */ 439 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); 440 mode_reg |= REG_MODE_ENA; 441 ctucan_write32(priv, CTUCANFD_MODE, mode_reg); 442 443 return 0; 444 } 445 446 /** 447 * ctucan_do_set_mode() - Sets mode of the driver 448 * @ndev: Pointer to net_device structure 449 * @mode: Tells the mode of the driver 450 * 451 * This check the drivers state and calls the corresponding modes to set. 452 * 453 * Return: 0 on success and failure value on error 454 */ 455 static int ctucan_do_set_mode(struct net_device *ndev, enum can_mode mode) 456 { 457 int ret; 458 459 ctucan_netdev_dbg(ndev, "%s\n", __func__); 460 461 switch (mode) { 462 case CAN_MODE_START: 463 ret = ctucan_reset(ndev); 464 if (ret < 0) 465 return ret; 466 ret = ctucan_chip_start(ndev); 467 if (ret < 0) { 468 netdev_err(ndev, "ctucan_chip_start failed!\n"); 469 return ret; 470 } 471 netif_wake_queue(ndev); 472 break; 473 default: 474 ret = -EOPNOTSUPP; 475 break; 476 } 477 478 return ret; 479 } 480 481 /** 482 * ctucan_get_tx_status() - Gets status of TXT buffer 483 * @priv: Pointer to private data 484 * @buf: Buffer index (0-based) 485 * 486 * Return: Status of TXT buffer 487 */ 488 static inline enum ctucan_txtb_status ctucan_get_tx_status(struct ctucan_priv *priv, u8 buf) 489 { 490 u32 tx_status = ctucan_read32(priv, CTUCANFD_TX_STATUS); 491 enum ctucan_txtb_status status = (tx_status >> (buf * 4)) & 0x7; 492 493 return status; 494 } 495 496 /** 497 * ctucan_is_txt_buf_writable() - Checks if frame can be inserted to TXT Buffer 498 * @priv: Pointer to private data 499 * @buf: Buffer index (0-based) 500 * 501 * Return: True - Frame can be inserted to TXT Buffer, False - If attempted, frame will not be 502 * inserted to TXT Buffer 503 */ 504 static bool ctucan_is_txt_buf_writable(struct ctucan_priv *priv, u8 buf) 505 { 506 enum ctucan_txtb_status buf_status; 507 508 buf_status = ctucan_get_tx_status(priv, buf); 509 if (buf_status == TXT_RDY || buf_status == TXT_TRAN || buf_status == TXT_ABTP) 510 return false; 511 512 return true; 513 } 514 515 /** 516 * ctucan_insert_frame() - Inserts frame to TXT buffer 517 * @priv: Pointer to private data 518 * @cf: Pointer to CAN frame to be inserted 519 * @buf: TXT Buffer index to which frame is inserted (0-based) 520 * @isfdf: True - CAN FD Frame, False - CAN 2.0 Frame 521 * 522 * Return: True - Frame inserted successfully 523 * False - Frame was not inserted due to one of: 524 * 1. TXT Buffer is not writable (it is in wrong state) 525 * 2. Invalid TXT buffer index 526 * 3. Invalid frame length 527 */ 528 static bool ctucan_insert_frame(struct ctucan_priv *priv, const struct canfd_frame *cf, u8 buf, 529 bool isfdf) 530 { 531 u32 buf_base; 532 u32 ffw = 0; 533 u32 idw = 0; 534 unsigned int i; 535 536 if (buf >= priv->ntxbufs) 537 return false; 538 539 if (!ctucan_is_txt_buf_writable(priv, buf)) 540 return false; 541 542 if (cf->len > CANFD_MAX_DLEN) 543 return false; 544 545 /* Prepare Frame format */ 546 if (cf->can_id & CAN_RTR_FLAG) 547 ffw |= REG_FRAME_FORMAT_W_RTR; 548 549 if (cf->can_id & CAN_EFF_FLAG) 550 ffw |= REG_FRAME_FORMAT_W_IDE; 551 552 if (isfdf) { 553 ffw |= REG_FRAME_FORMAT_W_FDF; 554 if (cf->flags & CANFD_BRS) 555 ffw |= REG_FRAME_FORMAT_W_BRS; 556 } 557 558 ffw |= FIELD_PREP(REG_FRAME_FORMAT_W_DLC, can_fd_len2dlc(cf->len)); 559 560 /* Prepare identifier */ 561 if (cf->can_id & CAN_EFF_FLAG) 562 idw = cf->can_id & CAN_EFF_MASK; 563 else 564 idw = FIELD_PREP(REG_IDENTIFIER_W_IDENTIFIER_BASE, cf->can_id & CAN_SFF_MASK); 565 566 /* Write ID, Frame format, Don't write timestamp -> Time triggered transmission disabled */ 567 buf_base = (buf + 1) * 0x100; 568 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_FRAME_FORMAT_W, ffw); 569 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_IDENTIFIER_W, idw); 570 571 /* Write Data payload */ 572 if (!(cf->can_id & CAN_RTR_FLAG)) { 573 for (i = 0; i < cf->len; i += 4) { 574 u32 data = le32_to_cpu(*(__le32 *)(cf->data + i)); 575 576 ctucan_write_txt_buf(priv, buf_base, CTUCANFD_DATA_1_4_W + i, data); 577 } 578 } 579 580 return true; 581 } 582 583 /** 584 * ctucan_give_txtb_cmd() - Applies command on TXT buffer 585 * @priv: Pointer to private data 586 * @cmd: Command to give 587 * @buf: Buffer index (0-based) 588 */ 589 static void ctucan_give_txtb_cmd(struct ctucan_priv *priv, enum ctucan_txtb_command cmd, u8 buf) 590 { 591 u32 tx_cmd = cmd; 592 593 tx_cmd |= 1 << (buf + 8); 594 ctucan_write32(priv, CTUCANFD_TX_COMMAND, tx_cmd); 595 } 596 597 /** 598 * ctucan_start_xmit() - Starts the transmission 599 * @skb: sk_buff pointer that contains data to be Txed 600 * @ndev: Pointer to net_device structure 601 * 602 * Invoked from upper layers to initiate transmission. Uses the next available free TXT Buffer and 603 * populates its fields to start the transmission. 604 * 605 * Return: %NETDEV_TX_OK on success, %NETDEV_TX_BUSY when no free TXT buffer is available, 606 * negative return values reserved for error cases 607 */ 608 static netdev_tx_t ctucan_start_xmit(struct sk_buff *skb, struct net_device *ndev) 609 { 610 struct ctucan_priv *priv = netdev_priv(ndev); 611 struct canfd_frame *cf = (struct canfd_frame *)skb->data; 612 u32 txtb_id; 613 bool ok; 614 unsigned long flags; 615 616 if (can_dropped_invalid_skb(ndev, skb)) 617 return NETDEV_TX_OK; 618 619 if (unlikely(!CTU_CAN_FD_TXTNF(priv))) { 620 netif_stop_queue(ndev); 621 netdev_err(ndev, "BUG!, no TXB free when queue awake!\n"); 622 return NETDEV_TX_BUSY; 623 } 624 625 txtb_id = priv->txb_head % priv->ntxbufs; 626 ctucan_netdev_dbg(ndev, "%s: using TXB#%u\n", __func__, txtb_id); 627 ok = ctucan_insert_frame(priv, cf, txtb_id, can_is_canfd_skb(skb)); 628 629 if (!ok) { 630 netdev_err(ndev, "BUG! TXNF set but cannot insert frame into TXTB! HW Bug?"); 631 kfree_skb(skb); 632 ndev->stats.tx_dropped++; 633 return NETDEV_TX_OK; 634 } 635 636 can_put_echo_skb(skb, ndev, txtb_id, 0); 637 638 spin_lock_irqsave(&priv->tx_lock, flags); 639 ctucan_give_txtb_cmd(priv, TXT_CMD_SET_READY, txtb_id); 640 priv->txb_head++; 641 642 /* Check if all TX buffers are full */ 643 if (!CTU_CAN_FD_TXTNF(priv)) 644 netif_stop_queue(ndev); 645 646 spin_unlock_irqrestore(&priv->tx_lock, flags); 647 648 return NETDEV_TX_OK; 649 } 650 651 /** 652 * ctucan_read_rx_frame() - Reads frame from RX FIFO 653 * @priv: Pointer to CTU CAN FD's private data 654 * @cf: Pointer to CAN frame struct 655 * @ffw: Previously read frame format word 656 * 657 * Note: Frame format word must be read separately and provided in 'ffw'. 658 */ 659 static void ctucan_read_rx_frame(struct ctucan_priv *priv, struct canfd_frame *cf, u32 ffw) 660 { 661 u32 idw; 662 unsigned int i; 663 unsigned int wc; 664 unsigned int len; 665 666 idw = ctucan_read32(priv, CTUCANFD_RX_DATA); 667 if (FIELD_GET(REG_FRAME_FORMAT_W_IDE, ffw)) 668 cf->can_id = (idw & CAN_EFF_MASK) | CAN_EFF_FLAG; 669 else 670 cf->can_id = (idw >> 18) & CAN_SFF_MASK; 671 672 /* BRS, ESI, RTR Flags */ 673 cf->flags = 0; 674 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) { 675 if (FIELD_GET(REG_FRAME_FORMAT_W_BRS, ffw)) 676 cf->flags |= CANFD_BRS; 677 if (FIELD_GET(REG_FRAME_FORMAT_W_ESI_RSV, ffw)) 678 cf->flags |= CANFD_ESI; 679 } else if (FIELD_GET(REG_FRAME_FORMAT_W_RTR, ffw)) { 680 cf->can_id |= CAN_RTR_FLAG; 681 } 682 683 wc = FIELD_GET(REG_FRAME_FORMAT_W_RWCNT, ffw) - 3; 684 685 /* DLC */ 686 if (FIELD_GET(REG_FRAME_FORMAT_W_DLC, ffw) <= 8) { 687 len = FIELD_GET(REG_FRAME_FORMAT_W_DLC, ffw); 688 } else { 689 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) 690 len = wc << 2; 691 else 692 len = 8; 693 } 694 cf->len = len; 695 if (unlikely(len > wc * 4)) 696 len = wc * 4; 697 698 /* Timestamp - Read and throw away */ 699 ctucan_read32(priv, CTUCANFD_RX_DATA); 700 ctucan_read32(priv, CTUCANFD_RX_DATA); 701 702 /* Data */ 703 for (i = 0; i < len; i += 4) { 704 u32 data = ctucan_read32(priv, CTUCANFD_RX_DATA); 705 *(__le32 *)(cf->data + i) = cpu_to_le32(data); 706 } 707 while (unlikely(i < wc * 4)) { 708 ctucan_read32(priv, CTUCANFD_RX_DATA); 709 i += 4; 710 } 711 } 712 713 /** 714 * ctucan_rx() - Called from CAN ISR to complete the received frame processing 715 * @ndev: Pointer to net_device structure 716 * 717 * This function is invoked from the CAN isr(poll) to process the Rx frames. It does minimal 718 * processing and invokes "netif_receive_skb" to complete further processing. 719 * Return: 1 when frame is passed to the network layer, 0 when the first frame word is read but 720 * system is out of free SKBs temporally and left code to resolve SKB allocation later, 721 * -%EAGAIN in a case of empty Rx FIFO. 722 */ 723 static int ctucan_rx(struct net_device *ndev) 724 { 725 struct ctucan_priv *priv = netdev_priv(ndev); 726 struct net_device_stats *stats = &ndev->stats; 727 struct canfd_frame *cf; 728 struct sk_buff *skb; 729 u32 ffw; 730 731 if (test_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags)) { 732 ffw = priv->rxfrm_first_word; 733 clear_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 734 } else { 735 ffw = ctucan_read32(priv, CTUCANFD_RX_DATA); 736 } 737 738 if (!FIELD_GET(REG_FRAME_FORMAT_W_RWCNT, ffw)) 739 return -EAGAIN; 740 741 if (FIELD_GET(REG_FRAME_FORMAT_W_FDF, ffw)) 742 skb = alloc_canfd_skb(ndev, &cf); 743 else 744 skb = alloc_can_skb(ndev, (struct can_frame **)&cf); 745 746 if (unlikely(!skb)) { 747 priv->rxfrm_first_word = ffw; 748 set_bit(CTUCANFD_FLAG_RX_FFW_BUFFERED, &priv->drv_flags); 749 return 0; 750 } 751 752 ctucan_read_rx_frame(priv, cf, ffw); 753 754 stats->rx_bytes += cf->len; 755 stats->rx_packets++; 756 netif_receive_skb(skb); 757 758 return 1; 759 } 760 761 /** 762 * ctucan_read_fault_state() - Reads CTU CAN FDs fault confinement state. 763 * @priv: Pointer to private data 764 * 765 * Returns: Fault confinement state of controller 766 */ 767 static enum can_state ctucan_read_fault_state(struct ctucan_priv *priv) 768 { 769 u32 fs; 770 u32 rec_tec; 771 u32 ewl; 772 773 fs = ctucan_read32(priv, CTUCANFD_EWL); 774 rec_tec = ctucan_read32(priv, CTUCANFD_REC); 775 ewl = FIELD_GET(REG_EWL_EW_LIMIT, fs); 776 777 if (FIELD_GET(REG_EWL_ERA, fs)) { 778 if (ewl > FIELD_GET(REG_REC_REC_VAL, rec_tec) && 779 ewl > FIELD_GET(REG_REC_TEC_VAL, rec_tec)) 780 return CAN_STATE_ERROR_ACTIVE; 781 else 782 return CAN_STATE_ERROR_WARNING; 783 } else if (FIELD_GET(REG_EWL_ERP, fs)) { 784 return CAN_STATE_ERROR_PASSIVE; 785 } else if (FIELD_GET(REG_EWL_BOF, fs)) { 786 return CAN_STATE_BUS_OFF; 787 } 788 789 WARN(true, "Invalid error state"); 790 return CAN_STATE_ERROR_PASSIVE; 791 } 792 793 /** 794 * ctucan_get_rec_tec() - Reads REC/TEC counter values from controller 795 * @priv: Pointer to private data 796 * @bec: Pointer to Error counter structure 797 */ 798 static void ctucan_get_rec_tec(struct ctucan_priv *priv, struct can_berr_counter *bec) 799 { 800 u32 err_ctrs = ctucan_read32(priv, CTUCANFD_REC); 801 802 bec->rxerr = FIELD_GET(REG_REC_REC_VAL, err_ctrs); 803 bec->txerr = FIELD_GET(REG_REC_TEC_VAL, err_ctrs); 804 } 805 806 /** 807 * ctucan_err_interrupt() - Error frame ISR 808 * @ndev: net_device pointer 809 * @isr: interrupt status register value 810 * 811 * This is the CAN error interrupt and it will check the type of error and forward the error 812 * frame to upper layers. 813 */ 814 static void ctucan_err_interrupt(struct net_device *ndev, u32 isr) 815 { 816 struct ctucan_priv *priv = netdev_priv(ndev); 817 struct net_device_stats *stats = &ndev->stats; 818 struct can_frame *cf; 819 struct sk_buff *skb; 820 enum can_state state; 821 struct can_berr_counter bec; 822 u32 err_capt_alc; 823 int dologerr = net_ratelimit(); 824 825 ctucan_get_rec_tec(priv, &bec); 826 state = ctucan_read_fault_state(priv); 827 err_capt_alc = ctucan_read32(priv, CTUCANFD_ERR_CAPT); 828 829 if (dologerr) 830 netdev_info(ndev, "%s: ISR = 0x%08x, rxerr %d, txerr %d, error type %lu, pos %lu, ALC id_field %lu, bit %lu\n", 831 __func__, isr, bec.rxerr, bec.txerr, 832 FIELD_GET(REG_ERR_CAPT_ERR_TYPE, err_capt_alc), 833 FIELD_GET(REG_ERR_CAPT_ERR_POS, err_capt_alc), 834 FIELD_GET(REG_ERR_CAPT_ALC_ID_FIELD, err_capt_alc), 835 FIELD_GET(REG_ERR_CAPT_ALC_BIT, err_capt_alc)); 836 837 skb = alloc_can_err_skb(ndev, &cf); 838 839 /* EWLI: error warning limit condition met 840 * FCSI: fault confinement state changed 841 * ALI: arbitration lost (just informative) 842 * BEI: bus error interrupt 843 */ 844 if (FIELD_GET(REG_INT_STAT_FCSI, isr) || FIELD_GET(REG_INT_STAT_EWLI, isr)) { 845 netdev_info(ndev, "state changes from %s to %s\n", 846 ctucan_state_to_str(priv->can.state), 847 ctucan_state_to_str(state)); 848 849 if (priv->can.state == state) 850 netdev_warn(ndev, 851 "current and previous state is the same! (missed interrupt?)\n"); 852 853 priv->can.state = state; 854 switch (state) { 855 case CAN_STATE_BUS_OFF: 856 priv->can.can_stats.bus_off++; 857 can_bus_off(ndev); 858 if (skb) 859 cf->can_id |= CAN_ERR_BUSOFF; 860 break; 861 case CAN_STATE_ERROR_PASSIVE: 862 priv->can.can_stats.error_passive++; 863 if (skb) { 864 cf->can_id |= CAN_ERR_CRTL; 865 cf->data[1] = (bec.rxerr > 127) ? 866 CAN_ERR_CRTL_RX_PASSIVE : 867 CAN_ERR_CRTL_TX_PASSIVE; 868 cf->data[6] = bec.txerr; 869 cf->data[7] = bec.rxerr; 870 } 871 break; 872 case CAN_STATE_ERROR_WARNING: 873 priv->can.can_stats.error_warning++; 874 if (skb) { 875 cf->can_id |= CAN_ERR_CRTL; 876 cf->data[1] |= (bec.txerr > bec.rxerr) ? 877 CAN_ERR_CRTL_TX_WARNING : 878 CAN_ERR_CRTL_RX_WARNING; 879 cf->data[6] = bec.txerr; 880 cf->data[7] = bec.rxerr; 881 } 882 break; 883 case CAN_STATE_ERROR_ACTIVE: 884 cf->data[1] = CAN_ERR_CRTL_ACTIVE; 885 cf->data[6] = bec.txerr; 886 cf->data[7] = bec.rxerr; 887 break; 888 default: 889 netdev_warn(ndev, "unhandled error state (%d:%s)!\n", 890 state, ctucan_state_to_str(state)); 891 break; 892 } 893 } 894 895 /* Check for Arbitration Lost interrupt */ 896 if (FIELD_GET(REG_INT_STAT_ALI, isr)) { 897 if (dologerr) 898 netdev_info(ndev, "arbitration lost\n"); 899 priv->can.can_stats.arbitration_lost++; 900 if (skb) { 901 cf->can_id |= CAN_ERR_LOSTARB; 902 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC; 903 } 904 } 905 906 /* Check for Bus Error interrupt */ 907 if (FIELD_GET(REG_INT_STAT_BEI, isr)) { 908 netdev_info(ndev, "bus error\n"); 909 priv->can.can_stats.bus_error++; 910 stats->rx_errors++; 911 if (skb) { 912 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 913 cf->data[2] = CAN_ERR_PROT_UNSPEC; 914 cf->data[3] = CAN_ERR_PROT_LOC_UNSPEC; 915 } 916 } 917 918 if (skb) { 919 stats->rx_packets++; 920 stats->rx_bytes += cf->can_dlc; 921 netif_rx(skb); 922 } 923 } 924 925 /** 926 * ctucan_rx_poll() - Poll routine for rx packets (NAPI) 927 * @napi: NAPI structure pointer 928 * @quota: Max number of rx packets to be processed. 929 * 930 * This is the poll routine for rx part. It will process the packets maximux quota value. 931 * 932 * Return: Number of packets received 933 */ 934 static int ctucan_rx_poll(struct napi_struct *napi, int quota) 935 { 936 struct net_device *ndev = napi->dev; 937 struct ctucan_priv *priv = netdev_priv(ndev); 938 int work_done = 0; 939 u32 status; 940 u32 framecnt; 941 int res = 1; 942 943 framecnt = FIELD_GET(REG_RX_STATUS_RXFRC, ctucan_read32(priv, CTUCANFD_RX_STATUS)); 944 while (framecnt && work_done < quota && res > 0) { 945 res = ctucan_rx(ndev); 946 work_done++; 947 framecnt = FIELD_GET(REG_RX_STATUS_RXFRC, ctucan_read32(priv, CTUCANFD_RX_STATUS)); 948 } 949 950 /* Check for RX FIFO Overflow */ 951 status = ctucan_read32(priv, CTUCANFD_STATUS); 952 if (FIELD_GET(REG_STATUS_DOR, status)) { 953 struct net_device_stats *stats = &ndev->stats; 954 struct can_frame *cf; 955 struct sk_buff *skb; 956 957 netdev_info(ndev, "rx_poll: rx fifo overflow\n"); 958 stats->rx_over_errors++; 959 stats->rx_errors++; 960 skb = alloc_can_err_skb(ndev, &cf); 961 if (skb) { 962 cf->can_id |= CAN_ERR_CRTL; 963 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; 964 stats->rx_packets++; 965 stats->rx_bytes += cf->can_dlc; 966 netif_rx(skb); 967 } 968 969 /* Clear Data Overrun */ 970 ctucan_write32(priv, CTUCANFD_COMMAND, REG_COMMAND_CDO); 971 } 972 973 if (work_done) 974 can_led_event(ndev, CAN_LED_EVENT_RX); 975 976 if (!framecnt && res != 0) { 977 if (napi_complete_done(napi, work_done)) { 978 /* Clear and enable RBNEI. It is level-triggered, so 979 * there is no race condition. 980 */ 981 ctucan_write32(priv, CTUCANFD_INT_STAT, REG_INT_STAT_RBNEI); 982 ctucan_write32(priv, CTUCANFD_INT_MASK_CLR, REG_INT_STAT_RBNEI); 983 } 984 } 985 986 return work_done; 987 } 988 989 /** 990 * ctucan_rotate_txb_prio() - Rotates priorities of TXT Buffers 991 * @ndev: net_device pointer 992 */ 993 static void ctucan_rotate_txb_prio(struct net_device *ndev) 994 { 995 struct ctucan_priv *priv = netdev_priv(ndev); 996 u32 prio = priv->txb_prio; 997 998 prio = (prio << 4) | ((prio >> ((priv->ntxbufs - 1) * 4)) & 0xF); 999 ctucan_netdev_dbg(ndev, "%s: from 0x%08x to 0x%08x\n", __func__, priv->txb_prio, prio); 1000 priv->txb_prio = prio; 1001 ctucan_write32(priv, CTUCANFD_TX_PRIORITY, prio); 1002 } 1003 1004 /** 1005 * ctucan_tx_interrupt() - Tx done Isr 1006 * @ndev: net_device pointer 1007 */ 1008 static void ctucan_tx_interrupt(struct net_device *ndev) 1009 { 1010 struct ctucan_priv *priv = netdev_priv(ndev); 1011 struct net_device_stats *stats = &ndev->stats; 1012 bool first = true; 1013 bool some_buffers_processed; 1014 unsigned long flags; 1015 enum ctucan_txtb_status txtb_status; 1016 u32 txtb_id; 1017 1018 /* read tx_status 1019 * if txb[n].finished (bit 2) 1020 * if ok -> echo 1021 * if error / aborted -> ?? (find how to handle oneshot mode) 1022 * txb_tail++ 1023 */ 1024 do { 1025 spin_lock_irqsave(&priv->tx_lock, flags); 1026 1027 some_buffers_processed = false; 1028 while ((int)(priv->txb_head - priv->txb_tail) > 0) { 1029 txtb_id = priv->txb_tail % priv->ntxbufs; 1030 txtb_status = ctucan_get_tx_status(priv, txtb_id); 1031 1032 ctucan_netdev_dbg(ndev, "TXI: TXB#%u: status 0x%x\n", txtb_id, txtb_status); 1033 1034 switch (txtb_status) { 1035 case TXT_TOK: 1036 ctucan_netdev_dbg(ndev, "TXT_OK\n"); 1037 stats->tx_bytes += can_get_echo_skb(ndev, txtb_id, NULL); 1038 stats->tx_packets++; 1039 break; 1040 case TXT_ERR: 1041 /* This indicated that retransmit limit has been reached. Obviously 1042 * we should not echo the frame, but also not indicate any kind of 1043 * error. If desired, it was already reported (possible multiple 1044 * times) on each arbitration lost. 1045 */ 1046 netdev_warn(ndev, "TXB in Error state\n"); 1047 can_free_echo_skb(ndev, txtb_id, NULL); 1048 stats->tx_dropped++; 1049 break; 1050 case TXT_ABT: 1051 /* Same as for TXT_ERR, only with different cause. We *could* 1052 * re-queue the frame, but multiqueue/abort is not supported yet 1053 * anyway. 1054 */ 1055 netdev_warn(ndev, "TXB in Aborted state\n"); 1056 can_free_echo_skb(ndev, txtb_id, NULL); 1057 stats->tx_dropped++; 1058 break; 1059 default: 1060 /* Bug only if the first buffer is not finished, otherwise it is 1061 * pretty much expected. 1062 */ 1063 if (first) { 1064 netdev_err(ndev, 1065 "BUG: TXB#%u not in a finished state (0x%x)!\n", 1066 txtb_id, txtb_status); 1067 spin_unlock_irqrestore(&priv->tx_lock, flags); 1068 /* do not clear nor wake */ 1069 return; 1070 } 1071 goto clear; 1072 } 1073 priv->txb_tail++; 1074 first = false; 1075 some_buffers_processed = true; 1076 /* Adjust priorities *before* marking the buffer as empty. */ 1077 ctucan_rotate_txb_prio(ndev); 1078 ctucan_give_txtb_cmd(priv, TXT_CMD_SET_EMPTY, txtb_id); 1079 } 1080 clear: 1081 spin_unlock_irqrestore(&priv->tx_lock, flags); 1082 1083 /* If no buffers were processed this time, we cannot clear - that would introduce 1084 * a race condition. 1085 */ 1086 if (some_buffers_processed) { 1087 /* Clear the interrupt again. We do not want to receive again interrupt for 1088 * the buffer already handled. If it is the last finished one then it would 1089 * cause log of spurious interrupt. 1090 */ 1091 ctucan_write32(priv, CTUCANFD_INT_STAT, REG_INT_STAT_TXBHCI); 1092 } 1093 } while (some_buffers_processed); 1094 1095 can_led_event(ndev, CAN_LED_EVENT_TX); 1096 1097 spin_lock_irqsave(&priv->tx_lock, flags); 1098 1099 /* Check if at least one TX buffer is free */ 1100 if (CTU_CAN_FD_TXTNF(priv)) 1101 netif_wake_queue(ndev); 1102 1103 spin_unlock_irqrestore(&priv->tx_lock, flags); 1104 } 1105 1106 /** 1107 * ctucan_interrupt() - CAN Isr 1108 * @irq: irq number 1109 * @dev_id: device id poniter 1110 * 1111 * This is the CTU CAN FD ISR. It checks for the type of interrupt 1112 * and invokes the corresponding ISR. 1113 * 1114 * Return: 1115 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise 1116 */ 1117 static irqreturn_t ctucan_interrupt(int irq, void *dev_id) 1118 { 1119 struct net_device *ndev = (struct net_device *)dev_id; 1120 struct ctucan_priv *priv = netdev_priv(ndev); 1121 u32 isr, icr; 1122 u32 imask; 1123 int irq_loops; 1124 1125 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1126 1127 for (irq_loops = 0; irq_loops < 10000; irq_loops++) { 1128 /* Get the interrupt status */ 1129 isr = ctucan_read32(priv, CTUCANFD_INT_STAT); 1130 1131 if (!isr) 1132 return irq_loops ? IRQ_HANDLED : IRQ_NONE; 1133 1134 /* Receive Buffer Not Empty Interrupt */ 1135 if (FIELD_GET(REG_INT_STAT_RBNEI, isr)) { 1136 ctucan_netdev_dbg(ndev, "RXBNEI\n"); 1137 /* Mask RXBNEI the first, then clear interrupt and schedule NAPI. Even if 1138 * another IRQ fires, RBNEI will always be 0 (masked). 1139 */ 1140 icr = REG_INT_STAT_RBNEI; 1141 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, icr); 1142 ctucan_write32(priv, CTUCANFD_INT_STAT, icr); 1143 napi_schedule(&priv->napi); 1144 } 1145 1146 /* TXT Buffer HW Command Interrupt */ 1147 if (FIELD_GET(REG_INT_STAT_TXBHCI, isr)) { 1148 ctucan_netdev_dbg(ndev, "TXBHCI\n"); 1149 /* Cleared inside */ 1150 ctucan_tx_interrupt(ndev); 1151 } 1152 1153 /* Error interrupts */ 1154 if (FIELD_GET(REG_INT_STAT_EWLI, isr) || 1155 FIELD_GET(REG_INT_STAT_FCSI, isr) || 1156 FIELD_GET(REG_INT_STAT_ALI, isr)) { 1157 icr = isr & (REG_INT_STAT_EWLI | REG_INT_STAT_FCSI | REG_INT_STAT_ALI); 1158 1159 ctucan_netdev_dbg(ndev, "some ERR interrupt: clearing 0x%08x\n", icr); 1160 ctucan_write32(priv, CTUCANFD_INT_STAT, icr); 1161 ctucan_err_interrupt(ndev, isr); 1162 } 1163 /* Ignore RI, TI, LFI, RFI, BSI */ 1164 } 1165 1166 netdev_err(ndev, "%s: stuck interrupt (isr=0x%08x), stopping\n", __func__, isr); 1167 1168 if (FIELD_GET(REG_INT_STAT_TXBHCI, isr)) { 1169 int i; 1170 1171 netdev_err(ndev, "txb_head=0x%08x txb_tail=0x%08x\n", 1172 priv->txb_head, priv->txb_tail); 1173 for (i = 0; i < priv->ntxbufs; i++) { 1174 u32 status = ctucan_get_tx_status(priv, i); 1175 1176 netdev_err(ndev, "txb[%d] txb status=0x%08x\n", i, status); 1177 } 1178 } 1179 1180 imask = 0xffffffff; 1181 ctucan_write32(priv, CTUCANFD_INT_ENA_CLR, imask); 1182 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, imask); 1183 1184 return IRQ_HANDLED; 1185 } 1186 1187 /** 1188 * ctucan_chip_stop() - Driver stop routine 1189 * @ndev: Pointer to net_device structure 1190 * 1191 * This is the drivers stop routine. It will disable the 1192 * interrupts and disable the controller. 1193 */ 1194 static void ctucan_chip_stop(struct net_device *ndev) 1195 { 1196 struct ctucan_priv *priv = netdev_priv(ndev); 1197 u32 mask = 0xffffffff; 1198 u32 mode; 1199 1200 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1201 1202 /* Disable interrupts and disable CAN */ 1203 ctucan_write32(priv, CTUCANFD_INT_ENA_CLR, mask); 1204 ctucan_write32(priv, CTUCANFD_INT_MASK_SET, mask); 1205 mode = ctucan_read32(priv, CTUCANFD_MODE); 1206 mode &= ~REG_MODE_ENA; 1207 ctucan_write32(priv, CTUCANFD_MODE, mode); 1208 1209 priv->can.state = CAN_STATE_STOPPED; 1210 } 1211 1212 /** 1213 * ctucan_open() - Driver open routine 1214 * @ndev: Pointer to net_device structure 1215 * 1216 * This is the driver open routine. 1217 * Return: 0 on success and failure value on error 1218 */ 1219 static int ctucan_open(struct net_device *ndev) 1220 { 1221 struct ctucan_priv *priv = netdev_priv(ndev); 1222 int ret; 1223 1224 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1225 1226 ret = pm_runtime_get_sync(priv->dev); 1227 if (ret < 0) { 1228 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1229 __func__, ret); 1230 pm_runtime_put_noidle(priv->dev); 1231 return ret; 1232 } 1233 1234 ret = ctucan_reset(ndev); 1235 if (ret < 0) 1236 goto err_reset; 1237 1238 /* Common open */ 1239 ret = open_candev(ndev); 1240 if (ret) { 1241 netdev_warn(ndev, "open_candev failed!\n"); 1242 goto err_open; 1243 } 1244 1245 ret = request_irq(ndev->irq, ctucan_interrupt, priv->irq_flags, ndev->name, ndev); 1246 if (ret < 0) { 1247 netdev_err(ndev, "irq allocation for CAN failed\n"); 1248 goto err_irq; 1249 } 1250 1251 ret = ctucan_chip_start(ndev); 1252 if (ret < 0) { 1253 netdev_err(ndev, "ctucan_chip_start failed!\n"); 1254 goto err_chip_start; 1255 } 1256 1257 netdev_info(ndev, "ctu_can_fd device registered\n"); 1258 can_led_event(ndev, CAN_LED_EVENT_OPEN); 1259 napi_enable(&priv->napi); 1260 netif_start_queue(ndev); 1261 1262 return 0; 1263 1264 err_chip_start: 1265 free_irq(ndev->irq, ndev); 1266 err_irq: 1267 close_candev(ndev); 1268 err_open: 1269 err_reset: 1270 pm_runtime_put(priv->dev); 1271 1272 return ret; 1273 } 1274 1275 /** 1276 * ctucan_close() - Driver close routine 1277 * @ndev: Pointer to net_device structure 1278 * 1279 * Return: 0 always 1280 */ 1281 static int ctucan_close(struct net_device *ndev) 1282 { 1283 struct ctucan_priv *priv = netdev_priv(ndev); 1284 1285 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1286 1287 netif_stop_queue(ndev); 1288 napi_disable(&priv->napi); 1289 ctucan_chip_stop(ndev); 1290 free_irq(ndev->irq, ndev); 1291 close_candev(ndev); 1292 1293 can_led_event(ndev, CAN_LED_EVENT_STOP); 1294 pm_runtime_put(priv->dev); 1295 1296 return 0; 1297 } 1298 1299 /** 1300 * ctucan_get_berr_counter() - error counter routine 1301 * @ndev: Pointer to net_device structure 1302 * @bec: Pointer to can_berr_counter structure 1303 * 1304 * This is the driver error counter routine. 1305 * Return: 0 on success and failure value on error 1306 */ 1307 static int ctucan_get_berr_counter(const struct net_device *ndev, struct can_berr_counter *bec) 1308 { 1309 struct ctucan_priv *priv = netdev_priv(ndev); 1310 int ret; 1311 1312 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1313 1314 ret = pm_runtime_get_sync(priv->dev); 1315 if (ret < 0) { 1316 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", __func__, ret); 1317 pm_runtime_put_noidle(priv->dev); 1318 return ret; 1319 } 1320 1321 ctucan_get_rec_tec(priv, bec); 1322 pm_runtime_put(priv->dev); 1323 1324 return 0; 1325 } 1326 1327 static const struct net_device_ops ctucan_netdev_ops = { 1328 .ndo_open = ctucan_open, 1329 .ndo_stop = ctucan_close, 1330 .ndo_start_xmit = ctucan_start_xmit, 1331 .ndo_change_mtu = can_change_mtu, 1332 }; 1333 1334 int ctucan_suspend(struct device *dev) 1335 { 1336 struct net_device *ndev = dev_get_drvdata(dev); 1337 struct ctucan_priv *priv = netdev_priv(ndev); 1338 1339 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1340 1341 if (netif_running(ndev)) { 1342 netif_stop_queue(ndev); 1343 netif_device_detach(ndev); 1344 } 1345 1346 priv->can.state = CAN_STATE_SLEEPING; 1347 1348 return 0; 1349 } 1350 EXPORT_SYMBOL(ctucan_suspend); 1351 1352 int ctucan_resume(struct device *dev) 1353 { 1354 struct net_device *ndev = dev_get_drvdata(dev); 1355 struct ctucan_priv *priv = netdev_priv(ndev); 1356 1357 ctucan_netdev_dbg(ndev, "%s\n", __func__); 1358 1359 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1360 1361 if (netif_running(ndev)) { 1362 netif_device_attach(ndev); 1363 netif_start_queue(ndev); 1364 } 1365 1366 return 0; 1367 } 1368 EXPORT_SYMBOL(ctucan_resume); 1369 1370 int ctucan_probe_common(struct device *dev, void __iomem *addr, int irq, unsigned int ntxbufs, 1371 unsigned long can_clk_rate, int pm_enable_call, 1372 void (*set_drvdata_fnc)(struct device *dev, struct net_device *ndev)) 1373 { 1374 struct ctucan_priv *priv; 1375 struct net_device *ndev; 1376 int ret; 1377 1378 /* Create a CAN device instance */ 1379 ndev = alloc_candev(sizeof(struct ctucan_priv), ntxbufs); 1380 if (!ndev) 1381 return -ENOMEM; 1382 1383 priv = netdev_priv(ndev); 1384 spin_lock_init(&priv->tx_lock); 1385 INIT_LIST_HEAD(&priv->peers_on_pdev); 1386 priv->ntxbufs = ntxbufs; 1387 priv->dev = dev; 1388 priv->can.bittiming_const = &ctu_can_fd_bit_timing_max; 1389 priv->can.data_bittiming_const = &ctu_can_fd_bit_timing_data_max; 1390 priv->can.do_set_mode = ctucan_do_set_mode; 1391 1392 /* Needed for timing adjustment to be performed as soon as possible */ 1393 priv->can.do_set_bittiming = ctucan_set_bittiming; 1394 priv->can.do_set_data_bittiming = ctucan_set_data_bittiming; 1395 1396 priv->can.do_get_berr_counter = ctucan_get_berr_counter; 1397 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK 1398 | CAN_CTRLMODE_LISTENONLY 1399 | CAN_CTRLMODE_FD 1400 | CAN_CTRLMODE_PRESUME_ACK 1401 | CAN_CTRLMODE_BERR_REPORTING 1402 | CAN_CTRLMODE_FD_NON_ISO 1403 | CAN_CTRLMODE_ONE_SHOT; 1404 priv->mem_base = addr; 1405 1406 /* Get IRQ for the device */ 1407 ndev->irq = irq; 1408 ndev->flags |= IFF_ECHO; /* We support local echo */ 1409 1410 if (set_drvdata_fnc) 1411 set_drvdata_fnc(dev, ndev); 1412 SET_NETDEV_DEV(ndev, dev); 1413 ndev->netdev_ops = &ctucan_netdev_ops; 1414 1415 /* Getting the can_clk info */ 1416 if (!can_clk_rate) { 1417 priv->can_clk = devm_clk_get(dev, NULL); 1418 if (IS_ERR(priv->can_clk)) { 1419 dev_err(dev, "Device clock not found.\n"); 1420 ret = PTR_ERR(priv->can_clk); 1421 goto err_free; 1422 } 1423 can_clk_rate = clk_get_rate(priv->can_clk); 1424 } 1425 1426 priv->write_reg = ctucan_write32_le; 1427 priv->read_reg = ctucan_read32_le; 1428 1429 if (pm_enable_call) 1430 pm_runtime_enable(dev); 1431 ret = pm_runtime_get_sync(dev); 1432 if (ret < 0) { 1433 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n", 1434 __func__, ret); 1435 pm_runtime_put_noidle(priv->dev); 1436 goto err_pmdisable; 1437 } 1438 1439 /* Check for big-endianity and set according IO-accessors */ 1440 if ((ctucan_read32(priv, CTUCANFD_DEVICE_ID) & 0xFFFF) != CTUCANFD_ID) { 1441 priv->write_reg = ctucan_write32_be; 1442 priv->read_reg = ctucan_read32_be; 1443 if ((ctucan_read32(priv, CTUCANFD_DEVICE_ID) & 0xFFFF) != CTUCANFD_ID) { 1444 netdev_err(ndev, "CTU_CAN_FD signature not found\n"); 1445 ret = -ENODEV; 1446 goto err_deviceoff; 1447 } 1448 } 1449 1450 ret = ctucan_reset(ndev); 1451 if (ret < 0) 1452 goto err_deviceoff; 1453 1454 priv->can.clock.freq = can_clk_rate; 1455 1456 netif_napi_add(ndev, &priv->napi, ctucan_rx_poll, NAPI_POLL_WEIGHT); 1457 1458 ret = register_candev(ndev); 1459 if (ret) { 1460 dev_err(dev, "fail to register failed (err=%d)\n", ret); 1461 goto err_deviceoff; 1462 } 1463 1464 devm_can_led_init(ndev); 1465 1466 pm_runtime_put(dev); 1467 1468 netdev_dbg(ndev, "mem_base=0x%p irq=%d clock=%d, no. of txt buffers:%d\n", 1469 priv->mem_base, ndev->irq, priv->can.clock.freq, priv->ntxbufs); 1470 1471 return 0; 1472 1473 err_deviceoff: 1474 pm_runtime_put(priv->dev); 1475 err_pmdisable: 1476 if (pm_enable_call) 1477 pm_runtime_disable(dev); 1478 err_free: 1479 list_del_init(&priv->peers_on_pdev); 1480 free_candev(ndev); 1481 return ret; 1482 } 1483 EXPORT_SYMBOL(ctucan_probe_common); 1484 1485 MODULE_LICENSE("GPL"); 1486 MODULE_AUTHOR("Martin Jerabek <martin.jerabek01@gmail.com>"); 1487 MODULE_AUTHOR("Pavel Pisa <pisa@cmp.felk.cvut.cz>"); 1488 MODULE_AUTHOR("Ondrej Ille <ondrej.ille@gmail.com>"); 1489 MODULE_DESCRIPTION("CTU CAN FD interface"); 1490