1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/mtd/spi-nor.h> 11 12 #include "core.h" 13 14 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ 15 #define USE_CLSR BIT(0) 16 #define USE_CLPEF BIT(1) 17 18 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ 19 #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ 20 #define SPINOR_OP_CYPRESS_DIE_ERASE 0x61 /* Chip (die) erase */ 21 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ 22 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ 23 #define SPINOR_REG_CYPRESS_VREG 0x00800000 24 #define SPINOR_REG_CYPRESS_STR1 0x0 25 #define SPINOR_REG_CYPRESS_STR1V \ 26 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) 27 #define SPINOR_REG_CYPRESS_CFR1 0x2 28 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ 29 #define SPINOR_REG_CYPRESS_CFR2 0x3 30 #define SPINOR_REG_CYPRESS_CFR2V \ 31 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) 32 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) 33 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb 34 #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) 35 #define SPINOR_REG_CYPRESS_CFR3 0x4 36 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ 37 #define SPINOR_REG_CYPRESS_CFR5 0x6 38 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) 39 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) 40 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) 41 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ 42 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ 43 SPINOR_REG_CYPRESS_CFR5_OPI) 44 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 45 #define SPINOR_OP_CYPRESS_RD_FAST 0xee 46 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006 47 48 /* Cypress SPI NOR flash operations. */ 49 #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ 50 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ 51 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 52 SPI_MEM_OP_NO_DUMMY, \ 53 SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) 54 55 #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, ndummy, buf) \ 56 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ 57 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 58 SPI_MEM_OP_DUMMY(ndummy, 0), \ 59 SPI_MEM_OP_DATA_IN(1, buf, 0)) 60 61 #define SPANSION_OP(opcode) \ 62 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ 63 SPI_MEM_OP_NO_ADDR, \ 64 SPI_MEM_OP_NO_DUMMY, \ 65 SPI_MEM_OP_NO_DATA) 66 67 /** 68 * struct spansion_nor_params - Spansion private parameters. 69 * @clsr: Clear Status Register or Clear Program and Erase Failure Flag 70 * opcode. 71 */ 72 struct spansion_nor_params { 73 u8 clsr; 74 }; 75 76 /** 77 * spansion_nor_clear_sr() - Clear the Status Register. 78 * @nor: pointer to 'struct spi_nor'. 79 */ 80 static void spansion_nor_clear_sr(struct spi_nor *nor) 81 { 82 const struct spansion_nor_params *priv_params = nor->params->priv; 83 int ret; 84 85 if (nor->spimem) { 86 struct spi_mem_op op = SPANSION_OP(priv_params->clsr); 87 88 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 89 90 ret = spi_mem_exec_op(nor->spimem, &op); 91 } else { 92 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, 93 NULL, 0); 94 } 95 96 if (ret) 97 dev_dbg(nor->dev, "error %d clearing SR\n", ret); 98 } 99 100 static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr) 101 { 102 struct spi_nor_flash_parameter *params = nor->params; 103 struct spi_mem_op op = 104 CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, 105 0, nor->bouncebuf); 106 int ret; 107 108 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 109 op.addr.nbytes = nor->addr_nbytes; 110 op.dummy.nbytes = params->rdsr_dummy; 111 op.data.nbytes = 2; 112 } 113 114 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 115 if (ret) 116 return ret; 117 118 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 119 if (nor->bouncebuf[0] & SR_E_ERR) 120 dev_err(nor->dev, "Erase Error occurred\n"); 121 else 122 dev_err(nor->dev, "Programming Error occurred\n"); 123 124 spansion_nor_clear_sr(nor); 125 126 ret = spi_nor_write_disable(nor); 127 if (ret) 128 return ret; 129 130 return -EIO; 131 } 132 133 return !(nor->bouncebuf[0] & SR_WIP); 134 } 135 /** 136 * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by 137 * using Read Any Register command to see if the whole flash is ready for new 138 * commands and clear it if there are any errors. 139 * @nor: pointer to 'struct spi_nor'. 140 * 141 * Return: 1 if ready, 0 if not ready, -errno on errors. 142 */ 143 static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor) 144 { 145 struct spi_nor_flash_parameter *params = nor->params; 146 u64 addr; 147 int ret; 148 u8 i; 149 150 for (i = 0; i < params->n_dice; i++) { 151 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1; 152 ret = cypress_nor_sr_ready_and_clear_reg(nor, addr); 153 if (ret < 0) 154 return ret; 155 else if (ret == 0) 156 return 0; 157 } 158 159 return 1; 160 } 161 162 static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) 163 { 164 struct spi_mem_op op; 165 u8 *buf = nor->bouncebuf; 166 int ret; 167 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 168 169 op = (struct spi_mem_op) 170 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); 171 172 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 173 if (ret) 174 return ret; 175 176 /* Use 24 dummy cycles for memory array reads. */ 177 *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; 178 *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, 179 SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); 180 op = (struct spi_mem_op) 181 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); 182 183 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 184 if (ret) 185 return ret; 186 187 nor->read_dummy = 24; 188 189 return 0; 190 } 191 192 static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) 193 { 194 struct spi_mem_op op; 195 u8 *buf = nor->bouncebuf; 196 197 /* Set the octal and DTR enable bits. */ 198 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; 199 op = (struct spi_mem_op) 200 CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, 201 addr, 1, buf); 202 203 return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 204 } 205 206 static int cypress_nor_octal_dtr_en(struct spi_nor *nor) 207 { 208 const struct spi_nor_flash_parameter *params = nor->params; 209 u8 *buf = nor->bouncebuf; 210 u64 addr; 211 int i, ret; 212 213 for (i = 0; i < params->n_dice; i++) { 214 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; 215 ret = cypress_nor_set_memlat(nor, addr); 216 if (ret) 217 return ret; 218 219 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; 220 ret = cypress_nor_set_octal_dtr_bits(nor, addr); 221 if (ret) 222 return ret; 223 } 224 225 /* Read flash ID to make sure the switch was successful. */ 226 ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, 227 SNOR_PROTO_8_8_8_DTR); 228 if (ret) { 229 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); 230 return ret; 231 } 232 233 if (memcmp(buf, nor->info->id->bytes, nor->info->id->len)) 234 return -EINVAL; 235 236 return 0; 237 } 238 239 static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) 240 { 241 struct spi_mem_op op; 242 u8 *buf = nor->bouncebuf; 243 244 /* 245 * The register is 1-byte wide, but 1-byte transactions are not allowed 246 * in 8D-8D-8D mode. Since there is no register at the next location, 247 * just initialize the value to 0 and let the transaction go on. 248 */ 249 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; 250 buf[1] = 0; 251 op = (struct spi_mem_op) 252 CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); 253 return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); 254 } 255 256 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) 257 { 258 const struct spi_nor_flash_parameter *params = nor->params; 259 u8 *buf = nor->bouncebuf; 260 u64 addr; 261 int i, ret; 262 263 for (i = 0; i < params->n_dice; i++) { 264 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; 265 ret = cypress_nor_set_single_spi_bits(nor, addr); 266 if (ret) 267 return ret; 268 } 269 270 /* Read flash ID to make sure the switch was successful. */ 271 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); 272 if (ret) { 273 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); 274 return ret; 275 } 276 277 if (memcmp(buf, nor->info->id->bytes, nor->info->id->len)) 278 return -EINVAL; 279 280 return 0; 281 } 282 283 static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr) 284 { 285 struct spi_mem_op op; 286 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 287 u8 cfr1v_written; 288 int ret; 289 290 op = (struct spi_mem_op) 291 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, 292 nor->bouncebuf); 293 294 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 295 if (ret) 296 return ret; 297 298 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) 299 return 0; 300 301 /* Update the Quad Enable bit. */ 302 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; 303 op = (struct spi_mem_op) 304 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, 305 nor->bouncebuf); 306 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 307 if (ret) 308 return ret; 309 310 cfr1v_written = nor->bouncebuf[0]; 311 312 /* Read back and check it. */ 313 op = (struct spi_mem_op) 314 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, 315 nor->bouncebuf); 316 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 317 if (ret) 318 return ret; 319 320 if (nor->bouncebuf[0] != cfr1v_written) { 321 dev_err(nor->dev, "CFR1: Read back test failed\n"); 322 return -EIO; 323 } 324 325 return 0; 326 } 327 328 /** 329 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile 330 * register. 331 * @nor: pointer to a 'struct spi_nor' 332 * 333 * It is recommended to update volatile registers in the field application due 334 * to a risk of the non-volatile registers corruption by power interrupt. This 335 * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable 336 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer 337 * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is 338 * also set during Flash power-up. 339 * 340 * Return: 0 on success, -errno otherwise. 341 */ 342 static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) 343 { 344 struct spi_nor_flash_parameter *params = nor->params; 345 u64 addr; 346 u8 i; 347 int ret; 348 349 for (i = 0; i < params->n_dice; i++) { 350 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; 351 ret = cypress_nor_quad_enable_volatile_reg(nor, addr); 352 if (ret) 353 return ret; 354 } 355 356 return 0; 357 } 358 359 /** 360 * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode 361 * (3 or 4-byte) by querying status 362 * register 1 (SR1). 363 * @nor: pointer to a 'struct spi_nor' 364 * @addr_mode: ponter to a buffer where we return the determined 365 * address mode. 366 * 367 * This function tries to determine current address mode by comparing SR1 value 368 * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address). 369 * 370 * Return: 0 on success, -errno otherwise. 371 */ 372 static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor, 373 u8 *addr_mode) 374 { 375 struct spi_mem_op op = 376 CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, 377 nor->bouncebuf); 378 bool is3byte, is4byte; 379 int ret; 380 381 ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]); 382 if (ret) 383 return ret; 384 385 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 386 if (ret) 387 return ret; 388 389 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); 390 391 op = (struct spi_mem_op) 392 CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, 393 nor->bouncebuf); 394 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 395 if (ret) 396 return ret; 397 398 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); 399 400 if (is3byte == is4byte) 401 return -EIO; 402 if (is3byte) 403 *addr_mode = 3; 404 else 405 *addr_mode = 4; 406 407 return 0; 408 } 409 410 /** 411 * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of 412 * current address mode. 413 * @nor: pointer to a 'struct spi_nor' 414 * 415 * Determine current address mode by reading SR1 with different methods, then 416 * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte 417 * address mode. 418 * 419 * Return: 0 on success, -errno otherwise. 420 */ 421 static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) 422 { 423 struct spi_mem_op op; 424 u8 addr_mode; 425 int ret; 426 427 /* 428 * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable 429 * that sets bit-1 in SR1. 430 */ 431 ret = spi_nor_write_enable(nor); 432 if (ret) 433 return ret; 434 ret = cypress_nor_determine_addr_mode_by_sr1(nor, &addr_mode); 435 if (ret) { 436 ret = spi_nor_set_4byte_addr_mode(nor, true); 437 if (ret) 438 return ret; 439 return spi_nor_write_disable(nor); 440 } 441 ret = spi_nor_write_disable(nor); 442 if (ret) 443 return ret; 444 445 /* 446 * Query CFR2V and make sure no contradiction between determined address 447 * mode and CFR2V[7]. 448 */ 449 op = (struct spi_mem_op) 450 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V, 451 0, nor->bouncebuf); 452 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 453 if (ret) 454 return ret; 455 456 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { 457 if (addr_mode != 4) 458 return spi_nor_set_4byte_addr_mode(nor, true); 459 } else { 460 if (addr_mode != 3) 461 return spi_nor_set_4byte_addr_mode(nor, true); 462 } 463 464 nor->params->addr_nbytes = addr_mode; 465 nor->params->addr_mode_nbytes = addr_mode; 466 467 return 0; 468 } 469 470 /** 471 * cypress_nor_get_page_size() - Get flash page size configuration. 472 * @nor: pointer to a 'struct spi_nor' 473 * 474 * The BFPT table advertises a 512B or 256B page size depending on part but the 475 * page size is actually configurable (with the default being 256B). Read from 476 * CFR3V[4] and set the correct size. 477 * 478 * Return: 0 on success, -errno otherwise. 479 */ 480 static int cypress_nor_get_page_size(struct spi_nor *nor) 481 { 482 struct spi_mem_op op = 483 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 484 0, 0, nor->bouncebuf); 485 struct spi_nor_flash_parameter *params = nor->params; 486 int ret; 487 u8 i; 488 489 /* 490 * Use the minimum common page size configuration. Programming 256-byte 491 * under 512-byte page size configuration is safe. 492 */ 493 params->page_size = 256; 494 for (i = 0; i < params->n_dice; i++) { 495 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3; 496 497 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 498 if (ret) 499 return ret; 500 501 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) 502 return 0; 503 } 504 505 params->page_size = 512; 506 507 return 0; 508 } 509 510 static void cypress_nor_ecc_init(struct spi_nor *nor) 511 { 512 /* 513 * Programming is supported only in 16-byte ECC data unit granularity. 514 * Byte-programming, bit-walking, or multiple program operations to the 515 * same ECC data unit without an erase are not allowed. 516 */ 517 nor->params->writesize = 16; 518 nor->flags |= SNOR_F_ECC; 519 } 520 521 static int 522 s25fs256t_post_bfpt_fixup(struct spi_nor *nor, 523 const struct sfdp_parameter_header *bfpt_header, 524 const struct sfdp_bfpt *bfpt) 525 { 526 struct spi_mem_op op; 527 int ret; 528 529 ret = cypress_nor_set_addr_mode_nbytes(nor); 530 if (ret) 531 return ret; 532 533 /* Read Architecture Configuration Register (ARCFN) */ 534 op = (struct spi_mem_op) 535 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, 536 SPINOR_REG_CYPRESS_ARCFN, 1, 537 nor->bouncebuf); 538 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); 539 if (ret) 540 return ret; 541 542 /* ARCFN value must be 0 if uniform sector is selected */ 543 if (nor->bouncebuf[0]) 544 return -ENODEV; 545 546 return 0; 547 } 548 549 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) 550 { 551 struct spi_nor_flash_parameter *params = nor->params; 552 553 /* 554 * S25FS256T does not define the SCCR map, but we would like to use the 555 * same code base for both single and multi chip package devices, thus 556 * set the vreg_offset and n_dice to be able to do so. 557 */ 558 params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL); 559 if (!params->vreg_offset) 560 return -ENOMEM; 561 562 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; 563 params->n_dice = 1; 564 565 /* PP_1_1_4_4B is supported but missing in 4BAIT. */ 566 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 567 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 568 SPINOR_OP_PP_1_1_4_4B, 569 SNOR_PROTO_1_1_4); 570 571 return cypress_nor_get_page_size(nor); 572 } 573 574 static int s25fs256t_late_init(struct spi_nor *nor) 575 { 576 cypress_nor_ecc_init(nor); 577 578 return 0; 579 } 580 581 static struct spi_nor_fixups s25fs256t_fixups = { 582 .post_bfpt = s25fs256t_post_bfpt_fixup, 583 .post_sfdp = s25fs256t_post_sfdp_fixup, 584 .late_init = s25fs256t_late_init, 585 }; 586 587 static int 588 s25hx_t_post_bfpt_fixup(struct spi_nor *nor, 589 const struct sfdp_parameter_header *bfpt_header, 590 const struct sfdp_bfpt *bfpt) 591 { 592 int ret; 593 594 ret = cypress_nor_set_addr_mode_nbytes(nor); 595 if (ret) 596 return ret; 597 598 /* Replace Quad Enable with volatile version */ 599 nor->params->quad_enable = cypress_nor_quad_enable_volatile; 600 601 return 0; 602 } 603 604 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) 605 { 606 struct spi_nor_flash_parameter *params = nor->params; 607 struct spi_nor_erase_type *erase_type = params->erase_map.erase_type; 608 unsigned int i; 609 610 if (!params->n_dice || !params->vreg_offset) { 611 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", 612 __func__); 613 return -EOPNOTSUPP; 614 } 615 616 /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ 617 if (params->size == SZ_256M) 618 params->n_dice = 2; 619 620 /* 621 * In some parts, 3byte erase opcodes are advertised by 4BAIT. 622 * Convert them to 4byte erase opcodes. 623 */ 624 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 625 switch (erase_type[i].opcode) { 626 case SPINOR_OP_SE: 627 erase_type[i].opcode = SPINOR_OP_SE_4B; 628 break; 629 case SPINOR_OP_BE_4K: 630 erase_type[i].opcode = SPINOR_OP_BE_4K_4B; 631 break; 632 default: 633 break; 634 } 635 } 636 637 return cypress_nor_get_page_size(nor); 638 } 639 640 static int s25hx_t_late_init(struct spi_nor *nor) 641 { 642 struct spi_nor_flash_parameter *params = nor->params; 643 644 /* Fast Read 4B requires mode cycles */ 645 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; 646 params->ready = cypress_nor_sr_ready_and_clear; 647 cypress_nor_ecc_init(nor); 648 649 params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE; 650 return 0; 651 } 652 653 static struct spi_nor_fixups s25hx_t_fixups = { 654 .post_bfpt = s25hx_t_post_bfpt_fixup, 655 .post_sfdp = s25hx_t_post_sfdp_fixup, 656 .late_init = s25hx_t_late_init, 657 }; 658 659 /** 660 * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes. 661 * @nor: pointer to a 'struct spi_nor' 662 * @enable: whether to enable or disable Octal DTR 663 * 664 * This also sets the memory access latency cycles to 24 to allow the flash to 665 * run at up to 200MHz. 666 * 667 * Return: 0 on success, -errno otherwise. 668 */ 669 static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable) 670 { 671 return enable ? cypress_nor_octal_dtr_en(nor) : 672 cypress_nor_octal_dtr_dis(nor); 673 } 674 675 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) 676 { 677 struct spi_nor_flash_parameter *params = nor->params; 678 679 if (!params->n_dice || !params->vreg_offset) { 680 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", 681 __func__); 682 return -EOPNOTSUPP; 683 } 684 685 /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ 686 if (params->size == SZ_256M) 687 params->n_dice = 2; 688 689 /* 690 * On older versions of the flash the xSPI Profile 1.0 table has the 691 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. 692 */ 693 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) 694 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = 695 SPINOR_OP_CYPRESS_RD_FAST; 696 697 /* This flash is also missing the 4-byte Page Program opcode bit. */ 698 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 699 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); 700 /* 701 * Since xSPI Page Program opcode is backward compatible with 702 * Legacy SPI, use Legacy SPI opcode there as well. 703 */ 704 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 705 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); 706 707 /* 708 * The xSPI Profile 1.0 table advertises the number of additional 709 * address bytes needed for Read Status Register command as 0 but the 710 * actual value for that is 4. 711 */ 712 params->rdsr_addr_nbytes = 4; 713 714 return cypress_nor_get_page_size(nor); 715 } 716 717 static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, 718 const struct sfdp_parameter_header *bfpt_header, 719 const struct sfdp_bfpt *bfpt) 720 { 721 return cypress_nor_set_addr_mode_nbytes(nor); 722 } 723 724 static int s28hx_t_late_init(struct spi_nor *nor) 725 { 726 struct spi_nor_flash_parameter *params = nor->params; 727 728 params->set_octal_dtr = cypress_nor_set_octal_dtr; 729 params->ready = cypress_nor_sr_ready_and_clear; 730 cypress_nor_ecc_init(nor); 731 732 return 0; 733 } 734 735 static const struct spi_nor_fixups s28hx_t_fixups = { 736 .post_sfdp = s28hx_t_post_sfdp_fixup, 737 .post_bfpt = s28hx_t_post_bfpt_fixup, 738 .late_init = s28hx_t_late_init, 739 }; 740 741 static int 742 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, 743 const struct sfdp_parameter_header *bfpt_header, 744 const struct sfdp_bfpt *bfpt) 745 { 746 /* 747 * The S25FS-S chip family reports 512-byte pages in BFPT but 748 * in reality the write buffer still wraps at the safe default 749 * of 256 bytes. Overwrite the page size advertised by BFPT 750 * to get the writes working. 751 */ 752 nor->params->page_size = 256; 753 754 return 0; 755 } 756 757 static const struct spi_nor_fixups s25fs_s_nor_fixups = { 758 .post_bfpt = s25fs_s_nor_post_bfpt_fixups, 759 }; 760 761 static const struct flash_info spansion_nor_parts[] = { 762 { 763 .id = SNOR_ID(0x01, 0x02, 0x12), 764 .name = "s25sl004a", 765 .size = SZ_512K, 766 }, { 767 .id = SNOR_ID(0x01, 0x02, 0x13), 768 .name = "s25sl008a", 769 .size = SZ_1M, 770 }, { 771 .id = SNOR_ID(0x01, 0x02, 0x14), 772 .name = "s25sl016a", 773 .size = SZ_2M, 774 }, { 775 .id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00), 776 .name = "s25sl032p", 777 .size = SZ_4M, 778 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 779 }, { 780 .id = SNOR_ID(0x01, 0x02, 0x15), 781 .name = "s25sl032a", 782 .size = SZ_4M, 783 }, { 784 .id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00), 785 .name = "s25sl064p", 786 .size = SZ_8M, 787 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 788 }, { 789 .id = SNOR_ID(0x01, 0x02, 0x16), 790 .name = "s25sl064a", 791 .size = SZ_8M, 792 }, { 793 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80), 794 .name = "s25fl256s0", 795 .size = SZ_32M, 796 .sector_size = SZ_256K, 797 .no_sfdp_flags = SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 798 .mfr_flags = USE_CLSR, 799 }, { 800 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81), 801 .name = "s25fs256s0", 802 .size = SZ_32M, 803 .sector_size = SZ_256K, 804 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 805 .mfr_flags = USE_CLSR, 806 }, { 807 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80), 808 .name = "s25fl256s1", 809 .size = SZ_32M, 810 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 811 .mfr_flags = USE_CLSR, 812 }, { 813 .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x81), 814 .name = "s25fs256s1", 815 .size = SZ_32M, 816 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 817 .mfr_flags = USE_CLSR, 818 }, { 819 .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80), 820 .name = "s25fl512s", 821 .size = SZ_64M, 822 .sector_size = SZ_256K, 823 .flags = SPI_NOR_HAS_LOCK, 824 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 825 .mfr_flags = USE_CLSR, 826 }, { 827 .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), 828 .name = "s25fs512s", 829 .size = SZ_64M, 830 .sector_size = SZ_256K, 831 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 832 .mfr_flags = USE_CLSR, 833 .fixups = &s25fs_s_nor_fixups, 834 }, { 835 .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00), 836 .name = "s25sl12800", 837 .size = SZ_16M, 838 .sector_size = SZ_256K, 839 }, { 840 .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01), 841 .name = "s25sl12801", 842 .size = SZ_16M, 843 }, { 844 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80), 845 .name = "s25fl128s0", 846 .size = SZ_16M, 847 .sector_size = SZ_256K, 848 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 849 .mfr_flags = USE_CLSR, 850 }, { 851 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00), 852 .name = "s25fl129p0", 853 .size = SZ_16M, 854 .sector_size = SZ_256K, 855 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 856 .mfr_flags = USE_CLSR, 857 }, { 858 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80), 859 .name = "s25fl128s1", 860 .size = SZ_16M, 861 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 862 .mfr_flags = USE_CLSR, 863 }, { 864 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), 865 .name = "s25fs128s1", 866 .size = SZ_16M, 867 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 868 .mfr_flags = USE_CLSR, 869 .fixups = &s25fs_s_nor_fixups, 870 }, { 871 .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01), 872 .name = "s25fl129p1", 873 .size = SZ_16M, 874 .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 875 .mfr_flags = USE_CLSR, 876 }, { 877 .id = SNOR_ID(0x01, 0x40, 0x13), 878 .name = "s25fl204k", 879 .size = SZ_512K, 880 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ, 881 }, { 882 .id = SNOR_ID(0x01, 0x40, 0x14), 883 .name = "s25fl208k", 884 .size = SZ_1M, 885 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ, 886 }, { 887 .id = SNOR_ID(0x01, 0x40, 0x15), 888 .name = "s25fl116k", 889 .size = SZ_2M, 890 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 891 }, { 892 .id = SNOR_ID(0x01, 0x40, 0x16), 893 .name = "s25fl132k", 894 .size = SZ_4M, 895 .no_sfdp_flags = SECT_4K, 896 }, { 897 .id = SNOR_ID(0x01, 0x40, 0x17), 898 .name = "s25fl164k", 899 .size = SZ_8M, 900 .no_sfdp_flags = SECT_4K, 901 }, { 902 .id = SNOR_ID(0x01, 0x60, 0x17), 903 .name = "s25fl064l", 904 .size = SZ_8M, 905 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 906 .fixup_flags = SPI_NOR_4B_OPCODES, 907 }, { 908 .id = SNOR_ID(0x01, 0x60, 0x18), 909 .name = "s25fl128l", 910 .size = SZ_16M, 911 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 912 .fixup_flags = SPI_NOR_4B_OPCODES, 913 }, { 914 .id = SNOR_ID(0x01, 0x60, 0x19), 915 .name = "s25fl256l", 916 .size = SZ_32M, 917 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 918 .fixup_flags = SPI_NOR_4B_OPCODES, 919 }, { 920 .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f), 921 .name = "cy15x104q", 922 .size = SZ_512K, 923 .sector_size = SZ_512K, 924 .flags = SPI_NOR_NO_ERASE, 925 }, { 926 .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), 927 .name = "s25hl512t", 928 .mfr_flags = USE_CLPEF, 929 .fixups = &s25hx_t_fixups 930 }, { 931 .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), 932 .name = "s25hl01gt", 933 .mfr_flags = USE_CLPEF, 934 .fixups = &s25hx_t_fixups 935 }, { 936 .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), 937 .name = "s25hl02gt", 938 .mfr_flags = USE_CLPEF, 939 .fixups = &s25hx_t_fixups 940 }, { 941 .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), 942 .name = "s25fs256t", 943 .mfr_flags = USE_CLPEF, 944 .fixups = &s25fs256t_fixups 945 }, { 946 .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), 947 .name = "s25hs512t", 948 .mfr_flags = USE_CLPEF, 949 .fixups = &s25hx_t_fixups 950 }, { 951 .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), 952 .name = "s25hs01gt", 953 .mfr_flags = USE_CLPEF, 954 .fixups = &s25hx_t_fixups 955 }, { 956 .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), 957 .name = "s25hs02gt", 958 .mfr_flags = USE_CLPEF, 959 .fixups = &s25hx_t_fixups 960 }, { 961 .id = SNOR_ID(0x34, 0x5a, 0x1a), 962 .name = "s28hl512t", 963 .mfr_flags = USE_CLPEF, 964 .fixups = &s28hx_t_fixups, 965 }, { 966 .id = SNOR_ID(0x34, 0x5a, 0x1b), 967 .name = "s28hl01gt", 968 .mfr_flags = USE_CLPEF, 969 .fixups = &s28hx_t_fixups, 970 }, { 971 .id = SNOR_ID(0x34, 0x5b, 0x19), 972 .mfr_flags = USE_CLPEF, 973 .fixups = &s28hx_t_fixups, 974 }, { 975 .id = SNOR_ID(0x34, 0x5b, 0x1a), 976 .name = "s28hs512t", 977 .mfr_flags = USE_CLPEF, 978 .fixups = &s28hx_t_fixups, 979 }, { 980 .id = SNOR_ID(0x34, 0x5b, 0x1b), 981 .name = "s28hs01gt", 982 .mfr_flags = USE_CLPEF, 983 .fixups = &s28hx_t_fixups, 984 }, { 985 .id = SNOR_ID(0x34, 0x5b, 0x1c), 986 .name = "s28hs02gt", 987 .mfr_flags = USE_CLPEF, 988 .fixups = &s28hx_t_fixups, 989 }, { 990 .id = SNOR_ID(0xef, 0x40, 0x13), 991 .name = "s25fl004k", 992 .size = SZ_512K, 993 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 994 }, { 995 .id = SNOR_ID(0xef, 0x40, 0x14), 996 .name = "s25fl008k", 997 .size = SZ_1M, 998 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 999 }, { 1000 .id = SNOR_ID(0xef, 0x40, 0x15), 1001 .name = "s25fl016k", 1002 .size = SZ_2M, 1003 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 1004 }, { 1005 .id = SNOR_ID(0xef, 0x40, 0x17), 1006 .name = "s25fl064k", 1007 .size = SZ_8M, 1008 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 1009 } 1010 }; 1011 1012 /** 1013 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the 1014 * flash is ready for new commands and clear it if there are any errors. 1015 * @nor: pointer to 'struct spi_nor'. 1016 * 1017 * Return: 1 if ready, 0 if not ready, -errno on errors. 1018 */ 1019 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) 1020 { 1021 int ret; 1022 1023 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1024 if (ret) 1025 return ret; 1026 1027 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { 1028 if (nor->bouncebuf[0] & SR_E_ERR) 1029 dev_err(nor->dev, "Erase Error occurred\n"); 1030 else 1031 dev_err(nor->dev, "Programming Error occurred\n"); 1032 1033 spansion_nor_clear_sr(nor); 1034 1035 /* 1036 * WEL bit remains set to one when an erase or page program 1037 * error occurs. Issue a Write Disable command to protect 1038 * against inadvertent writes that can possibly corrupt the 1039 * contents of the memory. 1040 */ 1041 ret = spi_nor_write_disable(nor); 1042 if (ret) 1043 return ret; 1044 1045 return -EIO; 1046 } 1047 1048 return !(nor->bouncebuf[0] & SR_WIP); 1049 } 1050 1051 static int spansion_nor_late_init(struct spi_nor *nor) 1052 { 1053 struct spi_nor_flash_parameter *params = nor->params; 1054 struct spansion_nor_params *priv_params; 1055 u8 mfr_flags = nor->info->mfr_flags; 1056 1057 if (params->size > SZ_16M) { 1058 nor->flags |= SNOR_F_4B_OPCODES; 1059 /* No small sector erase for 4-byte command set */ 1060 nor->erase_opcode = SPINOR_OP_SE; 1061 nor->mtd.erasesize = nor->info->sector_size ?: 1062 SPI_NOR_DEFAULT_SECTOR_SIZE; 1063 } 1064 1065 if (mfr_flags & (USE_CLSR | USE_CLPEF)) { 1066 priv_params = devm_kmalloc(nor->dev, sizeof(*priv_params), 1067 GFP_KERNEL); 1068 if (!priv_params) 1069 return -ENOMEM; 1070 1071 if (mfr_flags & USE_CLSR) 1072 priv_params->clsr = SPINOR_OP_CLSR; 1073 else if (mfr_flags & USE_CLPEF) 1074 priv_params->clsr = SPINOR_OP_CLPEF; 1075 1076 params->priv = priv_params; 1077 params->ready = spansion_nor_sr_ready_and_clear; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static const struct spi_nor_fixups spansion_nor_fixups = { 1084 .late_init = spansion_nor_late_init, 1085 }; 1086 1087 const struct spi_nor_manufacturer spi_nor_spansion = { 1088 .name = "spansion", 1089 .parts = spansion_nor_parts, 1090 .nparts = ARRAY_SIZE(spansion_nor_parts), 1091 .fixups = &spansion_nor_fixups, 1092 }; 1093