1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 /* flash_info mfr_flag. Used to read proprietary FSR register. */ 12 #define USE_FSR BIT(0) 13 14 #define SPINOR_OP_MT_DIE_ERASE 0xc4 /* Chip (die) erase opcode */ 15 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ 16 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ 17 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ 18 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */ 19 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */ 20 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */ 21 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */ 22 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */ 23 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */ 24 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */ 25 26 /* Flag Status Register bits */ 27 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ 28 #define FSR_E_ERR BIT(5) /* Erase operation status */ 29 #define FSR_P_ERR BIT(4) /* Program operation status */ 30 #define FSR_PT_ERR BIT(1) /* Protection error bit */ 31 32 /* Micron ST SPI NOR flash operations. */ 33 #define MICRON_ST_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ 34 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \ 35 SPI_MEM_OP_ADDR(naddr, addr, 0), \ 36 SPI_MEM_OP_NO_DUMMY, \ 37 SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) 38 39 #define MICRON_ST_RDFSR_OP(buf) \ 40 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \ 41 SPI_MEM_OP_NO_ADDR, \ 42 SPI_MEM_OP_NO_DUMMY, \ 43 SPI_MEM_OP_DATA_IN(1, buf, 0)) 44 45 #define MICRON_ST_CLFSR_OP \ 46 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \ 47 SPI_MEM_OP_NO_ADDR, \ 48 SPI_MEM_OP_NO_DUMMY, \ 49 SPI_MEM_OP_NO_DATA) 50 51 static int micron_st_nor_octal_dtr_en(struct spi_nor *nor) 52 { 53 struct spi_mem_op op; 54 u8 *buf = nor->bouncebuf; 55 int ret; 56 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; 57 58 /* Use 20 dummy cycles for memory array reads. */ 59 *buf = 20; 60 op = (struct spi_mem_op) 61 MICRON_ST_NOR_WR_ANY_REG_OP(addr_mode_nbytes, 62 SPINOR_REG_MT_CFR1V, 1, buf); 63 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 64 if (ret) 65 return ret; 66 67 buf[0] = SPINOR_MT_OCT_DTR; 68 op = (struct spi_mem_op) 69 MICRON_ST_NOR_WR_ANY_REG_OP(addr_mode_nbytes, 70 SPINOR_REG_MT_CFR0V, 1, buf); 71 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); 72 if (ret) 73 return ret; 74 75 /* Read flash ID to make sure the switch was successful. */ 76 ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); 77 if (ret) { 78 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); 79 return ret; 80 } 81 82 if (memcmp(buf, nor->info->id->bytes, nor->info->id->len)) 83 return -EINVAL; 84 85 return 0; 86 } 87 88 static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) 89 { 90 struct spi_mem_op op; 91 u8 *buf = nor->bouncebuf; 92 int ret; 93 94 /* 95 * The register is 1-byte wide, but 1-byte transactions are not allowed 96 * in 8D-8D-8D mode. The next register is the dummy cycle configuration 97 * register. Since the transaction needs to be at least 2 bytes wide, 98 * set the next register to its default value. This also makes sense 99 * because the value was changed when enabling 8D-8D-8D mode, it should 100 * be reset when disabling. 101 */ 102 buf[0] = SPINOR_MT_EXSPI; 103 buf[1] = SPINOR_REG_MT_CFR1V_DEF; 104 op = (struct spi_mem_op) 105 MICRON_ST_NOR_WR_ANY_REG_OP(nor->addr_nbytes, 106 SPINOR_REG_MT_CFR0V, 2, buf); 107 ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); 108 if (ret) 109 return ret; 110 111 /* Read flash ID to make sure the switch was successful. */ 112 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); 113 if (ret) { 114 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); 115 return ret; 116 } 117 118 if (memcmp(buf, nor->info->id->bytes, nor->info->id->len)) 119 return -EINVAL; 120 121 return 0; 122 } 123 124 static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable) 125 { 126 return enable ? micron_st_nor_octal_dtr_en(nor) : 127 micron_st_nor_octal_dtr_dis(nor); 128 } 129 130 static int micron_st_nor_four_die_late_init(struct spi_nor *nor) 131 { 132 struct spi_nor_flash_parameter *params = nor->params; 133 134 params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; 135 params->n_dice = 4; 136 137 /* 138 * Unfortunately the die erase opcode does not have a 4-byte opcode 139 * correspondent for these flashes. The SFDP 4BAIT table fails to 140 * consider the die erase too. We're forced to enter in the 4 byte 141 * address mode in order to benefit of the die erase. 142 */ 143 return spi_nor_set_4byte_addr_mode(nor, true); 144 } 145 146 static int micron_st_nor_two_die_late_init(struct spi_nor *nor) 147 { 148 struct spi_nor_flash_parameter *params = nor->params; 149 150 params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; 151 params->n_dice = 2; 152 153 /* 154 * Unfortunately the die erase opcode does not have a 4-byte opcode 155 * correspondent for these flashes. The SFDP 4BAIT table fails to 156 * consider the die erase too. We're forced to enter in the 4 byte 157 * address mode in order to benefit of the die erase. 158 */ 159 return spi_nor_set_4byte_addr_mode(nor, true); 160 } 161 162 static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) 163 { 164 /* Set the Fast Read settings. */ 165 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 166 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], 167 0, 20, SPINOR_OP_MT_DTR_RD, 168 SNOR_PROTO_8_8_8_DTR); 169 170 /* 171 * Some batches of mt35xu512aba do not contain the OCT DTR command 172 * information, but do support OCT DTR mode. Add the settings for 173 * SNOR_CMD_PP_8_8_8_DTR here. This also makes sure the flash can switch 174 * to OCT DTR mode. 175 */ 176 nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 177 spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], 178 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); 179 180 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; 181 nor->params->rdsr_dummy = 8; 182 nor->params->rdsr_addr_nbytes = 0; 183 184 /* 185 * The BFPT quad enable field is set to a reserved value so the quad 186 * enable function is ignored by spi_nor_parse_bfpt(). Make sure we 187 * disable it. 188 */ 189 nor->params->quad_enable = NULL; 190 191 return 0; 192 } 193 194 static const struct spi_nor_fixups mt35xu512aba_fixups = { 195 .post_sfdp = mt35xu512aba_post_sfdp_fixup, 196 }; 197 198 static const struct spi_nor_fixups mt35_two_die_fixups = { 199 .post_sfdp = mt35xu512aba_post_sfdp_fixup, 200 .late_init = micron_st_nor_two_die_late_init, 201 }; 202 203 static const struct flash_info micron_nor_parts[] = { 204 { 205 /* MT35XU512ABA */ 206 .id = SNOR_ID(0x2c, 0x5b, 0x1a), 207 .mfr_flags = USE_FSR, 208 .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, 209 .fixups = &mt35xu512aba_fixups, 210 }, { 211 /* MT35XU01GBBA */ 212 .id = SNOR_ID(0x2c, 0x5b, 0x1b), 213 .mfr_flags = USE_FSR, 214 .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, 215 .fixups = &mt35_two_die_fixups, 216 }, { 217 .id = SNOR_ID(0x2c, 0x5b, 0x1c), 218 .name = "mt35xu02g", 219 .sector_size = SZ_128K, 220 .size = SZ_256M, 221 .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ, 222 .mfr_flags = USE_FSR, 223 .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE, 224 .fixups = &mt35_two_die_fixups, 225 }, 226 }; 227 228 static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor, 229 const struct sfdp_parameter_header *bfpt_header, 230 const struct sfdp_bfpt *bfpt) 231 { 232 nor->flags &= ~SNOR_F_HAS_16BIT_SR; 233 return 0; 234 } 235 236 static const struct spi_nor_fixups mt25qu512a_fixups = { 237 .post_bfpt = mt25qu512a_post_bfpt_fixup, 238 }; 239 240 static const struct spi_nor_fixups n25q00_fixups = { 241 .late_init = micron_st_nor_four_die_late_init, 242 }; 243 244 static const struct spi_nor_fixups mt25q01_fixups = { 245 .late_init = micron_st_nor_two_die_late_init, 246 }; 247 248 static const struct spi_nor_fixups mt25q02_fixups = { 249 .late_init = micron_st_nor_four_die_late_init, 250 }; 251 252 static const struct flash_info st_nor_parts[] = { 253 { 254 .name = "m25p05-nonjedec", 255 .sector_size = SZ_32K, 256 .size = SZ_64K, 257 }, { 258 .name = "m25p10-nonjedec", 259 .sector_size = SZ_32K, 260 .size = SZ_128K, 261 }, { 262 .name = "m25p20-nonjedec", 263 .size = SZ_256K, 264 }, { 265 .name = "m25p40-nonjedec", 266 .size = SZ_512K, 267 }, { 268 .name = "m25p80-nonjedec", 269 .size = SZ_1M, 270 }, { 271 .name = "m25p16-nonjedec", 272 .size = SZ_2M, 273 }, { 274 .name = "m25p32-nonjedec", 275 .size = SZ_4M, 276 }, { 277 .name = "m25p64-nonjedec", 278 .size = SZ_8M, 279 }, { 280 .name = "m25p128-nonjedec", 281 .sector_size = SZ_256K, 282 .size = SZ_16M, 283 }, { 284 .id = SNOR_ID(0x20, 0x20, 0x10), 285 .name = "m25p05", 286 .sector_size = SZ_32K, 287 .size = SZ_64K, 288 }, { 289 .id = SNOR_ID(0x20, 0x20, 0x11), 290 .name = "m25p10", 291 .sector_size = SZ_32K, 292 .size = SZ_128K, 293 }, { 294 .id = SNOR_ID(0x20, 0x20, 0x12), 295 .name = "m25p20", 296 .size = SZ_256K, 297 }, { 298 .id = SNOR_ID(0x20, 0x20, 0x13), 299 .name = "m25p40", 300 .size = SZ_512K, 301 }, { 302 .id = SNOR_ID(0x20, 0x20, 0x14), 303 .name = "m25p80", 304 .size = SZ_1M, 305 }, { 306 .id = SNOR_ID(0x20, 0x20, 0x15), 307 .name = "m25p16", 308 .size = SZ_2M, 309 }, { 310 .id = SNOR_ID(0x20, 0x20, 0x16), 311 .name = "m25p32", 312 .size = SZ_4M, 313 }, { 314 .id = SNOR_ID(0x20, 0x20, 0x17), 315 .name = "m25p64", 316 .size = SZ_8M, 317 }, { 318 .id = SNOR_ID(0x20, 0x20, 0x18), 319 .name = "m25p128", 320 .sector_size = SZ_256K, 321 .size = SZ_16M, 322 }, { 323 .id = SNOR_ID(0x20, 0x40, 0x11), 324 .name = "m45pe10", 325 .size = SZ_128K, 326 }, { 327 .id = SNOR_ID(0x20, 0x40, 0x14), 328 .name = "m45pe80", 329 .size = SZ_1M, 330 }, { 331 .id = SNOR_ID(0x20, 0x40, 0x15), 332 .name = "m45pe16", 333 .size = SZ_2M, 334 }, { 335 .id = SNOR_ID(0x20, 0x63, 0x16), 336 .name = "m25px32-s1", 337 .size = SZ_4M, 338 .no_sfdp_flags = SECT_4K, 339 }, { 340 .id = SNOR_ID(0x20, 0x71, 0x14), 341 .name = "m25px80", 342 .size = SZ_1M, 343 }, { 344 .id = SNOR_ID(0x20, 0x71, 0x15), 345 .name = "m25px16", 346 .size = SZ_2M, 347 .no_sfdp_flags = SECT_4K, 348 }, { 349 .id = SNOR_ID(0x20, 0x71, 0x16), 350 .name = "m25px32", 351 .size = SZ_4M, 352 .no_sfdp_flags = SECT_4K, 353 }, { 354 .id = SNOR_ID(0x20, 0x71, 0x17), 355 .name = "m25px64", 356 .size = SZ_8M, 357 }, { 358 .id = SNOR_ID(0x20, 0x73, 0x16), 359 .name = "m25px32-s0", 360 .size = SZ_4M, 361 .no_sfdp_flags = SECT_4K, 362 }, { 363 .id = SNOR_ID(0x20, 0x80, 0x12), 364 .name = "m25pe20", 365 .size = SZ_256K, 366 }, { 367 .id = SNOR_ID(0x20, 0x80, 0x14), 368 .name = "m25pe80", 369 .size = SZ_1M, 370 }, { 371 .id = SNOR_ID(0x20, 0x80, 0x15), 372 .name = "m25pe16", 373 .size = SZ_2M, 374 .no_sfdp_flags = SECT_4K, 375 }, { 376 .id = SNOR_ID(0x20, 0xba, 0x16), 377 .name = "n25q032", 378 .size = SZ_4M, 379 .no_sfdp_flags = SPI_NOR_QUAD_READ, 380 }, { 381 .id = SNOR_ID(0x20, 0xba, 0x17), 382 .name = "n25q064", 383 .size = SZ_8M, 384 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 385 }, { 386 .id = SNOR_ID(0x20, 0xba, 0x18), 387 .name = "n25q128a13", 388 .size = SZ_16M, 389 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 390 SPI_NOR_BP3_SR_BIT6, 391 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 392 .mfr_flags = USE_FSR, 393 }, { 394 .id = SNOR_ID(0x20, 0xba, 0x19, 0x10, 0x44, 0x00), 395 .name = "mt25ql256a", 396 .size = SZ_32M, 397 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 398 .fixup_flags = SPI_NOR_4B_OPCODES, 399 .mfr_flags = USE_FSR, 400 }, { 401 .id = SNOR_ID(0x20, 0xba, 0x19), 402 .name = "n25q256a", 403 .size = SZ_32M, 404 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 405 .mfr_flags = USE_FSR, 406 }, { 407 .id = SNOR_ID(0x20, 0xba, 0x20, 0x10, 0x44, 0x00), 408 .name = "mt25ql512a", 409 .size = SZ_64M, 410 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 411 .fixup_flags = SPI_NOR_4B_OPCODES, 412 .mfr_flags = USE_FSR, 413 }, { 414 .id = SNOR_ID(0x20, 0xba, 0x20), 415 .name = "n25q512ax3", 416 .size = SZ_64M, 417 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 418 SPI_NOR_BP3_SR_BIT6, 419 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 420 .mfr_flags = USE_FSR, 421 }, { 422 .id = SNOR_ID(0x20, 0xba, 0x21), 423 .name = "n25q00", 424 .size = SZ_128M, 425 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 426 SPI_NOR_BP3_SR_BIT6, 427 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 428 .mfr_flags = USE_FSR, 429 .fixups = &n25q00_fixups, 430 }, { 431 .id = SNOR_ID(0x20, 0xba, 0x22), 432 .name = "mt25ql02g", 433 .size = SZ_256M, 434 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 435 .mfr_flags = USE_FSR, 436 .fixups = &mt25q02_fixups, 437 }, { 438 .id = SNOR_ID(0x20, 0xbb, 0x15), 439 .name = "n25q016a", 440 .size = SZ_2M, 441 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 442 }, { 443 .id = SNOR_ID(0x20, 0xbb, 0x16), 444 .name = "n25q032a", 445 .size = SZ_4M, 446 .no_sfdp_flags = SPI_NOR_QUAD_READ, 447 }, { 448 .id = SNOR_ID(0x20, 0xbb, 0x17), 449 .name = "n25q064a", 450 .size = SZ_8M, 451 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 452 SPI_NOR_BP3_SR_BIT6, 453 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 454 }, { 455 .id = SNOR_ID(0x20, 0xbb, 0x18), 456 .name = "n25q128a11", 457 .size = SZ_16M, 458 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 459 SPI_NOR_BP3_SR_BIT6, 460 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 461 .mfr_flags = USE_FSR, 462 }, { 463 .id = SNOR_ID(0x20, 0xbb, 0x19, 0x10, 0x44, 0x00), 464 .name = "mt25qu256a", 465 .size = SZ_32M, 466 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 467 SPI_NOR_BP3_SR_BIT6, 468 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 469 .fixup_flags = SPI_NOR_4B_OPCODES, 470 .mfr_flags = USE_FSR, 471 }, { 472 .id = SNOR_ID(0x20, 0xbb, 0x19), 473 .name = "n25q256ax1", 474 .size = SZ_32M, 475 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 476 .mfr_flags = USE_FSR, 477 }, { 478 .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), 479 .name = "mt25qu512a", 480 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 481 SPI_NOR_BP3_SR_BIT6, 482 .mfr_flags = USE_FSR, 483 .fixups = &mt25qu512a_fixups, 484 }, { 485 .id = SNOR_ID(0x20, 0xbb, 0x20), 486 .name = "n25q512a", 487 .size = SZ_64M, 488 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | 489 SPI_NOR_BP3_SR_BIT6, 490 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 491 .mfr_flags = USE_FSR, 492 }, { 493 .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), 494 .name = "mt25qu01g", 495 .mfr_flags = USE_FSR, 496 .fixups = &mt25q01_fixups, 497 }, { 498 .id = SNOR_ID(0x20, 0xbb, 0x21), 499 .name = "n25q00a", 500 .size = SZ_128M, 501 .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, 502 .mfr_flags = USE_FSR, 503 .fixups = &n25q00_fixups, 504 }, { 505 .id = SNOR_ID(0x20, 0xbb, 0x22), 506 .name = "mt25qu02g", 507 .size = SZ_256M, 508 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 509 .mfr_flags = USE_FSR, 510 .fixups = &mt25q02_fixups, 511 } 512 }; 513 514 /** 515 * micron_st_nor_read_fsr() - Read the Flag Status Register. 516 * @nor: pointer to 'struct spi_nor' 517 * @fsr: pointer to a DMA-able buffer where the value of the 518 * Flag Status Register will be written. Should be at least 2 519 * bytes. 520 * 521 * Return: 0 on success, -errno otherwise. 522 */ 523 static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr) 524 { 525 int ret; 526 527 if (nor->spimem) { 528 struct spi_mem_op op = MICRON_ST_RDFSR_OP(fsr); 529 530 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 531 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 532 op.dummy.nbytes = nor->params->rdsr_dummy; 533 /* 534 * We don't want to read only one byte in DTR mode. So, 535 * read 2 and then discard the second byte. 536 */ 537 op.data.nbytes = 2; 538 } 539 540 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 541 542 ret = spi_mem_exec_op(nor->spimem, &op); 543 } else { 544 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDFSR, fsr, 545 1); 546 } 547 548 if (ret) 549 dev_dbg(nor->dev, "error %d reading FSR\n", ret); 550 551 return ret; 552 } 553 554 /** 555 * micron_st_nor_clear_fsr() - Clear the Flag Status Register. 556 * @nor: pointer to 'struct spi_nor'. 557 */ 558 static void micron_st_nor_clear_fsr(struct spi_nor *nor) 559 { 560 int ret; 561 562 if (nor->spimem) { 563 struct spi_mem_op op = MICRON_ST_CLFSR_OP; 564 565 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 566 567 ret = spi_mem_exec_op(nor->spimem, &op); 568 } else { 569 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLFSR, 570 NULL, 0); 571 } 572 573 if (ret) 574 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); 575 } 576 577 /** 578 * micron_st_nor_ready() - Query the Status Register as well as the Flag Status 579 * Register to see if the flash is ready for new commands. If there are any 580 * errors in the FSR clear them. 581 * @nor: pointer to 'struct spi_nor'. 582 * 583 * Return: 1 if ready, 0 if not ready, -errno on errors. 584 */ 585 static int micron_st_nor_ready(struct spi_nor *nor) 586 { 587 int sr_ready, ret; 588 589 sr_ready = spi_nor_sr_ready(nor); 590 if (sr_ready < 0) 591 return sr_ready; 592 593 ret = micron_st_nor_read_fsr(nor, nor->bouncebuf); 594 if (ret) { 595 /* 596 * Some controllers, such as Intel SPI, do not support low 597 * level operations such as reading the flag status 598 * register. They only expose small amount of high level 599 * operations to the software. If this is the case we use 600 * only the status register value. 601 */ 602 return ret == -EOPNOTSUPP ? sr_ready : ret; 603 } 604 605 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { 606 if (nor->bouncebuf[0] & FSR_E_ERR) 607 dev_err(nor->dev, "Erase operation failed.\n"); 608 else 609 dev_err(nor->dev, "Program operation failed.\n"); 610 611 if (nor->bouncebuf[0] & FSR_PT_ERR) 612 dev_err(nor->dev, 613 "Attempted to modify a protected sector.\n"); 614 615 micron_st_nor_clear_fsr(nor); 616 617 /* 618 * WEL bit remains set to one when an erase or page program 619 * error occurs. Issue a Write Disable command to protect 620 * against inadvertent writes that can possibly corrupt the 621 * contents of the memory. 622 */ 623 ret = spi_nor_write_disable(nor); 624 if (ret) 625 return ret; 626 627 return -EIO; 628 } 629 630 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); 631 } 632 633 static void micron_st_nor_default_init(struct spi_nor *nor) 634 { 635 nor->flags |= SNOR_F_HAS_LOCK; 636 nor->flags &= ~SNOR_F_HAS_16BIT_SR; 637 nor->params->quad_enable = NULL; 638 } 639 640 static int micron_st_nor_late_init(struct spi_nor *nor) 641 { 642 struct spi_nor_flash_parameter *params = nor->params; 643 644 if (nor->info->mfr_flags & USE_FSR) 645 params->ready = micron_st_nor_ready; 646 647 if (!params->set_4byte_addr_mode) 648 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b; 649 650 params->set_octal_dtr = micron_st_nor_set_octal_dtr; 651 652 return 0; 653 } 654 655 static const struct spi_nor_fixups micron_st_nor_fixups = { 656 .default_init = micron_st_nor_default_init, 657 .late_init = micron_st_nor_late_init, 658 }; 659 660 const struct spi_nor_manufacturer spi_nor_micron = { 661 .name = "micron", 662 .parts = micron_nor_parts, 663 .nparts = ARRAY_SIZE(micron_nor_parts), 664 .fixups = µn_st_nor_fixups, 665 }; 666 667 const struct spi_nor_manufacturer spi_nor_st = { 668 .name = "st", 669 .parts = st_nor_parts, 670 .nparts = ARRAY_SIZE(st_nor_parts), 671 .fixups = µn_st_nor_fixups, 672 }; 673