1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef __LINUX_MTD_SPI_NOR_INTERNAL_H 8 #define __LINUX_MTD_SPI_NOR_INTERNAL_H 9 10 #include "sfdp.h" 11 12 #define SPI_NOR_MAX_ID_LEN 6 13 14 enum spi_nor_option_flags { 15 SNOR_F_USE_FSR = BIT(0), 16 SNOR_F_HAS_SR_TB = BIT(1), 17 SNOR_F_NO_OP_CHIP_ERASE = BIT(2), 18 SNOR_F_READY_XSR_RDY = BIT(3), 19 SNOR_F_USE_CLSR = BIT(4), 20 SNOR_F_BROKEN_RESET = BIT(5), 21 SNOR_F_4B_OPCODES = BIT(6), 22 SNOR_F_HAS_4BAIT = BIT(7), 23 SNOR_F_HAS_LOCK = BIT(8), 24 SNOR_F_HAS_16BIT_SR = BIT(9), 25 SNOR_F_NO_READ_CR = BIT(10), 26 SNOR_F_HAS_SR_TB_BIT6 = BIT(11), 27 SNOR_F_HAS_4BIT_BP = BIT(12), 28 SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), 29 SNOR_F_IO_MODE_EN_VOLATILE = BIT(14), 30 SNOR_F_SOFT_RESET = BIT(15), 31 SNOR_F_SWP_IS_VOLATILE = BIT(16), 32 }; 33 34 struct spi_nor_read_command { 35 u8 num_mode_clocks; 36 u8 num_wait_states; 37 u8 opcode; 38 enum spi_nor_protocol proto; 39 }; 40 41 struct spi_nor_pp_command { 42 u8 opcode; 43 enum spi_nor_protocol proto; 44 }; 45 46 enum spi_nor_read_command_index { 47 SNOR_CMD_READ, 48 SNOR_CMD_READ_FAST, 49 SNOR_CMD_READ_1_1_1_DTR, 50 51 /* Dual SPI */ 52 SNOR_CMD_READ_1_1_2, 53 SNOR_CMD_READ_1_2_2, 54 SNOR_CMD_READ_2_2_2, 55 SNOR_CMD_READ_1_2_2_DTR, 56 57 /* Quad SPI */ 58 SNOR_CMD_READ_1_1_4, 59 SNOR_CMD_READ_1_4_4, 60 SNOR_CMD_READ_4_4_4, 61 SNOR_CMD_READ_1_4_4_DTR, 62 63 /* Octal SPI */ 64 SNOR_CMD_READ_1_1_8, 65 SNOR_CMD_READ_1_8_8, 66 SNOR_CMD_READ_8_8_8, 67 SNOR_CMD_READ_1_8_8_DTR, 68 SNOR_CMD_READ_8_8_8_DTR, 69 70 SNOR_CMD_READ_MAX 71 }; 72 73 enum spi_nor_pp_command_index { 74 SNOR_CMD_PP, 75 76 /* Quad SPI */ 77 SNOR_CMD_PP_1_1_4, 78 SNOR_CMD_PP_1_4_4, 79 SNOR_CMD_PP_4_4_4, 80 81 /* Octal SPI */ 82 SNOR_CMD_PP_1_1_8, 83 SNOR_CMD_PP_1_8_8, 84 SNOR_CMD_PP_8_8_8, 85 SNOR_CMD_PP_8_8_8_DTR, 86 87 SNOR_CMD_PP_MAX 88 }; 89 90 /** 91 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type 92 * @size: the size of the sector/block erased by the erase type. 93 * JEDEC JESD216B imposes erase sizes to be a power of 2. 94 * @size_shift: @size is a power of 2, the shift is stored in 95 * @size_shift. 96 * @size_mask: the size mask based on @size_shift. 97 * @opcode: the SPI command op code to erase the sector/block. 98 * @idx: Erase Type index as sorted in the Basic Flash Parameter 99 * Table. It will be used to synchronize the supported 100 * Erase Types with the ones identified in the SFDP 101 * optional tables. 102 */ 103 struct spi_nor_erase_type { 104 u32 size; 105 u32 size_shift; 106 u32 size_mask; 107 u8 opcode; 108 u8 idx; 109 }; 110 111 /** 112 * struct spi_nor_erase_command - Used for non-uniform erases 113 * The structure is used to describe a list of erase commands to be executed 114 * once we validate that the erase can be performed. The elements in the list 115 * are run-length encoded. 116 * @list: for inclusion into the list of erase commands. 117 * @count: how many times the same erase command should be 118 * consecutively used. 119 * @size: the size of the sector/block erased by the command. 120 * @opcode: the SPI command op code to erase the sector/block. 121 */ 122 struct spi_nor_erase_command { 123 struct list_head list; 124 u32 count; 125 u32 size; 126 u8 opcode; 127 }; 128 129 /** 130 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region 131 * @offset: the offset in the data array of erase region start. 132 * LSB bits are used as a bitmask encoding flags to 133 * determine if this region is overlaid, if this region is 134 * the last in the SPI NOR flash memory and to indicate 135 * all the supported erase commands inside this region. 136 * The erase types are sorted in ascending order with the 137 * smallest Erase Type size being at BIT(0). 138 * @size: the size of the region in bytes. 139 */ 140 struct spi_nor_erase_region { 141 u64 offset; 142 u64 size; 143 }; 144 145 #define SNOR_ERASE_TYPE_MAX 4 146 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0) 147 148 #define SNOR_LAST_REGION BIT(4) 149 #define SNOR_OVERLAID_REGION BIT(5) 150 151 #define SNOR_ERASE_FLAGS_MAX 6 152 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0) 153 154 /** 155 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map 156 * @regions: array of erase regions. The regions are consecutive in 157 * address space. Walking through the regions is done 158 * incrementally. 159 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform 160 * sector size (legacy implementation). 161 * @erase_type: an array of erase types shared by all the regions. 162 * The erase types are sorted in ascending order, with the 163 * smallest Erase Type size being the first member in the 164 * erase_type array. 165 * @uniform_erase_type: bitmask encoding erase types that can erase the 166 * entire memory. This member is completed at init by 167 * uniform and non-uniform SPI NOR flash memories if they 168 * support at least one erase type that can erase the 169 * entire memory. 170 */ 171 struct spi_nor_erase_map { 172 struct spi_nor_erase_region *regions; 173 struct spi_nor_erase_region uniform_region; 174 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX]; 175 u8 uniform_erase_type; 176 }; 177 178 /** 179 * struct spi_nor_locking_ops - SPI NOR locking methods 180 * @lock: lock a region of the SPI NOR. 181 * @unlock: unlock a region of the SPI NOR. 182 * @is_locked: check if a region of the SPI NOR is completely locked 183 */ 184 struct spi_nor_locking_ops { 185 int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 186 int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); 187 int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); 188 }; 189 190 /** 191 * struct spi_nor_otp_organization - Structure to describe the SPI NOR OTP regions 192 * @len: size of one OTP region in bytes. 193 * @base: start address of the OTP area. 194 * @offset: offset between consecutive OTP regions if there are more 195 * than one. 196 * @n_regions: number of individual OTP regions. 197 */ 198 struct spi_nor_otp_organization { 199 size_t len; 200 loff_t base; 201 loff_t offset; 202 unsigned int n_regions; 203 }; 204 205 /** 206 * struct spi_nor_otp_ops - SPI NOR OTP methods 207 * @read: read from the SPI NOR OTP area. 208 * @write: write to the SPI NOR OTP area. 209 * @lock: lock an OTP region. 210 * @is_locked: check if an OTP region of the SPI NOR is locked. 211 */ 212 struct spi_nor_otp_ops { 213 int (*read)(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf); 214 int (*write)(struct spi_nor *nor, loff_t addr, size_t len, 215 const u8 *buf); 216 int (*lock)(struct spi_nor *nor, unsigned int region); 217 int (*is_locked)(struct spi_nor *nor, unsigned int region); 218 }; 219 220 /** 221 * struct spi_nor_otp - SPI NOR OTP grouping structure 222 * @org: OTP region organization 223 * @ops: OTP access ops 224 */ 225 struct spi_nor_otp { 226 const struct spi_nor_otp_organization *org; 227 const struct spi_nor_otp_ops *ops; 228 }; 229 230 /** 231 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings. 232 * Includes legacy flash parameters and settings that can be overwritten 233 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216 234 * Serial Flash Discoverable Parameters (SFDP) tables. 235 * 236 * @size: the flash memory density in bytes. 237 * @writesize Minimal writable flash unit size. Defaults to 1. Set to 238 * ECC unit size for ECC-ed flashes. 239 * @page_size: the page size of the SPI NOR flash memory. 240 * @rdsr_dummy: dummy cycles needed for Read Status Register command. 241 * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register 242 * command. 243 * @hwcaps: describes the read and page program hardware 244 * capabilities. 245 * @reads: read capabilities ordered by priority: the higher index 246 * in the array, the higher priority. 247 * @page_programs: page program capabilities ordered by priority: the 248 * higher index in the array, the higher priority. 249 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter 250 * Table. 251 * @otp_info: describes the OTP regions. 252 * @octal_dtr_enable: enables SPI NOR octal DTR mode. 253 * @quad_enable: enables SPI NOR quad mode. 254 * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. 255 * @convert_addr: converts an absolute address into something the flash 256 * will understand. Particularly useful when pagesize is 257 * not a power-of-2. 258 * @setup: configures the SPI NOR memory. Useful for SPI NOR 259 * flashes that have peculiarities to the SPI NOR standard 260 * e.g. different opcodes, specific address calculation, 261 * page size, etc. 262 * @locking_ops: SPI NOR locking methods. 263 * @otp: SPI NOR OTP methods. 264 */ 265 struct spi_nor_flash_parameter { 266 u64 size; 267 u32 writesize; 268 u32 page_size; 269 u8 rdsr_dummy; 270 u8 rdsr_addr_nbytes; 271 272 struct spi_nor_hwcaps hwcaps; 273 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 274 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 275 276 struct spi_nor_erase_map erase_map; 277 struct spi_nor_otp otp; 278 279 int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); 280 int (*quad_enable)(struct spi_nor *nor); 281 int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); 282 u32 (*convert_addr)(struct spi_nor *nor, u32 addr); 283 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); 284 285 const struct spi_nor_locking_ops *locking_ops; 286 }; 287 288 /** 289 * struct spi_nor_fixups - SPI NOR fixup hooks 290 * @default_init: called after default flash parameters init. Used to tweak 291 * flash parameters when information provided by the flash_info 292 * table is incomplete or wrong. 293 * @post_bfpt: called after the BFPT table has been parsed 294 * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs 295 * that do not support RDSFDP). Typically used to tweak various 296 * parameters that could not be extracted by other means (i.e. 297 * when information provided by the SFDP/flash_info tables are 298 * incomplete or wrong). 299 * 300 * Those hooks can be used to tweak the SPI NOR configuration when the SFDP 301 * table is broken or not available. 302 */ 303 struct spi_nor_fixups { 304 void (*default_init)(struct spi_nor *nor); 305 int (*post_bfpt)(struct spi_nor *nor, 306 const struct sfdp_parameter_header *bfpt_header, 307 const struct sfdp_bfpt *bfpt); 308 void (*post_sfdp)(struct spi_nor *nor); 309 }; 310 311 struct flash_info { 312 char *name; 313 314 /* 315 * This array stores the ID bytes. 316 * The first three bytes are the JEDIC ID. 317 * JEDEC ID zero means "no ID" (mostly older chips). 318 */ 319 u8 id[SPI_NOR_MAX_ID_LEN]; 320 u8 id_len; 321 322 /* The size listed here is what works with SPINOR_OP_SE, which isn't 323 * necessarily called a "sector" by the vendor. 324 */ 325 unsigned sector_size; 326 u16 n_sectors; 327 328 u16 page_size; 329 u16 addr_width; 330 331 u32 flags; 332 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 333 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 334 #define SST_WRITE BIT(2) /* use SST byte programming */ 335 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 336 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 337 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 338 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 339 #define USE_FSR BIT(7) /* use flag status register */ 340 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 341 #define SPI_NOR_HAS_TB BIT(9) /* 342 * Flash SR has Top/Bottom (TB) protect 343 * bit. Must be used with 344 * SPI_NOR_HAS_LOCK. 345 */ 346 #define SPI_NOR_XSR_RDY BIT(10) /* 347 * S3AN flashes have specific opcode to 348 * read the status register. 349 */ 350 #define SPI_NOR_4B_OPCODES BIT(11) /* 351 * Use dedicated 4byte address op codes 352 * to support memory size above 128Mib. 353 */ 354 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 355 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 356 #define USE_CLSR BIT(14) /* use CLSR command */ 357 #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ 358 #define SPI_NOR_TB_SR_BIT6 BIT(16) /* 359 * Top/Bottom (TB) is bit 6 of 360 * status register. Must be used with 361 * SPI_NOR_HAS_TB. 362 */ 363 #define SPI_NOR_4BIT_BP BIT(17) /* 364 * Flash SR has 4 bit fields (BP0-3) 365 * for block protection. 366 */ 367 #define SPI_NOR_BP3_SR_BIT6 BIT(18) /* 368 * BP3 is bit 6 of status register. 369 * Must be used with SPI_NOR_4BIT_BP. 370 */ 371 #define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR Read. */ 372 #define SPI_NOR_OCTAL_DTR_PP BIT(20) /* Flash supports Octal DTR Page Program */ 373 #define SPI_NOR_IO_MODE_EN_VOLATILE BIT(21) /* 374 * Flash enables the best 375 * available I/O mode via a 376 * volatile bit. 377 */ 378 #define SPI_NOR_SWP_IS_VOLATILE BIT(22) /* 379 * Flash has volatile software write 380 * protection bits. Usually these will 381 * power-up in a write-protected state. 382 */ 383 384 const struct spi_nor_otp_organization otp_org; 385 386 /* Part specific fixup hooks. */ 387 const struct spi_nor_fixups *fixups; 388 }; 389 390 /* Used when the "_ext_id" is two bytes at most */ 391 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 392 .id = { \ 393 ((_jedec_id) >> 16) & 0xff, \ 394 ((_jedec_id) >> 8) & 0xff, \ 395 (_jedec_id) & 0xff, \ 396 ((_ext_id) >> 8) & 0xff, \ 397 (_ext_id) & 0xff, \ 398 }, \ 399 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 400 .sector_size = (_sector_size), \ 401 .n_sectors = (_n_sectors), \ 402 .page_size = 256, \ 403 .flags = (_flags), 404 405 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 406 .id = { \ 407 ((_jedec_id) >> 16) & 0xff, \ 408 ((_jedec_id) >> 8) & 0xff, \ 409 (_jedec_id) & 0xff, \ 410 ((_ext_id) >> 16) & 0xff, \ 411 ((_ext_id) >> 8) & 0xff, \ 412 (_ext_id) & 0xff, \ 413 }, \ 414 .id_len = 6, \ 415 .sector_size = (_sector_size), \ 416 .n_sectors = (_n_sectors), \ 417 .page_size = 256, \ 418 .flags = (_flags), 419 420 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ 421 .sector_size = (_sector_size), \ 422 .n_sectors = (_n_sectors), \ 423 .page_size = (_page_size), \ 424 .addr_width = (_addr_width), \ 425 .flags = (_flags), 426 427 #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ 428 .id = { \ 429 ((_jedec_id) >> 16) & 0xff, \ 430 ((_jedec_id) >> 8) & 0xff, \ 431 (_jedec_id) & 0xff \ 432 }, \ 433 .id_len = 3, \ 434 .sector_size = (8*_page_size), \ 435 .n_sectors = (_n_sectors), \ 436 .page_size = _page_size, \ 437 .addr_width = 3, \ 438 .flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY, 439 440 #define OTP_INFO(_len, _n_regions, _base, _offset) \ 441 .otp_org = { \ 442 .len = (_len), \ 443 .base = (_base), \ 444 .offset = (_offset), \ 445 .n_regions = (_n_regions), \ 446 }, 447 448 /** 449 * struct spi_nor_manufacturer - SPI NOR manufacturer object 450 * @name: manufacturer name 451 * @parts: array of parts supported by this manufacturer 452 * @nparts: number of entries in the parts array 453 * @fixups: hooks called at various points in time during spi_nor_scan() 454 */ 455 struct spi_nor_manufacturer { 456 const char *name; 457 const struct flash_info *parts; 458 unsigned int nparts; 459 const struct spi_nor_fixups *fixups; 460 }; 461 462 /* Manufacturer drivers. */ 463 extern const struct spi_nor_manufacturer spi_nor_atmel; 464 extern const struct spi_nor_manufacturer spi_nor_catalyst; 465 extern const struct spi_nor_manufacturer spi_nor_eon; 466 extern const struct spi_nor_manufacturer spi_nor_esmt; 467 extern const struct spi_nor_manufacturer spi_nor_everspin; 468 extern const struct spi_nor_manufacturer spi_nor_fujitsu; 469 extern const struct spi_nor_manufacturer spi_nor_gigadevice; 470 extern const struct spi_nor_manufacturer spi_nor_intel; 471 extern const struct spi_nor_manufacturer spi_nor_issi; 472 extern const struct spi_nor_manufacturer spi_nor_macronix; 473 extern const struct spi_nor_manufacturer spi_nor_micron; 474 extern const struct spi_nor_manufacturer spi_nor_st; 475 extern const struct spi_nor_manufacturer spi_nor_spansion; 476 extern const struct spi_nor_manufacturer spi_nor_sst; 477 extern const struct spi_nor_manufacturer spi_nor_winbond; 478 extern const struct spi_nor_manufacturer spi_nor_xilinx; 479 extern const struct spi_nor_manufacturer spi_nor_xmc; 480 481 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 482 struct spi_mem_op *op, 483 const enum spi_nor_protocol proto); 484 int spi_nor_write_enable(struct spi_nor *nor); 485 int spi_nor_write_disable(struct spi_nor *nor); 486 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); 487 int spi_nor_write_ear(struct spi_nor *nor, u8 ear); 488 int spi_nor_wait_till_ready(struct spi_nor *nor); 489 int spi_nor_global_block_unlock(struct spi_nor *nor); 490 int spi_nor_lock_and_prep(struct spi_nor *nor); 491 void spi_nor_unlock_and_unprep(struct spi_nor *nor); 492 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); 493 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); 494 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); 495 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr); 496 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr); 497 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); 498 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1); 499 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr); 500 501 int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); 502 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 503 u8 *buf); 504 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 505 const u8 *buf); 506 507 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf); 508 int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len, 509 const u8 *buf); 510 int spi_nor_otp_lock_sr2(struct spi_nor *nor, unsigned int region); 511 int spi_nor_otp_is_locked_sr2(struct spi_nor *nor, unsigned int region); 512 513 int spi_nor_hwcaps_read2cmd(u32 hwcaps); 514 u8 spi_nor_convert_3to4_read(u8 opcode); 515 void spi_nor_set_read_settings(struct spi_nor_read_command *read, 516 u8 num_mode_clocks, 517 u8 num_wait_states, 518 u8 opcode, 519 enum spi_nor_protocol proto); 520 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 521 enum spi_nor_protocol proto); 522 523 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 524 u8 opcode); 525 struct spi_nor_erase_region * 526 spi_nor_region_next(struct spi_nor_erase_region *region); 527 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 528 u8 erase_mask, u64 flash_size); 529 530 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 531 const struct sfdp_parameter_header *bfpt_header, 532 const struct sfdp_bfpt *bfpt); 533 534 void spi_nor_init_default_locking_ops(struct spi_nor *nor); 535 void spi_nor_try_unlock_all(struct spi_nor *nor); 536 void spi_nor_register_locking_ops(struct spi_nor *nor); 537 void spi_nor_otp_init(struct spi_nor *nor); 538 539 static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd) 540 { 541 return mtd->priv; 542 } 543 544 #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */ 545