1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/err.h> 11 #include <linux/errno.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/math64.h> 15 #include <linux/module.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/spi-nor.h> 18 #include <linux/mutex.h> 19 #include <linux/of_platform.h> 20 #include <linux/sched/task_stack.h> 21 #include <linux/sizes.h> 22 #include <linux/slab.h> 23 #include <linux/spi/flash.h> 24 25 #include "core.h" 26 27 /* Define max times to check status register before we give up. */ 28 29 /* 30 * For everything but full-chip erase; probably could be much smaller, but kept 31 * around for safety for now 32 */ 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 /* 36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 37 * for larger flash 38 */ 39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 40 41 #define SPI_NOR_MAX_ADDR_NBYTES 4 42 43 #define SPI_NOR_SRST_SLEEP_MIN 200 44 #define SPI_NOR_SRST_SLEEP_MAX 400 45 46 /** 47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the 48 * extension type. 49 * @nor: pointer to a 'struct spi_nor' 50 * @op: pointer to the 'struct spi_mem_op' whose properties 51 * need to be initialized. 52 * 53 * Right now, only "repeat" and "invert" are supported. 54 * 55 * Return: The opcode extension. 56 */ 57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, 58 const struct spi_mem_op *op) 59 { 60 switch (nor->cmd_ext_type) { 61 case SPI_NOR_EXT_INVERT: 62 return ~op->cmd.opcode; 63 64 case SPI_NOR_EXT_REPEAT: 65 return op->cmd.opcode; 66 67 default: 68 dev_err(nor->dev, "Unknown command extension type\n"); 69 return 0; 70 } 71 } 72 73 /** 74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. 75 * @nor: pointer to a 'struct spi_nor' 76 * @op: pointer to the 'struct spi_mem_op' whose properties 77 * need to be initialized. 78 * @proto: the protocol from which the properties need to be set. 79 */ 80 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 81 struct spi_mem_op *op, 82 const enum spi_nor_protocol proto) 83 { 84 u8 ext; 85 86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); 87 88 if (op->addr.nbytes) 89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); 90 91 if (op->dummy.nbytes) 92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); 93 94 if (op->data.nbytes) 95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); 96 97 if (spi_nor_protocol_is_dtr(proto)) { 98 /* 99 * SPIMEM supports mixed DTR modes, but right now we can only 100 * have all phases either DTR or STR. IOW, SPIMEM can have 101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 102 * phases to either DTR or STR. 103 */ 104 op->cmd.dtr = true; 105 op->addr.dtr = true; 106 op->dummy.dtr = true; 107 op->data.dtr = true; 108 109 /* 2 bytes per clock cycle in DTR mode. */ 110 op->dummy.nbytes *= 2; 111 112 ext = spi_nor_get_cmd_ext(nor, op); 113 op->cmd.opcode = (op->cmd.opcode << 8) | ext; 114 op->cmd.nbytes = 2; 115 } 116 } 117 118 /** 119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 120 * transfer 121 * @nor: pointer to 'struct spi_nor' 122 * @op: pointer to 'struct spi_mem_op' template for transfer 123 * 124 * If we have to use the bounce buffer, the data field in @op will be updated. 125 * 126 * Return: true if the bounce buffer is needed, false if not 127 */ 128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 129 { 130 /* op->data.buf.in occupies the same memory as op->data.buf.out */ 131 if (object_is_on_stack(op->data.buf.in) || 132 !virt_addr_valid(op->data.buf.in)) { 133 if (op->data.nbytes > nor->bouncebuf_size) 134 op->data.nbytes = nor->bouncebuf_size; 135 op->data.buf.in = nor->bouncebuf; 136 return true; 137 } 138 139 return false; 140 } 141 142 /** 143 * spi_nor_spimem_exec_op() - execute a memory operation 144 * @nor: pointer to 'struct spi_nor' 145 * @op: pointer to 'struct spi_mem_op' template for transfer 146 * 147 * Return: 0 on success, -error otherwise. 148 */ 149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 150 { 151 int error; 152 153 error = spi_mem_adjust_op_size(nor->spimem, op); 154 if (error) 155 return error; 156 157 return spi_mem_exec_op(nor->spimem, op); 158 } 159 160 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, 161 u8 *buf, size_t len) 162 { 163 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 164 return -EOPNOTSUPP; 165 166 return nor->controller_ops->read_reg(nor, opcode, buf, len); 167 } 168 169 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, 170 const u8 *buf, size_t len) 171 { 172 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 173 return -EOPNOTSUPP; 174 175 return nor->controller_ops->write_reg(nor, opcode, buf, len); 176 } 177 178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) 179 { 180 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 181 return -EOPNOTSUPP; 182 183 return nor->controller_ops->erase(nor, offs); 184 } 185 186 /** 187 * spi_nor_spimem_read_data() - read data from flash's memory region via 188 * spi-mem 189 * @nor: pointer to 'struct spi_nor' 190 * @from: offset to read from 191 * @len: number of bytes to read 192 * @buf: pointer to dst buffer 193 * 194 * Return: number of bytes read successfully, -errno otherwise 195 */ 196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 197 size_t len, u8 *buf) 198 { 199 struct spi_mem_op op = 200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 201 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0), 202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 203 SPI_MEM_OP_DATA_IN(len, buf, 0)); 204 bool usebouncebuf; 205 ssize_t nbytes; 206 int error; 207 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); 209 210 /* convert the dummy cycles to the number of bytes */ 211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 212 if (spi_nor_protocol_is_dtr(nor->read_proto)) 213 op.dummy.nbytes *= 2; 214 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op); 216 217 if (nor->dirmap.rdesc) { 218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 219 op.data.nbytes, op.data.buf.in); 220 } else { 221 error = spi_nor_spimem_exec_op(nor, &op); 222 if (error) 223 return error; 224 nbytes = op.data.nbytes; 225 } 226 227 if (usebouncebuf && nbytes > 0) 228 memcpy(buf, op.data.buf.in, nbytes); 229 230 return nbytes; 231 } 232 233 /** 234 * spi_nor_read_data() - read data from flash memory 235 * @nor: pointer to 'struct spi_nor' 236 * @from: offset to read from 237 * @len: number of bytes to read 238 * @buf: pointer to dst buffer 239 * 240 * Return: number of bytes read successfully, -errno otherwise 241 */ 242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 243 { 244 if (nor->spimem) 245 return spi_nor_spimem_read_data(nor, from, len, buf); 246 247 return nor->controller_ops->read(nor, from, len, buf); 248 } 249 250 /** 251 * spi_nor_spimem_write_data() - write data to flash memory via 252 * spi-mem 253 * @nor: pointer to 'struct spi_nor' 254 * @to: offset to write to 255 * @len: number of bytes to write 256 * @buf: pointer to src buffer 257 * 258 * Return: number of bytes written successfully, -errno otherwise 259 */ 260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 261 size_t len, const u8 *buf) 262 { 263 struct spi_mem_op op = 264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 265 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0), 266 SPI_MEM_OP_NO_DUMMY, 267 SPI_MEM_OP_DATA_OUT(len, buf, 0)); 268 ssize_t nbytes; 269 int error; 270 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 272 op.addr.nbytes = 0; 273 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 275 276 if (spi_nor_spimem_bounce(nor, &op)) 277 memcpy(nor->bouncebuf, buf, op.data.nbytes); 278 279 if (nor->dirmap.wdesc) { 280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 281 op.data.nbytes, op.data.buf.out); 282 } else { 283 error = spi_nor_spimem_exec_op(nor, &op); 284 if (error) 285 return error; 286 nbytes = op.data.nbytes; 287 } 288 289 return nbytes; 290 } 291 292 /** 293 * spi_nor_write_data() - write data to flash memory 294 * @nor: pointer to 'struct spi_nor' 295 * @to: offset to write to 296 * @len: number of bytes to write 297 * @buf: pointer to src buffer 298 * 299 * Return: number of bytes written successfully, -errno otherwise 300 */ 301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 302 const u8 *buf) 303 { 304 if (nor->spimem) 305 return spi_nor_spimem_write_data(nor, to, len, buf); 306 307 return nor->controller_ops->write(nor, to, len, buf); 308 } 309 310 /** 311 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or 312 * volatile. 313 * @nor: pointer to 'struct spi_nor'. 314 * @op: SPI memory operation. op->data.buf must be DMA-able. 315 * @proto: SPI protocol to use for the register operation. 316 * 317 * Return: zero on success, -errno otherwise 318 */ 319 int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op, 320 enum spi_nor_protocol proto) 321 { 322 if (!nor->spimem) 323 return -EOPNOTSUPP; 324 325 spi_nor_spimem_setup_op(nor, op, proto); 326 return spi_nor_spimem_exec_op(nor, op); 327 } 328 329 /** 330 * spi_nor_write_any_volatile_reg() - write any volatile register to flash 331 * memory. 332 * @nor: pointer to 'struct spi_nor' 333 * @op: SPI memory operation. op->data.buf must be DMA-able. 334 * @proto: SPI protocol to use for the register operation. 335 * 336 * Writing volatile registers are instant according to some manufacturers 337 * (Cypress, Micron) and do not need any status polling. 338 * 339 * Return: zero on success, -errno otherwise 340 */ 341 int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op, 342 enum spi_nor_protocol proto) 343 { 344 int ret; 345 346 if (!nor->spimem) 347 return -EOPNOTSUPP; 348 349 ret = spi_nor_write_enable(nor); 350 if (ret) 351 return ret; 352 spi_nor_spimem_setup_op(nor, op, proto); 353 return spi_nor_spimem_exec_op(nor, op); 354 } 355 356 /** 357 * spi_nor_write_enable() - Set write enable latch with Write Enable command. 358 * @nor: pointer to 'struct spi_nor'. 359 * 360 * Return: 0 on success, -errno otherwise. 361 */ 362 int spi_nor_write_enable(struct spi_nor *nor) 363 { 364 int ret; 365 366 if (nor->spimem) { 367 struct spi_mem_op op = SPI_NOR_WREN_OP; 368 369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 370 371 ret = spi_mem_exec_op(nor->spimem, &op); 372 } else { 373 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, 374 NULL, 0); 375 } 376 377 if (ret) 378 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 379 380 return ret; 381 } 382 383 /** 384 * spi_nor_write_disable() - Send Write Disable instruction to the chip. 385 * @nor: pointer to 'struct spi_nor'. 386 * 387 * Return: 0 on success, -errno otherwise. 388 */ 389 int spi_nor_write_disable(struct spi_nor *nor) 390 { 391 int ret; 392 393 if (nor->spimem) { 394 struct spi_mem_op op = SPI_NOR_WRDI_OP; 395 396 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 397 398 ret = spi_mem_exec_op(nor->spimem, &op); 399 } else { 400 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, 401 NULL, 0); 402 } 403 404 if (ret) 405 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 406 407 return ret; 408 } 409 410 /** 411 * spi_nor_read_id() - Read the JEDEC ID. 412 * @nor: pointer to 'struct spi_nor'. 413 * @naddr: number of address bytes to send. Can be zero if the operation 414 * does not need to send an address. 415 * @ndummy: number of dummy bytes to send after an opcode or address. Can 416 * be zero if the operation does not require dummy bytes. 417 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID 418 * will be written. 419 * @proto: the SPI protocol for register operation. 420 * 421 * Return: 0 on success, -errno otherwise. 422 */ 423 int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id, 424 enum spi_nor_protocol proto) 425 { 426 int ret; 427 428 if (nor->spimem) { 429 struct spi_mem_op op = 430 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN); 431 432 spi_nor_spimem_setup_op(nor, &op, proto); 433 ret = spi_mem_exec_op(nor->spimem, &op); 434 } else { 435 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 436 SPI_NOR_MAX_ID_LEN); 437 } 438 return ret; 439 } 440 441 /** 442 * spi_nor_read_sr() - Read the Status Register. 443 * @nor: pointer to 'struct spi_nor'. 444 * @sr: pointer to a DMA-able buffer where the value of the 445 * Status Register will be written. Should be at least 2 bytes. 446 * 447 * Return: 0 on success, -errno otherwise. 448 */ 449 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 450 { 451 int ret; 452 453 if (nor->spimem) { 454 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr); 455 456 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 457 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 458 op.dummy.nbytes = nor->params->rdsr_dummy; 459 /* 460 * We don't want to read only one byte in DTR mode. So, 461 * read 2 and then discard the second byte. 462 */ 463 op.data.nbytes = 2; 464 } 465 466 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 467 468 ret = spi_mem_exec_op(nor->spimem, &op); 469 } else { 470 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, 471 1); 472 } 473 474 if (ret) 475 dev_dbg(nor->dev, "error %d reading SR\n", ret); 476 477 return ret; 478 } 479 480 /** 481 * spi_nor_read_cr() - Read the Configuration Register using the 482 * SPINOR_OP_RDCR (35h) command. 483 * @nor: pointer to 'struct spi_nor' 484 * @cr: pointer to a DMA-able buffer where the value of the 485 * Configuration Register will be written. 486 * 487 * Return: 0 on success, -errno otherwise. 488 */ 489 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 490 { 491 int ret; 492 493 if (nor->spimem) { 494 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr); 495 496 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 497 498 ret = spi_mem_exec_op(nor->spimem, &op); 499 } else { 500 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, 501 1); 502 } 503 504 if (ret) 505 dev_dbg(nor->dev, "error %d reading CR\n", ret); 506 507 return ret; 508 } 509 510 /** 511 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode 512 * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by 513 * Winbond and Macronix. 514 * @nor: pointer to 'struct spi_nor'. 515 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 516 * address mode. 517 * 518 * Return: 0 on success, -errno otherwise. 519 */ 520 int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable) 521 { 522 int ret; 523 524 if (nor->spimem) { 525 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable); 526 527 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 528 529 ret = spi_mem_exec_op(nor->spimem, &op); 530 } else { 531 ret = spi_nor_controller_ops_write_reg(nor, 532 enable ? SPINOR_OP_EN4B : 533 SPINOR_OP_EX4B, 534 NULL, 0); 535 } 536 537 if (ret) 538 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 539 540 return ret; 541 } 542 543 /** 544 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using 545 * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used 546 * by ST and Micron flashes. 547 * @nor: pointer to 'struct spi_nor'. 548 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 549 * address mode. 550 * 551 * Return: 0 on success, -errno otherwise. 552 */ 553 int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable) 554 { 555 int ret; 556 557 ret = spi_nor_write_enable(nor); 558 if (ret) 559 return ret; 560 561 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); 562 if (ret) 563 return ret; 564 565 return spi_nor_write_disable(nor); 566 } 567 568 /** 569 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using 570 * SPINOR_OP_BRWR. Typically used by Spansion flashes. 571 * @nor: pointer to 'struct spi_nor'. 572 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 573 * address mode. 574 * 575 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is 576 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte 577 * address mode is active and A[30:24] bits are don’t care. Write instruction is 578 * SPINOR_OP_BRWR(17h) with 1 byte of data. 579 * 580 * Return: 0 on success, -errno otherwise. 581 */ 582 int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable) 583 { 584 int ret; 585 586 nor->bouncebuf[0] = enable << 7; 587 588 if (nor->spimem) { 589 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf); 590 591 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 592 593 ret = spi_mem_exec_op(nor->spimem, &op); 594 } else { 595 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, 596 nor->bouncebuf, 1); 597 } 598 599 if (ret) 600 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 601 602 return ret; 603 } 604 605 /** 606 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 607 * for new commands. 608 * @nor: pointer to 'struct spi_nor'. 609 * 610 * Return: 1 if ready, 0 if not ready, -errno on errors. 611 */ 612 int spi_nor_sr_ready(struct spi_nor *nor) 613 { 614 int ret; 615 616 ret = spi_nor_read_sr(nor, nor->bouncebuf); 617 if (ret) 618 return ret; 619 620 return !(nor->bouncebuf[0] & SR_WIP); 621 } 622 623 /** 624 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used 625 * @nor: pointer to 'struct spi_nor'. 626 * 627 * Return: true if parallel locking is enabled, false otherwise. 628 */ 629 static bool spi_nor_use_parallel_locking(struct spi_nor *nor) 630 { 631 return nor->flags & SNOR_F_RWW; 632 } 633 634 /* Locking helpers for status read operations */ 635 static int spi_nor_rww_start_rdst(struct spi_nor *nor) 636 { 637 struct spi_nor_rww *rww = &nor->rww; 638 int ret = -EAGAIN; 639 640 mutex_lock(&nor->lock); 641 642 if (rww->ongoing_io || rww->ongoing_rd) 643 goto busy; 644 645 rww->ongoing_io = true; 646 rww->ongoing_rd = true; 647 ret = 0; 648 649 busy: 650 mutex_unlock(&nor->lock); 651 return ret; 652 } 653 654 static void spi_nor_rww_end_rdst(struct spi_nor *nor) 655 { 656 struct spi_nor_rww *rww = &nor->rww; 657 658 mutex_lock(&nor->lock); 659 660 rww->ongoing_io = false; 661 rww->ongoing_rd = false; 662 663 mutex_unlock(&nor->lock); 664 } 665 666 static int spi_nor_lock_rdst(struct spi_nor *nor) 667 { 668 if (spi_nor_use_parallel_locking(nor)) 669 return spi_nor_rww_start_rdst(nor); 670 671 return 0; 672 } 673 674 static void spi_nor_unlock_rdst(struct spi_nor *nor) 675 { 676 if (spi_nor_use_parallel_locking(nor)) { 677 spi_nor_rww_end_rdst(nor); 678 wake_up(&nor->rww.wait); 679 } 680 } 681 682 /** 683 * spi_nor_ready() - Query the flash to see if it is ready for new commands. 684 * @nor: pointer to 'struct spi_nor'. 685 * 686 * Return: 1 if ready, 0 if not ready, -errno on errors. 687 */ 688 static int spi_nor_ready(struct spi_nor *nor) 689 { 690 int ret; 691 692 ret = spi_nor_lock_rdst(nor); 693 if (ret) 694 return 0; 695 696 /* Flashes might override the standard routine. */ 697 if (nor->params->ready) 698 ret = nor->params->ready(nor); 699 else 700 ret = spi_nor_sr_ready(nor); 701 702 spi_nor_unlock_rdst(nor); 703 704 return ret; 705 } 706 707 /** 708 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 709 * Status Register until ready, or timeout occurs. 710 * @nor: pointer to "struct spi_nor". 711 * @timeout_jiffies: jiffies to wait until timeout. 712 * 713 * Return: 0 on success, -errno otherwise. 714 */ 715 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 716 unsigned long timeout_jiffies) 717 { 718 unsigned long deadline; 719 int timeout = 0, ret; 720 721 deadline = jiffies + timeout_jiffies; 722 723 while (!timeout) { 724 if (time_after_eq(jiffies, deadline)) 725 timeout = 1; 726 727 ret = spi_nor_ready(nor); 728 if (ret < 0) 729 return ret; 730 if (ret) 731 return 0; 732 733 cond_resched(); 734 } 735 736 dev_dbg(nor->dev, "flash operation timed out\n"); 737 738 return -ETIMEDOUT; 739 } 740 741 /** 742 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 743 * flash to be ready, or timeout occurs. 744 * @nor: pointer to "struct spi_nor". 745 * 746 * Return: 0 on success, -errno otherwise. 747 */ 748 int spi_nor_wait_till_ready(struct spi_nor *nor) 749 { 750 return spi_nor_wait_till_ready_with_timeout(nor, 751 DEFAULT_READY_WAIT_JIFFIES); 752 } 753 754 /** 755 * spi_nor_global_block_unlock() - Unlock Global Block Protection. 756 * @nor: pointer to 'struct spi_nor'. 757 * 758 * Return: 0 on success, -errno otherwise. 759 */ 760 int spi_nor_global_block_unlock(struct spi_nor *nor) 761 { 762 int ret; 763 764 ret = spi_nor_write_enable(nor); 765 if (ret) 766 return ret; 767 768 if (nor->spimem) { 769 struct spi_mem_op op = SPI_NOR_GBULK_OP; 770 771 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 772 773 ret = spi_mem_exec_op(nor->spimem, &op); 774 } else { 775 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, 776 NULL, 0); 777 } 778 779 if (ret) { 780 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); 781 return ret; 782 } 783 784 return spi_nor_wait_till_ready(nor); 785 } 786 787 /** 788 * spi_nor_write_sr() - Write the Status Register. 789 * @nor: pointer to 'struct spi_nor'. 790 * @sr: pointer to DMA-able buffer to write to the Status Register. 791 * @len: number of bytes to write to the Status Register. 792 * 793 * Return: 0 on success, -errno otherwise. 794 */ 795 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 796 { 797 int ret; 798 799 ret = spi_nor_write_enable(nor); 800 if (ret) 801 return ret; 802 803 if (nor->spimem) { 804 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len); 805 806 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 807 808 ret = spi_mem_exec_op(nor->spimem, &op); 809 } else { 810 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, 811 len); 812 } 813 814 if (ret) { 815 dev_dbg(nor->dev, "error %d writing SR\n", ret); 816 return ret; 817 } 818 819 return spi_nor_wait_till_ready(nor); 820 } 821 822 /** 823 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 824 * ensure that the byte written match the received value. 825 * @nor: pointer to a 'struct spi_nor'. 826 * @sr1: byte value to be written to the Status Register. 827 * 828 * Return: 0 on success, -errno otherwise. 829 */ 830 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 831 { 832 int ret; 833 834 nor->bouncebuf[0] = sr1; 835 836 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 837 if (ret) 838 return ret; 839 840 ret = spi_nor_read_sr(nor, nor->bouncebuf); 841 if (ret) 842 return ret; 843 844 if (nor->bouncebuf[0] != sr1) { 845 dev_dbg(nor->dev, "SR1: read back test failed\n"); 846 return -EIO; 847 } 848 849 return 0; 850 } 851 852 /** 853 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 854 * Status Register 2 in one shot. Ensure that the byte written in the Status 855 * Register 1 match the received value, and that the 16-bit Write did not 856 * affect what was already in the Status Register 2. 857 * @nor: pointer to a 'struct spi_nor'. 858 * @sr1: byte value to be written to the Status Register 1. 859 * 860 * Return: 0 on success, -errno otherwise. 861 */ 862 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 863 { 864 int ret; 865 u8 *sr_cr = nor->bouncebuf; 866 u8 cr_written; 867 868 /* Make sure we don't overwrite the contents of Status Register 2. */ 869 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 870 ret = spi_nor_read_cr(nor, &sr_cr[1]); 871 if (ret) 872 return ret; 873 } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 && 874 spi_nor_get_protocol_width(nor->write_proto) == 4 && 875 nor->params->quad_enable) { 876 /* 877 * If the Status Register 2 Read command (35h) is not 878 * supported, we should at least be sure we don't 879 * change the value of the SR2 Quad Enable bit. 880 * 881 * When the Quad Enable method is set and the buswidth is 4, we 882 * can safely assume that the value of the QE bit is one, as a 883 * consequence of the nor->params->quad_enable() call. 884 * 885 * According to the JESD216 revB standard, BFPT DWORDS[15], 886 * bits 22:20, the 16-bit Write Status (01h) command is 887 * available just for the cases in which the QE bit is 888 * described in SR2 at BIT(1). 889 */ 890 sr_cr[1] = SR2_QUAD_EN_BIT1; 891 } else { 892 sr_cr[1] = 0; 893 } 894 895 sr_cr[0] = sr1; 896 897 ret = spi_nor_write_sr(nor, sr_cr, 2); 898 if (ret) 899 return ret; 900 901 ret = spi_nor_read_sr(nor, sr_cr); 902 if (ret) 903 return ret; 904 905 if (sr1 != sr_cr[0]) { 906 dev_dbg(nor->dev, "SR: Read back test failed\n"); 907 return -EIO; 908 } 909 910 if (nor->flags & SNOR_F_NO_READ_CR) 911 return 0; 912 913 cr_written = sr_cr[1]; 914 915 ret = spi_nor_read_cr(nor, &sr_cr[1]); 916 if (ret) 917 return ret; 918 919 if (cr_written != sr_cr[1]) { 920 dev_dbg(nor->dev, "CR: read back test failed\n"); 921 return -EIO; 922 } 923 924 return 0; 925 } 926 927 /** 928 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 929 * Configuration Register in one shot. Ensure that the byte written in the 930 * Configuration Register match the received value, and that the 16-bit Write 931 * did not affect what was already in the Status Register 1. 932 * @nor: pointer to a 'struct spi_nor'. 933 * @cr: byte value to be written to the Configuration Register. 934 * 935 * Return: 0 on success, -errno otherwise. 936 */ 937 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 938 { 939 int ret; 940 u8 *sr_cr = nor->bouncebuf; 941 u8 sr_written; 942 943 /* Keep the current value of the Status Register 1. */ 944 ret = spi_nor_read_sr(nor, sr_cr); 945 if (ret) 946 return ret; 947 948 sr_cr[1] = cr; 949 950 ret = spi_nor_write_sr(nor, sr_cr, 2); 951 if (ret) 952 return ret; 953 954 sr_written = sr_cr[0]; 955 956 ret = spi_nor_read_sr(nor, sr_cr); 957 if (ret) 958 return ret; 959 960 if (sr_written != sr_cr[0]) { 961 dev_dbg(nor->dev, "SR: Read back test failed\n"); 962 return -EIO; 963 } 964 965 if (nor->flags & SNOR_F_NO_READ_CR) 966 return 0; 967 968 ret = spi_nor_read_cr(nor, &sr_cr[1]); 969 if (ret) 970 return ret; 971 972 if (cr != sr_cr[1]) { 973 dev_dbg(nor->dev, "CR: read back test failed\n"); 974 return -EIO; 975 } 976 977 return 0; 978 } 979 980 /** 981 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 982 * the byte written match the received value without affecting other bits in the 983 * Status Register 1 and 2. 984 * @nor: pointer to a 'struct spi_nor'. 985 * @sr1: byte value to be written to the Status Register. 986 * 987 * Return: 0 on success, -errno otherwise. 988 */ 989 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 990 { 991 if (nor->flags & SNOR_F_HAS_16BIT_SR) 992 return spi_nor_write_16bit_sr_and_check(nor, sr1); 993 994 return spi_nor_write_sr1_and_check(nor, sr1); 995 } 996 997 /** 998 * spi_nor_write_sr2() - Write the Status Register 2 using the 999 * SPINOR_OP_WRSR2 (3eh) command. 1000 * @nor: pointer to 'struct spi_nor'. 1001 * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 1002 * 1003 * Return: 0 on success, -errno otherwise. 1004 */ 1005 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 1006 { 1007 int ret; 1008 1009 ret = spi_nor_write_enable(nor); 1010 if (ret) 1011 return ret; 1012 1013 if (nor->spimem) { 1014 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2); 1015 1016 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1017 1018 ret = spi_mem_exec_op(nor->spimem, &op); 1019 } else { 1020 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, 1021 sr2, 1); 1022 } 1023 1024 if (ret) { 1025 dev_dbg(nor->dev, "error %d writing SR2\n", ret); 1026 return ret; 1027 } 1028 1029 return spi_nor_wait_till_ready(nor); 1030 } 1031 1032 /** 1033 * spi_nor_read_sr2() - Read the Status Register 2 using the 1034 * SPINOR_OP_RDSR2 (3fh) command. 1035 * @nor: pointer to 'struct spi_nor'. 1036 * @sr2: pointer to DMA-able buffer where the value of the 1037 * Status Register 2 will be written. 1038 * 1039 * Return: 0 on success, -errno otherwise. 1040 */ 1041 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 1042 { 1043 int ret; 1044 1045 if (nor->spimem) { 1046 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2); 1047 1048 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1049 1050 ret = spi_mem_exec_op(nor->spimem, &op); 1051 } else { 1052 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, 1053 1); 1054 } 1055 1056 if (ret) 1057 dev_dbg(nor->dev, "error %d reading SR2\n", ret); 1058 1059 return ret; 1060 } 1061 1062 /** 1063 * spi_nor_erase_chip() - Erase the entire flash memory. 1064 * @nor: pointer to 'struct spi_nor'. 1065 * 1066 * Return: 0 on success, -errno otherwise. 1067 */ 1068 static int spi_nor_erase_chip(struct spi_nor *nor) 1069 { 1070 int ret; 1071 1072 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 1073 1074 if (nor->spimem) { 1075 struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP; 1076 1077 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1078 1079 ret = spi_mem_exec_op(nor->spimem, &op); 1080 } else { 1081 ret = spi_nor_controller_ops_write_reg(nor, 1082 SPINOR_OP_CHIP_ERASE, 1083 NULL, 0); 1084 } 1085 1086 if (ret) 1087 dev_dbg(nor->dev, "error %d erasing chip\n", ret); 1088 1089 return ret; 1090 } 1091 1092 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 1093 { 1094 size_t i; 1095 1096 for (i = 0; i < size; i++) 1097 if (table[i][0] == opcode) 1098 return table[i][1]; 1099 1100 /* No conversion found, keep input op code. */ 1101 return opcode; 1102 } 1103 1104 u8 spi_nor_convert_3to4_read(u8 opcode) 1105 { 1106 static const u8 spi_nor_3to4_read[][2] = { 1107 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1108 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1109 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1110 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1111 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1112 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1113 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1114 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1115 1116 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1117 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1118 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1119 }; 1120 1121 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1122 ARRAY_SIZE(spi_nor_3to4_read)); 1123 } 1124 1125 static u8 spi_nor_convert_3to4_program(u8 opcode) 1126 { 1127 static const u8 spi_nor_3to4_program[][2] = { 1128 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1129 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1130 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1131 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1132 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1133 }; 1134 1135 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1136 ARRAY_SIZE(spi_nor_3to4_program)); 1137 } 1138 1139 static u8 spi_nor_convert_3to4_erase(u8 opcode) 1140 { 1141 static const u8 spi_nor_3to4_erase[][2] = { 1142 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1143 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1144 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1145 }; 1146 1147 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1148 ARRAY_SIZE(spi_nor_3to4_erase)); 1149 } 1150 1151 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1152 { 1153 return !!nor->params->erase_map.uniform_erase_type; 1154 } 1155 1156 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1157 { 1158 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1159 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1160 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1161 1162 if (!spi_nor_has_uniform_erase(nor)) { 1163 struct spi_nor_erase_map *map = &nor->params->erase_map; 1164 struct spi_nor_erase_type *erase; 1165 int i; 1166 1167 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1168 erase = &map->erase_type[i]; 1169 erase->opcode = 1170 spi_nor_convert_3to4_erase(erase->opcode); 1171 } 1172 } 1173 } 1174 1175 static int spi_nor_prep(struct spi_nor *nor) 1176 { 1177 int ret = 0; 1178 1179 if (nor->controller_ops && nor->controller_ops->prepare) 1180 ret = nor->controller_ops->prepare(nor); 1181 1182 return ret; 1183 } 1184 1185 static void spi_nor_unprep(struct spi_nor *nor) 1186 { 1187 if (nor->controller_ops && nor->controller_ops->unprepare) 1188 nor->controller_ops->unprepare(nor); 1189 } 1190 1191 static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len, 1192 u8 *first, u8 *last) 1193 { 1194 /* This is currently safe, the number of banks being very small */ 1195 *first = DIV_ROUND_DOWN_ULL(start, bank_size); 1196 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size); 1197 } 1198 1199 /* Generic helpers for internal locking and serialization */ 1200 static bool spi_nor_rww_start_io(struct spi_nor *nor) 1201 { 1202 struct spi_nor_rww *rww = &nor->rww; 1203 bool start = false; 1204 1205 mutex_lock(&nor->lock); 1206 1207 if (rww->ongoing_io) 1208 goto busy; 1209 1210 rww->ongoing_io = true; 1211 start = true; 1212 1213 busy: 1214 mutex_unlock(&nor->lock); 1215 return start; 1216 } 1217 1218 static void spi_nor_rww_end_io(struct spi_nor *nor) 1219 { 1220 mutex_lock(&nor->lock); 1221 nor->rww.ongoing_io = false; 1222 mutex_unlock(&nor->lock); 1223 } 1224 1225 static int spi_nor_lock_device(struct spi_nor *nor) 1226 { 1227 if (!spi_nor_use_parallel_locking(nor)) 1228 return 0; 1229 1230 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor)); 1231 } 1232 1233 static void spi_nor_unlock_device(struct spi_nor *nor) 1234 { 1235 if (spi_nor_use_parallel_locking(nor)) { 1236 spi_nor_rww_end_io(nor); 1237 wake_up(&nor->rww.wait); 1238 } 1239 } 1240 1241 /* Generic helpers for internal locking and serialization */ 1242 static bool spi_nor_rww_start_exclusive(struct spi_nor *nor) 1243 { 1244 struct spi_nor_rww *rww = &nor->rww; 1245 bool start = false; 1246 1247 mutex_lock(&nor->lock); 1248 1249 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) 1250 goto busy; 1251 1252 rww->ongoing_io = true; 1253 rww->ongoing_rd = true; 1254 rww->ongoing_pe = true; 1255 start = true; 1256 1257 busy: 1258 mutex_unlock(&nor->lock); 1259 return start; 1260 } 1261 1262 static void spi_nor_rww_end_exclusive(struct spi_nor *nor) 1263 { 1264 struct spi_nor_rww *rww = &nor->rww; 1265 1266 mutex_lock(&nor->lock); 1267 rww->ongoing_io = false; 1268 rww->ongoing_rd = false; 1269 rww->ongoing_pe = false; 1270 mutex_unlock(&nor->lock); 1271 } 1272 1273 int spi_nor_prep_and_lock(struct spi_nor *nor) 1274 { 1275 int ret; 1276 1277 ret = spi_nor_prep(nor); 1278 if (ret) 1279 return ret; 1280 1281 if (!spi_nor_use_parallel_locking(nor)) 1282 mutex_lock(&nor->lock); 1283 else 1284 ret = wait_event_killable(nor->rww.wait, 1285 spi_nor_rww_start_exclusive(nor)); 1286 1287 return ret; 1288 } 1289 1290 void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1291 { 1292 if (!spi_nor_use_parallel_locking(nor)) { 1293 mutex_unlock(&nor->lock); 1294 } else { 1295 spi_nor_rww_end_exclusive(nor); 1296 wake_up(&nor->rww.wait); 1297 } 1298 1299 spi_nor_unprep(nor); 1300 } 1301 1302 /* Internal locking helpers for program and erase operations */ 1303 static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len) 1304 { 1305 struct spi_nor_rww *rww = &nor->rww; 1306 unsigned int used_banks = 0; 1307 bool started = false; 1308 u8 first, last; 1309 int bank; 1310 1311 mutex_lock(&nor->lock); 1312 1313 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe) 1314 goto busy; 1315 1316 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1317 for (bank = first; bank <= last; bank++) { 1318 if (rww->used_banks & BIT(bank)) 1319 goto busy; 1320 1321 used_banks |= BIT(bank); 1322 } 1323 1324 rww->used_banks |= used_banks; 1325 rww->ongoing_pe = true; 1326 started = true; 1327 1328 busy: 1329 mutex_unlock(&nor->lock); 1330 return started; 1331 } 1332 1333 static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len) 1334 { 1335 struct spi_nor_rww *rww = &nor->rww; 1336 u8 first, last; 1337 int bank; 1338 1339 mutex_lock(&nor->lock); 1340 1341 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1342 for (bank = first; bank <= last; bank++) 1343 rww->used_banks &= ~BIT(bank); 1344 1345 rww->ongoing_pe = false; 1346 1347 mutex_unlock(&nor->lock); 1348 } 1349 1350 static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len) 1351 { 1352 int ret; 1353 1354 ret = spi_nor_prep(nor); 1355 if (ret) 1356 return ret; 1357 1358 if (!spi_nor_use_parallel_locking(nor)) 1359 mutex_lock(&nor->lock); 1360 else 1361 ret = wait_event_killable(nor->rww.wait, 1362 spi_nor_rww_start_pe(nor, start, len)); 1363 1364 return ret; 1365 } 1366 1367 static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len) 1368 { 1369 if (!spi_nor_use_parallel_locking(nor)) { 1370 mutex_unlock(&nor->lock); 1371 } else { 1372 spi_nor_rww_end_pe(nor, start, len); 1373 wake_up(&nor->rww.wait); 1374 } 1375 1376 spi_nor_unprep(nor); 1377 } 1378 1379 /* Internal locking helpers for read operations */ 1380 static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len) 1381 { 1382 struct spi_nor_rww *rww = &nor->rww; 1383 unsigned int used_banks = 0; 1384 bool started = false; 1385 u8 first, last; 1386 int bank; 1387 1388 mutex_lock(&nor->lock); 1389 1390 if (rww->ongoing_io || rww->ongoing_rd) 1391 goto busy; 1392 1393 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1394 for (bank = first; bank <= last; bank++) { 1395 if (rww->used_banks & BIT(bank)) 1396 goto busy; 1397 1398 used_banks |= BIT(bank); 1399 } 1400 1401 rww->used_banks |= used_banks; 1402 rww->ongoing_io = true; 1403 rww->ongoing_rd = true; 1404 started = true; 1405 1406 busy: 1407 mutex_unlock(&nor->lock); 1408 return started; 1409 } 1410 1411 static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len) 1412 { 1413 struct spi_nor_rww *rww = &nor->rww; 1414 u8 first, last; 1415 int bank; 1416 1417 mutex_lock(&nor->lock); 1418 1419 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last); 1420 for (bank = first; bank <= last; bank++) 1421 nor->rww.used_banks &= ~BIT(bank); 1422 1423 rww->ongoing_io = false; 1424 rww->ongoing_rd = false; 1425 1426 mutex_unlock(&nor->lock); 1427 } 1428 1429 static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len) 1430 { 1431 int ret; 1432 1433 ret = spi_nor_prep(nor); 1434 if (ret) 1435 return ret; 1436 1437 if (!spi_nor_use_parallel_locking(nor)) 1438 mutex_lock(&nor->lock); 1439 else 1440 ret = wait_event_killable(nor->rww.wait, 1441 spi_nor_rww_start_rd(nor, start, len)); 1442 1443 return ret; 1444 } 1445 1446 static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len) 1447 { 1448 if (!spi_nor_use_parallel_locking(nor)) { 1449 mutex_unlock(&nor->lock); 1450 } else { 1451 spi_nor_rww_end_rd(nor, start, len); 1452 wake_up(&nor->rww.wait); 1453 } 1454 1455 spi_nor_unprep(nor); 1456 } 1457 1458 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1459 { 1460 if (!nor->params->convert_addr) 1461 return addr; 1462 1463 return nor->params->convert_addr(nor, addr); 1464 } 1465 1466 /* 1467 * Initiate the erasure of a single sector 1468 */ 1469 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1470 { 1471 int i; 1472 1473 addr = spi_nor_convert_addr(nor, addr); 1474 1475 if (nor->spimem) { 1476 struct spi_mem_op op = 1477 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode, 1478 nor->addr_nbytes, addr); 1479 1480 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 1481 1482 return spi_mem_exec_op(nor->spimem, &op); 1483 } else if (nor->controller_ops->erase) { 1484 return spi_nor_controller_ops_erase(nor, addr); 1485 } 1486 1487 /* 1488 * Default implementation, if driver doesn't have a specialized HW 1489 * control 1490 */ 1491 for (i = nor->addr_nbytes - 1; i >= 0; i--) { 1492 nor->bouncebuf[i] = addr & 0xff; 1493 addr >>= 8; 1494 } 1495 1496 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, 1497 nor->bouncebuf, nor->addr_nbytes); 1498 } 1499 1500 /** 1501 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1502 * @erase: pointer to a structure that describes a SPI NOR erase type 1503 * @dividend: dividend value 1504 * @remainder: pointer to u32 remainder (will be updated) 1505 * 1506 * Return: the result of the division 1507 */ 1508 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1509 u64 dividend, u32 *remainder) 1510 { 1511 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1512 *remainder = (u32)dividend & erase->size_mask; 1513 return dividend >> erase->size_shift; 1514 } 1515 1516 /** 1517 * spi_nor_find_best_erase_type() - find the best erase type for the given 1518 * offset in the serial flash memory and the 1519 * number of bytes to erase. The region in 1520 * which the address fits is expected to be 1521 * provided. 1522 * @map: the erase map of the SPI NOR 1523 * @region: pointer to a structure that describes a SPI NOR erase region 1524 * @addr: offset in the serial flash memory 1525 * @len: number of bytes to erase 1526 * 1527 * Return: a pointer to the best fitted erase type, NULL otherwise. 1528 */ 1529 static const struct spi_nor_erase_type * 1530 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1531 const struct spi_nor_erase_region *region, 1532 u64 addr, u32 len) 1533 { 1534 const struct spi_nor_erase_type *erase; 1535 u32 rem; 1536 int i; 1537 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1538 1539 /* 1540 * Erase types are ordered by size, with the smallest erase type at 1541 * index 0. 1542 */ 1543 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1544 /* Does the erase region support the tested erase type? */ 1545 if (!(erase_mask & BIT(i))) 1546 continue; 1547 1548 erase = &map->erase_type[i]; 1549 if (!erase->size) 1550 continue; 1551 1552 /* Alignment is not mandatory for overlaid regions */ 1553 if (region->offset & SNOR_OVERLAID_REGION && 1554 region->size <= len) 1555 return erase; 1556 1557 /* Don't erase more than what the user has asked for. */ 1558 if (erase->size > len) 1559 continue; 1560 1561 spi_nor_div_by_erase_size(erase, addr, &rem); 1562 if (!rem) 1563 return erase; 1564 } 1565 1566 return NULL; 1567 } 1568 1569 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 1570 { 1571 return region->offset & SNOR_LAST_REGION; 1572 } 1573 1574 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region) 1575 { 1576 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 1577 } 1578 1579 /** 1580 * spi_nor_region_next() - get the next spi nor region 1581 * @region: pointer to a structure that describes a SPI NOR erase region 1582 * 1583 * Return: the next spi nor region or NULL if last region. 1584 */ 1585 struct spi_nor_erase_region * 1586 spi_nor_region_next(struct spi_nor_erase_region *region) 1587 { 1588 if (spi_nor_region_is_last(region)) 1589 return NULL; 1590 region++; 1591 return region; 1592 } 1593 1594 /** 1595 * spi_nor_find_erase_region() - find the region of the serial flash memory in 1596 * which the offset fits 1597 * @map: the erase map of the SPI NOR 1598 * @addr: offset in the serial flash memory 1599 * 1600 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1601 * otherwise. 1602 */ 1603 static struct spi_nor_erase_region * 1604 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1605 { 1606 struct spi_nor_erase_region *region = map->regions; 1607 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1608 u64 region_end = region_start + region->size; 1609 1610 while (addr < region_start || addr >= region_end) { 1611 region = spi_nor_region_next(region); 1612 if (!region) 1613 return ERR_PTR(-EINVAL); 1614 1615 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1616 region_end = region_start + region->size; 1617 } 1618 1619 return region; 1620 } 1621 1622 /** 1623 * spi_nor_init_erase_cmd() - initialize an erase command 1624 * @region: pointer to a structure that describes a SPI NOR erase region 1625 * @erase: pointer to a structure that describes a SPI NOR erase type 1626 * 1627 * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1628 * otherwise. 1629 */ 1630 static struct spi_nor_erase_command * 1631 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1632 const struct spi_nor_erase_type *erase) 1633 { 1634 struct spi_nor_erase_command *cmd; 1635 1636 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1637 if (!cmd) 1638 return ERR_PTR(-ENOMEM); 1639 1640 INIT_LIST_HEAD(&cmd->list); 1641 cmd->opcode = erase->opcode; 1642 cmd->count = 1; 1643 1644 if (region->offset & SNOR_OVERLAID_REGION) 1645 cmd->size = region->size; 1646 else 1647 cmd->size = erase->size; 1648 1649 return cmd; 1650 } 1651 1652 /** 1653 * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1654 * @erase_list: list of erase commands 1655 */ 1656 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1657 { 1658 struct spi_nor_erase_command *cmd, *next; 1659 1660 list_for_each_entry_safe(cmd, next, erase_list, list) { 1661 list_del(&cmd->list); 1662 kfree(cmd); 1663 } 1664 } 1665 1666 /** 1667 * spi_nor_init_erase_cmd_list() - initialize erase command list 1668 * @nor: pointer to a 'struct spi_nor' 1669 * @erase_list: list of erase commands to be executed once we validate that the 1670 * erase can be performed 1671 * @addr: offset in the serial flash memory 1672 * @len: number of bytes to erase 1673 * 1674 * Builds the list of best fitted erase commands and verifies if the erase can 1675 * be performed. 1676 * 1677 * Return: 0 on success, -errno otherwise. 1678 */ 1679 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1680 struct list_head *erase_list, 1681 u64 addr, u32 len) 1682 { 1683 const struct spi_nor_erase_map *map = &nor->params->erase_map; 1684 const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1685 struct spi_nor_erase_region *region; 1686 struct spi_nor_erase_command *cmd = NULL; 1687 u64 region_end; 1688 int ret = -EINVAL; 1689 1690 region = spi_nor_find_erase_region(map, addr); 1691 if (IS_ERR(region)) 1692 return PTR_ERR(region); 1693 1694 region_end = spi_nor_region_end(region); 1695 1696 while (len) { 1697 erase = spi_nor_find_best_erase_type(map, region, addr, len); 1698 if (!erase) 1699 goto destroy_erase_cmd_list; 1700 1701 if (prev_erase != erase || 1702 erase->size != cmd->size || 1703 region->offset & SNOR_OVERLAID_REGION) { 1704 cmd = spi_nor_init_erase_cmd(region, erase); 1705 if (IS_ERR(cmd)) { 1706 ret = PTR_ERR(cmd); 1707 goto destroy_erase_cmd_list; 1708 } 1709 1710 list_add_tail(&cmd->list, erase_list); 1711 } else { 1712 cmd->count++; 1713 } 1714 1715 addr += cmd->size; 1716 len -= cmd->size; 1717 1718 if (len && addr >= region_end) { 1719 region = spi_nor_region_next(region); 1720 if (!region) 1721 goto destroy_erase_cmd_list; 1722 region_end = spi_nor_region_end(region); 1723 } 1724 1725 prev_erase = erase; 1726 } 1727 1728 return 0; 1729 1730 destroy_erase_cmd_list: 1731 spi_nor_destroy_erase_cmd_list(erase_list); 1732 return ret; 1733 } 1734 1735 /** 1736 * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1737 * @nor: pointer to a 'struct spi_nor' 1738 * @addr: offset in the serial flash memory 1739 * @len: number of bytes to erase 1740 * 1741 * Build a list of best fitted erase commands and execute it once we validate 1742 * that the erase can be performed. 1743 * 1744 * Return: 0 on success, -errno otherwise. 1745 */ 1746 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1747 { 1748 LIST_HEAD(erase_list); 1749 struct spi_nor_erase_command *cmd, *next; 1750 int ret; 1751 1752 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1753 if (ret) 1754 return ret; 1755 1756 list_for_each_entry_safe(cmd, next, &erase_list, list) { 1757 nor->erase_opcode = cmd->opcode; 1758 while (cmd->count) { 1759 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n", 1760 cmd->size, cmd->opcode, cmd->count); 1761 1762 ret = spi_nor_lock_device(nor); 1763 if (ret) 1764 goto destroy_erase_cmd_list; 1765 1766 ret = spi_nor_write_enable(nor); 1767 if (ret) { 1768 spi_nor_unlock_device(nor); 1769 goto destroy_erase_cmd_list; 1770 } 1771 1772 ret = spi_nor_erase_sector(nor, addr); 1773 spi_nor_unlock_device(nor); 1774 if (ret) 1775 goto destroy_erase_cmd_list; 1776 1777 ret = spi_nor_wait_till_ready(nor); 1778 if (ret) 1779 goto destroy_erase_cmd_list; 1780 1781 addr += cmd->size; 1782 cmd->count--; 1783 } 1784 list_del(&cmd->list); 1785 kfree(cmd); 1786 } 1787 1788 return 0; 1789 1790 destroy_erase_cmd_list: 1791 spi_nor_destroy_erase_cmd_list(&erase_list); 1792 return ret; 1793 } 1794 1795 /* 1796 * Erase an address range on the nor chip. The address range may extend 1797 * one or more erase sectors. Return an error if there is a problem erasing. 1798 */ 1799 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1800 { 1801 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1802 u32 addr, len, rem; 1803 int ret; 1804 1805 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1806 (long long)instr->len); 1807 1808 if (spi_nor_has_uniform_erase(nor)) { 1809 div_u64_rem(instr->len, mtd->erasesize, &rem); 1810 if (rem) 1811 return -EINVAL; 1812 } 1813 1814 addr = instr->addr; 1815 len = instr->len; 1816 1817 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); 1818 if (ret) 1819 return ret; 1820 1821 /* whole-chip erase? */ 1822 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1823 unsigned long timeout; 1824 1825 ret = spi_nor_lock_device(nor); 1826 if (ret) 1827 goto erase_err; 1828 1829 ret = spi_nor_write_enable(nor); 1830 if (ret) { 1831 spi_nor_unlock_device(nor); 1832 goto erase_err; 1833 } 1834 1835 ret = spi_nor_erase_chip(nor); 1836 spi_nor_unlock_device(nor); 1837 if (ret) 1838 goto erase_err; 1839 1840 /* 1841 * Scale the timeout linearly with the size of the flash, with 1842 * a minimum calibrated to an old 2MB flash. We could try to 1843 * pull these from CFI/SFDP, but these values should be good 1844 * enough for now. 1845 */ 1846 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1847 CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1848 (unsigned long)(mtd->size / SZ_2M)); 1849 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1850 if (ret) 1851 goto erase_err; 1852 1853 /* REVISIT in some cases we could speed up erasing large regions 1854 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1855 * to use "small sector erase", but that's not always optimal. 1856 */ 1857 1858 /* "sector"-at-a-time erase */ 1859 } else if (spi_nor_has_uniform_erase(nor)) { 1860 while (len) { 1861 ret = spi_nor_lock_device(nor); 1862 if (ret) 1863 goto erase_err; 1864 1865 ret = spi_nor_write_enable(nor); 1866 if (ret) { 1867 spi_nor_unlock_device(nor); 1868 goto erase_err; 1869 } 1870 1871 ret = spi_nor_erase_sector(nor, addr); 1872 spi_nor_unlock_device(nor); 1873 if (ret) 1874 goto erase_err; 1875 1876 ret = spi_nor_wait_till_ready(nor); 1877 if (ret) 1878 goto erase_err; 1879 1880 addr += mtd->erasesize; 1881 len -= mtd->erasesize; 1882 } 1883 1884 /* erase multiple sectors */ 1885 } else { 1886 ret = spi_nor_erase_multi_sectors(nor, addr, len); 1887 if (ret) 1888 goto erase_err; 1889 } 1890 1891 ret = spi_nor_write_disable(nor); 1892 1893 erase_err: 1894 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len); 1895 1896 return ret; 1897 } 1898 1899 /** 1900 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 1901 * Register 1. 1902 * @nor: pointer to a 'struct spi_nor' 1903 * 1904 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 1905 * 1906 * Return: 0 on success, -errno otherwise. 1907 */ 1908 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 1909 { 1910 int ret; 1911 1912 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1913 if (ret) 1914 return ret; 1915 1916 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 1917 return 0; 1918 1919 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 1920 1921 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 1922 } 1923 1924 /** 1925 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 1926 * Register 2. 1927 * @nor: pointer to a 'struct spi_nor'. 1928 * 1929 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 1930 * 1931 * Return: 0 on success, -errno otherwise. 1932 */ 1933 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 1934 { 1935 int ret; 1936 1937 if (nor->flags & SNOR_F_NO_READ_CR) 1938 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 1939 1940 ret = spi_nor_read_cr(nor, nor->bouncebuf); 1941 if (ret) 1942 return ret; 1943 1944 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 1945 return 0; 1946 1947 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 1948 1949 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 1950 } 1951 1952 /** 1953 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 1954 * @nor: pointer to a 'struct spi_nor' 1955 * 1956 * Set the Quad Enable (QE) bit in the Status Register 2. 1957 * 1958 * This is one of the procedures to set the QE bit described in the SFDP 1959 * (JESD216 rev B) specification but no manufacturer using this procedure has 1960 * been identified yet, hence the name of the function. 1961 * 1962 * Return: 0 on success, -errno otherwise. 1963 */ 1964 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 1965 { 1966 u8 *sr2 = nor->bouncebuf; 1967 int ret; 1968 u8 sr2_written; 1969 1970 /* Check current Quad Enable bit value. */ 1971 ret = spi_nor_read_sr2(nor, sr2); 1972 if (ret) 1973 return ret; 1974 if (*sr2 & SR2_QUAD_EN_BIT7) 1975 return 0; 1976 1977 /* Update the Quad Enable bit. */ 1978 *sr2 |= SR2_QUAD_EN_BIT7; 1979 1980 ret = spi_nor_write_sr2(nor, sr2); 1981 if (ret) 1982 return ret; 1983 1984 sr2_written = *sr2; 1985 1986 /* Read back and check it. */ 1987 ret = spi_nor_read_sr2(nor, sr2); 1988 if (ret) 1989 return ret; 1990 1991 if (*sr2 != sr2_written) { 1992 dev_dbg(nor->dev, "SR2: Read back test failed\n"); 1993 return -EIO; 1994 } 1995 1996 return 0; 1997 } 1998 1999 static const struct spi_nor_manufacturer *manufacturers[] = { 2000 &spi_nor_atmel, 2001 &spi_nor_eon, 2002 &spi_nor_esmt, 2003 &spi_nor_everspin, 2004 &spi_nor_gigadevice, 2005 &spi_nor_intel, 2006 &spi_nor_issi, 2007 &spi_nor_macronix, 2008 &spi_nor_micron, 2009 &spi_nor_st, 2010 &spi_nor_spansion, 2011 &spi_nor_sst, 2012 &spi_nor_winbond, 2013 &spi_nor_xilinx, 2014 &spi_nor_xmc, 2015 }; 2016 2017 static const struct flash_info spi_nor_generic_flash = { 2018 .name = "spi-nor-generic", 2019 }; 2020 2021 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 2022 const u8 *id) 2023 { 2024 const struct flash_info *part; 2025 unsigned int i, j; 2026 2027 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2028 for (j = 0; j < manufacturers[i]->nparts; j++) { 2029 part = &manufacturers[i]->parts[j]; 2030 if (part->id && 2031 !memcmp(part->id->bytes, id, part->id->len)) { 2032 nor->manufacturer = manufacturers[i]; 2033 return part; 2034 } 2035 } 2036 } 2037 2038 return NULL; 2039 } 2040 2041 static const struct flash_info *spi_nor_detect(struct spi_nor *nor) 2042 { 2043 const struct flash_info *info; 2044 u8 *id = nor->bouncebuf; 2045 int ret; 2046 2047 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto); 2048 if (ret) { 2049 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 2050 return ERR_PTR(ret); 2051 } 2052 2053 /* Cache the complete flash ID. */ 2054 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL); 2055 if (!nor->id) 2056 return ERR_PTR(-ENOMEM); 2057 2058 info = spi_nor_match_id(nor, id); 2059 2060 /* Fallback to a generic flash described only by its SFDP data. */ 2061 if (!info) { 2062 ret = spi_nor_check_sfdp_signature(nor); 2063 if (!ret) 2064 info = &spi_nor_generic_flash; 2065 } 2066 2067 if (!info) { 2068 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 2069 SPI_NOR_MAX_ID_LEN, id); 2070 return ERR_PTR(-ENODEV); 2071 } 2072 return info; 2073 } 2074 2075 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 2076 size_t *retlen, u_char *buf) 2077 { 2078 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2079 loff_t from_lock = from; 2080 size_t len_lock = len; 2081 ssize_t ret; 2082 2083 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 2084 2085 ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock); 2086 if (ret) 2087 return ret; 2088 2089 while (len) { 2090 loff_t addr = from; 2091 2092 addr = spi_nor_convert_addr(nor, addr); 2093 2094 ret = spi_nor_read_data(nor, addr, len, buf); 2095 if (ret == 0) { 2096 /* We shouldn't see 0-length reads */ 2097 ret = -EIO; 2098 goto read_err; 2099 } 2100 if (ret < 0) 2101 goto read_err; 2102 2103 WARN_ON(ret > len); 2104 *retlen += ret; 2105 buf += ret; 2106 from += ret; 2107 len -= ret; 2108 } 2109 ret = 0; 2110 2111 read_err: 2112 spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock); 2113 2114 return ret; 2115 } 2116 2117 /* 2118 * Write an address range to the nor chip. Data must be written in 2119 * FLASH_PAGESIZE chunks. The address range may be any size provided 2120 * it is within the physical boundaries. 2121 */ 2122 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 2123 size_t *retlen, const u_char *buf) 2124 { 2125 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2126 size_t page_offset, page_remain, i; 2127 ssize_t ret; 2128 u32 page_size = nor->params->page_size; 2129 2130 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 2131 2132 ret = spi_nor_prep_and_lock_pe(nor, to, len); 2133 if (ret) 2134 return ret; 2135 2136 for (i = 0; i < len; ) { 2137 ssize_t written; 2138 loff_t addr = to + i; 2139 2140 /* 2141 * If page_size is a power of two, the offset can be quickly 2142 * calculated with an AND operation. On the other cases we 2143 * need to do a modulus operation (more expensive). 2144 */ 2145 if (is_power_of_2(page_size)) { 2146 page_offset = addr & (page_size - 1); 2147 } else { 2148 u64 aux = addr; 2149 2150 page_offset = do_div(aux, page_size); 2151 } 2152 /* the size of data remaining on the first page */ 2153 page_remain = min_t(size_t, page_size - page_offset, len - i); 2154 2155 addr = spi_nor_convert_addr(nor, addr); 2156 2157 ret = spi_nor_lock_device(nor); 2158 if (ret) 2159 goto write_err; 2160 2161 ret = spi_nor_write_enable(nor); 2162 if (ret) { 2163 spi_nor_unlock_device(nor); 2164 goto write_err; 2165 } 2166 2167 ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 2168 spi_nor_unlock_device(nor); 2169 if (ret < 0) 2170 goto write_err; 2171 written = ret; 2172 2173 ret = spi_nor_wait_till_ready(nor); 2174 if (ret) 2175 goto write_err; 2176 *retlen += written; 2177 i += written; 2178 } 2179 2180 write_err: 2181 spi_nor_unlock_and_unprep_pe(nor, to, len); 2182 2183 return ret; 2184 } 2185 2186 static int spi_nor_check(struct spi_nor *nor) 2187 { 2188 if (!nor->dev || 2189 (!nor->spimem && !nor->controller_ops) || 2190 (!nor->spimem && nor->controller_ops && 2191 (!nor->controller_ops->read || 2192 !nor->controller_ops->write || 2193 !nor->controller_ops->read_reg || 2194 !nor->controller_ops->write_reg))) { 2195 pr_err("spi-nor: please fill all the necessary fields!\n"); 2196 return -EINVAL; 2197 } 2198 2199 if (nor->spimem && nor->controller_ops) { 2200 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 2201 return -EINVAL; 2202 } 2203 2204 return 0; 2205 } 2206 2207 void 2208 spi_nor_set_read_settings(struct spi_nor_read_command *read, 2209 u8 num_mode_clocks, 2210 u8 num_wait_states, 2211 u8 opcode, 2212 enum spi_nor_protocol proto) 2213 { 2214 read->num_mode_clocks = num_mode_clocks; 2215 read->num_wait_states = num_wait_states; 2216 read->opcode = opcode; 2217 read->proto = proto; 2218 } 2219 2220 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 2221 enum spi_nor_protocol proto) 2222 { 2223 pp->opcode = opcode; 2224 pp->proto = proto; 2225 } 2226 2227 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2228 { 2229 size_t i; 2230 2231 for (i = 0; i < size; i++) 2232 if (table[i][0] == (int)hwcaps) 2233 return table[i][1]; 2234 2235 return -EINVAL; 2236 } 2237 2238 int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2239 { 2240 static const int hwcaps_read2cmd[][2] = { 2241 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2242 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2243 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2244 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2245 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2246 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2247 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2248 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2249 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2250 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2251 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2252 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2253 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2254 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2255 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2256 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, 2257 }; 2258 2259 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2260 ARRAY_SIZE(hwcaps_read2cmd)); 2261 } 2262 2263 int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2264 { 2265 static const int hwcaps_pp2cmd[][2] = { 2266 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2267 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2268 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2269 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2270 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2271 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2272 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2273 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, 2274 }; 2275 2276 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2277 ARRAY_SIZE(hwcaps_pp2cmd)); 2278 } 2279 2280 /** 2281 * spi_nor_spimem_check_op - check if the operation is supported 2282 * by controller 2283 *@nor: pointer to a 'struct spi_nor' 2284 *@op: pointer to op template to be checked 2285 * 2286 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2287 */ 2288 static int spi_nor_spimem_check_op(struct spi_nor *nor, 2289 struct spi_mem_op *op) 2290 { 2291 /* 2292 * First test with 4 address bytes. The opcode itself might 2293 * be a 3B addressing opcode but we don't care, because 2294 * SPI controller implementation should not check the opcode, 2295 * but just the sequence. 2296 */ 2297 op->addr.nbytes = 4; 2298 if (!spi_mem_supports_op(nor->spimem, op)) { 2299 if (nor->params->size > SZ_16M) 2300 return -EOPNOTSUPP; 2301 2302 /* If flash size <= 16MB, 3 address bytes are sufficient */ 2303 op->addr.nbytes = 3; 2304 if (!spi_mem_supports_op(nor->spimem, op)) 2305 return -EOPNOTSUPP; 2306 } 2307 2308 return 0; 2309 } 2310 2311 /** 2312 * spi_nor_spimem_check_readop - check if the read op is supported 2313 * by controller 2314 *@nor: pointer to a 'struct spi_nor' 2315 *@read: pointer to op template to be checked 2316 * 2317 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2318 */ 2319 static int spi_nor_spimem_check_readop(struct spi_nor *nor, 2320 const struct spi_nor_read_command *read) 2321 { 2322 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode); 2323 2324 spi_nor_spimem_setup_op(nor, &op, read->proto); 2325 2326 /* convert the dummy cycles to the number of bytes */ 2327 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * 2328 op.dummy.buswidth / 8; 2329 if (spi_nor_protocol_is_dtr(nor->read_proto)) 2330 op.dummy.nbytes *= 2; 2331 2332 return spi_nor_spimem_check_op(nor, &op); 2333 } 2334 2335 /** 2336 * spi_nor_spimem_check_pp - check if the page program op is supported 2337 * by controller 2338 *@nor: pointer to a 'struct spi_nor' 2339 *@pp: pointer to op template to be checked 2340 * 2341 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 2342 */ 2343 static int spi_nor_spimem_check_pp(struct spi_nor *nor, 2344 const struct spi_nor_pp_command *pp) 2345 { 2346 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode); 2347 2348 spi_nor_spimem_setup_op(nor, &op, pp->proto); 2349 2350 return spi_nor_spimem_check_op(nor, &op); 2351 } 2352 2353 /** 2354 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 2355 * based on SPI controller capabilities 2356 * @nor: pointer to a 'struct spi_nor' 2357 * @hwcaps: pointer to resulting capabilities after adjusting 2358 * according to controller and flash's capability 2359 */ 2360 static void 2361 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 2362 { 2363 struct spi_nor_flash_parameter *params = nor->params; 2364 unsigned int cap; 2365 2366 /* X-X-X modes are not supported yet, mask them all. */ 2367 *hwcaps &= ~SNOR_HWCAPS_X_X_X; 2368 2369 /* 2370 * If the reset line is broken, we do not want to enter a stateful 2371 * mode. 2372 */ 2373 if (nor->flags & SNOR_F_BROKEN_RESET) 2374 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); 2375 2376 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 2377 int rdidx, ppidx; 2378 2379 if (!(*hwcaps & BIT(cap))) 2380 continue; 2381 2382 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 2383 if (rdidx >= 0 && 2384 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) 2385 *hwcaps &= ~BIT(cap); 2386 2387 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 2388 if (ppidx < 0) 2389 continue; 2390 2391 if (spi_nor_spimem_check_pp(nor, 2392 ¶ms->page_programs[ppidx])) 2393 *hwcaps &= ~BIT(cap); 2394 } 2395 } 2396 2397 /** 2398 * spi_nor_set_erase_type() - set a SPI NOR erase type 2399 * @erase: pointer to a structure that describes a SPI NOR erase type 2400 * @size: the size of the sector/block erased by the erase type 2401 * @opcode: the SPI command op code to erase the sector/block 2402 */ 2403 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2404 u8 opcode) 2405 { 2406 erase->size = size; 2407 erase->opcode = opcode; 2408 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2409 erase->size_shift = ffs(erase->size) - 1; 2410 erase->size_mask = (1 << erase->size_shift) - 1; 2411 } 2412 2413 /** 2414 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type 2415 * @erase: pointer to a structure that describes a SPI NOR erase type 2416 */ 2417 void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase) 2418 { 2419 erase->size = 0; 2420 } 2421 2422 /** 2423 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2424 * @map: the erase map of the SPI NOR 2425 * @erase_mask: bitmask encoding erase types that can erase the entire 2426 * flash memory 2427 * @flash_size: the spi nor flash memory size 2428 */ 2429 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2430 u8 erase_mask, u64 flash_size) 2431 { 2432 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 2433 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 2434 SNOR_LAST_REGION; 2435 map->uniform_region.size = flash_size; 2436 map->regions = &map->uniform_region; 2437 map->uniform_erase_type = erase_mask; 2438 } 2439 2440 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2441 const struct sfdp_parameter_header *bfpt_header, 2442 const struct sfdp_bfpt *bfpt) 2443 { 2444 int ret; 2445 2446 if (nor->manufacturer && nor->manufacturer->fixups && 2447 nor->manufacturer->fixups->post_bfpt) { 2448 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2449 bfpt); 2450 if (ret) 2451 return ret; 2452 } 2453 2454 if (nor->info->fixups && nor->info->fixups->post_bfpt) 2455 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt); 2456 2457 return 0; 2458 } 2459 2460 static int spi_nor_select_read(struct spi_nor *nor, 2461 u32 shared_hwcaps) 2462 { 2463 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2464 const struct spi_nor_read_command *read; 2465 2466 if (best_match < 0) 2467 return -EINVAL; 2468 2469 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2470 if (cmd < 0) 2471 return -EINVAL; 2472 2473 read = &nor->params->reads[cmd]; 2474 nor->read_opcode = read->opcode; 2475 nor->read_proto = read->proto; 2476 2477 /* 2478 * In the SPI NOR framework, we don't need to make the difference 2479 * between mode clock cycles and wait state clock cycles. 2480 * Indeed, the value of the mode clock cycles is used by a QSPI 2481 * flash memory to know whether it should enter or leave its 0-4-4 2482 * (Continuous Read / XIP) mode. 2483 * eXecution In Place is out of the scope of the mtd sub-system. 2484 * Hence we choose to merge both mode and wait state clock cycles 2485 * into the so called dummy clock cycles. 2486 */ 2487 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2488 return 0; 2489 } 2490 2491 static int spi_nor_select_pp(struct spi_nor *nor, 2492 u32 shared_hwcaps) 2493 { 2494 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2495 const struct spi_nor_pp_command *pp; 2496 2497 if (best_match < 0) 2498 return -EINVAL; 2499 2500 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2501 if (cmd < 0) 2502 return -EINVAL; 2503 2504 pp = &nor->params->page_programs[cmd]; 2505 nor->program_opcode = pp->opcode; 2506 nor->write_proto = pp->proto; 2507 return 0; 2508 } 2509 2510 /** 2511 * spi_nor_select_uniform_erase() - select optimum uniform erase type 2512 * @map: the erase map of the SPI NOR 2513 * 2514 * Once the optimum uniform sector erase command is found, disable all the 2515 * other. 2516 * 2517 * Return: pointer to erase type on success, NULL otherwise. 2518 */ 2519 static const struct spi_nor_erase_type * 2520 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map) 2521 { 2522 const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2523 int i; 2524 u8 uniform_erase_type = map->uniform_erase_type; 2525 2526 /* 2527 * Search for the biggest erase size, except for when compiled 2528 * to use 4k erases. 2529 */ 2530 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2531 if (!(uniform_erase_type & BIT(i))) 2532 continue; 2533 2534 tested_erase = &map->erase_type[i]; 2535 2536 /* Skip masked erase types. */ 2537 if (!tested_erase->size) 2538 continue; 2539 2540 /* 2541 * If the current erase size is the 4k one, stop here, 2542 * we have found the right uniform Sector Erase command. 2543 */ 2544 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS) && 2545 tested_erase->size == SZ_4K) { 2546 erase = tested_erase; 2547 break; 2548 } 2549 2550 /* 2551 * Otherwise, the current erase size is still a valid candidate. 2552 * Select the biggest valid candidate. 2553 */ 2554 if (!erase && tested_erase->size) 2555 erase = tested_erase; 2556 /* keep iterating to find the wanted_size */ 2557 } 2558 2559 if (!erase) 2560 return NULL; 2561 2562 /* Disable all other Sector Erase commands. */ 2563 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 2564 map->uniform_erase_type |= BIT(erase - map->erase_type); 2565 return erase; 2566 } 2567 2568 static int spi_nor_select_erase(struct spi_nor *nor) 2569 { 2570 struct spi_nor_erase_map *map = &nor->params->erase_map; 2571 const struct spi_nor_erase_type *erase = NULL; 2572 struct mtd_info *mtd = &nor->mtd; 2573 int i; 2574 2575 /* 2576 * The previous implementation handling Sector Erase commands assumed 2577 * that the SPI flash memory has an uniform layout then used only one 2578 * of the supported erase sizes for all Sector Erase commands. 2579 * So to be backward compatible, the new implementation also tries to 2580 * manage the SPI flash memory as uniform with a single erase sector 2581 * size, when possible. 2582 */ 2583 if (spi_nor_has_uniform_erase(nor)) { 2584 erase = spi_nor_select_uniform_erase(map); 2585 if (!erase) 2586 return -EINVAL; 2587 nor->erase_opcode = erase->opcode; 2588 mtd->erasesize = erase->size; 2589 return 0; 2590 } 2591 2592 /* 2593 * For non-uniform SPI flash memory, set mtd->erasesize to the 2594 * maximum erase sector size. No need to set nor->erase_opcode. 2595 */ 2596 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2597 if (map->erase_type[i].size) { 2598 erase = &map->erase_type[i]; 2599 break; 2600 } 2601 } 2602 2603 if (!erase) 2604 return -EINVAL; 2605 2606 mtd->erasesize = erase->size; 2607 return 0; 2608 } 2609 2610 static int spi_nor_default_setup(struct spi_nor *nor, 2611 const struct spi_nor_hwcaps *hwcaps) 2612 { 2613 struct spi_nor_flash_parameter *params = nor->params; 2614 u32 ignored_mask, shared_mask; 2615 int err; 2616 2617 /* 2618 * Keep only the hardware capabilities supported by both the SPI 2619 * controller and the SPI flash memory. 2620 */ 2621 shared_mask = hwcaps->mask & params->hwcaps.mask; 2622 2623 if (nor->spimem) { 2624 /* 2625 * When called from spi_nor_probe(), all caps are set and we 2626 * need to discard some of them based on what the SPI 2627 * controller actually supports (using spi_mem_supports_op()). 2628 */ 2629 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2630 } else { 2631 /* 2632 * SPI n-n-n protocols are not supported when the SPI 2633 * controller directly implements the spi_nor interface. 2634 * Yet another reason to switch to spi-mem. 2635 */ 2636 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR; 2637 if (shared_mask & ignored_mask) { 2638 dev_dbg(nor->dev, 2639 "SPI n-n-n protocols are not supported.\n"); 2640 shared_mask &= ~ignored_mask; 2641 } 2642 } 2643 2644 /* Select the (Fast) Read command. */ 2645 err = spi_nor_select_read(nor, shared_mask); 2646 if (err) { 2647 dev_dbg(nor->dev, 2648 "can't select read settings supported by both the SPI controller and memory.\n"); 2649 return err; 2650 } 2651 2652 /* Select the Page Program command. */ 2653 err = spi_nor_select_pp(nor, shared_mask); 2654 if (err) { 2655 dev_dbg(nor->dev, 2656 "can't select write settings supported by both the SPI controller and memory.\n"); 2657 return err; 2658 } 2659 2660 /* Select the Sector Erase command. */ 2661 err = spi_nor_select_erase(nor); 2662 if (err) { 2663 dev_dbg(nor->dev, 2664 "can't select erase settings supported by both the SPI controller and memory.\n"); 2665 return err; 2666 } 2667 2668 return 0; 2669 } 2670 2671 static int spi_nor_set_addr_nbytes(struct spi_nor *nor) 2672 { 2673 if (nor->params->addr_nbytes) { 2674 nor->addr_nbytes = nor->params->addr_nbytes; 2675 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { 2676 /* 2677 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So 2678 * in this protocol an odd addr_nbytes cannot be used because 2679 * then the address phase would only span a cycle and a half. 2680 * Half a cycle would be left over. We would then have to start 2681 * the dummy phase in the middle of a cycle and so too the data 2682 * phase, and we will end the transaction with half a cycle left 2683 * over. 2684 * 2685 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to 2686 * avoid this situation. 2687 */ 2688 nor->addr_nbytes = 4; 2689 } else if (nor->info->addr_nbytes) { 2690 nor->addr_nbytes = nor->info->addr_nbytes; 2691 } else { 2692 nor->addr_nbytes = 3; 2693 } 2694 2695 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) { 2696 /* enable 4-byte addressing if the device exceeds 16MiB */ 2697 nor->addr_nbytes = 4; 2698 } 2699 2700 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) { 2701 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n", 2702 nor->addr_nbytes); 2703 return -EINVAL; 2704 } 2705 2706 /* Set 4byte opcodes when possible. */ 2707 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES && 2708 !(nor->flags & SNOR_F_HAS_4BAIT)) 2709 spi_nor_set_4byte_opcodes(nor); 2710 2711 return 0; 2712 } 2713 2714 static int spi_nor_setup(struct spi_nor *nor, 2715 const struct spi_nor_hwcaps *hwcaps) 2716 { 2717 int ret; 2718 2719 if (nor->params->setup) 2720 ret = nor->params->setup(nor, hwcaps); 2721 else 2722 ret = spi_nor_default_setup(nor, hwcaps); 2723 if (ret) 2724 return ret; 2725 2726 return spi_nor_set_addr_nbytes(nor); 2727 } 2728 2729 /** 2730 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2731 * settings based on MFR register and ->default_init() hook. 2732 * @nor: pointer to a 'struct spi_nor'. 2733 */ 2734 static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2735 { 2736 if (nor->manufacturer && nor->manufacturer->fixups && 2737 nor->manufacturer->fixups->default_init) 2738 nor->manufacturer->fixups->default_init(nor); 2739 2740 if (nor->info->fixups && nor->info->fixups->default_init) 2741 nor->info->fixups->default_init(nor); 2742 } 2743 2744 /** 2745 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and 2746 * settings based on nor->info->sfdp_flags. This method should be called only by 2747 * flashes that do not define SFDP tables. If the flash supports SFDP but the 2748 * information is wrong and the settings from this function can not be retrieved 2749 * by parsing SFDP, one should instead use the fixup hooks and update the wrong 2750 * bits. 2751 * @nor: pointer to a 'struct spi_nor'. 2752 */ 2753 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) 2754 { 2755 struct spi_nor_flash_parameter *params = nor->params; 2756 struct spi_nor_erase_map *map = ¶ms->erase_map; 2757 const struct flash_info *info = nor->info; 2758 const u8 no_sfdp_flags = info->no_sfdp_flags; 2759 u8 i, erase_mask; 2760 2761 if (no_sfdp_flags & SPI_NOR_DUAL_READ) { 2762 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2763 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2764 0, 8, SPINOR_OP_READ_1_1_2, 2765 SNOR_PROTO_1_1_2); 2766 } 2767 2768 if (no_sfdp_flags & SPI_NOR_QUAD_READ) { 2769 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2770 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2771 0, 8, SPINOR_OP_READ_1_1_4, 2772 SNOR_PROTO_1_1_4); 2773 } 2774 2775 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) { 2776 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2777 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], 2778 0, 8, SPINOR_OP_READ_1_1_8, 2779 SNOR_PROTO_1_1_8); 2780 } 2781 2782 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) { 2783 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 2784 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 2785 0, 20, SPINOR_OP_READ_FAST, 2786 SNOR_PROTO_8_8_8_DTR); 2787 } 2788 2789 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) { 2790 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 2791 /* 2792 * Since xSPI Page Program opcode is backward compatible with 2793 * Legacy SPI, use Legacy SPI opcode there as well. 2794 */ 2795 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 2796 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); 2797 } 2798 2799 /* 2800 * Sector Erase settings. Sort Erase Types in ascending order, with the 2801 * smallest erase size starting at BIT(0). 2802 */ 2803 erase_mask = 0; 2804 i = 0; 2805 if (no_sfdp_flags & SECT_4K) { 2806 erase_mask |= BIT(i); 2807 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2808 SPINOR_OP_BE_4K); 2809 i++; 2810 } 2811 erase_mask |= BIT(i); 2812 spi_nor_set_erase_type(&map->erase_type[i], 2813 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE, 2814 SPINOR_OP_SE); 2815 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 2816 } 2817 2818 /** 2819 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined 2820 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP. 2821 * @nor: pointer to a 'struct spi_nor' 2822 */ 2823 static void spi_nor_init_flags(struct spi_nor *nor) 2824 { 2825 struct device_node *np = spi_nor_get_flash_node(nor); 2826 const u16 flags = nor->info->flags; 2827 2828 if (of_property_read_bool(np, "broken-flash-reset")) 2829 nor->flags |= SNOR_F_BROKEN_RESET; 2830 2831 if (of_property_read_bool(np, "no-wp")) 2832 nor->flags |= SNOR_F_NO_WP; 2833 2834 if (flags & SPI_NOR_SWP_IS_VOLATILE) 2835 nor->flags |= SNOR_F_SWP_IS_VOLATILE; 2836 2837 if (flags & SPI_NOR_HAS_LOCK) 2838 nor->flags |= SNOR_F_HAS_LOCK; 2839 2840 if (flags & SPI_NOR_HAS_TB) { 2841 nor->flags |= SNOR_F_HAS_SR_TB; 2842 if (flags & SPI_NOR_TB_SR_BIT6) 2843 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 2844 } 2845 2846 if (flags & SPI_NOR_4BIT_BP) { 2847 nor->flags |= SNOR_F_HAS_4BIT_BP; 2848 if (flags & SPI_NOR_BP3_SR_BIT6) 2849 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 2850 } 2851 2852 if (flags & NO_CHIP_ERASE) 2853 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2854 2855 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && 2856 !nor->controller_ops) 2857 nor->flags |= SNOR_F_RWW; 2858 } 2859 2860 /** 2861 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not 2862 * be discovered by SFDP for this particular flash because the SFDP table that 2863 * indicates this support is not defined in the flash. In case the table for 2864 * this support is defined but has wrong values, one should instead use a 2865 * post_sfdp() hook to set the SNOR_F equivalent flag. 2866 * @nor: pointer to a 'struct spi_nor' 2867 */ 2868 static void spi_nor_init_fixup_flags(struct spi_nor *nor) 2869 { 2870 const u8 fixup_flags = nor->info->fixup_flags; 2871 2872 if (fixup_flags & SPI_NOR_4B_OPCODES) 2873 nor->flags |= SNOR_F_4B_OPCODES; 2874 2875 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) 2876 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; 2877 } 2878 2879 /** 2880 * spi_nor_late_init_params() - Late initialization of default flash parameters. 2881 * @nor: pointer to a 'struct spi_nor' 2882 * 2883 * Used to initialize flash parameters that are not declared in the JESD216 2884 * SFDP standard, or where SFDP tables are not defined at all. 2885 * Will replace the spi_nor_manufacturer_init_params() method. 2886 */ 2887 static int spi_nor_late_init_params(struct spi_nor *nor) 2888 { 2889 struct spi_nor_flash_parameter *params = nor->params; 2890 int ret; 2891 2892 if (nor->manufacturer && nor->manufacturer->fixups && 2893 nor->manufacturer->fixups->late_init) { 2894 ret = nor->manufacturer->fixups->late_init(nor); 2895 if (ret) 2896 return ret; 2897 } 2898 2899 if (nor->info->fixups && nor->info->fixups->late_init) { 2900 ret = nor->info->fixups->late_init(nor); 2901 if (ret) 2902 return ret; 2903 } 2904 2905 /* Default method kept for backward compatibility. */ 2906 if (!params->set_4byte_addr_mode) 2907 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr; 2908 2909 spi_nor_init_flags(nor); 2910 spi_nor_init_fixup_flags(nor); 2911 2912 /* 2913 * NOR protection support. When locking_ops are not provided, we pick 2914 * the default ones. 2915 */ 2916 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 2917 spi_nor_init_default_locking_ops(nor); 2918 2919 if (params->n_banks > 1) 2920 params->bank_size = div64_u64(params->size, params->n_banks); 2921 2922 return 0; 2923 } 2924 2925 /** 2926 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash 2927 * parameters and settings based on JESD216 SFDP standard. 2928 * @nor: pointer to a 'struct spi_nor'. 2929 * 2930 * The method has a roll-back mechanism: in case the SFDP parsing fails, the 2931 * legacy flash parameters and settings will be restored. 2932 */ 2933 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor) 2934 { 2935 struct spi_nor_flash_parameter sfdp_params; 2936 2937 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 2938 2939 if (spi_nor_parse_sfdp(nor)) { 2940 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 2941 nor->flags &= ~SNOR_F_4B_OPCODES; 2942 } 2943 } 2944 2945 /** 2946 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash 2947 * parameters and settings. 2948 * @nor: pointer to a 'struct spi_nor'. 2949 * 2950 * The method assumes that flash doesn't support SFDP so it initializes flash 2951 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten 2952 * when parsing SFDP, if supported. 2953 */ 2954 static void spi_nor_init_params_deprecated(struct spi_nor *nor) 2955 { 2956 spi_nor_no_sfdp_init_params(nor); 2957 2958 spi_nor_manufacturer_init_params(nor); 2959 2960 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | 2961 SPI_NOR_QUAD_READ | 2962 SPI_NOR_OCTAL_READ | 2963 SPI_NOR_OCTAL_DTR_READ)) 2964 spi_nor_sfdp_init_params_deprecated(nor); 2965 } 2966 2967 /** 2968 * spi_nor_init_default_params() - Default initialization of flash parameters 2969 * and settings. Done for all flashes, regardless is they define SFDP tables 2970 * or not. 2971 * @nor: pointer to a 'struct spi_nor'. 2972 */ 2973 static void spi_nor_init_default_params(struct spi_nor *nor) 2974 { 2975 struct spi_nor_flash_parameter *params = nor->params; 2976 const struct flash_info *info = nor->info; 2977 struct device_node *np = spi_nor_get_flash_node(nor); 2978 2979 params->quad_enable = spi_nor_sr2_bit1_quad_enable; 2980 params->otp.org = info->otp; 2981 2982 /* Default to 16-bit Write Status (01h) Command */ 2983 nor->flags |= SNOR_F_HAS_16BIT_SR; 2984 2985 /* Set SPI NOR sizes. */ 2986 params->writesize = 1; 2987 params->size = info->size; 2988 params->bank_size = params->size; 2989 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE; 2990 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS; 2991 2992 if (!(info->flags & SPI_NOR_NO_FR)) { 2993 /* Default to Fast Read for DT and non-DT platform devices. */ 2994 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2995 2996 /* Mask out Fast Read if not requested at DT instantiation. */ 2997 if (np && !of_property_read_bool(np, "m25p,fast-read")) 2998 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2999 } 3000 3001 /* (Fast) Read settings. */ 3002 params->hwcaps.mask |= SNOR_HWCAPS_READ; 3003 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 3004 0, 0, SPINOR_OP_READ, 3005 SNOR_PROTO_1_1_1); 3006 3007 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 3008 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 3009 0, 8, SPINOR_OP_READ_FAST, 3010 SNOR_PROTO_1_1_1); 3011 /* Page Program settings. */ 3012 params->hwcaps.mask |= SNOR_HWCAPS_PP; 3013 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 3014 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 3015 3016 if (info->flags & SPI_NOR_QUAD_PP) { 3017 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 3018 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 3019 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 3020 } 3021 } 3022 3023 /** 3024 * spi_nor_init_params() - Initialize the flash's parameters and settings. 3025 * @nor: pointer to a 'struct spi_nor'. 3026 * 3027 * The flash parameters and settings are initialized based on a sequence of 3028 * calls that are ordered by priority: 3029 * 3030 * 1/ Default flash parameters initialization. The initializations are done 3031 * based on nor->info data: 3032 * spi_nor_info_init_params() 3033 * 3034 * which can be overwritten by: 3035 * 2/ Manufacturer flash parameters initialization. The initializations are 3036 * done based on MFR register, or when the decisions can not be done solely 3037 * based on MFR, by using specific flash_info tweeks, ->default_init(): 3038 * spi_nor_manufacturer_init_params() 3039 * 3040 * which can be overwritten by: 3041 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 3042 * should be more accurate that the above. 3043 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params() 3044 * 3045 * Please note that there is a ->post_bfpt() fixup hook that can overwrite 3046 * the flash parameters and settings immediately after parsing the Basic 3047 * Flash Parameter Table. 3048 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed. 3049 * It is used to tweak various flash parameters when information provided 3050 * by the SFDP tables are wrong. 3051 * 3052 * which can be overwritten by: 3053 * 4/ Late flash parameters initialization, used to initialize flash 3054 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP 3055 * tables are not defined at all. 3056 * spi_nor_late_init_params() 3057 * 3058 * Return: 0 on success, -errno otherwise. 3059 */ 3060 static int spi_nor_init_params(struct spi_nor *nor) 3061 { 3062 int ret; 3063 3064 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 3065 if (!nor->params) 3066 return -ENOMEM; 3067 3068 spi_nor_init_default_params(nor); 3069 3070 if (spi_nor_needs_sfdp(nor)) { 3071 ret = spi_nor_parse_sfdp(nor); 3072 if (ret) { 3073 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n"); 3074 return ret; 3075 } 3076 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) { 3077 spi_nor_no_sfdp_init_params(nor); 3078 } else { 3079 spi_nor_init_params_deprecated(nor); 3080 } 3081 3082 return spi_nor_late_init_params(nor); 3083 } 3084 3085 /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. 3086 * @nor: pointer to a 'struct spi_nor' 3087 * @enable: whether to enable or disable Octal DTR 3088 * 3089 * Return: 0 on success, -errno otherwise. 3090 */ 3091 static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable) 3092 { 3093 int ret; 3094 3095 if (!nor->params->set_octal_dtr) 3096 return 0; 3097 3098 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && 3099 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) 3100 return 0; 3101 3102 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) 3103 return 0; 3104 3105 ret = nor->params->set_octal_dtr(nor, enable); 3106 if (ret) 3107 return ret; 3108 3109 if (enable) 3110 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; 3111 else 3112 nor->reg_proto = SNOR_PROTO_1_1_1; 3113 3114 return 0; 3115 } 3116 3117 /** 3118 * spi_nor_quad_enable() - enable Quad I/O if needed. 3119 * @nor: pointer to a 'struct spi_nor' 3120 * 3121 * Return: 0 on success, -errno otherwise. 3122 */ 3123 static int spi_nor_quad_enable(struct spi_nor *nor) 3124 { 3125 if (!nor->params->quad_enable) 3126 return 0; 3127 3128 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 3129 spi_nor_get_protocol_width(nor->write_proto) == 4)) 3130 return 0; 3131 3132 return nor->params->quad_enable(nor); 3133 } 3134 3135 /** 3136 * spi_nor_set_4byte_addr_mode() - Set address mode. 3137 * @nor: pointer to a 'struct spi_nor'. 3138 * @enable: enable/disable 4 byte address mode. 3139 * 3140 * Return: 0 on success, -errno otherwise. 3141 */ 3142 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 3143 { 3144 struct spi_nor_flash_parameter *params = nor->params; 3145 int ret; 3146 3147 ret = params->set_4byte_addr_mode(nor, enable); 3148 if (ret && ret != -ENOTSUPP) 3149 return ret; 3150 3151 if (enable) { 3152 params->addr_nbytes = 4; 3153 params->addr_mode_nbytes = 4; 3154 } else { 3155 params->addr_nbytes = 3; 3156 params->addr_mode_nbytes = 3; 3157 } 3158 3159 return 0; 3160 } 3161 3162 static int spi_nor_init(struct spi_nor *nor) 3163 { 3164 int err; 3165 3166 err = spi_nor_set_octal_dtr(nor, true); 3167 if (err) { 3168 dev_dbg(nor->dev, "octal mode not supported\n"); 3169 return err; 3170 } 3171 3172 err = spi_nor_quad_enable(nor); 3173 if (err) { 3174 dev_dbg(nor->dev, "quad mode not supported\n"); 3175 return err; 3176 } 3177 3178 /* 3179 * Some SPI NOR flashes are write protected by default after a power-on 3180 * reset cycle, in order to avoid inadvertent writes during power-up. 3181 * Backward compatibility imposes to unlock the entire flash memory 3182 * array at power-up by default. Depending on the kernel configuration 3183 * (1) do nothing, (2) always unlock the entire flash array or (3) 3184 * unlock the entire flash array only when the software write 3185 * protection bits are volatile. The latter is indicated by 3186 * SNOR_F_SWP_IS_VOLATILE. 3187 */ 3188 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || 3189 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && 3190 nor->flags & SNOR_F_SWP_IS_VOLATILE)) 3191 spi_nor_try_unlock_all(nor); 3192 3193 if (nor->addr_nbytes == 4 && 3194 nor->read_proto != SNOR_PROTO_8_8_8_DTR && 3195 !(nor->flags & SNOR_F_4B_OPCODES)) { 3196 /* 3197 * If the RESET# pin isn't hooked up properly, or the system 3198 * otherwise doesn't perform a reset command in the boot 3199 * sequence, it's impossible to 100% protect against unexpected 3200 * reboots (e.g., crashes). Warn the user (or hopefully, system 3201 * designer) that this is bad. 3202 */ 3203 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 3204 "enabling reset hack; may not recover from unexpected reboots\n"); 3205 err = spi_nor_set_4byte_addr_mode(nor, true); 3206 if (err) 3207 return err; 3208 } 3209 3210 return 0; 3211 } 3212 3213 /** 3214 * spi_nor_soft_reset() - Perform a software reset 3215 * @nor: pointer to 'struct spi_nor' 3216 * 3217 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets 3218 * the device to its power-on-reset state. This is useful when the software has 3219 * made some changes to device (volatile) registers and needs to reset it before 3220 * shutting down, for example. 3221 * 3222 * Not every flash supports this sequence. The same set of opcodes might be used 3223 * for some other operation on a flash that does not support this. Support for 3224 * this sequence can be discovered via SFDP in the BFPT table. 3225 * 3226 * Return: 0 on success, -errno otherwise. 3227 */ 3228 static void spi_nor_soft_reset(struct spi_nor *nor) 3229 { 3230 struct spi_mem_op op; 3231 int ret; 3232 3233 op = (struct spi_mem_op)SPINOR_SRSTEN_OP; 3234 3235 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3236 3237 ret = spi_mem_exec_op(nor->spimem, &op); 3238 if (ret) { 3239 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3240 return; 3241 } 3242 3243 op = (struct spi_mem_op)SPINOR_SRST_OP; 3244 3245 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 3246 3247 ret = spi_mem_exec_op(nor->spimem, &op); 3248 if (ret) { 3249 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 3250 return; 3251 } 3252 3253 /* 3254 * Software Reset is not instant, and the delay varies from flash to 3255 * flash. Looking at a few flashes, most range somewhere below 100 3256 * microseconds. So, sleep for a range of 200-400 us. 3257 */ 3258 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); 3259 } 3260 3261 /* mtd suspend handler */ 3262 static int spi_nor_suspend(struct mtd_info *mtd) 3263 { 3264 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3265 int ret; 3266 3267 /* Disable octal DTR mode if we enabled it. */ 3268 ret = spi_nor_set_octal_dtr(nor, false); 3269 if (ret) 3270 dev_err(nor->dev, "suspend() failed\n"); 3271 3272 return ret; 3273 } 3274 3275 /* mtd resume handler */ 3276 static void spi_nor_resume(struct mtd_info *mtd) 3277 { 3278 struct spi_nor *nor = mtd_to_spi_nor(mtd); 3279 struct device *dev = nor->dev; 3280 int ret; 3281 3282 /* re-initialize the nor chip */ 3283 ret = spi_nor_init(nor); 3284 if (ret) 3285 dev_err(dev, "resume() failed\n"); 3286 } 3287 3288 static int spi_nor_get_device(struct mtd_info *mtd) 3289 { 3290 struct mtd_info *master = mtd_get_master(mtd); 3291 struct spi_nor *nor = mtd_to_spi_nor(master); 3292 struct device *dev; 3293 3294 if (nor->spimem) 3295 dev = nor->spimem->spi->controller->dev.parent; 3296 else 3297 dev = nor->dev; 3298 3299 if (!try_module_get(dev->driver->owner)) 3300 return -ENODEV; 3301 3302 return 0; 3303 } 3304 3305 static void spi_nor_put_device(struct mtd_info *mtd) 3306 { 3307 struct mtd_info *master = mtd_get_master(mtd); 3308 struct spi_nor *nor = mtd_to_spi_nor(master); 3309 struct device *dev; 3310 3311 if (nor->spimem) 3312 dev = nor->spimem->spi->controller->dev.parent; 3313 else 3314 dev = nor->dev; 3315 3316 module_put(dev->driver->owner); 3317 } 3318 3319 static void spi_nor_restore(struct spi_nor *nor) 3320 { 3321 int ret; 3322 3323 /* restore the addressing mode */ 3324 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 3325 nor->flags & SNOR_F_BROKEN_RESET) { 3326 ret = spi_nor_set_4byte_addr_mode(nor, false); 3327 if (ret) 3328 /* 3329 * Do not stop the execution in the hope that the flash 3330 * will default to the 3-byte address mode after the 3331 * software reset. 3332 */ 3333 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret); 3334 } 3335 3336 if (nor->flags & SNOR_F_SOFT_RESET) 3337 spi_nor_soft_reset(nor); 3338 } 3339 3340 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, 3341 const char *name) 3342 { 3343 unsigned int i, j; 3344 3345 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 3346 for (j = 0; j < manufacturers[i]->nparts; j++) { 3347 if (!strcmp(name, manufacturers[i]->parts[j].name)) { 3348 nor->manufacturer = manufacturers[i]; 3349 return &manufacturers[i]->parts[j]; 3350 } 3351 } 3352 } 3353 3354 return NULL; 3355 } 3356 3357 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 3358 const char *name) 3359 { 3360 const struct flash_info *info = NULL; 3361 3362 if (name) 3363 info = spi_nor_match_name(nor, name); 3364 /* Try to auto-detect if chip name wasn't specified or not found */ 3365 if (!info) 3366 return spi_nor_detect(nor); 3367 3368 /* 3369 * If caller has specified name of flash model that can normally be 3370 * detected using JEDEC, let's verify it. 3371 */ 3372 if (name && info->id) { 3373 const struct flash_info *jinfo; 3374 3375 jinfo = spi_nor_detect(nor); 3376 if (IS_ERR(jinfo)) { 3377 return jinfo; 3378 } else if (jinfo != info) { 3379 /* 3380 * JEDEC knows better, so overwrite platform ID. We 3381 * can't trust partitions any longer, but we'll let 3382 * mtd apply them anyway, since some partitions may be 3383 * marked read-only, and we don't want to loose that 3384 * information, even if it's not 100% accurate. 3385 */ 3386 dev_warn(nor->dev, "found %s, expected %s\n", 3387 jinfo->name, info->name); 3388 info = jinfo; 3389 } 3390 } 3391 3392 return info; 3393 } 3394 3395 static void spi_nor_set_mtd_info(struct spi_nor *nor) 3396 { 3397 struct mtd_info *mtd = &nor->mtd; 3398 struct device *dev = nor->dev; 3399 3400 spi_nor_set_mtd_locking_ops(nor); 3401 spi_nor_set_mtd_otp_ops(nor); 3402 3403 mtd->dev.parent = dev; 3404 if (!mtd->name) 3405 mtd->name = dev_name(dev); 3406 mtd->type = MTD_NORFLASH; 3407 mtd->flags = MTD_CAP_NORFLASH; 3408 /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */ 3409 if (nor->flags & SNOR_F_ECC) 3410 mtd->flags &= ~MTD_BIT_WRITEABLE; 3411 if (nor->info->flags & SPI_NOR_NO_ERASE) 3412 mtd->flags |= MTD_NO_ERASE; 3413 else 3414 mtd->_erase = spi_nor_erase; 3415 mtd->writesize = nor->params->writesize; 3416 mtd->writebufsize = nor->params->page_size; 3417 mtd->size = nor->params->size; 3418 mtd->_read = spi_nor_read; 3419 /* Might be already set by some SST flashes. */ 3420 if (!mtd->_write) 3421 mtd->_write = spi_nor_write; 3422 mtd->_suspend = spi_nor_suspend; 3423 mtd->_resume = spi_nor_resume; 3424 mtd->_get_device = spi_nor_get_device; 3425 mtd->_put_device = spi_nor_put_device; 3426 } 3427 3428 static int spi_nor_hw_reset(struct spi_nor *nor) 3429 { 3430 struct gpio_desc *reset; 3431 3432 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW); 3433 if (IS_ERR_OR_NULL(reset)) 3434 return PTR_ERR_OR_ZERO(reset); 3435 3436 /* 3437 * Experimental delay values by looking at different flash device 3438 * vendors datasheets. 3439 */ 3440 usleep_range(1, 5); 3441 gpiod_set_value_cansleep(reset, 1); 3442 usleep_range(100, 150); 3443 gpiod_set_value_cansleep(reset, 0); 3444 usleep_range(1000, 1200); 3445 3446 return 0; 3447 } 3448 3449 int spi_nor_scan(struct spi_nor *nor, const char *name, 3450 const struct spi_nor_hwcaps *hwcaps) 3451 { 3452 const struct flash_info *info; 3453 struct device *dev = nor->dev; 3454 struct mtd_info *mtd = &nor->mtd; 3455 int ret; 3456 int i; 3457 3458 ret = spi_nor_check(nor); 3459 if (ret) 3460 return ret; 3461 3462 /* Reset SPI protocol for all commands. */ 3463 nor->reg_proto = SNOR_PROTO_1_1_1; 3464 nor->read_proto = SNOR_PROTO_1_1_1; 3465 nor->write_proto = SNOR_PROTO_1_1_1; 3466 3467 /* 3468 * We need the bounce buffer early to read/write registers when going 3469 * through the spi-mem layer (buffers have to be DMA-able). 3470 * For spi-mem drivers, we'll reallocate a new buffer if 3471 * nor->params->page_size turns out to be greater than PAGE_SIZE (which 3472 * shouldn't happen before long since NOR pages are usually less 3473 * than 1KB) after spi_nor_scan() returns. 3474 */ 3475 nor->bouncebuf_size = PAGE_SIZE; 3476 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 3477 GFP_KERNEL); 3478 if (!nor->bouncebuf) 3479 return -ENOMEM; 3480 3481 ret = spi_nor_hw_reset(nor); 3482 if (ret) 3483 return ret; 3484 3485 info = spi_nor_get_flash_info(nor, name); 3486 if (IS_ERR(info)) 3487 return PTR_ERR(info); 3488 3489 nor->info = info; 3490 3491 mutex_init(&nor->lock); 3492 3493 /* Init flash parameters based on flash_info struct and SFDP */ 3494 ret = spi_nor_init_params(nor); 3495 if (ret) 3496 return ret; 3497 3498 if (spi_nor_use_parallel_locking(nor)) 3499 init_waitqueue_head(&nor->rww.wait); 3500 3501 /* 3502 * Configure the SPI memory: 3503 * - select op codes for (Fast) Read, Page Program and Sector Erase. 3504 * - set the number of dummy cycles (mode cycles + wait states). 3505 * - set the SPI protocols for register and memory accesses. 3506 * - set the number of address bytes. 3507 */ 3508 ret = spi_nor_setup(nor, hwcaps); 3509 if (ret) 3510 return ret; 3511 3512 /* Send all the required SPI flash commands to initialize device */ 3513 ret = spi_nor_init(nor); 3514 if (ret) 3515 return ret; 3516 3517 /* No mtd_info fields should be used up to this point. */ 3518 spi_nor_set_mtd_info(nor); 3519 3520 dev_info(dev, "%s (%lld Kbytes)\n", info->name, 3521 (long long)mtd->size >> 10); 3522 3523 dev_dbg(dev, 3524 "mtd .name = %s, .size = 0x%llx (%lldMiB), " 3525 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 3526 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 3527 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 3528 3529 if (mtd->numeraseregions) 3530 for (i = 0; i < mtd->numeraseregions; i++) 3531 dev_dbg(dev, 3532 "mtd.eraseregions[%d] = { .offset = 0x%llx, " 3533 ".erasesize = 0x%.8x (%uKiB), " 3534 ".numblocks = %d }\n", 3535 i, (long long)mtd->eraseregions[i].offset, 3536 mtd->eraseregions[i].erasesize, 3537 mtd->eraseregions[i].erasesize / 1024, 3538 mtd->eraseregions[i].numblocks); 3539 return 0; 3540 } 3541 EXPORT_SYMBOL_GPL(spi_nor_scan); 3542 3543 static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3544 { 3545 struct spi_mem_dirmap_info info = { 3546 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 3547 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), 3548 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 3549 SPI_MEM_OP_DATA_IN(0, NULL, 0)), 3550 .offset = 0, 3551 .length = nor->params->size, 3552 }; 3553 struct spi_mem_op *op = &info.op_tmpl; 3554 3555 spi_nor_spimem_setup_op(nor, op, nor->read_proto); 3556 3557 /* convert the dummy cycles to the number of bytes */ 3558 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3559 if (spi_nor_protocol_is_dtr(nor->read_proto)) 3560 op->dummy.nbytes *= 2; 3561 3562 /* 3563 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3564 * of data bytes is non-zero, the data buswidth won't be set here. So, 3565 * do it explicitly. 3566 */ 3567 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3568 3569 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3570 &info); 3571 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3572 } 3573 3574 static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3575 { 3576 struct spi_mem_dirmap_info info = { 3577 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 3578 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), 3579 SPI_MEM_OP_NO_DUMMY, 3580 SPI_MEM_OP_DATA_OUT(0, NULL, 0)), 3581 .offset = 0, 3582 .length = nor->params->size, 3583 }; 3584 struct spi_mem_op *op = &info.op_tmpl; 3585 3586 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3587 op->addr.nbytes = 0; 3588 3589 spi_nor_spimem_setup_op(nor, op, nor->write_proto); 3590 3591 /* 3592 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3593 * of data bytes is non-zero, the data buswidth won't be set here. So, 3594 * do it explicitly. 3595 */ 3596 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3597 3598 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3599 &info); 3600 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3601 } 3602 3603 static int spi_nor_probe(struct spi_mem *spimem) 3604 { 3605 struct spi_device *spi = spimem->spi; 3606 struct flash_platform_data *data = dev_get_platdata(&spi->dev); 3607 struct spi_nor *nor; 3608 /* 3609 * Enable all caps by default. The core will mask them after 3610 * checking what's really supported using spi_mem_supports_op(). 3611 */ 3612 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3613 char *flash_name; 3614 int ret; 3615 3616 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 3617 if (!nor) 3618 return -ENOMEM; 3619 3620 nor->spimem = spimem; 3621 nor->dev = &spi->dev; 3622 spi_nor_set_flash_node(nor, spi->dev.of_node); 3623 3624 spi_mem_set_drvdata(spimem, nor); 3625 3626 if (data && data->name) 3627 nor->mtd.name = data->name; 3628 3629 if (!nor->mtd.name) 3630 nor->mtd.name = spi_mem_get_name(spimem); 3631 3632 /* 3633 * For some (historical?) reason many platforms provide two different 3634 * names in flash_platform_data: "name" and "type". Quite often name is 3635 * set to "m25p80" and then "type" provides a real chip name. 3636 * If that's the case, respect "type" and ignore a "name". 3637 */ 3638 if (data && data->type) 3639 flash_name = data->type; 3640 else if (!strcmp(spi->modalias, "spi-nor")) 3641 flash_name = NULL; /* auto-detect */ 3642 else 3643 flash_name = spi->modalias; 3644 3645 ret = spi_nor_scan(nor, flash_name, &hwcaps); 3646 if (ret) 3647 return ret; 3648 3649 spi_nor_debugfs_register(nor); 3650 3651 /* 3652 * None of the existing parts have > 512B pages, but let's play safe 3653 * and add this logic so that if anyone ever adds support for such 3654 * a NOR we don't end up with buffer overflows. 3655 */ 3656 if (nor->params->page_size > PAGE_SIZE) { 3657 nor->bouncebuf_size = nor->params->page_size; 3658 devm_kfree(nor->dev, nor->bouncebuf); 3659 nor->bouncebuf = devm_kmalloc(nor->dev, 3660 nor->bouncebuf_size, 3661 GFP_KERNEL); 3662 if (!nor->bouncebuf) 3663 return -ENOMEM; 3664 } 3665 3666 ret = spi_nor_create_read_dirmap(nor); 3667 if (ret) 3668 return ret; 3669 3670 ret = spi_nor_create_write_dirmap(nor); 3671 if (ret) 3672 return ret; 3673 3674 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3675 data ? data->nr_parts : 0); 3676 } 3677 3678 static int spi_nor_remove(struct spi_mem *spimem) 3679 { 3680 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3681 3682 spi_nor_restore(nor); 3683 3684 /* Clean up MTD stuff. */ 3685 return mtd_device_unregister(&nor->mtd); 3686 } 3687 3688 static void spi_nor_shutdown(struct spi_mem *spimem) 3689 { 3690 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3691 3692 spi_nor_restore(nor); 3693 } 3694 3695 /* 3696 * Do NOT add to this array without reading the following: 3697 * 3698 * Historically, many flash devices are bound to this driver by their name. But 3699 * since most of these flash are compatible to some extent, and their 3700 * differences can often be differentiated by the JEDEC read-ID command, we 3701 * encourage new users to add support to the spi-nor library, and simply bind 3702 * against a generic string here (e.g., "jedec,spi-nor"). 3703 * 3704 * Many flash names are kept here in this list to keep them available 3705 * as module aliases for existing platforms. 3706 */ 3707 static const struct spi_device_id spi_nor_dev_ids[] = { 3708 /* 3709 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3710 * hack around the fact that the SPI core does not provide uevent 3711 * matching for .of_match_table 3712 */ 3713 {"spi-nor"}, 3714 3715 /* 3716 * Entries not used in DTs that should be safe to drop after replacing 3717 * them with "spi-nor" in platform data. 3718 */ 3719 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3720 3721 /* 3722 * Entries that were used in DTs without "jedec,spi-nor" fallback and 3723 * should be kept for backward compatibility. 3724 */ 3725 {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3726 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3727 {"mx25l25635e"},{"mx66l51235l"}, 3728 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3729 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3730 {"s25fl064k"}, 3731 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3732 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3733 {"m25p64"}, {"m25p128"}, 3734 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3735 {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3736 3737 /* Flashes that can't be detected using JEDEC */ 3738 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3739 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3740 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3741 3742 /* Everspin MRAMs (non-JEDEC) */ 3743 { "mr25h128" }, /* 128 Kib, 40 MHz */ 3744 { "mr25h256" }, /* 256 Kib, 40 MHz */ 3745 { "mr25h10" }, /* 1 Mib, 40 MHz */ 3746 { "mr25h40" }, /* 4 Mib, 40 MHz */ 3747 3748 { }, 3749 }; 3750 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3751 3752 static const struct of_device_id spi_nor_of_table[] = { 3753 /* 3754 * Generic compatibility for SPI NOR that can be identified by the 3755 * JEDEC READ ID opcode (0x9F). Use this, if possible. 3756 */ 3757 { .compatible = "jedec,spi-nor" }, 3758 { /* sentinel */ }, 3759 }; 3760 MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3761 3762 /* 3763 * REVISIT: many of these chips have deep power-down modes, which 3764 * should clearly be entered on suspend() to minimize power use. 3765 * And also when they're otherwise idle... 3766 */ 3767 static struct spi_mem_driver spi_nor_driver = { 3768 .spidrv = { 3769 .driver = { 3770 .name = "spi-nor", 3771 .of_match_table = spi_nor_of_table, 3772 .dev_groups = spi_nor_sysfs_groups, 3773 }, 3774 .id_table = spi_nor_dev_ids, 3775 }, 3776 .probe = spi_nor_probe, 3777 .remove = spi_nor_remove, 3778 .shutdown = spi_nor_shutdown, 3779 }; 3780 3781 static int __init spi_nor_module_init(void) 3782 { 3783 return spi_mem_driver_register(&spi_nor_driver); 3784 } 3785 module_init(spi_nor_module_init); 3786 3787 static void __exit spi_nor_module_exit(void) 3788 { 3789 spi_mem_driver_unregister(&spi_nor_driver); 3790 spi_nor_debugfs_shutdown(); 3791 } 3792 module_exit(spi_nor_module_exit); 3793 3794 MODULE_LICENSE("GPL v2"); 3795 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3796 MODULE_AUTHOR("Mike Lavender"); 3797 MODULE_DESCRIPTION("framework for SPI NOR"); 3798