1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/err.h> 11 #include <linux/errno.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/mutex.h> 15 #include <linux/math64.h> 16 #include <linux/sizes.h> 17 #include <linux/slab.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/of_platform.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/spi/flash.h> 23 #include <linux/mtd/spi-nor.h> 24 25 #include "core.h" 26 27 /* Define max times to check status register before we give up. */ 28 29 /* 30 * For everything but full-chip erase; probably could be much smaller, but kept 31 * around for safety for now 32 */ 33 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 34 35 /* 36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up 37 * for larger flash 38 */ 39 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) 40 41 #define SPI_NOR_MAX_ADDR_WIDTH 4 42 43 #define SPI_NOR_SRST_SLEEP_MIN 200 44 #define SPI_NOR_SRST_SLEEP_MAX 400 45 46 /** 47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the 48 * extension type. 49 * @nor: pointer to a 'struct spi_nor' 50 * @op: pointer to the 'struct spi_mem_op' whose properties 51 * need to be initialized. 52 * 53 * Right now, only "repeat" and "invert" are supported. 54 * 55 * Return: The opcode extension. 56 */ 57 static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor, 58 const struct spi_mem_op *op) 59 { 60 switch (nor->cmd_ext_type) { 61 case SPI_NOR_EXT_INVERT: 62 return ~op->cmd.opcode; 63 64 case SPI_NOR_EXT_REPEAT: 65 return op->cmd.opcode; 66 67 default: 68 dev_err(nor->dev, "Unknown command extension type\n"); 69 return 0; 70 } 71 } 72 73 /** 74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. 75 * @nor: pointer to a 'struct spi_nor' 76 * @op: pointer to the 'struct spi_mem_op' whose properties 77 * need to be initialized. 78 * @proto: the protocol from which the properties need to be set. 79 */ 80 void spi_nor_spimem_setup_op(const struct spi_nor *nor, 81 struct spi_mem_op *op, 82 const enum spi_nor_protocol proto) 83 { 84 u8 ext; 85 86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); 87 88 if (op->addr.nbytes) 89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto); 90 91 if (op->dummy.nbytes) 92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto); 93 94 if (op->data.nbytes) 95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); 96 97 if (spi_nor_protocol_is_dtr(proto)) { 98 /* 99 * SPIMEM supports mixed DTR modes, but right now we can only 100 * have all phases either DTR or STR. IOW, SPIMEM can have 101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 102 * phases to either DTR or STR. 103 */ 104 op->cmd.dtr = true; 105 op->addr.dtr = true; 106 op->dummy.dtr = true; 107 op->data.dtr = true; 108 109 /* 2 bytes per clock cycle in DTR mode. */ 110 op->dummy.nbytes *= 2; 111 112 ext = spi_nor_get_cmd_ext(nor, op); 113 op->cmd.opcode = (op->cmd.opcode << 8) | ext; 114 op->cmd.nbytes = 2; 115 } 116 } 117 118 /** 119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data 120 * transfer 121 * @nor: pointer to 'struct spi_nor' 122 * @op: pointer to 'struct spi_mem_op' template for transfer 123 * 124 * If we have to use the bounce buffer, the data field in @op will be updated. 125 * 126 * Return: true if the bounce buffer is needed, false if not 127 */ 128 static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op) 129 { 130 /* op->data.buf.in occupies the same memory as op->data.buf.out */ 131 if (object_is_on_stack(op->data.buf.in) || 132 !virt_addr_valid(op->data.buf.in)) { 133 if (op->data.nbytes > nor->bouncebuf_size) 134 op->data.nbytes = nor->bouncebuf_size; 135 op->data.buf.in = nor->bouncebuf; 136 return true; 137 } 138 139 return false; 140 } 141 142 /** 143 * spi_nor_spimem_exec_op() - execute a memory operation 144 * @nor: pointer to 'struct spi_nor' 145 * @op: pointer to 'struct spi_mem_op' template for transfer 146 * 147 * Return: 0 on success, -error otherwise. 148 */ 149 static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op) 150 { 151 int error; 152 153 error = spi_mem_adjust_op_size(nor->spimem, op); 154 if (error) 155 return error; 156 157 return spi_mem_exec_op(nor->spimem, op); 158 } 159 160 int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode, 161 u8 *buf, size_t len) 162 { 163 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 164 return -EOPNOTSUPP; 165 166 return nor->controller_ops->read_reg(nor, opcode, buf, len); 167 } 168 169 int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode, 170 const u8 *buf, size_t len) 171 { 172 if (spi_nor_protocol_is_dtr(nor->reg_proto)) 173 return -EOPNOTSUPP; 174 175 return nor->controller_ops->write_reg(nor, opcode, buf, len); 176 } 177 178 static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs) 179 { 180 if (spi_nor_protocol_is_dtr(nor->write_proto)) 181 return -EOPNOTSUPP; 182 183 return nor->controller_ops->erase(nor, offs); 184 } 185 186 /** 187 * spi_nor_spimem_read_data() - read data from flash's memory region via 188 * spi-mem 189 * @nor: pointer to 'struct spi_nor' 190 * @from: offset to read from 191 * @len: number of bytes to read 192 * @buf: pointer to dst buffer 193 * 194 * Return: number of bytes read successfully, -errno otherwise 195 */ 196 static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, 197 size_t len, u8 *buf) 198 { 199 struct spi_mem_op op = 200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 201 SPI_MEM_OP_ADDR(nor->addr_width, from, 0), 202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 203 SPI_MEM_OP_DATA_IN(len, buf, 0)); 204 bool usebouncebuf; 205 ssize_t nbytes; 206 int error; 207 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto); 209 210 /* convert the dummy cycles to the number of bytes */ 211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 212 if (spi_nor_protocol_is_dtr(nor->read_proto)) 213 op.dummy.nbytes *= 2; 214 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op); 216 217 if (nor->dirmap.rdesc) { 218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val, 219 op.data.nbytes, op.data.buf.in); 220 } else { 221 error = spi_nor_spimem_exec_op(nor, &op); 222 if (error) 223 return error; 224 nbytes = op.data.nbytes; 225 } 226 227 if (usebouncebuf && nbytes > 0) 228 memcpy(buf, op.data.buf.in, nbytes); 229 230 return nbytes; 231 } 232 233 /** 234 * spi_nor_read_data() - read data from flash memory 235 * @nor: pointer to 'struct spi_nor' 236 * @from: offset to read from 237 * @len: number of bytes to read 238 * @buf: pointer to dst buffer 239 * 240 * Return: number of bytes read successfully, -errno otherwise 241 */ 242 ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) 243 { 244 if (nor->spimem) 245 return spi_nor_spimem_read_data(nor, from, len, buf); 246 247 return nor->controller_ops->read(nor, from, len, buf); 248 } 249 250 /** 251 * spi_nor_spimem_write_data() - write data to flash memory via 252 * spi-mem 253 * @nor: pointer to 'struct spi_nor' 254 * @to: offset to write to 255 * @len: number of bytes to write 256 * @buf: pointer to src buffer 257 * 258 * Return: number of bytes written successfully, -errno otherwise 259 */ 260 static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to, 261 size_t len, const u8 *buf) 262 { 263 struct spi_mem_op op = 264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 265 SPI_MEM_OP_ADDR(nor->addr_width, to, 0), 266 SPI_MEM_OP_NO_DUMMY, 267 SPI_MEM_OP_DATA_OUT(len, buf, 0)); 268 ssize_t nbytes; 269 int error; 270 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 272 op.addr.nbytes = 0; 273 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 275 276 if (spi_nor_spimem_bounce(nor, &op)) 277 memcpy(nor->bouncebuf, buf, op.data.nbytes); 278 279 if (nor->dirmap.wdesc) { 280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val, 281 op.data.nbytes, op.data.buf.out); 282 } else { 283 error = spi_nor_spimem_exec_op(nor, &op); 284 if (error) 285 return error; 286 nbytes = op.data.nbytes; 287 } 288 289 return nbytes; 290 } 291 292 /** 293 * spi_nor_write_data() - write data to flash memory 294 * @nor: pointer to 'struct spi_nor' 295 * @to: offset to write to 296 * @len: number of bytes to write 297 * @buf: pointer to src buffer 298 * 299 * Return: number of bytes written successfully, -errno otherwise 300 */ 301 ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 302 const u8 *buf) 303 { 304 if (nor->spimem) 305 return spi_nor_spimem_write_data(nor, to, len, buf); 306 307 return nor->controller_ops->write(nor, to, len, buf); 308 } 309 310 /** 311 * spi_nor_write_enable() - Set write enable latch with Write Enable command. 312 * @nor: pointer to 'struct spi_nor'. 313 * 314 * Return: 0 on success, -errno otherwise. 315 */ 316 int spi_nor_write_enable(struct spi_nor *nor) 317 { 318 int ret; 319 320 if (nor->spimem) { 321 struct spi_mem_op op = 322 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 0), 323 SPI_MEM_OP_NO_ADDR, 324 SPI_MEM_OP_NO_DUMMY, 325 SPI_MEM_OP_NO_DATA); 326 327 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 328 329 ret = spi_mem_exec_op(nor->spimem, &op); 330 } else { 331 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN, 332 NULL, 0); 333 } 334 335 if (ret) 336 dev_dbg(nor->dev, "error %d on Write Enable\n", ret); 337 338 return ret; 339 } 340 341 /** 342 * spi_nor_write_disable() - Send Write Disable instruction to the chip. 343 * @nor: pointer to 'struct spi_nor'. 344 * 345 * Return: 0 on success, -errno otherwise. 346 */ 347 int spi_nor_write_disable(struct spi_nor *nor) 348 { 349 int ret; 350 351 if (nor->spimem) { 352 struct spi_mem_op op = 353 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 0), 354 SPI_MEM_OP_NO_ADDR, 355 SPI_MEM_OP_NO_DUMMY, 356 SPI_MEM_OP_NO_DATA); 357 358 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 359 360 ret = spi_mem_exec_op(nor->spimem, &op); 361 } else { 362 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI, 363 NULL, 0); 364 } 365 366 if (ret) 367 dev_dbg(nor->dev, "error %d on Write Disable\n", ret); 368 369 return ret; 370 } 371 372 /** 373 * spi_nor_read_sr() - Read the Status Register. 374 * @nor: pointer to 'struct spi_nor'. 375 * @sr: pointer to a DMA-able buffer where the value of the 376 * Status Register will be written. Should be at least 2 bytes. 377 * 378 * Return: 0 on success, -errno otherwise. 379 */ 380 int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) 381 { 382 int ret; 383 384 if (nor->spimem) { 385 struct spi_mem_op op = 386 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0), 387 SPI_MEM_OP_NO_ADDR, 388 SPI_MEM_OP_NO_DUMMY, 389 SPI_MEM_OP_DATA_IN(1, sr, 0)); 390 391 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { 392 op.addr.nbytes = nor->params->rdsr_addr_nbytes; 393 op.dummy.nbytes = nor->params->rdsr_dummy; 394 /* 395 * We don't want to read only one byte in DTR mode. So, 396 * read 2 and then discard the second byte. 397 */ 398 op.data.nbytes = 2; 399 } 400 401 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 402 403 ret = spi_mem_exec_op(nor->spimem, &op); 404 } else { 405 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr, 406 1); 407 } 408 409 if (ret) 410 dev_dbg(nor->dev, "error %d reading SR\n", ret); 411 412 return ret; 413 } 414 415 /** 416 * spi_nor_read_cr() - Read the Configuration Register using the 417 * SPINOR_OP_RDCR (35h) command. 418 * @nor: pointer to 'struct spi_nor' 419 * @cr: pointer to a DMA-able buffer where the value of the 420 * Configuration Register will be written. 421 * 422 * Return: 0 on success, -errno otherwise. 423 */ 424 int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) 425 { 426 int ret; 427 428 if (nor->spimem) { 429 struct spi_mem_op op = 430 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 0), 431 SPI_MEM_OP_NO_ADDR, 432 SPI_MEM_OP_NO_DUMMY, 433 SPI_MEM_OP_DATA_IN(1, cr, 0)); 434 435 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 436 437 ret = spi_mem_exec_op(nor->spimem, &op); 438 } else { 439 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr, 440 1); 441 } 442 443 if (ret) 444 dev_dbg(nor->dev, "error %d reading CR\n", ret); 445 446 return ret; 447 } 448 449 /** 450 * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. 451 * @nor: pointer to 'struct spi_nor'. 452 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 453 * address mode. 454 * 455 * Return: 0 on success, -errno otherwise. 456 */ 457 int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 458 { 459 int ret; 460 461 if (nor->spimem) { 462 struct spi_mem_op op = 463 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ? 464 SPINOR_OP_EN4B : 465 SPINOR_OP_EX4B, 466 0), 467 SPI_MEM_OP_NO_ADDR, 468 SPI_MEM_OP_NO_DUMMY, 469 SPI_MEM_OP_NO_DATA); 470 471 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 472 473 ret = spi_mem_exec_op(nor->spimem, &op); 474 } else { 475 ret = spi_nor_controller_ops_write_reg(nor, 476 enable ? SPINOR_OP_EN4B : 477 SPINOR_OP_EX4B, 478 NULL, 0); 479 } 480 481 if (ret) 482 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 483 484 return ret; 485 } 486 487 /** 488 * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion 489 * flashes. 490 * @nor: pointer to 'struct spi_nor'. 491 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 492 * address mode. 493 * 494 * Return: 0 on success, -errno otherwise. 495 */ 496 static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 497 { 498 int ret; 499 500 nor->bouncebuf[0] = enable << 7; 501 502 if (nor->spimem) { 503 struct spi_mem_op op = 504 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_BRWR, 0), 505 SPI_MEM_OP_NO_ADDR, 506 SPI_MEM_OP_NO_DUMMY, 507 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 508 509 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 510 511 ret = spi_mem_exec_op(nor->spimem, &op); 512 } else { 513 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR, 514 nor->bouncebuf, 1); 515 } 516 517 if (ret) 518 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret); 519 520 return ret; 521 } 522 523 /** 524 * spi_nor_write_ear() - Write Extended Address Register. 525 * @nor: pointer to 'struct spi_nor'. 526 * @ear: value to write to the Extended Address Register. 527 * 528 * Return: 0 on success, -errno otherwise. 529 */ 530 int spi_nor_write_ear(struct spi_nor *nor, u8 ear) 531 { 532 int ret; 533 534 nor->bouncebuf[0] = ear; 535 536 if (nor->spimem) { 537 struct spi_mem_op op = 538 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREAR, 0), 539 SPI_MEM_OP_NO_ADDR, 540 SPI_MEM_OP_NO_DUMMY, 541 SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 0)); 542 543 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 544 545 ret = spi_mem_exec_op(nor->spimem, &op); 546 } else { 547 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREAR, 548 nor->bouncebuf, 1); 549 } 550 551 if (ret) 552 dev_dbg(nor->dev, "error %d writing EAR\n", ret); 553 554 return ret; 555 } 556 557 /** 558 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready 559 * for new commands. 560 * @nor: pointer to 'struct spi_nor'. 561 * 562 * Return: 1 if ready, 0 if not ready, -errno on errors. 563 */ 564 int spi_nor_sr_ready(struct spi_nor *nor) 565 { 566 int ret; 567 568 ret = spi_nor_read_sr(nor, nor->bouncebuf); 569 if (ret) 570 return ret; 571 572 return !(nor->bouncebuf[0] & SR_WIP); 573 } 574 575 /** 576 * spi_nor_ready() - Query the flash to see if it is ready for new commands. 577 * @nor: pointer to 'struct spi_nor'. 578 * 579 * Return: 1 if ready, 0 if not ready, -errno on errors. 580 */ 581 static int spi_nor_ready(struct spi_nor *nor) 582 { 583 /* Flashes might override the standard routine. */ 584 if (nor->params->ready) 585 return nor->params->ready(nor); 586 587 return spi_nor_sr_ready(nor); 588 } 589 590 /** 591 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the 592 * Status Register until ready, or timeout occurs. 593 * @nor: pointer to "struct spi_nor". 594 * @timeout_jiffies: jiffies to wait until timeout. 595 * 596 * Return: 0 on success, -errno otherwise. 597 */ 598 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 599 unsigned long timeout_jiffies) 600 { 601 unsigned long deadline; 602 int timeout = 0, ret; 603 604 deadline = jiffies + timeout_jiffies; 605 606 while (!timeout) { 607 if (time_after_eq(jiffies, deadline)) 608 timeout = 1; 609 610 ret = spi_nor_ready(nor); 611 if (ret < 0) 612 return ret; 613 if (ret) 614 return 0; 615 616 cond_resched(); 617 } 618 619 dev_dbg(nor->dev, "flash operation timed out\n"); 620 621 return -ETIMEDOUT; 622 } 623 624 /** 625 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the 626 * flash to be ready, or timeout occurs. 627 * @nor: pointer to "struct spi_nor". 628 * 629 * Return: 0 on success, -errno otherwise. 630 */ 631 int spi_nor_wait_till_ready(struct spi_nor *nor) 632 { 633 return spi_nor_wait_till_ready_with_timeout(nor, 634 DEFAULT_READY_WAIT_JIFFIES); 635 } 636 637 /** 638 * spi_nor_global_block_unlock() - Unlock Global Block Protection. 639 * @nor: pointer to 'struct spi_nor'. 640 * 641 * Return: 0 on success, -errno otherwise. 642 */ 643 int spi_nor_global_block_unlock(struct spi_nor *nor) 644 { 645 int ret; 646 647 ret = spi_nor_write_enable(nor); 648 if (ret) 649 return ret; 650 651 if (nor->spimem) { 652 struct spi_mem_op op = 653 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_GBULK, 0), 654 SPI_MEM_OP_NO_ADDR, 655 SPI_MEM_OP_NO_DUMMY, 656 SPI_MEM_OP_NO_DATA); 657 658 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 659 660 ret = spi_mem_exec_op(nor->spimem, &op); 661 } else { 662 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK, 663 NULL, 0); 664 } 665 666 if (ret) { 667 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret); 668 return ret; 669 } 670 671 return spi_nor_wait_till_ready(nor); 672 } 673 674 /** 675 * spi_nor_write_sr() - Write the Status Register. 676 * @nor: pointer to 'struct spi_nor'. 677 * @sr: pointer to DMA-able buffer to write to the Status Register. 678 * @len: number of bytes to write to the Status Register. 679 * 680 * Return: 0 on success, -errno otherwise. 681 */ 682 int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) 683 { 684 int ret; 685 686 ret = spi_nor_write_enable(nor); 687 if (ret) 688 return ret; 689 690 if (nor->spimem) { 691 struct spi_mem_op op = 692 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 0), 693 SPI_MEM_OP_NO_ADDR, 694 SPI_MEM_OP_NO_DUMMY, 695 SPI_MEM_OP_DATA_OUT(len, sr, 0)); 696 697 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 698 699 ret = spi_mem_exec_op(nor->spimem, &op); 700 } else { 701 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr, 702 len); 703 } 704 705 if (ret) { 706 dev_dbg(nor->dev, "error %d writing SR\n", ret); 707 return ret; 708 } 709 710 return spi_nor_wait_till_ready(nor); 711 } 712 713 /** 714 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and 715 * ensure that the byte written match the received value. 716 * @nor: pointer to a 'struct spi_nor'. 717 * @sr1: byte value to be written to the Status Register. 718 * 719 * Return: 0 on success, -errno otherwise. 720 */ 721 static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1) 722 { 723 int ret; 724 725 nor->bouncebuf[0] = sr1; 726 727 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1); 728 if (ret) 729 return ret; 730 731 ret = spi_nor_read_sr(nor, nor->bouncebuf); 732 if (ret) 733 return ret; 734 735 if (nor->bouncebuf[0] != sr1) { 736 dev_dbg(nor->dev, "SR1: read back test failed\n"); 737 return -EIO; 738 } 739 740 return 0; 741 } 742 743 /** 744 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the 745 * Status Register 2 in one shot. Ensure that the byte written in the Status 746 * Register 1 match the received value, and that the 16-bit Write did not 747 * affect what was already in the Status Register 2. 748 * @nor: pointer to a 'struct spi_nor'. 749 * @sr1: byte value to be written to the Status Register 1. 750 * 751 * Return: 0 on success, -errno otherwise. 752 */ 753 static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) 754 { 755 int ret; 756 u8 *sr_cr = nor->bouncebuf; 757 u8 cr_written; 758 759 /* Make sure we don't overwrite the contents of Status Register 2. */ 760 if (!(nor->flags & SNOR_F_NO_READ_CR)) { 761 ret = spi_nor_read_cr(nor, &sr_cr[1]); 762 if (ret) 763 return ret; 764 } else if (nor->params->quad_enable) { 765 /* 766 * If the Status Register 2 Read command (35h) is not 767 * supported, we should at least be sure we don't 768 * change the value of the SR2 Quad Enable bit. 769 * 770 * We can safely assume that when the Quad Enable method is 771 * set, the value of the QE bit is one, as a consequence of the 772 * nor->params->quad_enable() call. 773 * 774 * We can safely assume that the Quad Enable bit is present in 775 * the Status Register 2 at BIT(1). According to the JESD216 776 * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit 777 * Write Status (01h) command is available just for the cases 778 * in which the QE bit is described in SR2 at BIT(1). 779 */ 780 sr_cr[1] = SR2_QUAD_EN_BIT1; 781 } else { 782 sr_cr[1] = 0; 783 } 784 785 sr_cr[0] = sr1; 786 787 ret = spi_nor_write_sr(nor, sr_cr, 2); 788 if (ret) 789 return ret; 790 791 if (nor->flags & SNOR_F_NO_READ_CR) 792 return 0; 793 794 cr_written = sr_cr[1]; 795 796 ret = spi_nor_read_cr(nor, &sr_cr[1]); 797 if (ret) 798 return ret; 799 800 if (cr_written != sr_cr[1]) { 801 dev_dbg(nor->dev, "CR: read back test failed\n"); 802 return -EIO; 803 } 804 805 return 0; 806 } 807 808 /** 809 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the 810 * Configuration Register in one shot. Ensure that the byte written in the 811 * Configuration Register match the received value, and that the 16-bit Write 812 * did not affect what was already in the Status Register 1. 813 * @nor: pointer to a 'struct spi_nor'. 814 * @cr: byte value to be written to the Configuration Register. 815 * 816 * Return: 0 on success, -errno otherwise. 817 */ 818 int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr) 819 { 820 int ret; 821 u8 *sr_cr = nor->bouncebuf; 822 u8 sr_written; 823 824 /* Keep the current value of the Status Register 1. */ 825 ret = spi_nor_read_sr(nor, sr_cr); 826 if (ret) 827 return ret; 828 829 sr_cr[1] = cr; 830 831 ret = spi_nor_write_sr(nor, sr_cr, 2); 832 if (ret) 833 return ret; 834 835 sr_written = sr_cr[0]; 836 837 ret = spi_nor_read_sr(nor, sr_cr); 838 if (ret) 839 return ret; 840 841 if (sr_written != sr_cr[0]) { 842 dev_dbg(nor->dev, "SR: Read back test failed\n"); 843 return -EIO; 844 } 845 846 if (nor->flags & SNOR_F_NO_READ_CR) 847 return 0; 848 849 ret = spi_nor_read_cr(nor, &sr_cr[1]); 850 if (ret) 851 return ret; 852 853 if (cr != sr_cr[1]) { 854 dev_dbg(nor->dev, "CR: read back test failed\n"); 855 return -EIO; 856 } 857 858 return 0; 859 } 860 861 /** 862 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that 863 * the byte written match the received value without affecting other bits in the 864 * Status Register 1 and 2. 865 * @nor: pointer to a 'struct spi_nor'. 866 * @sr1: byte value to be written to the Status Register. 867 * 868 * Return: 0 on success, -errno otherwise. 869 */ 870 int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1) 871 { 872 if (nor->flags & SNOR_F_HAS_16BIT_SR) 873 return spi_nor_write_16bit_sr_and_check(nor, sr1); 874 875 return spi_nor_write_sr1_and_check(nor, sr1); 876 } 877 878 /** 879 * spi_nor_write_sr2() - Write the Status Register 2 using the 880 * SPINOR_OP_WRSR2 (3eh) command. 881 * @nor: pointer to 'struct spi_nor'. 882 * @sr2: pointer to DMA-able buffer to write to the Status Register 2. 883 * 884 * Return: 0 on success, -errno otherwise. 885 */ 886 static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2) 887 { 888 int ret; 889 890 ret = spi_nor_write_enable(nor); 891 if (ret) 892 return ret; 893 894 if (nor->spimem) { 895 struct spi_mem_op op = 896 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR2, 0), 897 SPI_MEM_OP_NO_ADDR, 898 SPI_MEM_OP_NO_DUMMY, 899 SPI_MEM_OP_DATA_OUT(1, sr2, 0)); 900 901 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 902 903 ret = spi_mem_exec_op(nor->spimem, &op); 904 } else { 905 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2, 906 sr2, 1); 907 } 908 909 if (ret) { 910 dev_dbg(nor->dev, "error %d writing SR2\n", ret); 911 return ret; 912 } 913 914 return spi_nor_wait_till_ready(nor); 915 } 916 917 /** 918 * spi_nor_read_sr2() - Read the Status Register 2 using the 919 * SPINOR_OP_RDSR2 (3fh) command. 920 * @nor: pointer to 'struct spi_nor'. 921 * @sr2: pointer to DMA-able buffer where the value of the 922 * Status Register 2 will be written. 923 * 924 * Return: 0 on success, -errno otherwise. 925 */ 926 static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) 927 { 928 int ret; 929 930 if (nor->spimem) { 931 struct spi_mem_op op = 932 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2, 0), 933 SPI_MEM_OP_NO_ADDR, 934 SPI_MEM_OP_NO_DUMMY, 935 SPI_MEM_OP_DATA_IN(1, sr2, 0)); 936 937 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 938 939 ret = spi_mem_exec_op(nor->spimem, &op); 940 } else { 941 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2, 942 1); 943 } 944 945 if (ret) 946 dev_dbg(nor->dev, "error %d reading SR2\n", ret); 947 948 return ret; 949 } 950 951 /** 952 * spi_nor_erase_chip() - Erase the entire flash memory. 953 * @nor: pointer to 'struct spi_nor'. 954 * 955 * Return: 0 on success, -errno otherwise. 956 */ 957 static int spi_nor_erase_chip(struct spi_nor *nor) 958 { 959 int ret; 960 961 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); 962 963 if (nor->spimem) { 964 struct spi_mem_op op = 965 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), 966 SPI_MEM_OP_NO_ADDR, 967 SPI_MEM_OP_NO_DUMMY, 968 SPI_MEM_OP_NO_DATA); 969 970 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 971 972 ret = spi_mem_exec_op(nor->spimem, &op); 973 } else { 974 ret = spi_nor_controller_ops_write_reg(nor, 975 SPINOR_OP_CHIP_ERASE, 976 NULL, 0); 977 } 978 979 if (ret) 980 dev_dbg(nor->dev, "error %d erasing chip\n", ret); 981 982 return ret; 983 } 984 985 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 986 { 987 size_t i; 988 989 for (i = 0; i < size; i++) 990 if (table[i][0] == opcode) 991 return table[i][1]; 992 993 /* No conversion found, keep input op code. */ 994 return opcode; 995 } 996 997 u8 spi_nor_convert_3to4_read(u8 opcode) 998 { 999 static const u8 spi_nor_3to4_read[][2] = { 1000 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 1001 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 1002 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 1003 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 1004 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 1005 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 1006 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B }, 1007 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B }, 1008 1009 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 1010 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 1011 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 1012 }; 1013 1014 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 1015 ARRAY_SIZE(spi_nor_3to4_read)); 1016 } 1017 1018 static u8 spi_nor_convert_3to4_program(u8 opcode) 1019 { 1020 static const u8 spi_nor_3to4_program[][2] = { 1021 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 1022 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 1023 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 1024 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B }, 1025 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B }, 1026 }; 1027 1028 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 1029 ARRAY_SIZE(spi_nor_3to4_program)); 1030 } 1031 1032 static u8 spi_nor_convert_3to4_erase(u8 opcode) 1033 { 1034 static const u8 spi_nor_3to4_erase[][2] = { 1035 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 1036 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 1037 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 1038 }; 1039 1040 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 1041 ARRAY_SIZE(spi_nor_3to4_erase)); 1042 } 1043 1044 static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) 1045 { 1046 return !!nor->params->erase_map.uniform_erase_type; 1047 } 1048 1049 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor) 1050 { 1051 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 1052 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 1053 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 1054 1055 if (!spi_nor_has_uniform_erase(nor)) { 1056 struct spi_nor_erase_map *map = &nor->params->erase_map; 1057 struct spi_nor_erase_type *erase; 1058 int i; 1059 1060 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { 1061 erase = &map->erase_type[i]; 1062 erase->opcode = 1063 spi_nor_convert_3to4_erase(erase->opcode); 1064 } 1065 } 1066 } 1067 1068 int spi_nor_lock_and_prep(struct spi_nor *nor) 1069 { 1070 int ret = 0; 1071 1072 mutex_lock(&nor->lock); 1073 1074 if (nor->controller_ops && nor->controller_ops->prepare) { 1075 ret = nor->controller_ops->prepare(nor); 1076 if (ret) { 1077 mutex_unlock(&nor->lock); 1078 return ret; 1079 } 1080 } 1081 return ret; 1082 } 1083 1084 void spi_nor_unlock_and_unprep(struct spi_nor *nor) 1085 { 1086 if (nor->controller_ops && nor->controller_ops->unprepare) 1087 nor->controller_ops->unprepare(nor); 1088 mutex_unlock(&nor->lock); 1089 } 1090 1091 static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr) 1092 { 1093 if (!nor->params->convert_addr) 1094 return addr; 1095 1096 return nor->params->convert_addr(nor, addr); 1097 } 1098 1099 /* 1100 * Initiate the erasure of a single sector 1101 */ 1102 int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 1103 { 1104 int i; 1105 1106 addr = spi_nor_convert_addr(nor, addr); 1107 1108 if (nor->spimem) { 1109 struct spi_mem_op op = 1110 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0), 1111 SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), 1112 SPI_MEM_OP_NO_DUMMY, 1113 SPI_MEM_OP_NO_DATA); 1114 1115 spi_nor_spimem_setup_op(nor, &op, nor->write_proto); 1116 1117 return spi_mem_exec_op(nor->spimem, &op); 1118 } else if (nor->controller_ops->erase) { 1119 return spi_nor_controller_ops_erase(nor, addr); 1120 } 1121 1122 /* 1123 * Default implementation, if driver doesn't have a specialized HW 1124 * control 1125 */ 1126 for (i = nor->addr_width - 1; i >= 0; i--) { 1127 nor->bouncebuf[i] = addr & 0xff; 1128 addr >>= 8; 1129 } 1130 1131 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode, 1132 nor->bouncebuf, nor->addr_width); 1133 } 1134 1135 /** 1136 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend 1137 * @erase: pointer to a structure that describes a SPI NOR erase type 1138 * @dividend: dividend value 1139 * @remainder: pointer to u32 remainder (will be updated) 1140 * 1141 * Return: the result of the division 1142 */ 1143 static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase, 1144 u64 dividend, u32 *remainder) 1145 { 1146 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 1147 *remainder = (u32)dividend & erase->size_mask; 1148 return dividend >> erase->size_shift; 1149 } 1150 1151 /** 1152 * spi_nor_find_best_erase_type() - find the best erase type for the given 1153 * offset in the serial flash memory and the 1154 * number of bytes to erase. The region in 1155 * which the address fits is expected to be 1156 * provided. 1157 * @map: the erase map of the SPI NOR 1158 * @region: pointer to a structure that describes a SPI NOR erase region 1159 * @addr: offset in the serial flash memory 1160 * @len: number of bytes to erase 1161 * 1162 * Return: a pointer to the best fitted erase type, NULL otherwise. 1163 */ 1164 static const struct spi_nor_erase_type * 1165 spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map, 1166 const struct spi_nor_erase_region *region, 1167 u64 addr, u32 len) 1168 { 1169 const struct spi_nor_erase_type *erase; 1170 u32 rem; 1171 int i; 1172 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK; 1173 1174 /* 1175 * Erase types are ordered by size, with the smallest erase type at 1176 * index 0. 1177 */ 1178 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 1179 /* Does the erase region support the tested erase type? */ 1180 if (!(erase_mask & BIT(i))) 1181 continue; 1182 1183 erase = &map->erase_type[i]; 1184 1185 /* Alignment is not mandatory for overlaid regions */ 1186 if (region->offset & SNOR_OVERLAID_REGION && 1187 region->size <= len) 1188 return erase; 1189 1190 /* Don't erase more than what the user has asked for. */ 1191 if (erase->size > len) 1192 continue; 1193 1194 spi_nor_div_by_erase_size(erase, addr, &rem); 1195 if (!rem) 1196 return erase; 1197 } 1198 1199 return NULL; 1200 } 1201 1202 static u64 spi_nor_region_is_last(const struct spi_nor_erase_region *region) 1203 { 1204 return region->offset & SNOR_LAST_REGION; 1205 } 1206 1207 static u64 spi_nor_region_end(const struct spi_nor_erase_region *region) 1208 { 1209 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size; 1210 } 1211 1212 /** 1213 * spi_nor_region_next() - get the next spi nor region 1214 * @region: pointer to a structure that describes a SPI NOR erase region 1215 * 1216 * Return: the next spi nor region or NULL if last region. 1217 */ 1218 struct spi_nor_erase_region * 1219 spi_nor_region_next(struct spi_nor_erase_region *region) 1220 { 1221 if (spi_nor_region_is_last(region)) 1222 return NULL; 1223 region++; 1224 return region; 1225 } 1226 1227 /** 1228 * spi_nor_find_erase_region() - find the region of the serial flash memory in 1229 * which the offset fits 1230 * @map: the erase map of the SPI NOR 1231 * @addr: offset in the serial flash memory 1232 * 1233 * Return: a pointer to the spi_nor_erase_region struct, ERR_PTR(-errno) 1234 * otherwise. 1235 */ 1236 static struct spi_nor_erase_region * 1237 spi_nor_find_erase_region(const struct spi_nor_erase_map *map, u64 addr) 1238 { 1239 struct spi_nor_erase_region *region = map->regions; 1240 u64 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1241 u64 region_end = region_start + region->size; 1242 1243 while (addr < region_start || addr >= region_end) { 1244 region = spi_nor_region_next(region); 1245 if (!region) 1246 return ERR_PTR(-EINVAL); 1247 1248 region_start = region->offset & ~SNOR_ERASE_FLAGS_MASK; 1249 region_end = region_start + region->size; 1250 } 1251 1252 return region; 1253 } 1254 1255 /** 1256 * spi_nor_init_erase_cmd() - initialize an erase command 1257 * @region: pointer to a structure that describes a SPI NOR erase region 1258 * @erase: pointer to a structure that describes a SPI NOR erase type 1259 * 1260 * Return: the pointer to the allocated erase command, ERR_PTR(-errno) 1261 * otherwise. 1262 */ 1263 static struct spi_nor_erase_command * 1264 spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region, 1265 const struct spi_nor_erase_type *erase) 1266 { 1267 struct spi_nor_erase_command *cmd; 1268 1269 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL); 1270 if (!cmd) 1271 return ERR_PTR(-ENOMEM); 1272 1273 INIT_LIST_HEAD(&cmd->list); 1274 cmd->opcode = erase->opcode; 1275 cmd->count = 1; 1276 1277 if (region->offset & SNOR_OVERLAID_REGION) 1278 cmd->size = region->size; 1279 else 1280 cmd->size = erase->size; 1281 1282 return cmd; 1283 } 1284 1285 /** 1286 * spi_nor_destroy_erase_cmd_list() - destroy erase command list 1287 * @erase_list: list of erase commands 1288 */ 1289 static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list) 1290 { 1291 struct spi_nor_erase_command *cmd, *next; 1292 1293 list_for_each_entry_safe(cmd, next, erase_list, list) { 1294 list_del(&cmd->list); 1295 kfree(cmd); 1296 } 1297 } 1298 1299 /** 1300 * spi_nor_init_erase_cmd_list() - initialize erase command list 1301 * @nor: pointer to a 'struct spi_nor' 1302 * @erase_list: list of erase commands to be executed once we validate that the 1303 * erase can be performed 1304 * @addr: offset in the serial flash memory 1305 * @len: number of bytes to erase 1306 * 1307 * Builds the list of best fitted erase commands and verifies if the erase can 1308 * be performed. 1309 * 1310 * Return: 0 on success, -errno otherwise. 1311 */ 1312 static int spi_nor_init_erase_cmd_list(struct spi_nor *nor, 1313 struct list_head *erase_list, 1314 u64 addr, u32 len) 1315 { 1316 const struct spi_nor_erase_map *map = &nor->params->erase_map; 1317 const struct spi_nor_erase_type *erase, *prev_erase = NULL; 1318 struct spi_nor_erase_region *region; 1319 struct spi_nor_erase_command *cmd = NULL; 1320 u64 region_end; 1321 int ret = -EINVAL; 1322 1323 region = spi_nor_find_erase_region(map, addr); 1324 if (IS_ERR(region)) 1325 return PTR_ERR(region); 1326 1327 region_end = spi_nor_region_end(region); 1328 1329 while (len) { 1330 erase = spi_nor_find_best_erase_type(map, region, addr, len); 1331 if (!erase) 1332 goto destroy_erase_cmd_list; 1333 1334 if (prev_erase != erase || 1335 erase->size != cmd->size || 1336 region->offset & SNOR_OVERLAID_REGION) { 1337 cmd = spi_nor_init_erase_cmd(region, erase); 1338 if (IS_ERR(cmd)) { 1339 ret = PTR_ERR(cmd); 1340 goto destroy_erase_cmd_list; 1341 } 1342 1343 list_add_tail(&cmd->list, erase_list); 1344 } else { 1345 cmd->count++; 1346 } 1347 1348 addr += cmd->size; 1349 len -= cmd->size; 1350 1351 if (len && addr >= region_end) { 1352 region = spi_nor_region_next(region); 1353 if (!region) 1354 goto destroy_erase_cmd_list; 1355 region_end = spi_nor_region_end(region); 1356 } 1357 1358 prev_erase = erase; 1359 } 1360 1361 return 0; 1362 1363 destroy_erase_cmd_list: 1364 spi_nor_destroy_erase_cmd_list(erase_list); 1365 return ret; 1366 } 1367 1368 /** 1369 * spi_nor_erase_multi_sectors() - perform a non-uniform erase 1370 * @nor: pointer to a 'struct spi_nor' 1371 * @addr: offset in the serial flash memory 1372 * @len: number of bytes to erase 1373 * 1374 * Build a list of best fitted erase commands and execute it once we validate 1375 * that the erase can be performed. 1376 * 1377 * Return: 0 on success, -errno otherwise. 1378 */ 1379 static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) 1380 { 1381 LIST_HEAD(erase_list); 1382 struct spi_nor_erase_command *cmd, *next; 1383 int ret; 1384 1385 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len); 1386 if (ret) 1387 return ret; 1388 1389 list_for_each_entry_safe(cmd, next, &erase_list, list) { 1390 nor->erase_opcode = cmd->opcode; 1391 while (cmd->count) { 1392 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n", 1393 cmd->size, cmd->opcode, cmd->count); 1394 1395 ret = spi_nor_write_enable(nor); 1396 if (ret) 1397 goto destroy_erase_cmd_list; 1398 1399 ret = spi_nor_erase_sector(nor, addr); 1400 if (ret) 1401 goto destroy_erase_cmd_list; 1402 1403 ret = spi_nor_wait_till_ready(nor); 1404 if (ret) 1405 goto destroy_erase_cmd_list; 1406 1407 addr += cmd->size; 1408 cmd->count--; 1409 } 1410 list_del(&cmd->list); 1411 kfree(cmd); 1412 } 1413 1414 return 0; 1415 1416 destroy_erase_cmd_list: 1417 spi_nor_destroy_erase_cmd_list(&erase_list); 1418 return ret; 1419 } 1420 1421 /* 1422 * Erase an address range on the nor chip. The address range may extend 1423 * one or more erase sectors. Return an error if there is a problem erasing. 1424 */ 1425 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 1426 { 1427 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1428 u32 addr, len; 1429 uint32_t rem; 1430 int ret; 1431 1432 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 1433 (long long)instr->len); 1434 1435 if (spi_nor_has_uniform_erase(nor)) { 1436 div_u64_rem(instr->len, mtd->erasesize, &rem); 1437 if (rem) 1438 return -EINVAL; 1439 } 1440 1441 addr = instr->addr; 1442 len = instr->len; 1443 1444 ret = spi_nor_lock_and_prep(nor); 1445 if (ret) 1446 return ret; 1447 1448 /* whole-chip erase? */ 1449 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { 1450 unsigned long timeout; 1451 1452 ret = spi_nor_write_enable(nor); 1453 if (ret) 1454 goto erase_err; 1455 1456 ret = spi_nor_erase_chip(nor); 1457 if (ret) 1458 goto erase_err; 1459 1460 /* 1461 * Scale the timeout linearly with the size of the flash, with 1462 * a minimum calibrated to an old 2MB flash. We could try to 1463 * pull these from CFI/SFDP, but these values should be good 1464 * enough for now. 1465 */ 1466 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, 1467 CHIP_ERASE_2MB_READY_WAIT_JIFFIES * 1468 (unsigned long)(mtd->size / SZ_2M)); 1469 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); 1470 if (ret) 1471 goto erase_err; 1472 1473 /* REVISIT in some cases we could speed up erasing large regions 1474 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up 1475 * to use "small sector erase", but that's not always optimal. 1476 */ 1477 1478 /* "sector"-at-a-time erase */ 1479 } else if (spi_nor_has_uniform_erase(nor)) { 1480 while (len) { 1481 ret = spi_nor_write_enable(nor); 1482 if (ret) 1483 goto erase_err; 1484 1485 ret = spi_nor_erase_sector(nor, addr); 1486 if (ret) 1487 goto erase_err; 1488 1489 ret = spi_nor_wait_till_ready(nor); 1490 if (ret) 1491 goto erase_err; 1492 1493 addr += mtd->erasesize; 1494 len -= mtd->erasesize; 1495 } 1496 1497 /* erase multiple sectors */ 1498 } else { 1499 ret = spi_nor_erase_multi_sectors(nor, addr, len); 1500 if (ret) 1501 goto erase_err; 1502 } 1503 1504 ret = spi_nor_write_disable(nor); 1505 1506 erase_err: 1507 spi_nor_unlock_and_unprep(nor); 1508 1509 return ret; 1510 } 1511 1512 /** 1513 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status 1514 * Register 1. 1515 * @nor: pointer to a 'struct spi_nor' 1516 * 1517 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. 1518 * 1519 * Return: 0 on success, -errno otherwise. 1520 */ 1521 int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) 1522 { 1523 int ret; 1524 1525 ret = spi_nor_read_sr(nor, nor->bouncebuf); 1526 if (ret) 1527 return ret; 1528 1529 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) 1530 return 0; 1531 1532 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; 1533 1534 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); 1535 } 1536 1537 /** 1538 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status 1539 * Register 2. 1540 * @nor: pointer to a 'struct spi_nor'. 1541 * 1542 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. 1543 * 1544 * Return: 0 on success, -errno otherwise. 1545 */ 1546 int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) 1547 { 1548 int ret; 1549 1550 if (nor->flags & SNOR_F_NO_READ_CR) 1551 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1); 1552 1553 ret = spi_nor_read_cr(nor, nor->bouncebuf); 1554 if (ret) 1555 return ret; 1556 1557 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1) 1558 return 0; 1559 1560 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1; 1561 1562 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]); 1563 } 1564 1565 /** 1566 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2. 1567 * @nor: pointer to a 'struct spi_nor' 1568 * 1569 * Set the Quad Enable (QE) bit in the Status Register 2. 1570 * 1571 * This is one of the procedures to set the QE bit described in the SFDP 1572 * (JESD216 rev B) specification but no manufacturer using this procedure has 1573 * been identified yet, hence the name of the function. 1574 * 1575 * Return: 0 on success, -errno otherwise. 1576 */ 1577 int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 1578 { 1579 u8 *sr2 = nor->bouncebuf; 1580 int ret; 1581 u8 sr2_written; 1582 1583 /* Check current Quad Enable bit value. */ 1584 ret = spi_nor_read_sr2(nor, sr2); 1585 if (ret) 1586 return ret; 1587 if (*sr2 & SR2_QUAD_EN_BIT7) 1588 return 0; 1589 1590 /* Update the Quad Enable bit. */ 1591 *sr2 |= SR2_QUAD_EN_BIT7; 1592 1593 ret = spi_nor_write_sr2(nor, sr2); 1594 if (ret) 1595 return ret; 1596 1597 sr2_written = *sr2; 1598 1599 /* Read back and check it. */ 1600 ret = spi_nor_read_sr2(nor, sr2); 1601 if (ret) 1602 return ret; 1603 1604 if (*sr2 != sr2_written) { 1605 dev_dbg(nor->dev, "SR2: Read back test failed\n"); 1606 return -EIO; 1607 } 1608 1609 return 0; 1610 } 1611 1612 static const struct spi_nor_manufacturer *manufacturers[] = { 1613 &spi_nor_atmel, 1614 &spi_nor_catalyst, 1615 &spi_nor_eon, 1616 &spi_nor_esmt, 1617 &spi_nor_everspin, 1618 &spi_nor_fujitsu, 1619 &spi_nor_gigadevice, 1620 &spi_nor_intel, 1621 &spi_nor_issi, 1622 &spi_nor_macronix, 1623 &spi_nor_micron, 1624 &spi_nor_st, 1625 &spi_nor_spansion, 1626 &spi_nor_sst, 1627 &spi_nor_winbond, 1628 &spi_nor_xilinx, 1629 &spi_nor_xmc, 1630 }; 1631 1632 static const struct flash_info * 1633 spi_nor_search_part_by_id(const struct flash_info *parts, unsigned int nparts, 1634 const u8 *id) 1635 { 1636 unsigned int i; 1637 1638 for (i = 0; i < nparts; i++) { 1639 if (parts[i].id_len && 1640 !memcmp(parts[i].id, id, parts[i].id_len)) 1641 return &parts[i]; 1642 } 1643 1644 return NULL; 1645 } 1646 1647 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 1648 { 1649 const struct flash_info *info; 1650 u8 *id = nor->bouncebuf; 1651 unsigned int i; 1652 int ret; 1653 1654 if (nor->spimem) { 1655 struct spi_mem_op op = 1656 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), 1657 SPI_MEM_OP_NO_ADDR, 1658 SPI_MEM_OP_NO_DUMMY, 1659 SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, id, 1)); 1660 1661 ret = spi_mem_exec_op(nor->spimem, &op); 1662 } else { 1663 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id, 1664 SPI_NOR_MAX_ID_LEN); 1665 } 1666 if (ret) { 1667 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret); 1668 return ERR_PTR(ret); 1669 } 1670 1671 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 1672 info = spi_nor_search_part_by_id(manufacturers[i]->parts, 1673 manufacturers[i]->nparts, 1674 id); 1675 if (info) { 1676 nor->manufacturer = manufacturers[i]; 1677 return info; 1678 } 1679 } 1680 1681 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n", 1682 SPI_NOR_MAX_ID_LEN, id); 1683 return ERR_PTR(-ENODEV); 1684 } 1685 1686 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 1687 size_t *retlen, u_char *buf) 1688 { 1689 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1690 ssize_t ret; 1691 1692 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 1693 1694 ret = spi_nor_lock_and_prep(nor); 1695 if (ret) 1696 return ret; 1697 1698 while (len) { 1699 loff_t addr = from; 1700 1701 addr = spi_nor_convert_addr(nor, addr); 1702 1703 ret = spi_nor_read_data(nor, addr, len, buf); 1704 if (ret == 0) { 1705 /* We shouldn't see 0-length reads */ 1706 ret = -EIO; 1707 goto read_err; 1708 } 1709 if (ret < 0) 1710 goto read_err; 1711 1712 WARN_ON(ret > len); 1713 *retlen += ret; 1714 buf += ret; 1715 from += ret; 1716 len -= ret; 1717 } 1718 ret = 0; 1719 1720 read_err: 1721 spi_nor_unlock_and_unprep(nor); 1722 return ret; 1723 } 1724 1725 /* 1726 * Write an address range to the nor chip. Data must be written in 1727 * FLASH_PAGESIZE chunks. The address range may be any size provided 1728 * it is within the physical boundaries. 1729 */ 1730 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1731 size_t *retlen, const u_char *buf) 1732 { 1733 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1734 size_t page_offset, page_remain, i; 1735 ssize_t ret; 1736 u32 page_size = nor->params->page_size; 1737 1738 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1739 1740 ret = spi_nor_lock_and_prep(nor); 1741 if (ret) 1742 return ret; 1743 1744 for (i = 0; i < len; ) { 1745 ssize_t written; 1746 loff_t addr = to + i; 1747 1748 /* 1749 * If page_size is a power of two, the offset can be quickly 1750 * calculated with an AND operation. On the other cases we 1751 * need to do a modulus operation (more expensive). 1752 */ 1753 if (is_power_of_2(page_size)) { 1754 page_offset = addr & (page_size - 1); 1755 } else { 1756 uint64_t aux = addr; 1757 1758 page_offset = do_div(aux, page_size); 1759 } 1760 /* the size of data remaining on the first page */ 1761 page_remain = min_t(size_t, page_size - page_offset, len - i); 1762 1763 addr = spi_nor_convert_addr(nor, addr); 1764 1765 ret = spi_nor_write_enable(nor); 1766 if (ret) 1767 goto write_err; 1768 1769 ret = spi_nor_write_data(nor, addr, page_remain, buf + i); 1770 if (ret < 0) 1771 goto write_err; 1772 written = ret; 1773 1774 ret = spi_nor_wait_till_ready(nor); 1775 if (ret) 1776 goto write_err; 1777 *retlen += written; 1778 i += written; 1779 } 1780 1781 write_err: 1782 spi_nor_unlock_and_unprep(nor); 1783 return ret; 1784 } 1785 1786 static int spi_nor_check(struct spi_nor *nor) 1787 { 1788 if (!nor->dev || 1789 (!nor->spimem && !nor->controller_ops) || 1790 (!nor->spimem && nor->controller_ops && 1791 (!nor->controller_ops->read || 1792 !nor->controller_ops->write || 1793 !nor->controller_ops->read_reg || 1794 !nor->controller_ops->write_reg))) { 1795 pr_err("spi-nor: please fill all the necessary fields!\n"); 1796 return -EINVAL; 1797 } 1798 1799 if (nor->spimem && nor->controller_ops) { 1800 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n"); 1801 return -EINVAL; 1802 } 1803 1804 return 0; 1805 } 1806 1807 void 1808 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1809 u8 num_mode_clocks, 1810 u8 num_wait_states, 1811 u8 opcode, 1812 enum spi_nor_protocol proto) 1813 { 1814 read->num_mode_clocks = num_mode_clocks; 1815 read->num_wait_states = num_wait_states; 1816 read->opcode = opcode; 1817 read->proto = proto; 1818 } 1819 1820 void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode, 1821 enum spi_nor_protocol proto) 1822 { 1823 pp->opcode = opcode; 1824 pp->proto = proto; 1825 } 1826 1827 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 1828 { 1829 size_t i; 1830 1831 for (i = 0; i < size; i++) 1832 if (table[i][0] == (int)hwcaps) 1833 return table[i][1]; 1834 1835 return -EINVAL; 1836 } 1837 1838 int spi_nor_hwcaps_read2cmd(u32 hwcaps) 1839 { 1840 static const int hwcaps_read2cmd[][2] = { 1841 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 1842 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 1843 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 1844 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 1845 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 1846 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 1847 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 1848 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 1849 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 1850 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 1851 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 1852 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 1853 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 1854 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 1855 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 1856 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, 1857 }; 1858 1859 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 1860 ARRAY_SIZE(hwcaps_read2cmd)); 1861 } 1862 1863 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 1864 { 1865 static const int hwcaps_pp2cmd[][2] = { 1866 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 1867 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 1868 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 1869 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 1870 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 1871 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 1872 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 1873 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, 1874 }; 1875 1876 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 1877 ARRAY_SIZE(hwcaps_pp2cmd)); 1878 } 1879 1880 /** 1881 * spi_nor_spimem_check_op - check if the operation is supported 1882 * by controller 1883 *@nor: pointer to a 'struct spi_nor' 1884 *@op: pointer to op template to be checked 1885 * 1886 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 1887 */ 1888 static int spi_nor_spimem_check_op(struct spi_nor *nor, 1889 struct spi_mem_op *op) 1890 { 1891 /* 1892 * First test with 4 address bytes. The opcode itself might 1893 * be a 3B addressing opcode but we don't care, because 1894 * SPI controller implementation should not check the opcode, 1895 * but just the sequence. 1896 */ 1897 op->addr.nbytes = 4; 1898 if (!spi_mem_supports_op(nor->spimem, op)) { 1899 if (nor->params->size > SZ_16M) 1900 return -EOPNOTSUPP; 1901 1902 /* If flash size <= 16MB, 3 address bytes are sufficient */ 1903 op->addr.nbytes = 3; 1904 if (!spi_mem_supports_op(nor->spimem, op)) 1905 return -EOPNOTSUPP; 1906 } 1907 1908 return 0; 1909 } 1910 1911 /** 1912 * spi_nor_spimem_check_readop - check if the read op is supported 1913 * by controller 1914 *@nor: pointer to a 'struct spi_nor' 1915 *@read: pointer to op template to be checked 1916 * 1917 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 1918 */ 1919 static int spi_nor_spimem_check_readop(struct spi_nor *nor, 1920 const struct spi_nor_read_command *read) 1921 { 1922 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0), 1923 SPI_MEM_OP_ADDR(3, 0, 0), 1924 SPI_MEM_OP_DUMMY(1, 0), 1925 SPI_MEM_OP_DATA_IN(2, NULL, 0)); 1926 1927 spi_nor_spimem_setup_op(nor, &op, read->proto); 1928 1929 /* convert the dummy cycles to the number of bytes */ 1930 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 1931 if (spi_nor_protocol_is_dtr(nor->read_proto)) 1932 op.dummy.nbytes *= 2; 1933 1934 return spi_nor_spimem_check_op(nor, &op); 1935 } 1936 1937 /** 1938 * spi_nor_spimem_check_pp - check if the page program op is supported 1939 * by controller 1940 *@nor: pointer to a 'struct spi_nor' 1941 *@pp: pointer to op template to be checked 1942 * 1943 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise. 1944 */ 1945 static int spi_nor_spimem_check_pp(struct spi_nor *nor, 1946 const struct spi_nor_pp_command *pp) 1947 { 1948 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0), 1949 SPI_MEM_OP_ADDR(3, 0, 0), 1950 SPI_MEM_OP_NO_DUMMY, 1951 SPI_MEM_OP_DATA_OUT(2, NULL, 0)); 1952 1953 spi_nor_spimem_setup_op(nor, &op, pp->proto); 1954 1955 return spi_nor_spimem_check_op(nor, &op); 1956 } 1957 1958 /** 1959 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol 1960 * based on SPI controller capabilities 1961 * @nor: pointer to a 'struct spi_nor' 1962 * @hwcaps: pointer to resulting capabilities after adjusting 1963 * according to controller and flash's capability 1964 */ 1965 static void 1966 spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) 1967 { 1968 struct spi_nor_flash_parameter *params = nor->params; 1969 unsigned int cap; 1970 1971 /* X-X-X modes are not supported yet, mask them all. */ 1972 *hwcaps &= ~SNOR_HWCAPS_X_X_X; 1973 1974 /* 1975 * If the reset line is broken, we do not want to enter a stateful 1976 * mode. 1977 */ 1978 if (nor->flags & SNOR_F_BROKEN_RESET) 1979 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR); 1980 1981 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) { 1982 int rdidx, ppidx; 1983 1984 if (!(*hwcaps & BIT(cap))) 1985 continue; 1986 1987 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap)); 1988 if (rdidx >= 0 && 1989 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx])) 1990 *hwcaps &= ~BIT(cap); 1991 1992 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap)); 1993 if (ppidx < 0) 1994 continue; 1995 1996 if (spi_nor_spimem_check_pp(nor, 1997 ¶ms->page_programs[ppidx])) 1998 *hwcaps &= ~BIT(cap); 1999 } 2000 } 2001 2002 /** 2003 * spi_nor_set_erase_type() - set a SPI NOR erase type 2004 * @erase: pointer to a structure that describes a SPI NOR erase type 2005 * @size: the size of the sector/block erased by the erase type 2006 * @opcode: the SPI command op code to erase the sector/block 2007 */ 2008 void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size, 2009 u8 opcode) 2010 { 2011 erase->size = size; 2012 erase->opcode = opcode; 2013 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */ 2014 erase->size_shift = ffs(erase->size) - 1; 2015 erase->size_mask = (1 << erase->size_shift) - 1; 2016 } 2017 2018 /** 2019 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map 2020 * @map: the erase map of the SPI NOR 2021 * @erase_mask: bitmask encoding erase types that can erase the entire 2022 * flash memory 2023 * @flash_size: the spi nor flash memory size 2024 */ 2025 void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map, 2026 u8 erase_mask, u64 flash_size) 2027 { 2028 /* Offset 0 with erase_mask and SNOR_LAST_REGION bit set */ 2029 map->uniform_region.offset = (erase_mask & SNOR_ERASE_TYPE_MASK) | 2030 SNOR_LAST_REGION; 2031 map->uniform_region.size = flash_size; 2032 map->regions = &map->uniform_region; 2033 map->uniform_erase_type = erase_mask; 2034 } 2035 2036 int spi_nor_post_bfpt_fixups(struct spi_nor *nor, 2037 const struct sfdp_parameter_header *bfpt_header, 2038 const struct sfdp_bfpt *bfpt) 2039 { 2040 int ret; 2041 2042 if (nor->manufacturer && nor->manufacturer->fixups && 2043 nor->manufacturer->fixups->post_bfpt) { 2044 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header, 2045 bfpt); 2046 if (ret) 2047 return ret; 2048 } 2049 2050 if (nor->info->fixups && nor->info->fixups->post_bfpt) 2051 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt); 2052 2053 return 0; 2054 } 2055 2056 static int spi_nor_select_read(struct spi_nor *nor, 2057 u32 shared_hwcaps) 2058 { 2059 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2060 const struct spi_nor_read_command *read; 2061 2062 if (best_match < 0) 2063 return -EINVAL; 2064 2065 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2066 if (cmd < 0) 2067 return -EINVAL; 2068 2069 read = &nor->params->reads[cmd]; 2070 nor->read_opcode = read->opcode; 2071 nor->read_proto = read->proto; 2072 2073 /* 2074 * In the SPI NOR framework, we don't need to make the difference 2075 * between mode clock cycles and wait state clock cycles. 2076 * Indeed, the value of the mode clock cycles is used by a QSPI 2077 * flash memory to know whether it should enter or leave its 0-4-4 2078 * (Continuous Read / XIP) mode. 2079 * eXecution In Place is out of the scope of the mtd sub-system. 2080 * Hence we choose to merge both mode and wait state clock cycles 2081 * into the so called dummy clock cycles. 2082 */ 2083 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2084 return 0; 2085 } 2086 2087 static int spi_nor_select_pp(struct spi_nor *nor, 2088 u32 shared_hwcaps) 2089 { 2090 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2091 const struct spi_nor_pp_command *pp; 2092 2093 if (best_match < 0) 2094 return -EINVAL; 2095 2096 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2097 if (cmd < 0) 2098 return -EINVAL; 2099 2100 pp = &nor->params->page_programs[cmd]; 2101 nor->program_opcode = pp->opcode; 2102 nor->write_proto = pp->proto; 2103 return 0; 2104 } 2105 2106 /** 2107 * spi_nor_select_uniform_erase() - select optimum uniform erase type 2108 * @map: the erase map of the SPI NOR 2109 * @wanted_size: the erase type size to search for. Contains the value of 2110 * info->sector_size or of the "small sector" size in case 2111 * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined. 2112 * 2113 * Once the optimum uniform sector erase command is found, disable all the 2114 * other. 2115 * 2116 * Return: pointer to erase type on success, NULL otherwise. 2117 */ 2118 static const struct spi_nor_erase_type * 2119 spi_nor_select_uniform_erase(struct spi_nor_erase_map *map, 2120 const u32 wanted_size) 2121 { 2122 const struct spi_nor_erase_type *tested_erase, *erase = NULL; 2123 int i; 2124 u8 uniform_erase_type = map->uniform_erase_type; 2125 2126 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2127 if (!(uniform_erase_type & BIT(i))) 2128 continue; 2129 2130 tested_erase = &map->erase_type[i]; 2131 2132 /* 2133 * If the current erase size is the one, stop here: 2134 * we have found the right uniform Sector Erase command. 2135 */ 2136 if (tested_erase->size == wanted_size) { 2137 erase = tested_erase; 2138 break; 2139 } 2140 2141 /* 2142 * Otherwise, the current erase size is still a valid candidate. 2143 * Select the biggest valid candidate. 2144 */ 2145 if (!erase && tested_erase->size) 2146 erase = tested_erase; 2147 /* keep iterating to find the wanted_size */ 2148 } 2149 2150 if (!erase) 2151 return NULL; 2152 2153 /* Disable all other Sector Erase commands. */ 2154 map->uniform_erase_type &= ~SNOR_ERASE_TYPE_MASK; 2155 map->uniform_erase_type |= BIT(erase - map->erase_type); 2156 return erase; 2157 } 2158 2159 static int spi_nor_select_erase(struct spi_nor *nor) 2160 { 2161 struct spi_nor_erase_map *map = &nor->params->erase_map; 2162 const struct spi_nor_erase_type *erase = NULL; 2163 struct mtd_info *mtd = &nor->mtd; 2164 u32 wanted_size = nor->info->sector_size; 2165 int i; 2166 2167 /* 2168 * The previous implementation handling Sector Erase commands assumed 2169 * that the SPI flash memory has an uniform layout then used only one 2170 * of the supported erase sizes for all Sector Erase commands. 2171 * So to be backward compatible, the new implementation also tries to 2172 * manage the SPI flash memory as uniform with a single erase sector 2173 * size, when possible. 2174 */ 2175 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 2176 /* prefer "small sector" erase if possible */ 2177 wanted_size = 4096u; 2178 #endif 2179 2180 if (spi_nor_has_uniform_erase(nor)) { 2181 erase = spi_nor_select_uniform_erase(map, wanted_size); 2182 if (!erase) 2183 return -EINVAL; 2184 nor->erase_opcode = erase->opcode; 2185 mtd->erasesize = erase->size; 2186 return 0; 2187 } 2188 2189 /* 2190 * For non-uniform SPI flash memory, set mtd->erasesize to the 2191 * maximum erase sector size. No need to set nor->erase_opcode. 2192 */ 2193 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { 2194 if (map->erase_type[i].size) { 2195 erase = &map->erase_type[i]; 2196 break; 2197 } 2198 } 2199 2200 if (!erase) 2201 return -EINVAL; 2202 2203 mtd->erasesize = erase->size; 2204 return 0; 2205 } 2206 2207 static int spi_nor_default_setup(struct spi_nor *nor, 2208 const struct spi_nor_hwcaps *hwcaps) 2209 { 2210 struct spi_nor_flash_parameter *params = nor->params; 2211 u32 ignored_mask, shared_mask; 2212 int err; 2213 2214 /* 2215 * Keep only the hardware capabilities supported by both the SPI 2216 * controller and the SPI flash memory. 2217 */ 2218 shared_mask = hwcaps->mask & params->hwcaps.mask; 2219 2220 if (nor->spimem) { 2221 /* 2222 * When called from spi_nor_probe(), all caps are set and we 2223 * need to discard some of them based on what the SPI 2224 * controller actually supports (using spi_mem_supports_op()). 2225 */ 2226 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask); 2227 } else { 2228 /* 2229 * SPI n-n-n protocols are not supported when the SPI 2230 * controller directly implements the spi_nor interface. 2231 * Yet another reason to switch to spi-mem. 2232 */ 2233 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR; 2234 if (shared_mask & ignored_mask) { 2235 dev_dbg(nor->dev, 2236 "SPI n-n-n protocols are not supported.\n"); 2237 shared_mask &= ~ignored_mask; 2238 } 2239 } 2240 2241 /* Select the (Fast) Read command. */ 2242 err = spi_nor_select_read(nor, shared_mask); 2243 if (err) { 2244 dev_dbg(nor->dev, 2245 "can't select read settings supported by both the SPI controller and memory.\n"); 2246 return err; 2247 } 2248 2249 /* Select the Page Program command. */ 2250 err = spi_nor_select_pp(nor, shared_mask); 2251 if (err) { 2252 dev_dbg(nor->dev, 2253 "can't select write settings supported by both the SPI controller and memory.\n"); 2254 return err; 2255 } 2256 2257 /* Select the Sector Erase command. */ 2258 err = spi_nor_select_erase(nor); 2259 if (err) { 2260 dev_dbg(nor->dev, 2261 "can't select erase settings supported by both the SPI controller and memory.\n"); 2262 return err; 2263 } 2264 2265 return 0; 2266 } 2267 2268 static int spi_nor_set_addr_width(struct spi_nor *nor) 2269 { 2270 if (nor->addr_width) { 2271 /* already configured from SFDP */ 2272 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { 2273 /* 2274 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So 2275 * in this protocol an odd address width cannot be used because 2276 * then the address phase would only span a cycle and a half. 2277 * Half a cycle would be left over. We would then have to start 2278 * the dummy phase in the middle of a cycle and so too the data 2279 * phase, and we will end the transaction with half a cycle left 2280 * over. 2281 * 2282 * Force all 8D-8D-8D flashes to use an address width of 4 to 2283 * avoid this situation. 2284 */ 2285 nor->addr_width = 4; 2286 } else if (nor->info->addr_width) { 2287 nor->addr_width = nor->info->addr_width; 2288 } else { 2289 nor->addr_width = 3; 2290 } 2291 2292 if (nor->addr_width == 3 && nor->params->size > 0x1000000) { 2293 /* enable 4-byte addressing if the device exceeds 16MiB */ 2294 nor->addr_width = 4; 2295 } 2296 2297 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2298 dev_dbg(nor->dev, "address width is too large: %u\n", 2299 nor->addr_width); 2300 return -EINVAL; 2301 } 2302 2303 /* Set 4byte opcodes when possible. */ 2304 if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES && 2305 !(nor->flags & SNOR_F_HAS_4BAIT)) 2306 spi_nor_set_4byte_opcodes(nor); 2307 2308 return 0; 2309 } 2310 2311 static int spi_nor_setup(struct spi_nor *nor, 2312 const struct spi_nor_hwcaps *hwcaps) 2313 { 2314 int ret; 2315 2316 if (nor->params->setup) 2317 ret = nor->params->setup(nor, hwcaps); 2318 else 2319 ret = spi_nor_default_setup(nor, hwcaps); 2320 if (ret) 2321 return ret; 2322 2323 return spi_nor_set_addr_width(nor); 2324 } 2325 2326 /** 2327 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and 2328 * settings based on MFR register and ->default_init() hook. 2329 * @nor: pointer to a 'struct spi_nor'. 2330 */ 2331 static void spi_nor_manufacturer_init_params(struct spi_nor *nor) 2332 { 2333 if (nor->manufacturer && nor->manufacturer->fixups && 2334 nor->manufacturer->fixups->default_init) 2335 nor->manufacturer->fixups->default_init(nor); 2336 2337 if (nor->info->fixups && nor->info->fixups->default_init) 2338 nor->info->fixups->default_init(nor); 2339 } 2340 2341 /** 2342 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and 2343 * settings based on nor->info->sfdp_flags. This method should be called only by 2344 * flashes that do not define SFDP tables. If the flash supports SFDP but the 2345 * information is wrong and the settings from this function can not be retrieved 2346 * by parsing SFDP, one should instead use the fixup hooks and update the wrong 2347 * bits. 2348 * @nor: pointer to a 'struct spi_nor'. 2349 */ 2350 static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) 2351 { 2352 struct spi_nor_flash_parameter *params = nor->params; 2353 struct spi_nor_erase_map *map = ¶ms->erase_map; 2354 const u8 no_sfdp_flags = nor->info->no_sfdp_flags; 2355 u8 i, erase_mask; 2356 2357 if (no_sfdp_flags & SPI_NOR_DUAL_READ) { 2358 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2359 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 2360 0, 8, SPINOR_OP_READ_1_1_2, 2361 SNOR_PROTO_1_1_2); 2362 } 2363 2364 if (no_sfdp_flags & SPI_NOR_QUAD_READ) { 2365 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2366 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 2367 0, 8, SPINOR_OP_READ_1_1_4, 2368 SNOR_PROTO_1_1_4); 2369 } 2370 2371 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) { 2372 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; 2373 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], 2374 0, 8, SPINOR_OP_READ_1_1_8, 2375 SNOR_PROTO_1_1_8); 2376 } 2377 2378 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) { 2379 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; 2380 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], 2381 0, 20, SPINOR_OP_READ_FAST, 2382 SNOR_PROTO_8_8_8_DTR); 2383 } 2384 2385 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) { 2386 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; 2387 /* 2388 * Since xSPI Page Program opcode is backward compatible with 2389 * Legacy SPI, use Legacy SPI opcode there as well. 2390 */ 2391 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], 2392 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); 2393 } 2394 2395 /* 2396 * Sector Erase settings. Sort Erase Types in ascending order, with the 2397 * smallest erase size starting at BIT(0). 2398 */ 2399 erase_mask = 0; 2400 i = 0; 2401 if (no_sfdp_flags & SECT_4K_PMC) { 2402 erase_mask |= BIT(i); 2403 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2404 SPINOR_OP_BE_4K_PMC); 2405 i++; 2406 } else if (no_sfdp_flags & SECT_4K) { 2407 erase_mask |= BIT(i); 2408 spi_nor_set_erase_type(&map->erase_type[i], 4096u, 2409 SPINOR_OP_BE_4K); 2410 i++; 2411 } 2412 erase_mask |= BIT(i); 2413 spi_nor_set_erase_type(&map->erase_type[i], nor->info->sector_size, 2414 SPINOR_OP_SE); 2415 spi_nor_init_uniform_erase_map(map, erase_mask, params->size); 2416 } 2417 2418 /** 2419 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined 2420 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP. 2421 * @nor: pointer to a 'struct spi_nor' 2422 */ 2423 static void spi_nor_init_flags(struct spi_nor *nor) 2424 { 2425 struct device_node *np = spi_nor_get_flash_node(nor); 2426 const u16 flags = nor->info->flags; 2427 2428 if (of_property_read_bool(np, "broken-flash-reset")) 2429 nor->flags |= SNOR_F_BROKEN_RESET; 2430 2431 if (flags & SPI_NOR_SWP_IS_VOLATILE) 2432 nor->flags |= SNOR_F_SWP_IS_VOLATILE; 2433 2434 if (flags & SPI_NOR_HAS_LOCK) 2435 nor->flags |= SNOR_F_HAS_LOCK; 2436 2437 if (flags & SPI_NOR_HAS_TB) { 2438 nor->flags |= SNOR_F_HAS_SR_TB; 2439 if (flags & SPI_NOR_TB_SR_BIT6) 2440 nor->flags |= SNOR_F_HAS_SR_TB_BIT6; 2441 } 2442 2443 if (flags & SPI_NOR_4BIT_BP) { 2444 nor->flags |= SNOR_F_HAS_4BIT_BP; 2445 if (flags & SPI_NOR_BP3_SR_BIT6) 2446 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; 2447 } 2448 2449 if (flags & NO_CHIP_ERASE) 2450 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2451 } 2452 2453 /** 2454 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not 2455 * be discovered by SFDP for this particular flash because the SFDP table that 2456 * indicates this support is not defined in the flash. In case the table for 2457 * this support is defined but has wrong values, one should instead use a 2458 * post_sfdp() hook to set the SNOR_F equivalent flag. 2459 * @nor: pointer to a 'struct spi_nor' 2460 */ 2461 static void spi_nor_init_fixup_flags(struct spi_nor *nor) 2462 { 2463 const u8 fixup_flags = nor->info->fixup_flags; 2464 2465 if (fixup_flags & SPI_NOR_4B_OPCODES) 2466 nor->flags |= SNOR_F_4B_OPCODES; 2467 2468 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE) 2469 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; 2470 } 2471 2472 /** 2473 * spi_nor_late_init_params() - Late initialization of default flash parameters. 2474 * @nor: pointer to a 'struct spi_nor' 2475 * 2476 * Used to initialize flash parameters that are not declared in the JESD216 2477 * SFDP standard, or where SFDP tables are not defined at all. 2478 * Will replace the spi_nor_manufacturer_init_params() method. 2479 */ 2480 static void spi_nor_late_init_params(struct spi_nor *nor) 2481 { 2482 if (nor->manufacturer && nor->manufacturer->fixups && 2483 nor->manufacturer->fixups->late_init) 2484 nor->manufacturer->fixups->late_init(nor); 2485 2486 if (nor->info->fixups && nor->info->fixups->late_init) 2487 nor->info->fixups->late_init(nor); 2488 2489 spi_nor_init_flags(nor); 2490 spi_nor_init_fixup_flags(nor); 2491 2492 /* 2493 * NOR protection support. When locking_ops are not provided, we pick 2494 * the default ones. 2495 */ 2496 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) 2497 spi_nor_init_default_locking_ops(nor); 2498 } 2499 2500 /** 2501 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash 2502 * parameters and settings based on JESD216 SFDP standard. 2503 * @nor: pointer to a 'struct spi_nor'. 2504 * 2505 * The method has a roll-back mechanism: in case the SFDP parsing fails, the 2506 * legacy flash parameters and settings will be restored. 2507 */ 2508 static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor) 2509 { 2510 struct spi_nor_flash_parameter sfdp_params; 2511 2512 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params)); 2513 2514 if (spi_nor_parse_sfdp(nor)) { 2515 memcpy(nor->params, &sfdp_params, sizeof(*nor->params)); 2516 nor->addr_width = 0; 2517 nor->flags &= ~SNOR_F_4B_OPCODES; 2518 } 2519 } 2520 2521 /** 2522 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash 2523 * parameters and settings. 2524 * @nor: pointer to a 'struct spi_nor'. 2525 * 2526 * The method assumes that flash doesn't support SFDP so it initializes flash 2527 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten 2528 * when parsing SFDP, if supported. 2529 */ 2530 static void spi_nor_init_params_deprecated(struct spi_nor *nor) 2531 { 2532 spi_nor_no_sfdp_init_params(nor); 2533 2534 spi_nor_manufacturer_init_params(nor); 2535 2536 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ | 2537 SPI_NOR_QUAD_READ | 2538 SPI_NOR_OCTAL_READ | 2539 SPI_NOR_OCTAL_DTR_READ)) 2540 spi_nor_sfdp_init_params_deprecated(nor); 2541 } 2542 2543 /** 2544 * spi_nor_init_default_params() - Default initialization of flash parameters 2545 * and settings. Done for all flashes, regardless is they define SFDP tables 2546 * or not. 2547 * @nor: pointer to a 'struct spi_nor'. 2548 */ 2549 static void spi_nor_init_default_params(struct spi_nor *nor) 2550 { 2551 struct spi_nor_flash_parameter *params = nor->params; 2552 const struct flash_info *info = nor->info; 2553 struct device_node *np = spi_nor_get_flash_node(nor); 2554 2555 params->quad_enable = spi_nor_sr2_bit1_quad_enable; 2556 params->set_4byte_addr_mode = spansion_set_4byte_addr_mode; 2557 params->otp.org = &info->otp_org; 2558 2559 /* Default to 16-bit Write Status (01h) Command */ 2560 nor->flags |= SNOR_F_HAS_16BIT_SR; 2561 2562 /* Set SPI NOR sizes. */ 2563 params->writesize = 1; 2564 params->size = (u64)info->sector_size * info->n_sectors; 2565 params->page_size = info->page_size; 2566 2567 if (!(info->flags & SPI_NOR_NO_FR)) { 2568 /* Default to Fast Read for DT and non-DT platform devices. */ 2569 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 2570 2571 /* Mask out Fast Read if not requested at DT instantiation. */ 2572 if (np && !of_property_read_bool(np, "m25p,fast-read")) 2573 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2574 } 2575 2576 /* (Fast) Read settings. */ 2577 params->hwcaps.mask |= SNOR_HWCAPS_READ; 2578 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 2579 0, 0, SPINOR_OP_READ, 2580 SNOR_PROTO_1_1_1); 2581 2582 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) 2583 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 2584 0, 8, SPINOR_OP_READ_FAST, 2585 SNOR_PROTO_1_1_1); 2586 /* Page Program settings. */ 2587 params->hwcaps.mask |= SNOR_HWCAPS_PP; 2588 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 2589 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 2590 } 2591 2592 /** 2593 * spi_nor_init_params() - Initialize the flash's parameters and settings. 2594 * @nor: pointer to a 'struct spi_nor'. 2595 * 2596 * The flash parameters and settings are initialized based on a sequence of 2597 * calls that are ordered by priority: 2598 * 2599 * 1/ Default flash parameters initialization. The initializations are done 2600 * based on nor->info data: 2601 * spi_nor_info_init_params() 2602 * 2603 * which can be overwritten by: 2604 * 2/ Manufacturer flash parameters initialization. The initializations are 2605 * done based on MFR register, or when the decisions can not be done solely 2606 * based on MFR, by using specific flash_info tweeks, ->default_init(): 2607 * spi_nor_manufacturer_init_params() 2608 * 2609 * which can be overwritten by: 2610 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and 2611 * should be more accurate that the above. 2612 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params() 2613 * 2614 * Please note that there is a ->post_bfpt() fixup hook that can overwrite 2615 * the flash parameters and settings immediately after parsing the Basic 2616 * Flash Parameter Table. 2617 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed. 2618 * It is used to tweak various flash parameters when information provided 2619 * by the SFDP tables are wrong. 2620 * 2621 * which can be overwritten by: 2622 * 4/ Late flash parameters initialization, used to initialize flash 2623 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP 2624 * tables are not defined at all. 2625 * spi_nor_late_init_params() 2626 * 2627 * Return: 0 on success, -errno otherwise. 2628 */ 2629 static int spi_nor_init_params(struct spi_nor *nor) 2630 { 2631 int ret; 2632 2633 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); 2634 if (!nor->params) 2635 return -ENOMEM; 2636 2637 spi_nor_init_default_params(nor); 2638 2639 if (nor->info->parse_sfdp) { 2640 ret = spi_nor_parse_sfdp(nor); 2641 if (ret) { 2642 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n"); 2643 return ret; 2644 } 2645 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) { 2646 spi_nor_no_sfdp_init_params(nor); 2647 } else { 2648 spi_nor_init_params_deprecated(nor); 2649 } 2650 2651 spi_nor_late_init_params(nor); 2652 2653 return 0; 2654 } 2655 2656 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed 2657 * @nor: pointer to a 'struct spi_nor' 2658 * @enable: whether to enable or disable Octal DTR 2659 * 2660 * Return: 0 on success, -errno otherwise. 2661 */ 2662 static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) 2663 { 2664 int ret; 2665 2666 if (!nor->params->octal_dtr_enable) 2667 return 0; 2668 2669 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && 2670 nor->write_proto == SNOR_PROTO_8_8_8_DTR)) 2671 return 0; 2672 2673 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) 2674 return 0; 2675 2676 ret = nor->params->octal_dtr_enable(nor, enable); 2677 if (ret) 2678 return ret; 2679 2680 if (enable) 2681 nor->reg_proto = SNOR_PROTO_8_8_8_DTR; 2682 else 2683 nor->reg_proto = SNOR_PROTO_1_1_1; 2684 2685 return 0; 2686 } 2687 2688 /** 2689 * spi_nor_quad_enable() - enable Quad I/O if needed. 2690 * @nor: pointer to a 'struct spi_nor' 2691 * 2692 * Return: 0 on success, -errno otherwise. 2693 */ 2694 static int spi_nor_quad_enable(struct spi_nor *nor) 2695 { 2696 if (!nor->params->quad_enable) 2697 return 0; 2698 2699 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || 2700 spi_nor_get_protocol_width(nor->write_proto) == 4)) 2701 return 0; 2702 2703 return nor->params->quad_enable(nor); 2704 } 2705 2706 static int spi_nor_init(struct spi_nor *nor) 2707 { 2708 int err; 2709 2710 err = spi_nor_octal_dtr_enable(nor, true); 2711 if (err) { 2712 dev_dbg(nor->dev, "octal mode not supported\n"); 2713 return err; 2714 } 2715 2716 err = spi_nor_quad_enable(nor); 2717 if (err) { 2718 dev_dbg(nor->dev, "quad mode not supported\n"); 2719 return err; 2720 } 2721 2722 /* 2723 * Some SPI NOR flashes are write protected by default after a power-on 2724 * reset cycle, in order to avoid inadvertent writes during power-up. 2725 * Backward compatibility imposes to unlock the entire flash memory 2726 * array at power-up by default. Depending on the kernel configuration 2727 * (1) do nothing, (2) always unlock the entire flash array or (3) 2728 * unlock the entire flash array only when the software write 2729 * protection bits are volatile. The latter is indicated by 2730 * SNOR_F_SWP_IS_VOLATILE. 2731 */ 2732 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) || 2733 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) && 2734 nor->flags & SNOR_F_SWP_IS_VOLATILE)) 2735 spi_nor_try_unlock_all(nor); 2736 2737 if (nor->addr_width == 4 && 2738 nor->read_proto != SNOR_PROTO_8_8_8_DTR && 2739 !(nor->flags & SNOR_F_4B_OPCODES)) { 2740 /* 2741 * If the RESET# pin isn't hooked up properly, or the system 2742 * otherwise doesn't perform a reset command in the boot 2743 * sequence, it's impossible to 100% protect against unexpected 2744 * reboots (e.g., crashes). Warn the user (or hopefully, system 2745 * designer) that this is bad. 2746 */ 2747 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, 2748 "enabling reset hack; may not recover from unexpected reboots\n"); 2749 nor->params->set_4byte_addr_mode(nor, true); 2750 } 2751 2752 return 0; 2753 } 2754 2755 /** 2756 * spi_nor_soft_reset() - Perform a software reset 2757 * @nor: pointer to 'struct spi_nor' 2758 * 2759 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets 2760 * the device to its power-on-reset state. This is useful when the software has 2761 * made some changes to device (volatile) registers and needs to reset it before 2762 * shutting down, for example. 2763 * 2764 * Not every flash supports this sequence. The same set of opcodes might be used 2765 * for some other operation on a flash that does not support this. Support for 2766 * this sequence can be discovered via SFDP in the BFPT table. 2767 * 2768 * Return: 0 on success, -errno otherwise. 2769 */ 2770 static void spi_nor_soft_reset(struct spi_nor *nor) 2771 { 2772 struct spi_mem_op op; 2773 int ret; 2774 2775 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), 2776 SPI_MEM_OP_NO_DUMMY, 2777 SPI_MEM_OP_NO_ADDR, 2778 SPI_MEM_OP_NO_DATA); 2779 2780 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 2781 2782 ret = spi_mem_exec_op(nor->spimem, &op); 2783 if (ret) { 2784 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 2785 return; 2786 } 2787 2788 op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), 2789 SPI_MEM_OP_NO_DUMMY, 2790 SPI_MEM_OP_NO_ADDR, 2791 SPI_MEM_OP_NO_DATA); 2792 2793 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 2794 2795 ret = spi_mem_exec_op(nor->spimem, &op); 2796 if (ret) { 2797 dev_warn(nor->dev, "Software reset failed: %d\n", ret); 2798 return; 2799 } 2800 2801 /* 2802 * Software Reset is not instant, and the delay varies from flash to 2803 * flash. Looking at a few flashes, most range somewhere below 100 2804 * microseconds. So, sleep for a range of 200-400 us. 2805 */ 2806 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX); 2807 } 2808 2809 /* mtd suspend handler */ 2810 static int spi_nor_suspend(struct mtd_info *mtd) 2811 { 2812 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2813 int ret; 2814 2815 /* Disable octal DTR mode if we enabled it. */ 2816 ret = spi_nor_octal_dtr_enable(nor, false); 2817 if (ret) 2818 dev_err(nor->dev, "suspend() failed\n"); 2819 2820 return ret; 2821 } 2822 2823 /* mtd resume handler */ 2824 static void spi_nor_resume(struct mtd_info *mtd) 2825 { 2826 struct spi_nor *nor = mtd_to_spi_nor(mtd); 2827 struct device *dev = nor->dev; 2828 int ret; 2829 2830 /* re-initialize the nor chip */ 2831 ret = spi_nor_init(nor); 2832 if (ret) 2833 dev_err(dev, "resume() failed\n"); 2834 } 2835 2836 static int spi_nor_get_device(struct mtd_info *mtd) 2837 { 2838 struct mtd_info *master = mtd_get_master(mtd); 2839 struct spi_nor *nor = mtd_to_spi_nor(master); 2840 struct device *dev; 2841 2842 if (nor->spimem) 2843 dev = nor->spimem->spi->controller->dev.parent; 2844 else 2845 dev = nor->dev; 2846 2847 if (!try_module_get(dev->driver->owner)) 2848 return -ENODEV; 2849 2850 return 0; 2851 } 2852 2853 static void spi_nor_put_device(struct mtd_info *mtd) 2854 { 2855 struct mtd_info *master = mtd_get_master(mtd); 2856 struct spi_nor *nor = mtd_to_spi_nor(master); 2857 struct device *dev; 2858 2859 if (nor->spimem) 2860 dev = nor->spimem->spi->controller->dev.parent; 2861 else 2862 dev = nor->dev; 2863 2864 module_put(dev->driver->owner); 2865 } 2866 2867 void spi_nor_restore(struct spi_nor *nor) 2868 { 2869 /* restore the addressing mode */ 2870 if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) && 2871 nor->flags & SNOR_F_BROKEN_RESET) 2872 nor->params->set_4byte_addr_mode(nor, false); 2873 2874 if (nor->flags & SNOR_F_SOFT_RESET) 2875 spi_nor_soft_reset(nor); 2876 } 2877 EXPORT_SYMBOL_GPL(spi_nor_restore); 2878 2879 static const struct flash_info *spi_nor_match_id(struct spi_nor *nor, 2880 const char *name) 2881 { 2882 unsigned int i, j; 2883 2884 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { 2885 for (j = 0; j < manufacturers[i]->nparts; j++) { 2886 if (!strcmp(name, manufacturers[i]->parts[j].name)) { 2887 nor->manufacturer = manufacturers[i]; 2888 return &manufacturers[i]->parts[j]; 2889 } 2890 } 2891 } 2892 2893 return NULL; 2894 } 2895 2896 static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, 2897 const char *name) 2898 { 2899 const struct flash_info *info = NULL; 2900 2901 if (name) 2902 info = spi_nor_match_id(nor, name); 2903 /* Try to auto-detect if chip name wasn't specified or not found */ 2904 if (!info) 2905 info = spi_nor_read_id(nor); 2906 if (IS_ERR_OR_NULL(info)) 2907 return ERR_PTR(-ENOENT); 2908 2909 /* 2910 * If caller has specified name of flash model that can normally be 2911 * detected using JEDEC, let's verify it. 2912 */ 2913 if (name && info->id_len) { 2914 const struct flash_info *jinfo; 2915 2916 jinfo = spi_nor_read_id(nor); 2917 if (IS_ERR(jinfo)) { 2918 return jinfo; 2919 } else if (jinfo != info) { 2920 /* 2921 * JEDEC knows better, so overwrite platform ID. We 2922 * can't trust partitions any longer, but we'll let 2923 * mtd apply them anyway, since some partitions may be 2924 * marked read-only, and we don't want to lose that 2925 * information, even if it's not 100% accurate. 2926 */ 2927 dev_warn(nor->dev, "found %s, expected %s\n", 2928 jinfo->name, info->name); 2929 info = jinfo; 2930 } 2931 } 2932 2933 return info; 2934 } 2935 2936 static void spi_nor_set_mtd_info(struct spi_nor *nor) 2937 { 2938 struct mtd_info *mtd = &nor->mtd; 2939 struct device *dev = nor->dev; 2940 2941 spi_nor_set_mtd_locking_ops(nor); 2942 spi_nor_set_mtd_otp_ops(nor); 2943 2944 mtd->dev.parent = dev; 2945 if (!mtd->name) 2946 mtd->name = dev_name(dev); 2947 mtd->type = MTD_NORFLASH; 2948 mtd->flags = MTD_CAP_NORFLASH; 2949 if (nor->info->flags & SPI_NOR_NO_ERASE) 2950 mtd->flags |= MTD_NO_ERASE; 2951 else 2952 mtd->_erase = spi_nor_erase; 2953 mtd->writesize = nor->params->writesize; 2954 mtd->writebufsize = nor->params->page_size; 2955 mtd->size = nor->params->size; 2956 mtd->_read = spi_nor_read; 2957 /* Might be already set by some SST flashes. */ 2958 if (!mtd->_write) 2959 mtd->_write = spi_nor_write; 2960 mtd->_suspend = spi_nor_suspend; 2961 mtd->_resume = spi_nor_resume; 2962 mtd->_get_device = spi_nor_get_device; 2963 mtd->_put_device = spi_nor_put_device; 2964 } 2965 2966 int spi_nor_scan(struct spi_nor *nor, const char *name, 2967 const struct spi_nor_hwcaps *hwcaps) 2968 { 2969 const struct flash_info *info; 2970 struct device *dev = nor->dev; 2971 struct mtd_info *mtd = &nor->mtd; 2972 int ret; 2973 int i; 2974 2975 ret = spi_nor_check(nor); 2976 if (ret) 2977 return ret; 2978 2979 /* Reset SPI protocol for all commands. */ 2980 nor->reg_proto = SNOR_PROTO_1_1_1; 2981 nor->read_proto = SNOR_PROTO_1_1_1; 2982 nor->write_proto = SNOR_PROTO_1_1_1; 2983 2984 /* 2985 * We need the bounce buffer early to read/write registers when going 2986 * through the spi-mem layer (buffers have to be DMA-able). 2987 * For spi-mem drivers, we'll reallocate a new buffer if 2988 * nor->params->page_size turns out to be greater than PAGE_SIZE (which 2989 * shouldn't happen before long since NOR pages are usually less 2990 * than 1KB) after spi_nor_scan() returns. 2991 */ 2992 nor->bouncebuf_size = PAGE_SIZE; 2993 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size, 2994 GFP_KERNEL); 2995 if (!nor->bouncebuf) 2996 return -ENOMEM; 2997 2998 info = spi_nor_get_flash_info(nor, name); 2999 if (IS_ERR(info)) 3000 return PTR_ERR(info); 3001 3002 nor->info = info; 3003 3004 mutex_init(&nor->lock); 3005 3006 /* Init flash parameters based on flash_info struct and SFDP */ 3007 ret = spi_nor_init_params(nor); 3008 if (ret) 3009 return ret; 3010 3011 /* 3012 * Configure the SPI memory: 3013 * - select op codes for (Fast) Read, Page Program and Sector Erase. 3014 * - set the number of dummy cycles (mode cycles + wait states). 3015 * - set the SPI protocols for register and memory accesses. 3016 * - set the address width. 3017 */ 3018 ret = spi_nor_setup(nor, hwcaps); 3019 if (ret) 3020 return ret; 3021 3022 /* Send all the required SPI flash commands to initialize device */ 3023 ret = spi_nor_init(nor); 3024 if (ret) 3025 return ret; 3026 3027 /* No mtd_info fields should be used up to this point. */ 3028 spi_nor_set_mtd_info(nor); 3029 3030 dev_info(dev, "%s (%lld Kbytes)\n", info->name, 3031 (long long)mtd->size >> 10); 3032 3033 dev_dbg(dev, 3034 "mtd .name = %s, .size = 0x%llx (%lldMiB), " 3035 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 3036 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), 3037 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); 3038 3039 if (mtd->numeraseregions) 3040 for (i = 0; i < mtd->numeraseregions; i++) 3041 dev_dbg(dev, 3042 "mtd.eraseregions[%d] = { .offset = 0x%llx, " 3043 ".erasesize = 0x%.8x (%uKiB), " 3044 ".numblocks = %d }\n", 3045 i, (long long)mtd->eraseregions[i].offset, 3046 mtd->eraseregions[i].erasesize, 3047 mtd->eraseregions[i].erasesize / 1024, 3048 mtd->eraseregions[i].numblocks); 3049 return 0; 3050 } 3051 EXPORT_SYMBOL_GPL(spi_nor_scan); 3052 3053 static int spi_nor_create_read_dirmap(struct spi_nor *nor) 3054 { 3055 struct spi_mem_dirmap_info info = { 3056 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), 3057 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3058 SPI_MEM_OP_DUMMY(nor->read_dummy, 0), 3059 SPI_MEM_OP_DATA_IN(0, NULL, 0)), 3060 .offset = 0, 3061 .length = nor->params->size, 3062 }; 3063 struct spi_mem_op *op = &info.op_tmpl; 3064 3065 spi_nor_spimem_setup_op(nor, op, nor->read_proto); 3066 3067 /* convert the dummy cycles to the number of bytes */ 3068 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8; 3069 if (spi_nor_protocol_is_dtr(nor->read_proto)) 3070 op->dummy.nbytes *= 2; 3071 3072 /* 3073 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3074 * of data bytes is non-zero, the data buswidth won't be set here. So, 3075 * do it explicitly. 3076 */ 3077 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 3078 3079 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3080 &info); 3081 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc); 3082 } 3083 3084 static int spi_nor_create_write_dirmap(struct spi_nor *nor) 3085 { 3086 struct spi_mem_dirmap_info info = { 3087 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0), 3088 SPI_MEM_OP_ADDR(nor->addr_width, 0, 0), 3089 SPI_MEM_OP_NO_DUMMY, 3090 SPI_MEM_OP_DATA_OUT(0, NULL, 0)), 3091 .offset = 0, 3092 .length = nor->params->size, 3093 }; 3094 struct spi_mem_op *op = &info.op_tmpl; 3095 3096 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 3097 op->addr.nbytes = 0; 3098 3099 spi_nor_spimem_setup_op(nor, op, nor->write_proto); 3100 3101 /* 3102 * Since spi_nor_spimem_setup_op() only sets buswidth when the number 3103 * of data bytes is non-zero, the data buswidth won't be set here. So, 3104 * do it explicitly. 3105 */ 3106 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 3107 3108 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem, 3109 &info); 3110 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc); 3111 } 3112 3113 static int spi_nor_probe(struct spi_mem *spimem) 3114 { 3115 struct spi_device *spi = spimem->spi; 3116 struct flash_platform_data *data = dev_get_platdata(&spi->dev); 3117 struct spi_nor *nor; 3118 /* 3119 * Enable all caps by default. The core will mask them after 3120 * checking what's really supported using spi_mem_supports_op(). 3121 */ 3122 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; 3123 char *flash_name; 3124 int ret; 3125 3126 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL); 3127 if (!nor) 3128 return -ENOMEM; 3129 3130 nor->spimem = spimem; 3131 nor->dev = &spi->dev; 3132 spi_nor_set_flash_node(nor, spi->dev.of_node); 3133 3134 spi_mem_set_drvdata(spimem, nor); 3135 3136 if (data && data->name) 3137 nor->mtd.name = data->name; 3138 3139 if (!nor->mtd.name) 3140 nor->mtd.name = spi_mem_get_name(spimem); 3141 3142 /* 3143 * For some (historical?) reason many platforms provide two different 3144 * names in flash_platform_data: "name" and "type". Quite often name is 3145 * set to "m25p80" and then "type" provides a real chip name. 3146 * If that's the case, respect "type" and ignore a "name". 3147 */ 3148 if (data && data->type) 3149 flash_name = data->type; 3150 else if (!strcmp(spi->modalias, "spi-nor")) 3151 flash_name = NULL; /* auto-detect */ 3152 else 3153 flash_name = spi->modalias; 3154 3155 ret = spi_nor_scan(nor, flash_name, &hwcaps); 3156 if (ret) 3157 return ret; 3158 3159 /* 3160 * None of the existing parts have > 512B pages, but let's play safe 3161 * and add this logic so that if anyone ever adds support for such 3162 * a NOR we don't end up with buffer overflows. 3163 */ 3164 if (nor->params->page_size > PAGE_SIZE) { 3165 nor->bouncebuf_size = nor->params->page_size; 3166 devm_kfree(nor->dev, nor->bouncebuf); 3167 nor->bouncebuf = devm_kmalloc(nor->dev, 3168 nor->bouncebuf_size, 3169 GFP_KERNEL); 3170 if (!nor->bouncebuf) 3171 return -ENOMEM; 3172 } 3173 3174 ret = spi_nor_create_read_dirmap(nor); 3175 if (ret) 3176 return ret; 3177 3178 ret = spi_nor_create_write_dirmap(nor); 3179 if (ret) 3180 return ret; 3181 3182 return mtd_device_register(&nor->mtd, data ? data->parts : NULL, 3183 data ? data->nr_parts : 0); 3184 } 3185 3186 static int spi_nor_remove(struct spi_mem *spimem) 3187 { 3188 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3189 3190 spi_nor_restore(nor); 3191 3192 /* Clean up MTD stuff. */ 3193 return mtd_device_unregister(&nor->mtd); 3194 } 3195 3196 static void spi_nor_shutdown(struct spi_mem *spimem) 3197 { 3198 struct spi_nor *nor = spi_mem_get_drvdata(spimem); 3199 3200 spi_nor_restore(nor); 3201 } 3202 3203 /* 3204 * Do NOT add to this array without reading the following: 3205 * 3206 * Historically, many flash devices are bound to this driver by their name. But 3207 * since most of these flash are compatible to some extent, and their 3208 * differences can often be differentiated by the JEDEC read-ID command, we 3209 * encourage new users to add support to the spi-nor library, and simply bind 3210 * against a generic string here (e.g., "jedec,spi-nor"). 3211 * 3212 * Many flash names are kept here in this list to keep them available 3213 * as module aliases for existing platforms. 3214 */ 3215 static const struct spi_device_id spi_nor_dev_ids[] = { 3216 /* 3217 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and 3218 * hack around the fact that the SPI core does not provide uevent 3219 * matching for .of_match_table 3220 */ 3221 {"spi-nor"}, 3222 3223 /* 3224 * Entries not used in DTs that should be safe to drop after replacing 3225 * them with "spi-nor" in platform data. 3226 */ 3227 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, 3228 3229 /* 3230 * Entries that were used in DTs without "jedec,spi-nor" fallback and 3231 * should be kept for backward compatibility. 3232 */ 3233 {"at25df321a"}, {"at25df641"}, {"at26df081a"}, 3234 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"}, 3235 {"mx25l25635e"},{"mx66l51235l"}, 3236 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"}, 3237 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"}, 3238 {"s25fl064k"}, 3239 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"}, 3240 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"}, 3241 {"m25p64"}, {"m25p128"}, 3242 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"}, 3243 {"w25q80bl"}, {"w25q128"}, {"w25q256"}, 3244 3245 /* Flashes that can't be detected using JEDEC */ 3246 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"}, 3247 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"}, 3248 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"}, 3249 3250 /* Everspin MRAMs (non-JEDEC) */ 3251 { "mr25h128" }, /* 128 Kib, 40 MHz */ 3252 { "mr25h256" }, /* 256 Kib, 40 MHz */ 3253 { "mr25h10" }, /* 1 Mib, 40 MHz */ 3254 { "mr25h40" }, /* 4 Mib, 40 MHz */ 3255 3256 { }, 3257 }; 3258 MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids); 3259 3260 static const struct of_device_id spi_nor_of_table[] = { 3261 /* 3262 * Generic compatibility for SPI NOR that can be identified by the 3263 * JEDEC READ ID opcode (0x9F). Use this, if possible. 3264 */ 3265 { .compatible = "jedec,spi-nor" }, 3266 { /* sentinel */ }, 3267 }; 3268 MODULE_DEVICE_TABLE(of, spi_nor_of_table); 3269 3270 /* 3271 * REVISIT: many of these chips have deep power-down modes, which 3272 * should clearly be entered on suspend() to minimize power use. 3273 * And also when they're otherwise idle... 3274 */ 3275 static struct spi_mem_driver spi_nor_driver = { 3276 .spidrv = { 3277 .driver = { 3278 .name = "spi-nor", 3279 .of_match_table = spi_nor_of_table, 3280 .dev_groups = spi_nor_sysfs_groups, 3281 }, 3282 .id_table = spi_nor_dev_ids, 3283 }, 3284 .probe = spi_nor_probe, 3285 .remove = spi_nor_remove, 3286 .shutdown = spi_nor_shutdown, 3287 }; 3288 module_spi_mem_driver(spi_nor_driver); 3289 3290 MODULE_LICENSE("GPL v2"); 3291 MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); 3292 MODULE_AUTHOR("Mike Lavender"); 3293 MODULE_DESCRIPTION("framework for SPI NOR"); 3294