1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2017 Micron Technology, Inc. 4 * 5 * Authors: 6 * Peter Pan <peterpandong@micron.com> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #define pr_fmt(fmt) "spi-nand: " fmt 11 12 #include <linux/device.h> 13 #include <linux/jiffies.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mtd/spinand.h> 17 #include <linux/of.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi-mem.h> 22 23 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) 24 { 25 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, 26 spinand->scratchbuf); 27 int ret; 28 29 ret = spi_mem_exec_op(spinand->spimem, &op); 30 if (ret) 31 return ret; 32 33 *val = *spinand->scratchbuf; 34 return 0; 35 } 36 37 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) 38 { 39 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, 40 spinand->scratchbuf); 41 42 *spinand->scratchbuf = val; 43 return spi_mem_exec_op(spinand->spimem, &op); 44 } 45 46 static int spinand_read_status(struct spinand_device *spinand, u8 *status) 47 { 48 return spinand_read_reg_op(spinand, REG_STATUS, status); 49 } 50 51 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg) 52 { 53 struct nand_device *nand = spinand_to_nand(spinand); 54 55 if (WARN_ON(spinand->cur_target < 0 || 56 spinand->cur_target >= nand->memorg.ntargets)) 57 return -EINVAL; 58 59 *cfg = spinand->cfg_cache[spinand->cur_target]; 60 return 0; 61 } 62 63 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg) 64 { 65 struct nand_device *nand = spinand_to_nand(spinand); 66 int ret; 67 68 if (WARN_ON(spinand->cur_target < 0 || 69 spinand->cur_target >= nand->memorg.ntargets)) 70 return -EINVAL; 71 72 if (spinand->cfg_cache[spinand->cur_target] == cfg) 73 return 0; 74 75 ret = spinand_write_reg_op(spinand, REG_CFG, cfg); 76 if (ret) 77 return ret; 78 79 spinand->cfg_cache[spinand->cur_target] = cfg; 80 return 0; 81 } 82 83 /** 84 * spinand_upd_cfg() - Update the configuration register 85 * @spinand: the spinand device 86 * @mask: the mask encoding the bits to update in the config reg 87 * @val: the new value to apply 88 * 89 * Update the configuration register. 90 * 91 * Return: 0 on success, a negative error code otherwise. 92 */ 93 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val) 94 { 95 int ret; 96 u8 cfg; 97 98 ret = spinand_get_cfg(spinand, &cfg); 99 if (ret) 100 return ret; 101 102 cfg &= ~mask; 103 cfg |= val; 104 105 return spinand_set_cfg(spinand, cfg); 106 } 107 108 /** 109 * spinand_select_target() - Select a specific NAND target/die 110 * @spinand: the spinand device 111 * @target: the target/die to select 112 * 113 * Select a new target/die. If chip only has one die, this function is a NOOP. 114 * 115 * Return: 0 on success, a negative error code otherwise. 116 */ 117 int spinand_select_target(struct spinand_device *spinand, unsigned int target) 118 { 119 struct nand_device *nand = spinand_to_nand(spinand); 120 int ret; 121 122 if (WARN_ON(target >= nand->memorg.ntargets)) 123 return -EINVAL; 124 125 if (spinand->cur_target == target) 126 return 0; 127 128 if (nand->memorg.ntargets == 1) { 129 spinand->cur_target = target; 130 return 0; 131 } 132 133 ret = spinand->select_target(spinand, target); 134 if (ret) 135 return ret; 136 137 spinand->cur_target = target; 138 return 0; 139 } 140 141 static int spinand_init_cfg_cache(struct spinand_device *spinand) 142 { 143 struct nand_device *nand = spinand_to_nand(spinand); 144 struct device *dev = &spinand->spimem->spi->dev; 145 unsigned int target; 146 int ret; 147 148 spinand->cfg_cache = devm_kcalloc(dev, 149 nand->memorg.ntargets, 150 sizeof(*spinand->cfg_cache), 151 GFP_KERNEL); 152 if (!spinand->cfg_cache) 153 return -ENOMEM; 154 155 for (target = 0; target < nand->memorg.ntargets; target++) { 156 ret = spinand_select_target(spinand, target); 157 if (ret) 158 return ret; 159 160 /* 161 * We use spinand_read_reg_op() instead of spinand_get_cfg() 162 * here to bypass the config cache. 163 */ 164 ret = spinand_read_reg_op(spinand, REG_CFG, 165 &spinand->cfg_cache[target]); 166 if (ret) 167 return ret; 168 } 169 170 return 0; 171 } 172 173 static int spinand_init_quad_enable(struct spinand_device *spinand) 174 { 175 bool enable = false; 176 177 if (!(spinand->flags & SPINAND_HAS_QE_BIT)) 178 return 0; 179 180 if (spinand->op_templates.read_cache->data.buswidth == 4 || 181 spinand->op_templates.write_cache->data.buswidth == 4 || 182 spinand->op_templates.update_cache->data.buswidth == 4) 183 enable = true; 184 185 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, 186 enable ? CFG_QUAD_ENABLE : 0); 187 } 188 189 static int spinand_ecc_enable(struct spinand_device *spinand, 190 bool enable) 191 { 192 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE, 193 enable ? CFG_ECC_ENABLE : 0); 194 } 195 196 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status) 197 { 198 struct nand_device *nand = spinand_to_nand(spinand); 199 200 if (spinand->eccinfo.get_status) 201 return spinand->eccinfo.get_status(spinand, status); 202 203 switch (status & STATUS_ECC_MASK) { 204 case STATUS_ECC_NO_BITFLIPS: 205 return 0; 206 207 case STATUS_ECC_HAS_BITFLIPS: 208 /* 209 * We have no way to know exactly how many bitflips have been 210 * fixed, so let's return the maximum possible value so that 211 * wear-leveling layers move the data immediately. 212 */ 213 return nanddev_get_ecc_conf(nand)->strength; 214 215 case STATUS_ECC_UNCOR_ERROR: 216 return -EBADMSG; 217 218 default: 219 break; 220 } 221 222 return -EINVAL; 223 } 224 225 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section, 226 struct mtd_oob_region *region) 227 { 228 return -ERANGE; 229 } 230 231 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section, 232 struct mtd_oob_region *region) 233 { 234 if (section) 235 return -ERANGE; 236 237 /* Reserve 2 bytes for the BBM. */ 238 region->offset = 2; 239 region->length = 62; 240 241 return 0; 242 } 243 244 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = { 245 .ecc = spinand_noecc_ooblayout_ecc, 246 .free = spinand_noecc_ooblayout_free, 247 }; 248 249 static int spinand_ondie_ecc_init_ctx(struct nand_device *nand) 250 { 251 struct spinand_device *spinand = nand_to_spinand(nand); 252 struct mtd_info *mtd = nanddev_to_mtd(nand); 253 struct spinand_ondie_ecc_conf *engine_conf; 254 255 nand->ecc.ctx.conf.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE; 256 nand->ecc.ctx.conf.step_size = nand->ecc.requirements.step_size; 257 nand->ecc.ctx.conf.strength = nand->ecc.requirements.strength; 258 259 engine_conf = kzalloc(sizeof(*engine_conf), GFP_KERNEL); 260 if (!engine_conf) 261 return -ENOMEM; 262 263 nand->ecc.ctx.priv = engine_conf; 264 265 if (spinand->eccinfo.ooblayout) 266 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout); 267 else 268 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout); 269 270 return 0; 271 } 272 273 static void spinand_ondie_ecc_cleanup_ctx(struct nand_device *nand) 274 { 275 kfree(nand->ecc.ctx.priv); 276 } 277 278 static int spinand_ondie_ecc_prepare_io_req(struct nand_device *nand, 279 struct nand_page_io_req *req) 280 { 281 struct spinand_device *spinand = nand_to_spinand(nand); 282 bool enable = (req->mode != MTD_OPS_RAW); 283 284 /* Only enable or disable the engine */ 285 return spinand_ecc_enable(spinand, enable); 286 } 287 288 static int spinand_ondie_ecc_finish_io_req(struct nand_device *nand, 289 struct nand_page_io_req *req) 290 { 291 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv; 292 struct spinand_device *spinand = nand_to_spinand(nand); 293 294 if (req->mode == MTD_OPS_RAW) 295 return 0; 296 297 /* Nothing to do when finishing a page write */ 298 if (req->type == NAND_PAGE_WRITE) 299 return 0; 300 301 /* Finish a page write: check the status, report errors/bitflips */ 302 return spinand_check_ecc_status(spinand, engine_conf->status); 303 } 304 305 static struct nand_ecc_engine_ops spinand_ondie_ecc_engine_ops = { 306 .init_ctx = spinand_ondie_ecc_init_ctx, 307 .cleanup_ctx = spinand_ondie_ecc_cleanup_ctx, 308 .prepare_io_req = spinand_ondie_ecc_prepare_io_req, 309 .finish_io_req = spinand_ondie_ecc_finish_io_req, 310 }; 311 312 static struct nand_ecc_engine spinand_ondie_ecc_engine = { 313 .ops = &spinand_ondie_ecc_engine_ops, 314 }; 315 316 static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status) 317 { 318 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv; 319 320 if (nand->ecc.ctx.conf.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE && 321 engine_conf) 322 engine_conf->status = status; 323 } 324 325 static int spinand_write_enable_op(struct spinand_device *spinand) 326 { 327 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); 328 329 return spi_mem_exec_op(spinand->spimem, &op); 330 } 331 332 static int spinand_load_page_op(struct spinand_device *spinand, 333 const struct nand_page_io_req *req) 334 { 335 struct nand_device *nand = spinand_to_nand(spinand); 336 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 337 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row); 338 339 return spi_mem_exec_op(spinand->spimem, &op); 340 } 341 342 static int spinand_read_from_cache_op(struct spinand_device *spinand, 343 const struct nand_page_io_req *req) 344 { 345 struct nand_device *nand = spinand_to_nand(spinand); 346 struct mtd_info *mtd = spinand_to_mtd(spinand); 347 struct spi_mem_dirmap_desc *rdesc; 348 unsigned int nbytes = 0; 349 void *buf = NULL; 350 u16 column = 0; 351 ssize_t ret; 352 353 if (req->datalen) { 354 buf = spinand->databuf; 355 nbytes = nanddev_page_size(nand); 356 column = 0; 357 } 358 359 if (req->ooblen) { 360 nbytes += nanddev_per_page_oobsize(nand); 361 if (!buf) { 362 buf = spinand->oobbuf; 363 column = nanddev_page_size(nand); 364 } 365 } 366 367 rdesc = spinand->dirmaps[req->pos.plane].rdesc; 368 369 while (nbytes) { 370 ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); 371 if (ret < 0) 372 return ret; 373 374 if (!ret || ret > nbytes) 375 return -EIO; 376 377 nbytes -= ret; 378 column += ret; 379 buf += ret; 380 } 381 382 if (req->datalen) 383 memcpy(req->databuf.in, spinand->databuf + req->dataoffs, 384 req->datalen); 385 386 if (req->ooblen) { 387 if (req->mode == MTD_OPS_AUTO_OOB) 388 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in, 389 spinand->oobbuf, 390 req->ooboffs, 391 req->ooblen); 392 else 393 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs, 394 req->ooblen); 395 } 396 397 return 0; 398 } 399 400 static int spinand_write_to_cache_op(struct spinand_device *spinand, 401 const struct nand_page_io_req *req) 402 { 403 struct nand_device *nand = spinand_to_nand(spinand); 404 struct mtd_info *mtd = spinand_to_mtd(spinand); 405 struct spi_mem_dirmap_desc *wdesc; 406 unsigned int nbytes, column = 0; 407 void *buf = spinand->databuf; 408 ssize_t ret; 409 410 /* 411 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset 412 * the cache content to 0xFF (depends on vendor implementation), so we 413 * must fill the page cache entirely even if we only want to program 414 * the data portion of the page, otherwise we might corrupt the BBM or 415 * user data previously programmed in OOB area. 416 * 417 * Only reset the data buffer manually, the OOB buffer is prepared by 418 * ECC engines ->prepare_io_req() callback. 419 */ 420 nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand); 421 memset(spinand->databuf, 0xff, nanddev_page_size(nand)); 422 423 if (req->datalen) 424 memcpy(spinand->databuf + req->dataoffs, req->databuf.out, 425 req->datalen); 426 427 if (req->ooblen) { 428 if (req->mode == MTD_OPS_AUTO_OOB) 429 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out, 430 spinand->oobbuf, 431 req->ooboffs, 432 req->ooblen); 433 else 434 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out, 435 req->ooblen); 436 } 437 438 wdesc = spinand->dirmaps[req->pos.plane].wdesc; 439 440 while (nbytes) { 441 ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); 442 if (ret < 0) 443 return ret; 444 445 if (!ret || ret > nbytes) 446 return -EIO; 447 448 nbytes -= ret; 449 column += ret; 450 buf += ret; 451 } 452 453 return 0; 454 } 455 456 static int spinand_program_op(struct spinand_device *spinand, 457 const struct nand_page_io_req *req) 458 { 459 struct nand_device *nand = spinand_to_nand(spinand); 460 unsigned int row = nanddev_pos_to_row(nand, &req->pos); 461 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row); 462 463 return spi_mem_exec_op(spinand->spimem, &op); 464 } 465 466 static int spinand_erase_op(struct spinand_device *spinand, 467 const struct nand_pos *pos) 468 { 469 struct nand_device *nand = spinand_to_nand(spinand); 470 unsigned int row = nanddev_pos_to_row(nand, pos); 471 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row); 472 473 return spi_mem_exec_op(spinand->spimem, &op); 474 } 475 476 static int spinand_wait(struct spinand_device *spinand, u8 *s) 477 { 478 unsigned long timeo = jiffies + msecs_to_jiffies(400); 479 u8 status; 480 int ret; 481 482 do { 483 ret = spinand_read_status(spinand, &status); 484 if (ret) 485 return ret; 486 487 if (!(status & STATUS_BUSY)) 488 goto out; 489 } while (time_before(jiffies, timeo)); 490 491 /* 492 * Extra read, just in case the STATUS_READY bit has changed 493 * since our last check 494 */ 495 ret = spinand_read_status(spinand, &status); 496 if (ret) 497 return ret; 498 499 out: 500 if (s) 501 *s = status; 502 503 return status & STATUS_BUSY ? -ETIMEDOUT : 0; 504 } 505 506 static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr, 507 u8 ndummy, u8 *buf) 508 { 509 struct spi_mem_op op = SPINAND_READID_OP( 510 naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 511 int ret; 512 513 ret = spi_mem_exec_op(spinand->spimem, &op); 514 if (!ret) 515 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN); 516 517 return ret; 518 } 519 520 static int spinand_reset_op(struct spinand_device *spinand) 521 { 522 struct spi_mem_op op = SPINAND_RESET_OP; 523 int ret; 524 525 ret = spi_mem_exec_op(spinand->spimem, &op); 526 if (ret) 527 return ret; 528 529 return spinand_wait(spinand, NULL); 530 } 531 532 static int spinand_lock_block(struct spinand_device *spinand, u8 lock) 533 { 534 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); 535 } 536 537 static int spinand_read_page(struct spinand_device *spinand, 538 const struct nand_page_io_req *req) 539 { 540 struct nand_device *nand = spinand_to_nand(spinand); 541 u8 status; 542 int ret; 543 544 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req); 545 if (ret) 546 return ret; 547 548 ret = spinand_load_page_op(spinand, req); 549 if (ret) 550 return ret; 551 552 ret = spinand_wait(spinand, &status); 553 if (ret < 0) 554 return ret; 555 556 spinand_ondie_ecc_save_status(nand, status); 557 558 ret = spinand_read_from_cache_op(spinand, req); 559 if (ret) 560 return ret; 561 562 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req); 563 } 564 565 static int spinand_write_page(struct spinand_device *spinand, 566 const struct nand_page_io_req *req) 567 { 568 struct nand_device *nand = spinand_to_nand(spinand); 569 u8 status; 570 int ret; 571 572 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req); 573 if (ret) 574 return ret; 575 576 ret = spinand_write_enable_op(spinand); 577 if (ret) 578 return ret; 579 580 ret = spinand_write_to_cache_op(spinand, req); 581 if (ret) 582 return ret; 583 584 ret = spinand_program_op(spinand, req); 585 if (ret) 586 return ret; 587 588 ret = spinand_wait(spinand, &status); 589 if (!ret && (status & STATUS_PROG_FAILED)) 590 return -EIO; 591 592 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req); 593 } 594 595 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from, 596 struct mtd_oob_ops *ops) 597 { 598 struct spinand_device *spinand = mtd_to_spinand(mtd); 599 struct nand_device *nand = mtd_to_nanddev(mtd); 600 unsigned int max_bitflips = 0; 601 struct nand_io_iter iter; 602 bool disable_ecc = false; 603 bool ecc_failed = false; 604 int ret = 0; 605 606 if (ops->mode == MTD_OPS_RAW || !spinand->eccinfo.ooblayout) 607 disable_ecc = true; 608 609 mutex_lock(&spinand->lock); 610 611 nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) { 612 if (disable_ecc) 613 iter.req.mode = MTD_OPS_RAW; 614 615 ret = spinand_select_target(spinand, iter.req.pos.target); 616 if (ret) 617 break; 618 619 ret = spinand_read_page(spinand, &iter.req); 620 if (ret < 0 && ret != -EBADMSG) 621 break; 622 623 if (ret == -EBADMSG) { 624 ecc_failed = true; 625 mtd->ecc_stats.failed++; 626 } else { 627 mtd->ecc_stats.corrected += ret; 628 max_bitflips = max_t(unsigned int, max_bitflips, ret); 629 } 630 631 ret = 0; 632 ops->retlen += iter.req.datalen; 633 ops->oobretlen += iter.req.ooblen; 634 } 635 636 mutex_unlock(&spinand->lock); 637 638 if (ecc_failed && !ret) 639 ret = -EBADMSG; 640 641 return ret ? ret : max_bitflips; 642 } 643 644 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, 645 struct mtd_oob_ops *ops) 646 { 647 struct spinand_device *spinand = mtd_to_spinand(mtd); 648 struct nand_device *nand = mtd_to_nanddev(mtd); 649 struct nand_io_iter iter; 650 bool disable_ecc = false; 651 int ret = 0; 652 653 if (ops->mode == MTD_OPS_RAW || !mtd->ooblayout) 654 disable_ecc = true; 655 656 mutex_lock(&spinand->lock); 657 658 nanddev_io_for_each_page(nand, NAND_PAGE_WRITE, to, ops, &iter) { 659 if (disable_ecc) 660 iter.req.mode = MTD_OPS_RAW; 661 662 ret = spinand_select_target(spinand, iter.req.pos.target); 663 if (ret) 664 break; 665 666 ret = spinand_write_page(spinand, &iter.req); 667 if (ret) 668 break; 669 670 ops->retlen += iter.req.datalen; 671 ops->oobretlen += iter.req.ooblen; 672 } 673 674 mutex_unlock(&spinand->lock); 675 676 return ret; 677 } 678 679 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) 680 { 681 struct spinand_device *spinand = nand_to_spinand(nand); 682 u8 marker[2] = { }; 683 struct nand_page_io_req req = { 684 .pos = *pos, 685 .ooblen = sizeof(marker), 686 .ooboffs = 0, 687 .oobbuf.in = marker, 688 .mode = MTD_OPS_RAW, 689 }; 690 691 spinand_select_target(spinand, pos->target); 692 spinand_read_page(spinand, &req); 693 if (marker[0] != 0xff || marker[1] != 0xff) 694 return true; 695 696 return false; 697 } 698 699 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) 700 { 701 struct nand_device *nand = mtd_to_nanddev(mtd); 702 struct spinand_device *spinand = nand_to_spinand(nand); 703 struct nand_pos pos; 704 int ret; 705 706 nanddev_offs_to_pos(nand, offs, &pos); 707 mutex_lock(&spinand->lock); 708 ret = nanddev_isbad(nand, &pos); 709 mutex_unlock(&spinand->lock); 710 711 return ret; 712 } 713 714 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos) 715 { 716 struct spinand_device *spinand = nand_to_spinand(nand); 717 u8 marker[2] = { }; 718 struct nand_page_io_req req = { 719 .pos = *pos, 720 .ooboffs = 0, 721 .ooblen = sizeof(marker), 722 .oobbuf.out = marker, 723 .mode = MTD_OPS_RAW, 724 }; 725 int ret; 726 727 ret = spinand_select_target(spinand, pos->target); 728 if (ret) 729 return ret; 730 731 ret = spinand_write_enable_op(spinand); 732 if (ret) 733 return ret; 734 735 return spinand_write_page(spinand, &req); 736 } 737 738 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) 739 { 740 struct nand_device *nand = mtd_to_nanddev(mtd); 741 struct spinand_device *spinand = nand_to_spinand(nand); 742 struct nand_pos pos; 743 int ret; 744 745 nanddev_offs_to_pos(nand, offs, &pos); 746 mutex_lock(&spinand->lock); 747 ret = nanddev_markbad(nand, &pos); 748 mutex_unlock(&spinand->lock); 749 750 return ret; 751 } 752 753 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos) 754 { 755 struct spinand_device *spinand = nand_to_spinand(nand); 756 u8 status; 757 int ret; 758 759 ret = spinand_select_target(spinand, pos->target); 760 if (ret) 761 return ret; 762 763 ret = spinand_write_enable_op(spinand); 764 if (ret) 765 return ret; 766 767 ret = spinand_erase_op(spinand, pos); 768 if (ret) 769 return ret; 770 771 ret = spinand_wait(spinand, &status); 772 if (!ret && (status & STATUS_ERASE_FAILED)) 773 ret = -EIO; 774 775 return ret; 776 } 777 778 static int spinand_mtd_erase(struct mtd_info *mtd, 779 struct erase_info *einfo) 780 { 781 struct spinand_device *spinand = mtd_to_spinand(mtd); 782 int ret; 783 784 mutex_lock(&spinand->lock); 785 ret = nanddev_mtd_erase(mtd, einfo); 786 mutex_unlock(&spinand->lock); 787 788 return ret; 789 } 790 791 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs) 792 { 793 struct spinand_device *spinand = mtd_to_spinand(mtd); 794 struct nand_device *nand = mtd_to_nanddev(mtd); 795 struct nand_pos pos; 796 int ret; 797 798 nanddev_offs_to_pos(nand, offs, &pos); 799 mutex_lock(&spinand->lock); 800 ret = nanddev_isreserved(nand, &pos); 801 mutex_unlock(&spinand->lock); 802 803 return ret; 804 } 805 806 static int spinand_create_dirmap(struct spinand_device *spinand, 807 unsigned int plane) 808 { 809 struct nand_device *nand = spinand_to_nand(spinand); 810 struct spi_mem_dirmap_info info = { 811 .length = nanddev_page_size(nand) + 812 nanddev_per_page_oobsize(nand), 813 }; 814 struct spi_mem_dirmap_desc *desc; 815 816 /* The plane number is passed in MSB just above the column address */ 817 info.offset = plane << fls(nand->memorg.pagesize); 818 819 info.op_tmpl = *spinand->op_templates.update_cache; 820 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 821 spinand->spimem, &info); 822 if (IS_ERR(desc)) 823 return PTR_ERR(desc); 824 825 spinand->dirmaps[plane].wdesc = desc; 826 827 info.op_tmpl = *spinand->op_templates.read_cache; 828 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, 829 spinand->spimem, &info); 830 if (IS_ERR(desc)) 831 return PTR_ERR(desc); 832 833 spinand->dirmaps[plane].rdesc = desc; 834 835 return 0; 836 } 837 838 static int spinand_create_dirmaps(struct spinand_device *spinand) 839 { 840 struct nand_device *nand = spinand_to_nand(spinand); 841 int i, ret; 842 843 spinand->dirmaps = devm_kzalloc(&spinand->spimem->spi->dev, 844 sizeof(*spinand->dirmaps) * 845 nand->memorg.planes_per_lun, 846 GFP_KERNEL); 847 if (!spinand->dirmaps) 848 return -ENOMEM; 849 850 for (i = 0; i < nand->memorg.planes_per_lun; i++) { 851 ret = spinand_create_dirmap(spinand, i); 852 if (ret) 853 return ret; 854 } 855 856 return 0; 857 } 858 859 static const struct nand_ops spinand_ops = { 860 .erase = spinand_erase, 861 .markbad = spinand_markbad, 862 .isbad = spinand_isbad, 863 }; 864 865 static const struct spinand_manufacturer *spinand_manufacturers[] = { 866 &gigadevice_spinand_manufacturer, 867 ¯onix_spinand_manufacturer, 868 µn_spinand_manufacturer, 869 ¶gon_spinand_manufacturer, 870 &toshiba_spinand_manufacturer, 871 &winbond_spinand_manufacturer, 872 }; 873 874 static int spinand_manufacturer_match(struct spinand_device *spinand, 875 enum spinand_readid_method rdid_method) 876 { 877 u8 *id = spinand->id.data; 878 unsigned int i; 879 int ret; 880 881 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) { 882 const struct spinand_manufacturer *manufacturer = 883 spinand_manufacturers[i]; 884 885 if (id[0] != manufacturer->id) 886 continue; 887 888 ret = spinand_match_and_init(spinand, 889 manufacturer->chips, 890 manufacturer->nchips, 891 rdid_method); 892 if (ret < 0) 893 continue; 894 895 spinand->manufacturer = manufacturer; 896 return 0; 897 } 898 return -ENOTSUPP; 899 } 900 901 static int spinand_id_detect(struct spinand_device *spinand) 902 { 903 u8 *id = spinand->id.data; 904 int ret; 905 906 ret = spinand_read_id_op(spinand, 0, 0, id); 907 if (ret) 908 return ret; 909 ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE); 910 if (!ret) 911 return 0; 912 913 ret = spinand_read_id_op(spinand, 1, 0, id); 914 if (ret) 915 return ret; 916 ret = spinand_manufacturer_match(spinand, 917 SPINAND_READID_METHOD_OPCODE_ADDR); 918 if (!ret) 919 return 0; 920 921 ret = spinand_read_id_op(spinand, 0, 1, id); 922 if (ret) 923 return ret; 924 ret = spinand_manufacturer_match(spinand, 925 SPINAND_READID_METHOD_OPCODE_DUMMY); 926 927 return ret; 928 } 929 930 static int spinand_manufacturer_init(struct spinand_device *spinand) 931 { 932 if (spinand->manufacturer->ops->init) 933 return spinand->manufacturer->ops->init(spinand); 934 935 return 0; 936 } 937 938 static void spinand_manufacturer_cleanup(struct spinand_device *spinand) 939 { 940 /* Release manufacturer private data */ 941 if (spinand->manufacturer->ops->cleanup) 942 return spinand->manufacturer->ops->cleanup(spinand); 943 } 944 945 static const struct spi_mem_op * 946 spinand_select_op_variant(struct spinand_device *spinand, 947 const struct spinand_op_variants *variants) 948 { 949 struct nand_device *nand = spinand_to_nand(spinand); 950 unsigned int i; 951 952 for (i = 0; i < variants->nops; i++) { 953 struct spi_mem_op op = variants->ops[i]; 954 unsigned int nbytes; 955 int ret; 956 957 nbytes = nanddev_per_page_oobsize(nand) + 958 nanddev_page_size(nand); 959 960 while (nbytes) { 961 op.data.nbytes = nbytes; 962 ret = spi_mem_adjust_op_size(spinand->spimem, &op); 963 if (ret) 964 break; 965 966 if (!spi_mem_supports_op(spinand->spimem, &op)) 967 break; 968 969 nbytes -= op.data.nbytes; 970 } 971 972 if (!nbytes) 973 return &variants->ops[i]; 974 } 975 976 return NULL; 977 } 978 979 /** 980 * spinand_match_and_init() - Try to find a match between a device ID and an 981 * entry in a spinand_info table 982 * @spinand: SPI NAND object 983 * @table: SPI NAND device description table 984 * @table_size: size of the device description table 985 * @rdid_method: read id method to match 986 * 987 * Match between a device ID retrieved through the READ_ID command and an 988 * entry in the SPI NAND description table. If a match is found, the spinand 989 * object will be initialized with information provided by the matching 990 * spinand_info entry. 991 * 992 * Return: 0 on success, a negative error code otherwise. 993 */ 994 int spinand_match_and_init(struct spinand_device *spinand, 995 const struct spinand_info *table, 996 unsigned int table_size, 997 enum spinand_readid_method rdid_method) 998 { 999 u8 *id = spinand->id.data; 1000 struct nand_device *nand = spinand_to_nand(spinand); 1001 unsigned int i; 1002 1003 for (i = 0; i < table_size; i++) { 1004 const struct spinand_info *info = &table[i]; 1005 const struct spi_mem_op *op; 1006 1007 if (rdid_method != info->devid.method) 1008 continue; 1009 1010 if (memcmp(id + 1, info->devid.id, info->devid.len)) 1011 continue; 1012 1013 nand->memorg = table[i].memorg; 1014 nanddev_set_ecc_requirements(nand, &table[i].eccreq); 1015 spinand->eccinfo = table[i].eccinfo; 1016 spinand->flags = table[i].flags; 1017 spinand->id.len = 1 + table[i].devid.len; 1018 spinand->select_target = table[i].select_target; 1019 1020 op = spinand_select_op_variant(spinand, 1021 info->op_variants.read_cache); 1022 if (!op) 1023 return -ENOTSUPP; 1024 1025 spinand->op_templates.read_cache = op; 1026 1027 op = spinand_select_op_variant(spinand, 1028 info->op_variants.write_cache); 1029 if (!op) 1030 return -ENOTSUPP; 1031 1032 spinand->op_templates.write_cache = op; 1033 1034 op = spinand_select_op_variant(spinand, 1035 info->op_variants.update_cache); 1036 spinand->op_templates.update_cache = op; 1037 1038 return 0; 1039 } 1040 1041 return -ENOTSUPP; 1042 } 1043 1044 static int spinand_detect(struct spinand_device *spinand) 1045 { 1046 struct device *dev = &spinand->spimem->spi->dev; 1047 struct nand_device *nand = spinand_to_nand(spinand); 1048 int ret; 1049 1050 ret = spinand_reset_op(spinand); 1051 if (ret) 1052 return ret; 1053 1054 ret = spinand_id_detect(spinand); 1055 if (ret) { 1056 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN, 1057 spinand->id.data); 1058 return ret; 1059 } 1060 1061 if (nand->memorg.ntargets > 1 && !spinand->select_target) { 1062 dev_err(dev, 1063 "SPI NANDs with more than one die must implement ->select_target()\n"); 1064 return -EINVAL; 1065 } 1066 1067 dev_info(&spinand->spimem->spi->dev, 1068 "%s SPI NAND was found.\n", spinand->manufacturer->name); 1069 dev_info(&spinand->spimem->spi->dev, 1070 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n", 1071 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10, 1072 nanddev_page_size(nand), nanddev_per_page_oobsize(nand)); 1073 1074 return 0; 1075 } 1076 1077 static int spinand_init(struct spinand_device *spinand) 1078 { 1079 struct device *dev = &spinand->spimem->spi->dev; 1080 struct mtd_info *mtd = spinand_to_mtd(spinand); 1081 struct nand_device *nand = mtd_to_nanddev(mtd); 1082 int ret, i; 1083 1084 /* 1085 * We need a scratch buffer because the spi_mem interface requires that 1086 * buf passed in spi_mem_op->data.buf be DMA-able. 1087 */ 1088 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL); 1089 if (!spinand->scratchbuf) 1090 return -ENOMEM; 1091 1092 ret = spinand_detect(spinand); 1093 if (ret) 1094 goto err_free_bufs; 1095 1096 /* 1097 * Use kzalloc() instead of devm_kzalloc() here, because some drivers 1098 * may use this buffer for DMA access. 1099 * Memory allocated by devm_ does not guarantee DMA-safe alignment. 1100 */ 1101 spinand->databuf = kzalloc(nanddev_page_size(nand) + 1102 nanddev_per_page_oobsize(nand), 1103 GFP_KERNEL); 1104 if (!spinand->databuf) { 1105 ret = -ENOMEM; 1106 goto err_free_bufs; 1107 } 1108 1109 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand); 1110 1111 ret = spinand_init_cfg_cache(spinand); 1112 if (ret) 1113 goto err_free_bufs; 1114 1115 ret = spinand_init_quad_enable(spinand); 1116 if (ret) 1117 goto err_free_bufs; 1118 1119 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0); 1120 if (ret) 1121 goto err_free_bufs; 1122 1123 ret = spinand_manufacturer_init(spinand); 1124 if (ret) { 1125 dev_err(dev, 1126 "Failed to initialize the SPI NAND chip (err = %d)\n", 1127 ret); 1128 goto err_free_bufs; 1129 } 1130 1131 ret = spinand_create_dirmaps(spinand); 1132 if (ret) { 1133 dev_err(dev, 1134 "Failed to create direct mappings for read/write operations (err = %d)\n", 1135 ret); 1136 goto err_manuf_cleanup; 1137 } 1138 1139 /* After power up, all blocks are locked, so unlock them here. */ 1140 for (i = 0; i < nand->memorg.ntargets; i++) { 1141 ret = spinand_select_target(spinand, i); 1142 if (ret) 1143 goto err_manuf_cleanup; 1144 1145 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED); 1146 if (ret) 1147 goto err_manuf_cleanup; 1148 } 1149 1150 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); 1151 if (ret) 1152 goto err_manuf_cleanup; 1153 1154 /* SPI-NAND default ECC engine is on-die */ 1155 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE; 1156 nand->ecc.ondie_engine = &spinand_ondie_ecc_engine; 1157 1158 spinand_ecc_enable(spinand, false); 1159 ret = nanddev_ecc_engine_init(nand); 1160 if (ret) 1161 goto err_cleanup_nanddev; 1162 1163 mtd->_read_oob = spinand_mtd_read; 1164 mtd->_write_oob = spinand_mtd_write; 1165 mtd->_block_isbad = spinand_mtd_block_isbad; 1166 mtd->_block_markbad = spinand_mtd_block_markbad; 1167 mtd->_block_isreserved = spinand_mtd_block_isreserved; 1168 mtd->_erase = spinand_mtd_erase; 1169 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; 1170 1171 if (nand->ecc.engine) { 1172 ret = mtd_ooblayout_count_freebytes(mtd); 1173 if (ret < 0) 1174 goto err_cleanup_ecc_engine; 1175 } 1176 1177 mtd->oobavail = ret; 1178 1179 /* Propagate ECC information to mtd_info */ 1180 mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; 1181 mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; 1182 1183 return 0; 1184 1185 err_cleanup_ecc_engine: 1186 nanddev_ecc_engine_cleanup(nand); 1187 1188 err_cleanup_nanddev: 1189 nanddev_cleanup(nand); 1190 1191 err_manuf_cleanup: 1192 spinand_manufacturer_cleanup(spinand); 1193 1194 err_free_bufs: 1195 kfree(spinand->databuf); 1196 kfree(spinand->scratchbuf); 1197 return ret; 1198 } 1199 1200 static void spinand_cleanup(struct spinand_device *spinand) 1201 { 1202 struct nand_device *nand = spinand_to_nand(spinand); 1203 1204 nanddev_cleanup(nand); 1205 spinand_manufacturer_cleanup(spinand); 1206 kfree(spinand->databuf); 1207 kfree(spinand->scratchbuf); 1208 } 1209 1210 static int spinand_probe(struct spi_mem *mem) 1211 { 1212 struct spinand_device *spinand; 1213 struct mtd_info *mtd; 1214 int ret; 1215 1216 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand), 1217 GFP_KERNEL); 1218 if (!spinand) 1219 return -ENOMEM; 1220 1221 spinand->spimem = mem; 1222 spi_mem_set_drvdata(mem, spinand); 1223 spinand_set_of_node(spinand, mem->spi->dev.of_node); 1224 mutex_init(&spinand->lock); 1225 mtd = spinand_to_mtd(spinand); 1226 mtd->dev.parent = &mem->spi->dev; 1227 1228 ret = spinand_init(spinand); 1229 if (ret) 1230 return ret; 1231 1232 ret = mtd_device_register(mtd, NULL, 0); 1233 if (ret) 1234 goto err_spinand_cleanup; 1235 1236 return 0; 1237 1238 err_spinand_cleanup: 1239 spinand_cleanup(spinand); 1240 1241 return ret; 1242 } 1243 1244 static int spinand_remove(struct spi_mem *mem) 1245 { 1246 struct spinand_device *spinand; 1247 struct mtd_info *mtd; 1248 int ret; 1249 1250 spinand = spi_mem_get_drvdata(mem); 1251 mtd = spinand_to_mtd(spinand); 1252 1253 ret = mtd_device_unregister(mtd); 1254 if (ret) 1255 return ret; 1256 1257 spinand_cleanup(spinand); 1258 1259 return 0; 1260 } 1261 1262 static const struct spi_device_id spinand_ids[] = { 1263 { .name = "spi-nand" }, 1264 { /* sentinel */ }, 1265 }; 1266 1267 #ifdef CONFIG_OF 1268 static const struct of_device_id spinand_of_ids[] = { 1269 { .compatible = "spi-nand" }, 1270 { /* sentinel */ }, 1271 }; 1272 #endif 1273 1274 static struct spi_mem_driver spinand_drv = { 1275 .spidrv = { 1276 .id_table = spinand_ids, 1277 .driver = { 1278 .name = "spi-nand", 1279 .of_match_table = of_match_ptr(spinand_of_ids), 1280 }, 1281 }, 1282 .probe = spinand_probe, 1283 .remove = spinand_remove, 1284 }; 1285 module_spi_mem_driver(spinand_drv); 1286 1287 MODULE_DESCRIPTION("SPI NAND framework"); 1288 MODULE_AUTHOR("Peter Pan<peterpandong@micron.com>"); 1289 MODULE_LICENSE("GPL v2"); 1290