1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2008 Ilya Yanok, Emcraft Systems 4 */ 5 6 #include <linux/slab.h> 7 #include <linux/module.h> 8 #include <linux/mtd/mtd.h> 9 #include <linux/mtd/rawnand.h> 10 #include <linux/mtd/partitions.h> 11 #include <linux/of_address.h> 12 #include <linux/of_platform.h> 13 #include <linux/io.h> 14 15 #define FPGA_NAND_CMD_MASK (0x7 << 28) 16 #define FPGA_NAND_CMD_COMMAND (0x0 << 28) 17 #define FPGA_NAND_CMD_ADDR (0x1 << 28) 18 #define FPGA_NAND_CMD_READ (0x2 << 28) 19 #define FPGA_NAND_CMD_WRITE (0x3 << 28) 20 #define FPGA_NAND_BUSY (0x1 << 15) 21 #define FPGA_NAND_ENABLE (0x1 << 31) 22 #define FPGA_NAND_DATA_SHIFT 16 23 24 struct socrates_nand_host { 25 struct nand_chip nand_chip; 26 void __iomem *io_base; 27 struct device *dev; 28 }; 29 30 /** 31 * socrates_nand_write_buf - write buffer to chip 32 * @this: NAND chip object 33 * @buf: data buffer 34 * @len: number of bytes to write 35 */ 36 static void socrates_nand_write_buf(struct nand_chip *this, const uint8_t *buf, 37 int len) 38 { 39 int i; 40 struct socrates_nand_host *host = nand_get_controller_data(this); 41 42 for (i = 0; i < len; i++) { 43 out_be32(host->io_base, FPGA_NAND_ENABLE | 44 FPGA_NAND_CMD_WRITE | 45 (buf[i] << FPGA_NAND_DATA_SHIFT)); 46 } 47 } 48 49 /** 50 * socrates_nand_read_buf - read chip data into buffer 51 * @this: NAND chip object 52 * @buf: buffer to store date 53 * @len: number of bytes to read 54 */ 55 static void socrates_nand_read_buf(struct nand_chip *this, uint8_t *buf, 56 int len) 57 { 58 int i; 59 struct socrates_nand_host *host = nand_get_controller_data(this); 60 uint32_t val; 61 62 val = FPGA_NAND_ENABLE | FPGA_NAND_CMD_READ; 63 64 out_be32(host->io_base, val); 65 for (i = 0; i < len; i++) { 66 buf[i] = (in_be32(host->io_base) >> 67 FPGA_NAND_DATA_SHIFT) & 0xff; 68 } 69 } 70 71 /** 72 * socrates_nand_read_byte - read one byte from the chip 73 * @mtd: MTD device structure 74 */ 75 static uint8_t socrates_nand_read_byte(struct nand_chip *this) 76 { 77 uint8_t byte; 78 socrates_nand_read_buf(this, &byte, sizeof(byte)); 79 return byte; 80 } 81 82 /* 83 * Hardware specific access to control-lines 84 */ 85 static void socrates_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, 86 unsigned int ctrl) 87 { 88 struct socrates_nand_host *host = nand_get_controller_data(nand_chip); 89 uint32_t val; 90 91 if (cmd == NAND_CMD_NONE) 92 return; 93 94 if (ctrl & NAND_CLE) 95 val = FPGA_NAND_CMD_COMMAND; 96 else 97 val = FPGA_NAND_CMD_ADDR; 98 99 if (ctrl & NAND_NCE) 100 val |= FPGA_NAND_ENABLE; 101 102 val |= (cmd & 0xff) << FPGA_NAND_DATA_SHIFT; 103 104 out_be32(host->io_base, val); 105 } 106 107 /* 108 * Read the Device Ready pin. 109 */ 110 static int socrates_nand_device_ready(struct nand_chip *nand_chip) 111 { 112 struct socrates_nand_host *host = nand_get_controller_data(nand_chip); 113 114 if (in_be32(host->io_base) & FPGA_NAND_BUSY) 115 return 0; /* busy */ 116 return 1; 117 } 118 119 /* 120 * Probe for the NAND device. 121 */ 122 static int socrates_nand_probe(struct platform_device *ofdev) 123 { 124 struct socrates_nand_host *host; 125 struct mtd_info *mtd; 126 struct nand_chip *nand_chip; 127 int res; 128 129 /* Allocate memory for the device structure (and zero it) */ 130 host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL); 131 if (!host) 132 return -ENOMEM; 133 134 host->io_base = of_iomap(ofdev->dev.of_node, 0); 135 if (host->io_base == NULL) { 136 dev_err(&ofdev->dev, "ioremap failed\n"); 137 return -EIO; 138 } 139 140 nand_chip = &host->nand_chip; 141 mtd = nand_to_mtd(nand_chip); 142 host->dev = &ofdev->dev; 143 144 /* link the private data structures */ 145 nand_set_controller_data(nand_chip, host); 146 nand_set_flash_node(nand_chip, ofdev->dev.of_node); 147 mtd->name = "socrates_nand"; 148 mtd->dev.parent = &ofdev->dev; 149 150 nand_chip->legacy.cmd_ctrl = socrates_nand_cmd_ctrl; 151 nand_chip->legacy.read_byte = socrates_nand_read_byte; 152 nand_chip->legacy.write_buf = socrates_nand_write_buf; 153 nand_chip->legacy.read_buf = socrates_nand_read_buf; 154 nand_chip->legacy.dev_ready = socrates_nand_device_ready; 155 156 nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ 157 nand_chip->ecc.algo = NAND_ECC_HAMMING; 158 159 /* TODO: I have no idea what real delay is. */ 160 nand_chip->legacy.chip_delay = 20; /* 20us command delay time */ 161 162 dev_set_drvdata(&ofdev->dev, host); 163 164 res = nand_scan(nand_chip, 1); 165 if (res) 166 goto out; 167 168 res = mtd_device_register(mtd, NULL, 0); 169 if (!res) 170 return res; 171 172 nand_release(nand_chip); 173 174 out: 175 iounmap(host->io_base); 176 return res; 177 } 178 179 /* 180 * Remove a NAND device. 181 */ 182 static int socrates_nand_remove(struct platform_device *ofdev) 183 { 184 struct socrates_nand_host *host = dev_get_drvdata(&ofdev->dev); 185 186 nand_release(&host->nand_chip); 187 188 iounmap(host->io_base); 189 190 return 0; 191 } 192 193 static const struct of_device_id socrates_nand_match[] = 194 { 195 { 196 .compatible = "abb,socrates-nand", 197 }, 198 {}, 199 }; 200 201 MODULE_DEVICE_TABLE(of, socrates_nand_match); 202 203 static struct platform_driver socrates_nand_driver = { 204 .driver = { 205 .name = "socrates_nand", 206 .of_match_table = socrates_nand_match, 207 }, 208 .probe = socrates_nand_probe, 209 .remove = socrates_nand_remove, 210 }; 211 212 module_platform_driver(socrates_nand_driver); 213 214 MODULE_LICENSE("GPL"); 215 MODULE_AUTHOR("Ilya Yanok"); 216 MODULE_DESCRIPTION("NAND driver for Socrates board"); 217