1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Rockchip NAND Flash controller driver. 4 * Copyright (C) 2020 Rockchip Inc. 5 * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/mtd/mtd.h> 16 #include <linux/mtd/rawnand.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 21 /* 22 * NFC Page Data Layout: 23 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + 24 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + 25 * ...... 26 * NAND Page Data Layout: 27 * 1024 * n data + m Bytes oob 28 * Original Bad Block Mask Location: 29 * First byte of oob(spare). 30 * nand_chip->oob_poi data layout: 31 * 4Bytes sys data + .... + 4Bytes sys data + ECC data. 32 */ 33 34 /* NAND controller register definition */ 35 #define NFC_READ (0) 36 #define NFC_WRITE (1) 37 38 #define NFC_FMCTL (0x00) 39 #define FMCTL_CE_SEL_M 0xFF 40 #define FMCTL_CE_SEL(x) (1 << (x)) 41 #define FMCTL_WP BIT(8) 42 #define FMCTL_RDY BIT(9) 43 44 #define NFC_FMWAIT (0x04) 45 #define FLCTL_RST BIT(0) 46 #define FLCTL_WR (1) /* 0: read, 1: write */ 47 #define FLCTL_XFER_ST BIT(2) 48 #define FLCTL_XFER_EN BIT(3) 49 #define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */ 50 #define FLCTL_XFER_READY BIT(20) 51 #define FLCTL_XFER_SECTOR (22) 52 #define FLCTL_TOG_FIX BIT(29) 53 54 #define BCHCTL_BANK_M (7 << 5) 55 #define BCHCTL_BANK (5) 56 57 #define DMA_ST BIT(0) 58 #define DMA_WR (1) /* 0: write, 1: read */ 59 #define DMA_EN BIT(2) 60 #define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */ 61 #define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */ 62 #define DMA_INC_NUM (9) /* 1 - 16 */ 63 64 #define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\ 65 (((x) >> (e).high) & (e).high_mask) << (e).low_bn) 66 #define INT_DMA BIT(0) 67 #define NFC_BANK (0x800) 68 #define NFC_BANK_STEP (0x100) 69 #define BANK_DATA (0x00) 70 #define BANK_ADDR (0x04) 71 #define BANK_CMD (0x08) 72 #define NFC_SRAM0 (0x1000) 73 #define NFC_SRAM1 (0x1400) 74 #define NFC_SRAM_SIZE (0x400) 75 #define NFC_TIMEOUT (500000) 76 #define NFC_MAX_OOB_PER_STEP 128 77 #define NFC_MIN_OOB_PER_STEP 64 78 #define MAX_DATA_SIZE 0xFFFC 79 #define MAX_ADDRESS_CYC 6 80 #define NFC_ECC_MAX_MODES 4 81 #define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */ 82 #define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/ 83 #define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */ 84 #define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs)) 85 86 enum nfc_type { 87 NFC_V6, 88 NFC_V8, 89 NFC_V9, 90 }; 91 92 /** 93 * struct rk_ecc_cnt_status: represent a ecc status data. 94 * @err_flag_bit: error flag bit index at register. 95 * @low: ECC count low bit index at register. 96 * @low_mask: mask bit. 97 * @low_bn: ECC count low bit number. 98 * @high: ECC count high bit index at register. 99 * @high_mask: mask bit 100 */ 101 struct ecc_cnt_status { 102 u8 err_flag_bit; 103 u8 low; 104 u8 low_mask; 105 u8 low_bn; 106 u8 high; 107 u8 high_mask; 108 }; 109 110 /** 111 * @type: NFC version 112 * @ecc_strengths: ECC strengths 113 * @ecc_cfgs: ECC config values 114 * @flctl_off: FLCTL register offset 115 * @bchctl_off: BCHCTL register offset 116 * @dma_data_buf_off: DMA_DATA_BUF register offset 117 * @dma_oob_buf_off: DMA_OOB_BUF register offset 118 * @dma_cfg_off: DMA_CFG register offset 119 * @dma_st_off: DMA_ST register offset 120 * @bch_st_off: BCG_ST register offset 121 * @randmz_off: RANDMZ register offset 122 * @int_en_off: interrupt enable register offset 123 * @int_clr_off: interrupt clean register offset 124 * @int_st_off: interrupt status register offset 125 * @oob0_off: oob0 register offset 126 * @oob1_off: oob1 register offset 127 * @ecc0: represent ECC0 status data 128 * @ecc1: represent ECC1 status data 129 */ 130 struct nfc_cfg { 131 enum nfc_type type; 132 u8 ecc_strengths[NFC_ECC_MAX_MODES]; 133 u32 ecc_cfgs[NFC_ECC_MAX_MODES]; 134 u32 flctl_off; 135 u32 bchctl_off; 136 u32 dma_cfg_off; 137 u32 dma_data_buf_off; 138 u32 dma_oob_buf_off; 139 u32 dma_st_off; 140 u32 bch_st_off; 141 u32 randmz_off; 142 u32 int_en_off; 143 u32 int_clr_off; 144 u32 int_st_off; 145 u32 oob0_off; 146 u32 oob1_off; 147 struct ecc_cnt_status ecc0; 148 struct ecc_cnt_status ecc1; 149 }; 150 151 struct rk_nfc_nand_chip { 152 struct list_head node; 153 struct nand_chip chip; 154 155 u16 boot_blks; 156 u16 metadata_size; 157 u32 boot_ecc; 158 u32 timing; 159 160 u8 nsels; 161 u8 sels[] __counted_by(nsels); 162 }; 163 164 struct rk_nfc { 165 struct nand_controller controller; 166 const struct nfc_cfg *cfg; 167 struct device *dev; 168 169 struct clk *nfc_clk; 170 struct clk *ahb_clk; 171 void __iomem *regs; 172 173 u32 selected_bank; 174 u32 band_offset; 175 u32 cur_ecc; 176 u32 cur_timing; 177 178 struct completion done; 179 struct list_head chips; 180 181 u8 *page_buf; 182 u32 *oob_buf; 183 u32 page_buf_size; 184 u32 oob_buf_size; 185 186 unsigned long assigned_cs; 187 }; 188 189 static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip) 190 { 191 return container_of(chip, struct rk_nfc_nand_chip, chip); 192 } 193 194 static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i) 195 { 196 return (u8 *)p + i * chip->ecc.size; 197 } 198 199 static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i) 200 { 201 u8 *poi; 202 203 poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE; 204 205 return poi; 206 } 207 208 static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i) 209 { 210 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 211 u8 *poi; 212 213 poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i; 214 215 return poi; 216 } 217 218 static inline int rk_nfc_data_len(struct nand_chip *chip) 219 { 220 return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE; 221 } 222 223 static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i) 224 { 225 struct rk_nfc *nfc = nand_get_controller_data(chip); 226 227 return nfc->page_buf + i * rk_nfc_data_len(chip); 228 } 229 230 static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i) 231 { 232 struct rk_nfc *nfc = nand_get_controller_data(chip); 233 234 return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size; 235 } 236 237 static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength) 238 { 239 struct rk_nfc *nfc = nand_get_controller_data(chip); 240 u32 reg, i; 241 242 for (i = 0; i < NFC_ECC_MAX_MODES; i++) { 243 if (strength == nfc->cfg->ecc_strengths[i]) { 244 reg = nfc->cfg->ecc_cfgs[i]; 245 break; 246 } 247 } 248 249 if (i >= NFC_ECC_MAX_MODES) 250 return -EINVAL; 251 252 writel(reg, nfc->regs + nfc->cfg->bchctl_off); 253 254 /* Save chip ECC setting */ 255 nfc->cur_ecc = strength; 256 257 return 0; 258 } 259 260 static void rk_nfc_select_chip(struct nand_chip *chip, int cs) 261 { 262 struct rk_nfc *nfc = nand_get_controller_data(chip); 263 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 264 struct nand_ecc_ctrl *ecc = &chip->ecc; 265 u32 val; 266 267 if (cs < 0) { 268 nfc->selected_bank = -1; 269 /* Deselect the currently selected target. */ 270 val = readl_relaxed(nfc->regs + NFC_FMCTL); 271 val &= ~FMCTL_CE_SEL_M; 272 writel(val, nfc->regs + NFC_FMCTL); 273 return; 274 } 275 276 nfc->selected_bank = rknand->sels[cs]; 277 nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP; 278 279 val = readl_relaxed(nfc->regs + NFC_FMCTL); 280 val &= ~FMCTL_CE_SEL_M; 281 val |= FMCTL_CE_SEL(nfc->selected_bank); 282 283 writel(val, nfc->regs + NFC_FMCTL); 284 285 /* 286 * Compare current chip timing with selected chip timing and 287 * change if needed. 288 */ 289 if (nfc->cur_timing != rknand->timing) { 290 writel(rknand->timing, nfc->regs + NFC_FMWAIT); 291 nfc->cur_timing = rknand->timing; 292 } 293 294 /* 295 * Compare current chip ECC setting with selected chip ECC setting and 296 * change if needed. 297 */ 298 if (nfc->cur_ecc != ecc->strength) 299 rk_nfc_hw_ecc_setup(chip, ecc->strength); 300 } 301 302 static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc) 303 { 304 int rc; 305 u32 val; 306 307 rc = readl_relaxed_poll_timeout(nfc->regs + NFC_FMCTL, val, 308 val & FMCTL_RDY, 10, NFC_TIMEOUT); 309 310 return rc; 311 } 312 313 static void rk_nfc_read_buf(struct rk_nfc *nfc, u8 *buf, int len) 314 { 315 int i; 316 317 for (i = 0; i < len; i++) 318 buf[i] = readb_relaxed(nfc->regs + nfc->band_offset + 319 BANK_DATA); 320 } 321 322 static void rk_nfc_write_buf(struct rk_nfc *nfc, const u8 *buf, int len) 323 { 324 int i; 325 326 for (i = 0; i < len; i++) 327 writeb(buf[i], nfc->regs + nfc->band_offset + BANK_DATA); 328 } 329 330 static int rk_nfc_cmd(struct nand_chip *chip, 331 const struct nand_subop *subop) 332 { 333 struct rk_nfc *nfc = nand_get_controller_data(chip); 334 unsigned int i, j, remaining, start; 335 int reg_offset = nfc->band_offset; 336 u8 *inbuf = NULL; 337 const u8 *outbuf; 338 u32 cnt = 0; 339 int ret = 0; 340 341 for (i = 0; i < subop->ninstrs; i++) { 342 const struct nand_op_instr *instr = &subop->instrs[i]; 343 344 switch (instr->type) { 345 case NAND_OP_CMD_INSTR: 346 writeb(instr->ctx.cmd.opcode, 347 nfc->regs + reg_offset + BANK_CMD); 348 break; 349 350 case NAND_OP_ADDR_INSTR: 351 remaining = nand_subop_get_num_addr_cyc(subop, i); 352 start = nand_subop_get_addr_start_off(subop, i); 353 354 for (j = 0; j < 8 && j + start < remaining; j++) 355 writeb(instr->ctx.addr.addrs[j + start], 356 nfc->regs + reg_offset + BANK_ADDR); 357 break; 358 359 case NAND_OP_DATA_IN_INSTR: 360 case NAND_OP_DATA_OUT_INSTR: 361 start = nand_subop_get_data_start_off(subop, i); 362 cnt = nand_subop_get_data_len(subop, i); 363 364 if (instr->type == NAND_OP_DATA_OUT_INSTR) { 365 outbuf = instr->ctx.data.buf.out + start; 366 rk_nfc_write_buf(nfc, outbuf, cnt); 367 } else { 368 inbuf = instr->ctx.data.buf.in + start; 369 rk_nfc_read_buf(nfc, inbuf, cnt); 370 } 371 break; 372 373 case NAND_OP_WAITRDY_INSTR: 374 if (rk_nfc_wait_ioready(nfc) < 0) { 375 ret = -ETIMEDOUT; 376 dev_err(nfc->dev, "IO not ready\n"); 377 } 378 break; 379 } 380 } 381 382 return ret; 383 } 384 385 static const struct nand_op_parser rk_nfc_op_parser = NAND_OP_PARSER( 386 NAND_OP_PARSER_PATTERN( 387 rk_nfc_cmd, 388 NAND_OP_PARSER_PAT_CMD_ELEM(true), 389 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC), 390 NAND_OP_PARSER_PAT_CMD_ELEM(true), 391 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), 392 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)), 393 NAND_OP_PARSER_PATTERN( 394 rk_nfc_cmd, 395 NAND_OP_PARSER_PAT_CMD_ELEM(true), 396 NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYC), 397 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, MAX_DATA_SIZE), 398 NAND_OP_PARSER_PAT_CMD_ELEM(true), 399 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)), 400 ); 401 402 static int rk_nfc_exec_op(struct nand_chip *chip, 403 const struct nand_operation *op, 404 bool check_only) 405 { 406 if (!check_only) 407 rk_nfc_select_chip(chip, op->cs); 408 409 return nand_op_parser_exec_op(chip, &rk_nfc_op_parser, op, 410 check_only); 411 } 412 413 static int rk_nfc_setup_interface(struct nand_chip *chip, int target, 414 const struct nand_interface_config *conf) 415 { 416 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 417 struct rk_nfc *nfc = nand_get_controller_data(chip); 418 const struct nand_sdr_timings *timings; 419 u32 rate, tc2rw, trwpw, trw2c; 420 u32 temp; 421 422 if (target < 0) 423 return 0; 424 425 timings = nand_get_sdr_timings(conf); 426 if (IS_ERR(timings)) 427 return -EOPNOTSUPP; 428 429 if (IS_ERR(nfc->nfc_clk)) 430 rate = clk_get_rate(nfc->ahb_clk); 431 else 432 rate = clk_get_rate(nfc->nfc_clk); 433 434 /* Turn clock rate into kHz. */ 435 rate /= 1000; 436 437 tc2rw = 1; 438 trw2c = 1; 439 440 trwpw = max(timings->tWC_min, timings->tRC_min) / 1000; 441 trwpw = DIV_ROUND_UP(trwpw * rate, 1000000); 442 443 temp = timings->tREA_max / 1000; 444 temp = DIV_ROUND_UP(temp * rate, 1000000); 445 446 if (trwpw < temp) 447 trwpw = temp; 448 449 /* 450 * ACCON: access timing control register 451 * ------------------------------------- 452 * 31:18: reserved 453 * 17:12: csrw, clock cycles from the falling edge of CSn to the 454 * falling edge of RDn or WRn 455 * 11:11: reserved 456 * 10:05: rwpw, the width of RDn or WRn in processor clock cycles 457 * 04:00: rwcs, clock cycles from the rising edge of RDn or WRn to the 458 * rising edge of CSn 459 */ 460 461 /* Save chip timing */ 462 rknand->timing = ACCTIMING(tc2rw, trwpw, trw2c); 463 464 return 0; 465 } 466 467 static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB, 468 dma_addr_t dma_data, dma_addr_t dma_oob) 469 { 470 u32 dma_reg, fl_reg, bch_reg; 471 472 dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) | 473 (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM); 474 475 fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT | 476 (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX; 477 478 if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) { 479 bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off); 480 bch_reg = (bch_reg & (~BCHCTL_BANK_M)) | 481 (nfc->selected_bank << BCHCTL_BANK); 482 writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off); 483 } 484 485 writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off); 486 writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off); 487 writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off); 488 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); 489 fl_reg |= FLCTL_XFER_ST; 490 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); 491 } 492 493 static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc) 494 { 495 void __iomem *ptr; 496 u32 reg; 497 498 ptr = nfc->regs + nfc->cfg->flctl_off; 499 500 return readl_relaxed_poll_timeout(ptr, reg, 501 reg & FLCTL_XFER_READY, 502 10, NFC_TIMEOUT); 503 } 504 505 static int rk_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf, 506 int oob_on, int page) 507 { 508 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 509 struct rk_nfc *nfc = nand_get_controller_data(chip); 510 struct mtd_info *mtd = nand_to_mtd(chip); 511 struct nand_ecc_ctrl *ecc = &chip->ecc; 512 int i, pages_per_blk; 513 514 pages_per_blk = mtd->erasesize / mtd->writesize; 515 if ((chip->options & NAND_IS_BOOT_MEDIUM) && 516 (page < (pages_per_blk * rknand->boot_blks)) && 517 rknand->boot_ecc != ecc->strength) { 518 /* 519 * There's currently no method to notify the MTD framework that 520 * a different ECC strength is in use for the boot blocks. 521 */ 522 return -EIO; 523 } 524 525 if (!buf) 526 memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize); 527 528 for (i = 0; i < ecc->steps; i++) { 529 /* Copy data to the NFC buffer. */ 530 if (buf) 531 memcpy(rk_nfc_data_ptr(chip, i), 532 rk_nfc_buf_to_data_ptr(chip, buf, i), 533 ecc->size); 534 /* 535 * The first four bytes of OOB are reserved for the 536 * boot ROM. In some debugging cases, such as with a 537 * read, erase and write back test these 4 bytes stored 538 * in OOB also need to be written back. 539 * 540 * The function nand_block_bad detects bad blocks like: 541 * 542 * bad = chip->oob_poi[chip->badblockpos]; 543 * 544 * chip->badblockpos == 0 for a large page NAND Flash, 545 * so chip->oob_poi[0] is the bad block mask (BBM). 546 * 547 * The OOB data layout on the NFC is: 548 * 549 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... 550 * 551 * or 552 * 553 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... 554 * 555 * The code here just swaps the first 4 bytes with the last 556 * 4 bytes without losing any data. 557 * 558 * The chip->oob_poi data layout: 559 * 560 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 561 * 562 * The rk_nfc_ooblayout_free() function already has reserved 563 * these 4 bytes together with 2 bytes for BBM 564 * by reducing it's length: 565 * 566 * oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; 567 */ 568 if (!i) 569 memcpy(rk_nfc_oob_ptr(chip, i), 570 rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), 571 NFC_SYS_DATA_SIZE); 572 else 573 memcpy(rk_nfc_oob_ptr(chip, i), 574 rk_nfc_buf_to_oob_ptr(chip, i - 1), 575 NFC_SYS_DATA_SIZE); 576 /* Copy ECC data to the NFC buffer. */ 577 memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, 578 rk_nfc_buf_to_oob_ecc_ptr(chip, i), 579 ecc->bytes); 580 } 581 582 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 583 rk_nfc_write_buf(nfc, buf, mtd->writesize + mtd->oobsize); 584 return nand_prog_page_end_op(chip); 585 } 586 587 static int rk_nfc_write_page_hwecc(struct nand_chip *chip, const u8 *buf, 588 int oob_on, int page) 589 { 590 struct mtd_info *mtd = nand_to_mtd(chip); 591 struct rk_nfc *nfc = nand_get_controller_data(chip); 592 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 593 struct nand_ecc_ctrl *ecc = &chip->ecc; 594 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : 595 NFC_MIN_OOB_PER_STEP; 596 int pages_per_blk = mtd->erasesize / mtd->writesize; 597 int ret = 0, i, boot_rom_mode = 0; 598 dma_addr_t dma_data, dma_oob; 599 u32 tmp; 600 u8 *oob; 601 602 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 603 604 if (buf) 605 memcpy(nfc->page_buf, buf, mtd->writesize); 606 else 607 memset(nfc->page_buf, 0xFF, mtd->writesize); 608 609 /* 610 * The first blocks (4, 8 or 16 depending on the device) are used 611 * by the boot ROM and the first 32 bits of OOB need to link to 612 * the next page address in the same block. We can't directly copy 613 * OOB data from the MTD framework, because this page address 614 * conflicts for example with the bad block marker (BBM), 615 * so we shift all OOB data including the BBM with 4 byte positions. 616 * As a consequence the OOB size available to the MTD framework is 617 * also reduced with 4 bytes. 618 * 619 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... 620 * 621 * If a NAND is not a boot medium or the page is not a boot block, 622 * the first 4 bytes are left untouched by writing 0xFF to them. 623 * 624 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... 625 * 626 * The code here just swaps the first 4 bytes with the last 627 * 4 bytes without losing any data. 628 * 629 * The chip->oob_poi data layout: 630 * 631 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 632 * 633 * Configure the ECC algorithm supported by the boot ROM. 634 */ 635 if ((page < (pages_per_blk * rknand->boot_blks)) && 636 (chip->options & NAND_IS_BOOT_MEDIUM)) { 637 boot_rom_mode = 1; 638 if (rknand->boot_ecc != ecc->strength) 639 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); 640 } 641 642 for (i = 0; i < ecc->steps; i++) { 643 if (!i) 644 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; 645 else 646 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; 647 648 tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24; 649 650 if (nfc->cfg->type == NFC_V9) 651 nfc->oob_buf[i] = tmp; 652 else 653 nfc->oob_buf[i * (oob_step / 4)] = tmp; 654 } 655 656 dma_data = dma_map_single(nfc->dev, (void *)nfc->page_buf, 657 mtd->writesize, DMA_TO_DEVICE); 658 dma_oob = dma_map_single(nfc->dev, nfc->oob_buf, 659 ecc->steps * oob_step, 660 DMA_TO_DEVICE); 661 662 reinit_completion(&nfc->done); 663 writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off); 664 665 rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data, 666 dma_oob); 667 ret = wait_for_completion_timeout(&nfc->done, 668 msecs_to_jiffies(100)); 669 if (!ret) 670 dev_warn(nfc->dev, "write: wait dma done timeout.\n"); 671 /* 672 * Whether the DMA transfer is completed or not. The driver 673 * needs to check the NFC`s status register to see if the data 674 * transfer was completed. 675 */ 676 ret = rk_nfc_wait_for_xfer_done(nfc); 677 678 dma_unmap_single(nfc->dev, dma_data, mtd->writesize, 679 DMA_TO_DEVICE); 680 dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step, 681 DMA_TO_DEVICE); 682 683 if (boot_rom_mode && rknand->boot_ecc != ecc->strength) 684 rk_nfc_hw_ecc_setup(chip, ecc->strength); 685 686 if (ret) { 687 dev_err(nfc->dev, "write: wait transfer done timeout.\n"); 688 return -ETIMEDOUT; 689 } 690 691 return nand_prog_page_end_op(chip); 692 } 693 694 static int rk_nfc_write_oob(struct nand_chip *chip, int page) 695 { 696 return rk_nfc_write_page_hwecc(chip, NULL, 1, page); 697 } 698 699 static int rk_nfc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_on, 700 int page) 701 { 702 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 703 struct rk_nfc *nfc = nand_get_controller_data(chip); 704 struct mtd_info *mtd = nand_to_mtd(chip); 705 struct nand_ecc_ctrl *ecc = &chip->ecc; 706 int i, pages_per_blk; 707 708 pages_per_blk = mtd->erasesize / mtd->writesize; 709 if ((chip->options & NAND_IS_BOOT_MEDIUM) && 710 (page < (pages_per_blk * rknand->boot_blks)) && 711 rknand->boot_ecc != ecc->strength) { 712 /* 713 * There's currently no method to notify the MTD framework that 714 * a different ECC strength is in use for the boot blocks. 715 */ 716 return -EIO; 717 } 718 719 nand_read_page_op(chip, page, 0, NULL, 0); 720 rk_nfc_read_buf(nfc, nfc->page_buf, mtd->writesize + mtd->oobsize); 721 for (i = 0; i < ecc->steps; i++) { 722 /* 723 * The first four bytes of OOB are reserved for the 724 * boot ROM. In some debugging cases, such as with a read, 725 * erase and write back test, these 4 bytes also must be 726 * saved somewhere, otherwise this information will be 727 * lost during a write back. 728 */ 729 if (!i) 730 memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), 731 rk_nfc_oob_ptr(chip, i), 732 NFC_SYS_DATA_SIZE); 733 else 734 memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1), 735 rk_nfc_oob_ptr(chip, i), 736 NFC_SYS_DATA_SIZE); 737 738 /* Copy ECC data from the NFC buffer. */ 739 memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i), 740 rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, 741 ecc->bytes); 742 743 /* Copy data from the NFC buffer. */ 744 if (buf) 745 memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i), 746 rk_nfc_data_ptr(chip, i), 747 ecc->size); 748 } 749 750 return 0; 751 } 752 753 static int rk_nfc_read_page_hwecc(struct nand_chip *chip, u8 *buf, int oob_on, 754 int page) 755 { 756 struct mtd_info *mtd = nand_to_mtd(chip); 757 struct rk_nfc *nfc = nand_get_controller_data(chip); 758 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 759 struct nand_ecc_ctrl *ecc = &chip->ecc; 760 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : 761 NFC_MIN_OOB_PER_STEP; 762 int pages_per_blk = mtd->erasesize / mtd->writesize; 763 dma_addr_t dma_data, dma_oob; 764 int ret = 0, i, cnt, boot_rom_mode = 0; 765 int max_bitflips = 0, bch_st, ecc_fail = 0; 766 u8 *oob; 767 u32 tmp; 768 769 nand_read_page_op(chip, page, 0, NULL, 0); 770 771 dma_data = dma_map_single(nfc->dev, nfc->page_buf, 772 mtd->writesize, 773 DMA_FROM_DEVICE); 774 dma_oob = dma_map_single(nfc->dev, nfc->oob_buf, 775 ecc->steps * oob_step, 776 DMA_FROM_DEVICE); 777 778 /* 779 * The first blocks (4, 8 or 16 depending on the device) 780 * are used by the boot ROM. 781 * Configure the ECC algorithm supported by the boot ROM. 782 */ 783 if ((page < (pages_per_blk * rknand->boot_blks)) && 784 (chip->options & NAND_IS_BOOT_MEDIUM)) { 785 boot_rom_mode = 1; 786 if (rknand->boot_ecc != ecc->strength) 787 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); 788 } 789 790 reinit_completion(&nfc->done); 791 writel(INT_DMA, nfc->regs + nfc->cfg->int_en_off); 792 rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data, 793 dma_oob); 794 ret = wait_for_completion_timeout(&nfc->done, 795 msecs_to_jiffies(100)); 796 if (!ret) 797 dev_warn(nfc->dev, "read: wait dma done timeout.\n"); 798 /* 799 * Whether the DMA transfer is completed or not. The driver 800 * needs to check the NFC`s status register to see if the data 801 * transfer was completed. 802 */ 803 ret = rk_nfc_wait_for_xfer_done(nfc); 804 805 dma_unmap_single(nfc->dev, dma_data, mtd->writesize, 806 DMA_FROM_DEVICE); 807 dma_unmap_single(nfc->dev, dma_oob, ecc->steps * oob_step, 808 DMA_FROM_DEVICE); 809 810 if (ret) { 811 ret = -ETIMEDOUT; 812 dev_err(nfc->dev, "read: wait transfer done timeout.\n"); 813 goto timeout_err; 814 } 815 816 for (i = 0; i < ecc->steps; i++) { 817 if (!i) 818 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; 819 else 820 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; 821 822 if (nfc->cfg->type == NFC_V9) 823 tmp = nfc->oob_buf[i]; 824 else 825 tmp = nfc->oob_buf[i * (oob_step / 4)]; 826 827 *oob++ = (u8)tmp; 828 *oob++ = (u8)(tmp >> 8); 829 *oob++ = (u8)(tmp >> 16); 830 *oob++ = (u8)(tmp >> 24); 831 } 832 833 for (i = 0; i < (ecc->steps / 2); i++) { 834 bch_st = readl_relaxed(nfc->regs + 835 nfc->cfg->bch_st_off + i * 4); 836 if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) || 837 bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) { 838 mtd->ecc_stats.failed++; 839 ecc_fail = 1; 840 } else { 841 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0); 842 mtd->ecc_stats.corrected += cnt; 843 max_bitflips = max_t(u32, max_bitflips, cnt); 844 845 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1); 846 mtd->ecc_stats.corrected += cnt; 847 max_bitflips = max_t(u32, max_bitflips, cnt); 848 } 849 } 850 851 if (buf) 852 memcpy(buf, nfc->page_buf, mtd->writesize); 853 854 timeout_err: 855 if (boot_rom_mode && rknand->boot_ecc != ecc->strength) 856 rk_nfc_hw_ecc_setup(chip, ecc->strength); 857 858 if (ret) 859 return ret; 860 861 if (ecc_fail) { 862 dev_err(nfc->dev, "read page: %x ecc error!\n", page); 863 return 0; 864 } 865 866 return max_bitflips; 867 } 868 869 static int rk_nfc_read_oob(struct nand_chip *chip, int page) 870 { 871 return rk_nfc_read_page_hwecc(chip, NULL, 1, page); 872 } 873 874 static inline void rk_nfc_hw_init(struct rk_nfc *nfc) 875 { 876 /* Disable flash wp. */ 877 writel(FMCTL_WP, nfc->regs + NFC_FMCTL); 878 /* Config default timing 40ns at 150 Mhz NFC clock. */ 879 writel(0x1081, nfc->regs + NFC_FMWAIT); 880 nfc->cur_timing = 0x1081; 881 /* Disable randomizer and DMA. */ 882 writel(0, nfc->regs + nfc->cfg->randmz_off); 883 writel(0, nfc->regs + nfc->cfg->dma_cfg_off); 884 writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off); 885 } 886 887 static irqreturn_t rk_nfc_irq(int irq, void *id) 888 { 889 struct rk_nfc *nfc = id; 890 u32 sta, ien; 891 892 sta = readl_relaxed(nfc->regs + nfc->cfg->int_st_off); 893 ien = readl_relaxed(nfc->regs + nfc->cfg->int_en_off); 894 895 if (!(sta & ien)) 896 return IRQ_NONE; 897 898 writel(sta, nfc->regs + nfc->cfg->int_clr_off); 899 writel(~sta & ien, nfc->regs + nfc->cfg->int_en_off); 900 901 complete(&nfc->done); 902 903 return IRQ_HANDLED; 904 } 905 906 static int rk_nfc_enable_clks(struct device *dev, struct rk_nfc *nfc) 907 { 908 int ret; 909 910 if (!IS_ERR(nfc->nfc_clk)) { 911 ret = clk_prepare_enable(nfc->nfc_clk); 912 if (ret) { 913 dev_err(dev, "failed to enable NFC clk\n"); 914 return ret; 915 } 916 } 917 918 ret = clk_prepare_enable(nfc->ahb_clk); 919 if (ret) { 920 dev_err(dev, "failed to enable ahb clk\n"); 921 clk_disable_unprepare(nfc->nfc_clk); 922 return ret; 923 } 924 925 return 0; 926 } 927 928 static void rk_nfc_disable_clks(struct rk_nfc *nfc) 929 { 930 clk_disable_unprepare(nfc->nfc_clk); 931 clk_disable_unprepare(nfc->ahb_clk); 932 } 933 934 static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section, 935 struct mtd_oob_region *oob_region) 936 { 937 struct nand_chip *chip = mtd_to_nand(mtd); 938 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 939 940 if (section) 941 return -ERANGE; 942 943 oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; 944 oob_region->offset = 2; 945 946 return 0; 947 } 948 949 static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, 950 struct mtd_oob_region *oob_region) 951 { 952 struct nand_chip *chip = mtd_to_nand(mtd); 953 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 954 955 if (section) 956 return -ERANGE; 957 958 oob_region->length = mtd->oobsize - rknand->metadata_size; 959 oob_region->offset = rknand->metadata_size; 960 961 return 0; 962 } 963 964 static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = { 965 .free = rk_nfc_ooblayout_free, 966 .ecc = rk_nfc_ooblayout_ecc, 967 }; 968 969 static int rk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 970 { 971 struct nand_chip *chip = mtd_to_nand(mtd); 972 struct rk_nfc *nfc = nand_get_controller_data(chip); 973 struct nand_ecc_ctrl *ecc = &chip->ecc; 974 const u8 *strengths = nfc->cfg->ecc_strengths; 975 u8 max_strength, nfc_max_strength; 976 int i; 977 978 nfc_max_strength = nfc->cfg->ecc_strengths[0]; 979 /* If optional dt settings not present. */ 980 if (!ecc->size || !ecc->strength || 981 ecc->strength > nfc_max_strength) { 982 chip->ecc.size = 1024; 983 ecc->steps = mtd->writesize / ecc->size; 984 985 /* 986 * HW ECC always requests the number of ECC bytes per 1024 byte 987 * blocks. The first 4 OOB bytes are reserved for sys data. 988 */ 989 max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 / 990 fls(8 * 1024); 991 if (max_strength > nfc_max_strength) 992 max_strength = nfc_max_strength; 993 994 for (i = 0; i < 4; i++) { 995 if (max_strength >= strengths[i]) 996 break; 997 } 998 999 if (i >= 4) { 1000 dev_err(nfc->dev, "unsupported ECC strength\n"); 1001 return -EOPNOTSUPP; 1002 } 1003 1004 ecc->strength = strengths[i]; 1005 } 1006 ecc->steps = mtd->writesize / ecc->size; 1007 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8); 1008 1009 return 0; 1010 } 1011 1012 static int rk_nfc_attach_chip(struct nand_chip *chip) 1013 { 1014 struct mtd_info *mtd = nand_to_mtd(chip); 1015 struct device *dev = mtd->dev.parent; 1016 struct rk_nfc *nfc = nand_get_controller_data(chip); 1017 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 1018 struct nand_ecc_ctrl *ecc = &chip->ecc; 1019 int new_page_len, new_oob_len; 1020 void *buf; 1021 int ret; 1022 1023 if (chip->options & NAND_BUSWIDTH_16) { 1024 dev_err(dev, "16 bits bus width not supported"); 1025 return -EINVAL; 1026 } 1027 1028 if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 1029 return 0; 1030 1031 ret = rk_nfc_ecc_init(dev, mtd); 1032 if (ret) 1033 return ret; 1034 1035 rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; 1036 1037 if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { 1038 dev_err(dev, 1039 "driver needs at least %d bytes of meta data\n", 1040 NFC_SYS_DATA_SIZE + 2); 1041 return -EIO; 1042 } 1043 1044 /* Check buffer first, avoid duplicate alloc buffer. */ 1045 new_page_len = mtd->writesize + mtd->oobsize; 1046 if (nfc->page_buf && new_page_len > nfc->page_buf_size) { 1047 buf = krealloc(nfc->page_buf, new_page_len, 1048 GFP_KERNEL | GFP_DMA); 1049 if (!buf) 1050 return -ENOMEM; 1051 nfc->page_buf = buf; 1052 nfc->page_buf_size = new_page_len; 1053 } 1054 1055 new_oob_len = ecc->steps * NFC_MAX_OOB_PER_STEP; 1056 if (nfc->oob_buf && new_oob_len > nfc->oob_buf_size) { 1057 buf = krealloc(nfc->oob_buf, new_oob_len, 1058 GFP_KERNEL | GFP_DMA); 1059 if (!buf) { 1060 kfree(nfc->page_buf); 1061 nfc->page_buf = NULL; 1062 return -ENOMEM; 1063 } 1064 nfc->oob_buf = buf; 1065 nfc->oob_buf_size = new_oob_len; 1066 } 1067 1068 if (!nfc->page_buf) { 1069 nfc->page_buf = kzalloc(new_page_len, GFP_KERNEL | GFP_DMA); 1070 if (!nfc->page_buf) 1071 return -ENOMEM; 1072 nfc->page_buf_size = new_page_len; 1073 } 1074 1075 if (!nfc->oob_buf) { 1076 nfc->oob_buf = kzalloc(new_oob_len, GFP_KERNEL | GFP_DMA); 1077 if (!nfc->oob_buf) { 1078 kfree(nfc->page_buf); 1079 nfc->page_buf = NULL; 1080 return -ENOMEM; 1081 } 1082 nfc->oob_buf_size = new_oob_len; 1083 } 1084 1085 chip->ecc.write_page_raw = rk_nfc_write_page_raw; 1086 chip->ecc.write_page = rk_nfc_write_page_hwecc; 1087 chip->ecc.write_oob = rk_nfc_write_oob; 1088 1089 chip->ecc.read_page_raw = rk_nfc_read_page_raw; 1090 chip->ecc.read_page = rk_nfc_read_page_hwecc; 1091 chip->ecc.read_oob = rk_nfc_read_oob; 1092 1093 return 0; 1094 } 1095 1096 static const struct nand_controller_ops rk_nfc_controller_ops = { 1097 .attach_chip = rk_nfc_attach_chip, 1098 .exec_op = rk_nfc_exec_op, 1099 .setup_interface = rk_nfc_setup_interface, 1100 }; 1101 1102 static int rk_nfc_nand_chip_init(struct device *dev, struct rk_nfc *nfc, 1103 struct device_node *np) 1104 { 1105 struct rk_nfc_nand_chip *rknand; 1106 struct nand_chip *chip; 1107 struct mtd_info *mtd; 1108 int nsels; 1109 u32 tmp; 1110 int ret; 1111 int i; 1112 1113 if (!of_get_property(np, "reg", &nsels)) 1114 return -ENODEV; 1115 nsels /= sizeof(u32); 1116 if (!nsels || nsels > NFC_MAX_NSELS) { 1117 dev_err(dev, "invalid reg property size %d\n", nsels); 1118 return -EINVAL; 1119 } 1120 1121 rknand = devm_kzalloc(dev, struct_size(rknand, sels, nsels), 1122 GFP_KERNEL); 1123 if (!rknand) 1124 return -ENOMEM; 1125 1126 rknand->nsels = nsels; 1127 for (i = 0; i < nsels; i++) { 1128 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1129 if (ret) { 1130 dev_err(dev, "reg property failure : %d\n", ret); 1131 return ret; 1132 } 1133 1134 if (tmp >= NFC_MAX_NSELS) { 1135 dev_err(dev, "invalid CS: %u\n", tmp); 1136 return -EINVAL; 1137 } 1138 1139 if (test_and_set_bit(tmp, &nfc->assigned_cs)) { 1140 dev_err(dev, "CS %u already assigned\n", tmp); 1141 return -EINVAL; 1142 } 1143 1144 rknand->sels[i] = tmp; 1145 } 1146 1147 chip = &rknand->chip; 1148 chip->controller = &nfc->controller; 1149 1150 nand_set_flash_node(chip, np); 1151 1152 nand_set_controller_data(chip, nfc); 1153 1154 chip->options |= NAND_USES_DMA | NAND_NO_SUBPAGE_WRITE; 1155 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 1156 1157 /* Set default mode in case dt entry is missing. */ 1158 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1159 1160 mtd = nand_to_mtd(chip); 1161 mtd->owner = THIS_MODULE; 1162 mtd->dev.parent = dev; 1163 1164 if (!mtd->name) { 1165 dev_err(nfc->dev, "NAND label property is mandatory\n"); 1166 return -EINVAL; 1167 } 1168 1169 mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops); 1170 rk_nfc_hw_init(nfc); 1171 ret = nand_scan(chip, nsels); 1172 if (ret) 1173 return ret; 1174 1175 if (chip->options & NAND_IS_BOOT_MEDIUM) { 1176 ret = of_property_read_u32(np, "rockchip,boot-blks", &tmp); 1177 rknand->boot_blks = ret ? 0 : tmp; 1178 1179 ret = of_property_read_u32(np, "rockchip,boot-ecc-strength", 1180 &tmp); 1181 rknand->boot_ecc = ret ? chip->ecc.strength : tmp; 1182 } 1183 1184 ret = mtd_device_register(mtd, NULL, 0); 1185 if (ret) { 1186 dev_err(dev, "MTD parse partition error\n"); 1187 nand_cleanup(chip); 1188 return ret; 1189 } 1190 1191 list_add_tail(&rknand->node, &nfc->chips); 1192 1193 return 0; 1194 } 1195 1196 static void rk_nfc_chips_cleanup(struct rk_nfc *nfc) 1197 { 1198 struct rk_nfc_nand_chip *rknand, *tmp; 1199 struct nand_chip *chip; 1200 int ret; 1201 1202 list_for_each_entry_safe(rknand, tmp, &nfc->chips, node) { 1203 chip = &rknand->chip; 1204 ret = mtd_device_unregister(nand_to_mtd(chip)); 1205 WARN_ON(ret); 1206 nand_cleanup(chip); 1207 list_del(&rknand->node); 1208 } 1209 } 1210 1211 static int rk_nfc_nand_chips_init(struct device *dev, struct rk_nfc *nfc) 1212 { 1213 struct device_node *np = dev->of_node, *nand_np; 1214 int nchips = of_get_child_count(np); 1215 int ret; 1216 1217 if (!nchips || nchips > NFC_MAX_NSELS) { 1218 dev_err(nfc->dev, "incorrect number of NAND chips (%d)\n", 1219 nchips); 1220 return -EINVAL; 1221 } 1222 1223 for_each_child_of_node(np, nand_np) { 1224 ret = rk_nfc_nand_chip_init(dev, nfc, nand_np); 1225 if (ret) { 1226 of_node_put(nand_np); 1227 rk_nfc_chips_cleanup(nfc); 1228 return ret; 1229 } 1230 } 1231 1232 return 0; 1233 } 1234 1235 static struct nfc_cfg nfc_v6_cfg = { 1236 .type = NFC_V6, 1237 .ecc_strengths = {60, 40, 24, 16}, 1238 .ecc_cfgs = { 1239 0x00040011, 0x00040001, 0x00000011, 0x00000001, 1240 }, 1241 .flctl_off = 0x08, 1242 .bchctl_off = 0x0C, 1243 .dma_cfg_off = 0x10, 1244 .dma_data_buf_off = 0x14, 1245 .dma_oob_buf_off = 0x18, 1246 .dma_st_off = 0x1C, 1247 .bch_st_off = 0x20, 1248 .randmz_off = 0x150, 1249 .int_en_off = 0x16C, 1250 .int_clr_off = 0x170, 1251 .int_st_off = 0x174, 1252 .oob0_off = 0x200, 1253 .oob1_off = 0x230, 1254 .ecc0 = { 1255 .err_flag_bit = 2, 1256 .low = 3, 1257 .low_mask = 0x1F, 1258 .low_bn = 5, 1259 .high = 27, 1260 .high_mask = 0x1, 1261 }, 1262 .ecc1 = { 1263 .err_flag_bit = 15, 1264 .low = 16, 1265 .low_mask = 0x1F, 1266 .low_bn = 5, 1267 .high = 29, 1268 .high_mask = 0x1, 1269 }, 1270 }; 1271 1272 static struct nfc_cfg nfc_v8_cfg = { 1273 .type = NFC_V8, 1274 .ecc_strengths = {16, 16, 16, 16}, 1275 .ecc_cfgs = { 1276 0x00000001, 0x00000001, 0x00000001, 0x00000001, 1277 }, 1278 .flctl_off = 0x08, 1279 .bchctl_off = 0x0C, 1280 .dma_cfg_off = 0x10, 1281 .dma_data_buf_off = 0x14, 1282 .dma_oob_buf_off = 0x18, 1283 .dma_st_off = 0x1C, 1284 .bch_st_off = 0x20, 1285 .randmz_off = 0x150, 1286 .int_en_off = 0x16C, 1287 .int_clr_off = 0x170, 1288 .int_st_off = 0x174, 1289 .oob0_off = 0x200, 1290 .oob1_off = 0x230, 1291 .ecc0 = { 1292 .err_flag_bit = 2, 1293 .low = 3, 1294 .low_mask = 0x1F, 1295 .low_bn = 5, 1296 .high = 27, 1297 .high_mask = 0x1, 1298 }, 1299 .ecc1 = { 1300 .err_flag_bit = 15, 1301 .low = 16, 1302 .low_mask = 0x1F, 1303 .low_bn = 5, 1304 .high = 29, 1305 .high_mask = 0x1, 1306 }, 1307 }; 1308 1309 static struct nfc_cfg nfc_v9_cfg = { 1310 .type = NFC_V9, 1311 .ecc_strengths = {70, 60, 40, 16}, 1312 .ecc_cfgs = { 1313 0x00000001, 0x06000001, 0x04000001, 0x02000001, 1314 }, 1315 .flctl_off = 0x10, 1316 .bchctl_off = 0x20, 1317 .dma_cfg_off = 0x30, 1318 .dma_data_buf_off = 0x34, 1319 .dma_oob_buf_off = 0x38, 1320 .dma_st_off = 0x3C, 1321 .bch_st_off = 0x150, 1322 .randmz_off = 0x208, 1323 .int_en_off = 0x120, 1324 .int_clr_off = 0x124, 1325 .int_st_off = 0x128, 1326 .oob0_off = 0x200, 1327 .oob1_off = 0x204, 1328 .ecc0 = { 1329 .err_flag_bit = 2, 1330 .low = 3, 1331 .low_mask = 0x7F, 1332 .low_bn = 7, 1333 .high = 0, 1334 .high_mask = 0x0, 1335 }, 1336 .ecc1 = { 1337 .err_flag_bit = 18, 1338 .low = 19, 1339 .low_mask = 0x7F, 1340 .low_bn = 7, 1341 .high = 0, 1342 .high_mask = 0x0, 1343 }, 1344 }; 1345 1346 static const struct of_device_id rk_nfc_id_table[] = { 1347 { 1348 .compatible = "rockchip,px30-nfc", 1349 .data = &nfc_v9_cfg 1350 }, 1351 { 1352 .compatible = "rockchip,rk2928-nfc", 1353 .data = &nfc_v6_cfg 1354 }, 1355 { 1356 .compatible = "rockchip,rv1108-nfc", 1357 .data = &nfc_v8_cfg 1358 }, 1359 { /* sentinel */ } 1360 }; 1361 MODULE_DEVICE_TABLE(of, rk_nfc_id_table); 1362 1363 static int rk_nfc_probe(struct platform_device *pdev) 1364 { 1365 struct device *dev = &pdev->dev; 1366 struct rk_nfc *nfc; 1367 int ret, irq; 1368 1369 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1370 if (!nfc) 1371 return -ENOMEM; 1372 1373 nand_controller_init(&nfc->controller); 1374 INIT_LIST_HEAD(&nfc->chips); 1375 nfc->controller.ops = &rk_nfc_controller_ops; 1376 1377 nfc->cfg = of_device_get_match_data(dev); 1378 nfc->dev = dev; 1379 1380 init_completion(&nfc->done); 1381 1382 nfc->regs = devm_platform_ioremap_resource(pdev, 0); 1383 if (IS_ERR(nfc->regs)) { 1384 ret = PTR_ERR(nfc->regs); 1385 goto release_nfc; 1386 } 1387 1388 nfc->nfc_clk = devm_clk_get(dev, "nfc"); 1389 if (IS_ERR(nfc->nfc_clk)) { 1390 dev_dbg(dev, "no NFC clk\n"); 1391 /* Some earlier models, such as rk3066, have no NFC clk. */ 1392 } 1393 1394 nfc->ahb_clk = devm_clk_get(dev, "ahb"); 1395 if (IS_ERR(nfc->ahb_clk)) { 1396 dev_err(dev, "no ahb clk\n"); 1397 ret = PTR_ERR(nfc->ahb_clk); 1398 goto release_nfc; 1399 } 1400 1401 ret = rk_nfc_enable_clks(dev, nfc); 1402 if (ret) 1403 goto release_nfc; 1404 1405 irq = platform_get_irq(pdev, 0); 1406 if (irq < 0) { 1407 ret = -EINVAL; 1408 goto clk_disable; 1409 } 1410 1411 writel(0, nfc->regs + nfc->cfg->int_en_off); 1412 ret = devm_request_irq(dev, irq, rk_nfc_irq, 0x0, "rk-nand", nfc); 1413 if (ret) { 1414 dev_err(dev, "failed to request NFC irq\n"); 1415 goto clk_disable; 1416 } 1417 1418 platform_set_drvdata(pdev, nfc); 1419 1420 ret = rk_nfc_nand_chips_init(dev, nfc); 1421 if (ret) { 1422 dev_err(dev, "failed to init NAND chips\n"); 1423 goto clk_disable; 1424 } 1425 return 0; 1426 1427 clk_disable: 1428 rk_nfc_disable_clks(nfc); 1429 release_nfc: 1430 return ret; 1431 } 1432 1433 static void rk_nfc_remove(struct platform_device *pdev) 1434 { 1435 struct rk_nfc *nfc = platform_get_drvdata(pdev); 1436 1437 kfree(nfc->page_buf); 1438 kfree(nfc->oob_buf); 1439 rk_nfc_chips_cleanup(nfc); 1440 rk_nfc_disable_clks(nfc); 1441 } 1442 1443 static int __maybe_unused rk_nfc_suspend(struct device *dev) 1444 { 1445 struct rk_nfc *nfc = dev_get_drvdata(dev); 1446 1447 rk_nfc_disable_clks(nfc); 1448 1449 return 0; 1450 } 1451 1452 static int __maybe_unused rk_nfc_resume(struct device *dev) 1453 { 1454 struct rk_nfc *nfc = dev_get_drvdata(dev); 1455 struct rk_nfc_nand_chip *rknand; 1456 struct nand_chip *chip; 1457 int ret; 1458 u32 i; 1459 1460 ret = rk_nfc_enable_clks(dev, nfc); 1461 if (ret) 1462 return ret; 1463 1464 /* Reset NAND chip if VCC was powered off. */ 1465 list_for_each_entry(rknand, &nfc->chips, node) { 1466 chip = &rknand->chip; 1467 for (i = 0; i < rknand->nsels; i++) 1468 nand_reset(chip, i); 1469 } 1470 1471 return 0; 1472 } 1473 1474 static const struct dev_pm_ops rk_nfc_pm_ops = { 1475 SET_SYSTEM_SLEEP_PM_OPS(rk_nfc_suspend, rk_nfc_resume) 1476 }; 1477 1478 static struct platform_driver rk_nfc_driver = { 1479 .probe = rk_nfc_probe, 1480 .remove_new = rk_nfc_remove, 1481 .driver = { 1482 .name = "rockchip-nfc", 1483 .of_match_table = rk_nfc_id_table, 1484 .pm = &rk_nfc_pm_ops, 1485 }, 1486 }; 1487 1488 module_platform_driver(rk_nfc_driver); 1489 1490 MODULE_LICENSE("Dual MIT/GPL"); 1491 MODULE_AUTHOR("Yifeng Zhao <yifeng.zhao@rock-chips.com>"); 1492 MODULE_DESCRIPTION("Rockchip Nand Flash Controller Driver"); 1493 MODULE_ALIAS("platform:rockchip-nand-controller"); 1494