xref: /linux/drivers/mtd/nand/raw/pasemi_nand.c (revision 7f356166aebb0d956d367dfe55e19d7783277d09)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2006-2007 PA Semi, Inc
4  *
5  * Author: Egor Martovetsky <egor@pasemi.com>
6  * Maintained by: Olof Johansson <olof@lixom.net>
7  *
8  * Driver for the PWRficient onchip NAND flash interface
9  */
10 
11 #undef DEBUG
12 
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/nand_ecc.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/pci.h>
23 
24 #include <asm/io.h>
25 
26 #define LBICTRL_LPCCTL_NR		0x00004000
27 #define CLE_PIN_CTL			15
28 #define ALE_PIN_CTL			14
29 
30 static unsigned int lpcctl;
31 static struct mtd_info *pasemi_nand_mtd;
32 static struct nand_controller controller;
33 static const char driver_name[] = "pasemi-nand";
34 
35 static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len)
36 {
37 	while (len > 0x800) {
38 		memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800);
39 		buf += 0x800;
40 		len -= 0x800;
41 	}
42 	memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len);
43 }
44 
45 static void pasemi_write_buf(struct nand_chip *chip, const u_char *buf,
46 			     int len)
47 {
48 	while (len > 0x800) {
49 		memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800);
50 		buf += 0x800;
51 		len -= 0x800;
52 	}
53 	memcpy_toio(chip->legacy.IO_ADDR_R, buf, len);
54 }
55 
56 static void pasemi_hwcontrol(struct nand_chip *chip, int cmd,
57 			     unsigned int ctrl)
58 {
59 	if (cmd == NAND_CMD_NONE)
60 		return;
61 
62 	if (ctrl & NAND_CLE)
63 		out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
64 	else
65 		out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
66 
67 	/* Push out posted writes */
68 	eieio();
69 	inl(lpcctl);
70 }
71 
72 static int pasemi_device_ready(struct nand_chip *chip)
73 {
74 	return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR);
75 }
76 
77 static int pasemi_attach_chip(struct nand_chip *chip)
78 {
79 	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
80 	chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
81 
82 	return 0;
83 }
84 
85 static const struct nand_controller_ops pasemi_ops = {
86 	.attach_chip = pasemi_attach_chip,
87 };
88 
89 static int pasemi_nand_probe(struct platform_device *ofdev)
90 {
91 	struct device *dev = &ofdev->dev;
92 	struct pci_dev *pdev;
93 	struct device_node *np = dev->of_node;
94 	struct resource res;
95 	struct nand_chip *chip;
96 	int err = 0;
97 
98 	err = of_address_to_resource(np, 0, &res);
99 
100 	if (err)
101 		return -EINVAL;
102 
103 	/* We only support one device at the moment */
104 	if (pasemi_nand_mtd)
105 		return -ENODEV;
106 
107 	dev_dbg(dev, "pasemi_nand at %pR\n", &res);
108 
109 	/* Allocate memory for MTD device structure and private data */
110 	chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
111 	if (!chip) {
112 		err = -ENOMEM;
113 		goto out;
114 	}
115 
116 	controller.ops = &pasemi_ops;
117 	nand_controller_init(&controller);
118 	chip->controller = &controller;
119 
120 	pasemi_nand_mtd = nand_to_mtd(chip);
121 
122 	/* Link the private data with the MTD structure */
123 	pasemi_nand_mtd->dev.parent = dev;
124 
125 	chip->legacy.IO_ADDR_R = of_iomap(np, 0);
126 	chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
127 
128 	if (!chip->legacy.IO_ADDR_R) {
129 		err = -EIO;
130 		goto out_mtd;
131 	}
132 
133 	pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
134 	if (!pdev) {
135 		err = -ENODEV;
136 		goto out_ior;
137 	}
138 
139 	lpcctl = pci_resource_start(pdev, 0);
140 	pci_dev_put(pdev);
141 
142 	if (!request_region(lpcctl, 4, driver_name)) {
143 		err = -EBUSY;
144 		goto out_ior;
145 	}
146 
147 	chip->legacy.cmd_ctrl = pasemi_hwcontrol;
148 	chip->legacy.dev_ready = pasemi_device_ready;
149 	chip->legacy.read_buf = pasemi_read_buf;
150 	chip->legacy.write_buf = pasemi_write_buf;
151 	chip->legacy.chip_delay = 0;
152 
153 	/* Enable the following for a flash based bad block table */
154 	chip->bbt_options = NAND_BBT_USE_FLASH;
155 
156 	/* Scan to find existence of the device */
157 	err = nand_scan(chip, 1);
158 	if (err)
159 		goto out_lpc;
160 
161 	if (mtd_device_register(pasemi_nand_mtd, NULL, 0)) {
162 		dev_err(dev, "Unable to register MTD device\n");
163 		err = -ENODEV;
164 		goto out_cleanup_nand;
165 	}
166 
167 	dev_info(dev, "PA Semi NAND flash at %pR, control at I/O %x\n", &res,
168 		 lpcctl);
169 
170 	return 0;
171 
172  out_cleanup_nand:
173 	nand_cleanup(chip);
174  out_lpc:
175 	release_region(lpcctl, 4);
176  out_ior:
177 	iounmap(chip->legacy.IO_ADDR_R);
178  out_mtd:
179 	kfree(chip);
180  out:
181 	return err;
182 }
183 
184 static int pasemi_nand_remove(struct platform_device *ofdev)
185 {
186 	struct nand_chip *chip;
187 	int ret;
188 
189 	if (!pasemi_nand_mtd)
190 		return 0;
191 
192 	chip = mtd_to_nand(pasemi_nand_mtd);
193 
194 	/* Release resources, unregister device */
195 	ret = mtd_device_unregister(pasemi_nand_mtd);
196 	WARN_ON(ret);
197 	nand_cleanup(chip);
198 
199 	release_region(lpcctl, 4);
200 
201 	iounmap(chip->legacy.IO_ADDR_R);
202 
203 	/* Free the MTD device structure */
204 	kfree(chip);
205 
206 	pasemi_nand_mtd = NULL;
207 
208 	return 0;
209 }
210 
211 static const struct of_device_id pasemi_nand_match[] =
212 {
213 	{
214 		.compatible   = "pasemi,localbus-nand",
215 	},
216 	{},
217 };
218 
219 MODULE_DEVICE_TABLE(of, pasemi_nand_match);
220 
221 static struct platform_driver pasemi_nand_driver =
222 {
223 	.driver = {
224 		.name = driver_name,
225 		.of_match_table = pasemi_nand_match,
226 	},
227 	.probe		= pasemi_nand_probe,
228 	.remove		= pasemi_nand_remove,
229 };
230 
231 module_platform_driver(pasemi_nand_driver);
232 
233 MODULE_LICENSE("GPL");
234 MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>");
235 MODULE_DESCRIPTION("NAND flash interface driver for PA Semi PWRficient");
236