1 /* 2 * NAND flash simulator. 3 * 4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org> 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * 8 * Note: NS means "NAND Simulator". 9 * Note: Input means input TO flash chip, output means output FROM chip. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2, or (at your option) any later 14 * version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General 19 * Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA 24 */ 25 26 #define pr_fmt(fmt) "[nandsim]" fmt 27 28 #include <linux/init.h> 29 #include <linux/types.h> 30 #include <linux/module.h> 31 #include <linux/moduleparam.h> 32 #include <linux/vmalloc.h> 33 #include <linux/math64.h> 34 #include <linux/slab.h> 35 #include <linux/errno.h> 36 #include <linux/string.h> 37 #include <linux/mtd/mtd.h> 38 #include <linux/mtd/rawnand.h> 39 #include <linux/mtd/nand_bch.h> 40 #include <linux/mtd/partitions.h> 41 #include <linux/delay.h> 42 #include <linux/list.h> 43 #include <linux/random.h> 44 #include <linux/sched.h> 45 #include <linux/sched/mm.h> 46 #include <linux/fs.h> 47 #include <linux/pagemap.h> 48 #include <linux/seq_file.h> 49 #include <linux/debugfs.h> 50 51 /* Default simulator parameters values */ 52 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \ 53 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \ 54 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \ 55 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE) 56 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98 57 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39 58 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */ 59 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */ 60 #endif 61 62 #ifndef CONFIG_NANDSIM_ACCESS_DELAY 63 #define CONFIG_NANDSIM_ACCESS_DELAY 25 64 #endif 65 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY 66 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200 67 #endif 68 #ifndef CONFIG_NANDSIM_ERASE_DELAY 69 #define CONFIG_NANDSIM_ERASE_DELAY 2 70 #endif 71 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE 72 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40 73 #endif 74 #ifndef CONFIG_NANDSIM_INPUT_CYCLE 75 #define CONFIG_NANDSIM_INPUT_CYCLE 50 76 #endif 77 #ifndef CONFIG_NANDSIM_BUS_WIDTH 78 #define CONFIG_NANDSIM_BUS_WIDTH 8 79 #endif 80 #ifndef CONFIG_NANDSIM_DO_DELAYS 81 #define CONFIG_NANDSIM_DO_DELAYS 0 82 #endif 83 #ifndef CONFIG_NANDSIM_LOG 84 #define CONFIG_NANDSIM_LOG 0 85 #endif 86 #ifndef CONFIG_NANDSIM_DBG 87 #define CONFIG_NANDSIM_DBG 0 88 #endif 89 #ifndef CONFIG_NANDSIM_MAX_PARTS 90 #define CONFIG_NANDSIM_MAX_PARTS 32 91 #endif 92 93 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY; 94 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY; 95 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY; 96 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE; 97 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE; 98 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH; 99 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS; 100 static uint log = CONFIG_NANDSIM_LOG; 101 static uint dbg = CONFIG_NANDSIM_DBG; 102 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS]; 103 static unsigned int parts_num; 104 static char *badblocks = NULL; 105 static char *weakblocks = NULL; 106 static char *weakpages = NULL; 107 static unsigned int bitflips = 0; 108 static char *gravepages = NULL; 109 static unsigned int overridesize = 0; 110 static char *cache_file = NULL; 111 static unsigned int bbt; 112 static unsigned int bch; 113 static u_char id_bytes[8] = { 114 [0] = CONFIG_NANDSIM_FIRST_ID_BYTE, 115 [1] = CONFIG_NANDSIM_SECOND_ID_BYTE, 116 [2] = CONFIG_NANDSIM_THIRD_ID_BYTE, 117 [3] = CONFIG_NANDSIM_FOURTH_ID_BYTE, 118 [4 ... 7] = 0xFF, 119 }; 120 121 module_param_array(id_bytes, byte, NULL, 0400); 122 module_param_named(first_id_byte, id_bytes[0], byte, 0400); 123 module_param_named(second_id_byte, id_bytes[1], byte, 0400); 124 module_param_named(third_id_byte, id_bytes[2], byte, 0400); 125 module_param_named(fourth_id_byte, id_bytes[3], byte, 0400); 126 module_param(access_delay, uint, 0400); 127 module_param(programm_delay, uint, 0400); 128 module_param(erase_delay, uint, 0400); 129 module_param(output_cycle, uint, 0400); 130 module_param(input_cycle, uint, 0400); 131 module_param(bus_width, uint, 0400); 132 module_param(do_delays, uint, 0400); 133 module_param(log, uint, 0400); 134 module_param(dbg, uint, 0400); 135 module_param_array(parts, ulong, &parts_num, 0400); 136 module_param(badblocks, charp, 0400); 137 module_param(weakblocks, charp, 0400); 138 module_param(weakpages, charp, 0400); 139 module_param(bitflips, uint, 0400); 140 module_param(gravepages, charp, 0400); 141 module_param(overridesize, uint, 0400); 142 module_param(cache_file, charp, 0400); 143 module_param(bbt, uint, 0400); 144 module_param(bch, uint, 0400); 145 146 MODULE_PARM_DESC(id_bytes, "The ID bytes returned by NAND Flash 'read ID' command"); 147 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID) (obsolete)"); 148 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID) (obsolete)"); 149 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command (obsolete)"); 150 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command (obsolete)"); 151 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)"); 152 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds"); 153 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)"); 154 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)"); 155 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)"); 156 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)"); 157 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero"); 158 MODULE_PARM_DESC(log, "Perform logging if not zero"); 159 MODULE_PARM_DESC(dbg, "Output debug information if not zero"); 160 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas"); 161 /* Page and erase block positions for the following parameters are independent of any partitions */ 162 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas"); 163 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]" 164 " separated by commas e.g. 113:2 means eb 113" 165 " can be erased only twice before failing"); 166 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]" 167 " separated by commas e.g. 1401:2 means page 1401" 168 " can be written only twice before failing"); 169 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)"); 170 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]" 171 " separated by commas e.g. 1401:2 means page 1401" 172 " can be read only twice before failing"); 173 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. " 174 "The size is specified in erase blocks and as the exponent of a power of two" 175 " e.g. 5 means a size of 32 erase blocks"); 176 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory"); 177 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area"); 178 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should " 179 "be correctable in 512-byte blocks"); 180 181 /* The largest possible page size */ 182 #define NS_LARGEST_PAGE_SIZE 4096 183 184 /* Simulator's output macros (logging, debugging, warning, error) */ 185 #define NS_LOG(args...) \ 186 do { if (log) pr_debug(" log: " args); } while(0) 187 #define NS_DBG(args...) \ 188 do { if (dbg) pr_debug(" debug: " args); } while(0) 189 #define NS_WARN(args...) \ 190 do { pr_warn(" warning: " args); } while(0) 191 #define NS_ERR(args...) \ 192 do { pr_err(" error: " args); } while(0) 193 #define NS_INFO(args...) \ 194 do { pr_info(" " args); } while(0) 195 196 /* Busy-wait delay macros (microseconds, milliseconds) */ 197 #define NS_UDELAY(us) \ 198 do { if (do_delays) udelay(us); } while(0) 199 #define NS_MDELAY(us) \ 200 do { if (do_delays) mdelay(us); } while(0) 201 202 /* Is the nandsim structure initialized ? */ 203 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0) 204 205 /* Good operation completion status */ 206 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0))) 207 208 /* Operation failed completion status */ 209 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns)) 210 211 /* Calculate the page offset in flash RAM image by (row, column) address */ 212 #define NS_RAW_OFFSET(ns) \ 213 (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column) 214 215 /* Calculate the OOB offset in flash RAM image by (row, column) address */ 216 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz) 217 218 /* After a command is input, the simulator goes to one of the following states */ 219 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */ 220 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */ 221 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */ 222 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */ 223 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */ 224 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */ 225 #define STATE_CMD_STATUS 0x00000007 /* read status */ 226 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */ 227 #define STATE_CMD_READID 0x0000000A /* read ID */ 228 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */ 229 #define STATE_CMD_RESET 0x0000000C /* reset */ 230 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */ 231 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */ 232 #define STATE_CMD_MASK 0x0000000F /* command states mask */ 233 234 /* After an address is input, the simulator goes to one of these states */ 235 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */ 236 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */ 237 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */ 238 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */ 239 #define STATE_ADDR_MASK 0x00000070 /* address states mask */ 240 241 /* During data input/output the simulator is in these states */ 242 #define STATE_DATAIN 0x00000100 /* waiting for data input */ 243 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */ 244 245 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */ 246 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */ 247 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */ 248 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */ 249 250 /* Previous operation is done, ready to accept new requests */ 251 #define STATE_READY 0x00000000 252 253 /* This state is used to mark that the next state isn't known yet */ 254 #define STATE_UNKNOWN 0x10000000 255 256 /* Simulator's actions bit masks */ 257 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */ 258 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */ 259 #define ACTION_SECERASE 0x00300000 /* erase sector */ 260 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */ 261 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */ 262 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */ 263 #define ACTION_MASK 0x00700000 /* action mask */ 264 265 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */ 266 #define NS_OPER_STATES 6 /* Maximum number of states in operation */ 267 268 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */ 269 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */ 270 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */ 271 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */ 272 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */ 273 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */ 274 #define OPT_SMALLPAGE (OPT_PAGE512) /* 512-byte page chips */ 275 276 /* Remove action bits from state */ 277 #define NS_STATE(x) ((x) & ~ACTION_MASK) 278 279 /* 280 * Maximum previous states which need to be saved. Currently saving is 281 * only needed for page program operation with preceded read command 282 * (which is only valid for 512-byte pages). 283 */ 284 #define NS_MAX_PREVSTATES 1 285 286 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */ 287 #define NS_MAX_HELD_PAGES 16 288 289 /* 290 * A union to represent flash memory contents and flash buffer. 291 */ 292 union ns_mem { 293 u_char *byte; /* for byte access */ 294 uint16_t *word; /* for 16-bit word access */ 295 }; 296 297 /* 298 * The structure which describes all the internal simulator data. 299 */ 300 struct nandsim { 301 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS]; 302 unsigned int nbparts; 303 304 uint busw; /* flash chip bus width (8 or 16) */ 305 u_char ids[8]; /* chip's ID bytes */ 306 uint32_t options; /* chip's characteristic bits */ 307 uint32_t state; /* current chip state */ 308 uint32_t nxstate; /* next expected state */ 309 310 uint32_t *op; /* current operation, NULL operations isn't known yet */ 311 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */ 312 uint16_t npstates; /* number of previous states saved */ 313 uint16_t stateidx; /* current state index */ 314 315 /* The simulated NAND flash pages array */ 316 union ns_mem *pages; 317 318 /* Slab allocator for nand pages */ 319 struct kmem_cache *nand_pages_slab; 320 321 /* Internal buffer of page + OOB size bytes */ 322 union ns_mem buf; 323 324 /* NAND flash "geometry" */ 325 struct { 326 uint64_t totsz; /* total flash size, bytes */ 327 uint32_t secsz; /* flash sector (erase block) size, bytes */ 328 uint pgsz; /* NAND flash page size, bytes */ 329 uint oobsz; /* page OOB area size, bytes */ 330 uint64_t totszoob; /* total flash size including OOB, bytes */ 331 uint pgszoob; /* page size including OOB , bytes*/ 332 uint secszoob; /* sector size including OOB, bytes */ 333 uint pgnum; /* total number of pages */ 334 uint pgsec; /* number of pages per sector */ 335 uint secshift; /* bits number in sector size */ 336 uint pgshift; /* bits number in page size */ 337 uint pgaddrbytes; /* bytes per page address */ 338 uint secaddrbytes; /* bytes per sector address */ 339 uint idbytes; /* the number ID bytes that this chip outputs */ 340 } geom; 341 342 /* NAND flash internal registers */ 343 struct { 344 unsigned command; /* the command register */ 345 u_char status; /* the status register */ 346 uint row; /* the page number */ 347 uint column; /* the offset within page */ 348 uint count; /* internal counter */ 349 uint num; /* number of bytes which must be processed */ 350 uint off; /* fixed page offset */ 351 } regs; 352 353 /* NAND flash lines state */ 354 struct { 355 int ce; /* chip Enable */ 356 int cle; /* command Latch Enable */ 357 int ale; /* address Latch Enable */ 358 int wp; /* write Protect */ 359 } lines; 360 361 /* Fields needed when using a cache file */ 362 struct file *cfile; /* Open file */ 363 unsigned long *pages_written; /* Which pages have been written */ 364 void *file_buf; 365 struct page *held_pages[NS_MAX_HELD_PAGES]; 366 int held_cnt; 367 }; 368 369 /* 370 * Operations array. To perform any operation the simulator must pass 371 * through the correspondent states chain. 372 */ 373 static struct nandsim_operations { 374 uint32_t reqopts; /* options which are required to perform the operation */ 375 uint32_t states[NS_OPER_STATES]; /* operation's states */ 376 } ops[NS_OPER_NUM] = { 377 /* Read page + OOB from the beginning */ 378 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY, 379 STATE_DATAOUT, STATE_READY}}, 380 /* Read page + OOB from the second half */ 381 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY, 382 STATE_DATAOUT, STATE_READY}}, 383 /* Read OOB */ 384 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY, 385 STATE_DATAOUT, STATE_READY}}, 386 /* Program page starting from the beginning */ 387 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN, 388 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, 389 /* Program page starting from the beginning */ 390 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE, 391 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, 392 /* Program page starting from the second half */ 393 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE, 394 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, 395 /* Program OOB */ 396 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE, 397 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}}, 398 /* Erase sector */ 399 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}}, 400 /* Read status */ 401 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}}, 402 /* Read ID */ 403 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}}, 404 /* Large page devices read page */ 405 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY, 406 STATE_DATAOUT, STATE_READY}}, 407 /* Large page devices random page read */ 408 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY, 409 STATE_DATAOUT, STATE_READY}}, 410 }; 411 412 struct weak_block { 413 struct list_head list; 414 unsigned int erase_block_no; 415 unsigned int max_erases; 416 unsigned int erases_done; 417 }; 418 419 static LIST_HEAD(weak_blocks); 420 421 struct weak_page { 422 struct list_head list; 423 unsigned int page_no; 424 unsigned int max_writes; 425 unsigned int writes_done; 426 }; 427 428 static LIST_HEAD(weak_pages); 429 430 struct grave_page { 431 struct list_head list; 432 unsigned int page_no; 433 unsigned int max_reads; 434 unsigned int reads_done; 435 }; 436 437 static LIST_HEAD(grave_pages); 438 439 static unsigned long *erase_block_wear = NULL; 440 static unsigned int wear_eb_count = 0; 441 static unsigned long total_wear = 0; 442 443 /* MTD structure for NAND controller */ 444 static struct mtd_info *nsmtd; 445 446 static int nandsim_debugfs_show(struct seq_file *m, void *private) 447 { 448 unsigned long wmin = -1, wmax = 0, avg; 449 unsigned long deciles[10], decile_max[10], tot = 0; 450 unsigned int i; 451 452 /* Calc wear stats */ 453 for (i = 0; i < wear_eb_count; ++i) { 454 unsigned long wear = erase_block_wear[i]; 455 if (wear < wmin) 456 wmin = wear; 457 if (wear > wmax) 458 wmax = wear; 459 tot += wear; 460 } 461 462 for (i = 0; i < 9; ++i) { 463 deciles[i] = 0; 464 decile_max[i] = (wmax * (i + 1) + 5) / 10; 465 } 466 deciles[9] = 0; 467 decile_max[9] = wmax; 468 for (i = 0; i < wear_eb_count; ++i) { 469 int d; 470 unsigned long wear = erase_block_wear[i]; 471 for (d = 0; d < 10; ++d) 472 if (wear <= decile_max[d]) { 473 deciles[d] += 1; 474 break; 475 } 476 } 477 avg = tot / wear_eb_count; 478 479 /* Output wear report */ 480 seq_printf(m, "Total numbers of erases: %lu\n", tot); 481 seq_printf(m, "Number of erase blocks: %u\n", wear_eb_count); 482 seq_printf(m, "Average number of erases: %lu\n", avg); 483 seq_printf(m, "Maximum number of erases: %lu\n", wmax); 484 seq_printf(m, "Minimum number of erases: %lu\n", wmin); 485 for (i = 0; i < 10; ++i) { 486 unsigned long from = (i ? decile_max[i - 1] + 1 : 0); 487 if (from > decile_max[i]) 488 continue; 489 seq_printf(m, "Number of ebs with erase counts from %lu to %lu : %lu\n", 490 from, 491 decile_max[i], 492 deciles[i]); 493 } 494 495 return 0; 496 } 497 498 static int nandsim_debugfs_open(struct inode *inode, struct file *file) 499 { 500 return single_open(file, nandsim_debugfs_show, inode->i_private); 501 } 502 503 static const struct file_operations dfs_fops = { 504 .open = nandsim_debugfs_open, 505 .read = seq_read, 506 .llseek = seq_lseek, 507 .release = single_release, 508 }; 509 510 /** 511 * nandsim_debugfs_create - initialize debugfs 512 * @dev: nandsim device description object 513 * 514 * This function creates all debugfs files for UBI device @ubi. Returns zero in 515 * case of success and a negative error code in case of failure. 516 */ 517 static int nandsim_debugfs_create(struct nandsim *dev) 518 { 519 struct dentry *root = nsmtd->dbg.dfs_dir; 520 struct dentry *dent; 521 522 /* 523 * Just skip debugfs initialization when the debugfs directory is 524 * missing. 525 */ 526 if (IS_ERR_OR_NULL(root)) { 527 if (IS_ENABLED(CONFIG_DEBUG_FS) && 528 !IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) 529 NS_WARN("CONFIG_MTD_PARTITIONED_MASTER must be enabled to expose debugfs stuff\n"); 530 return 0; 531 } 532 533 dent = debugfs_create_file("nandsim_wear_report", S_IRUSR, 534 root, dev, &dfs_fops); 535 if (IS_ERR_OR_NULL(dent)) { 536 NS_ERR("cannot create \"nandsim_wear_report\" debugfs entry\n"); 537 return -1; 538 } 539 540 return 0; 541 } 542 543 /* 544 * Allocate array of page pointers, create slab allocation for an array 545 * and initialize the array by NULL pointers. 546 * 547 * RETURNS: 0 if success, -ENOMEM if memory alloc fails. 548 */ 549 static int __init alloc_device(struct nandsim *ns) 550 { 551 struct file *cfile; 552 int i, err; 553 554 if (cache_file) { 555 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600); 556 if (IS_ERR(cfile)) 557 return PTR_ERR(cfile); 558 if (!(cfile->f_mode & FMODE_CAN_READ)) { 559 NS_ERR("alloc_device: cache file not readable\n"); 560 err = -EINVAL; 561 goto err_close; 562 } 563 if (!(cfile->f_mode & FMODE_CAN_WRITE)) { 564 NS_ERR("alloc_device: cache file not writeable\n"); 565 err = -EINVAL; 566 goto err_close; 567 } 568 ns->pages_written = vzalloc(BITS_TO_LONGS(ns->geom.pgnum) * 569 sizeof(unsigned long)); 570 if (!ns->pages_written) { 571 NS_ERR("alloc_device: unable to allocate pages written array\n"); 572 err = -ENOMEM; 573 goto err_close; 574 } 575 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL); 576 if (!ns->file_buf) { 577 NS_ERR("alloc_device: unable to allocate file buf\n"); 578 err = -ENOMEM; 579 goto err_free; 580 } 581 ns->cfile = cfile; 582 return 0; 583 } 584 585 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem)); 586 if (!ns->pages) { 587 NS_ERR("alloc_device: unable to allocate page array\n"); 588 return -ENOMEM; 589 } 590 for (i = 0; i < ns->geom.pgnum; i++) { 591 ns->pages[i].byte = NULL; 592 } 593 ns->nand_pages_slab = kmem_cache_create("nandsim", 594 ns->geom.pgszoob, 0, 0, NULL); 595 if (!ns->nand_pages_slab) { 596 NS_ERR("cache_create: unable to create kmem_cache\n"); 597 return -ENOMEM; 598 } 599 600 return 0; 601 602 err_free: 603 vfree(ns->pages_written); 604 err_close: 605 filp_close(cfile, NULL); 606 return err; 607 } 608 609 /* 610 * Free any allocated pages, and free the array of page pointers. 611 */ 612 static void free_device(struct nandsim *ns) 613 { 614 int i; 615 616 if (ns->cfile) { 617 kfree(ns->file_buf); 618 vfree(ns->pages_written); 619 filp_close(ns->cfile, NULL); 620 return; 621 } 622 623 if (ns->pages) { 624 for (i = 0; i < ns->geom.pgnum; i++) { 625 if (ns->pages[i].byte) 626 kmem_cache_free(ns->nand_pages_slab, 627 ns->pages[i].byte); 628 } 629 kmem_cache_destroy(ns->nand_pages_slab); 630 vfree(ns->pages); 631 } 632 } 633 634 static char __init *get_partition_name(int i) 635 { 636 return kasprintf(GFP_KERNEL, "NAND simulator partition %d", i); 637 } 638 639 /* 640 * Initialize the nandsim structure. 641 * 642 * RETURNS: 0 if success, -ERRNO if failure. 643 */ 644 static int __init init_nandsim(struct mtd_info *mtd) 645 { 646 struct nand_chip *chip = mtd_to_nand(mtd); 647 struct nandsim *ns = nand_get_controller_data(chip); 648 int i, ret = 0; 649 uint64_t remains; 650 uint64_t next_offset; 651 652 if (NS_IS_INITIALIZED(ns)) { 653 NS_ERR("init_nandsim: nandsim is already initialized\n"); 654 return -EIO; 655 } 656 657 /* Force mtd to not do delays */ 658 chip->chip_delay = 0; 659 660 /* Initialize the NAND flash parameters */ 661 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8; 662 ns->geom.totsz = mtd->size; 663 ns->geom.pgsz = mtd->writesize; 664 ns->geom.oobsz = mtd->oobsize; 665 ns->geom.secsz = mtd->erasesize; 666 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz; 667 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz); 668 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz; 669 ns->geom.secshift = ffs(ns->geom.secsz) - 1; 670 ns->geom.pgshift = chip->page_shift; 671 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz; 672 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec; 673 ns->options = 0; 674 675 if (ns->geom.pgsz == 512) { 676 ns->options |= OPT_PAGE512; 677 if (ns->busw == 8) 678 ns->options |= OPT_PAGE512_8BIT; 679 } else if (ns->geom.pgsz == 2048) { 680 ns->options |= OPT_PAGE2048; 681 } else if (ns->geom.pgsz == 4096) { 682 ns->options |= OPT_PAGE4096; 683 } else { 684 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz); 685 return -EIO; 686 } 687 688 if (ns->options & OPT_SMALLPAGE) { 689 if (ns->geom.totsz <= (32 << 20)) { 690 ns->geom.pgaddrbytes = 3; 691 ns->geom.secaddrbytes = 2; 692 } else { 693 ns->geom.pgaddrbytes = 4; 694 ns->geom.secaddrbytes = 3; 695 } 696 } else { 697 if (ns->geom.totsz <= (128 << 20)) { 698 ns->geom.pgaddrbytes = 4; 699 ns->geom.secaddrbytes = 2; 700 } else { 701 ns->geom.pgaddrbytes = 5; 702 ns->geom.secaddrbytes = 3; 703 } 704 } 705 706 /* Fill the partition_info structure */ 707 if (parts_num > ARRAY_SIZE(ns->partitions)) { 708 NS_ERR("too many partitions.\n"); 709 return -EINVAL; 710 } 711 remains = ns->geom.totsz; 712 next_offset = 0; 713 for (i = 0; i < parts_num; ++i) { 714 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz; 715 716 if (!part_sz || part_sz > remains) { 717 NS_ERR("bad partition size.\n"); 718 return -EINVAL; 719 } 720 ns->partitions[i].name = get_partition_name(i); 721 if (!ns->partitions[i].name) { 722 NS_ERR("unable to allocate memory.\n"); 723 return -ENOMEM; 724 } 725 ns->partitions[i].offset = next_offset; 726 ns->partitions[i].size = part_sz; 727 next_offset += ns->partitions[i].size; 728 remains -= ns->partitions[i].size; 729 } 730 ns->nbparts = parts_num; 731 if (remains) { 732 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) { 733 NS_ERR("too many partitions.\n"); 734 return -EINVAL; 735 } 736 ns->partitions[i].name = get_partition_name(i); 737 if (!ns->partitions[i].name) { 738 NS_ERR("unable to allocate memory.\n"); 739 return -ENOMEM; 740 } 741 ns->partitions[i].offset = next_offset; 742 ns->partitions[i].size = remains; 743 ns->nbparts += 1; 744 } 745 746 if (ns->busw == 16) 747 NS_WARN("16-bit flashes support wasn't tested\n"); 748 749 printk("flash size: %llu MiB\n", 750 (unsigned long long)ns->geom.totsz >> 20); 751 printk("page size: %u bytes\n", ns->geom.pgsz); 752 printk("OOB area size: %u bytes\n", ns->geom.oobsz); 753 printk("sector size: %u KiB\n", ns->geom.secsz >> 10); 754 printk("pages number: %u\n", ns->geom.pgnum); 755 printk("pages per sector: %u\n", ns->geom.pgsec); 756 printk("bus width: %u\n", ns->busw); 757 printk("bits in sector size: %u\n", ns->geom.secshift); 758 printk("bits in page size: %u\n", ns->geom.pgshift); 759 printk("bits in OOB size: %u\n", ffs(ns->geom.oobsz) - 1); 760 printk("flash size with OOB: %llu KiB\n", 761 (unsigned long long)ns->geom.totszoob >> 10); 762 printk("page address bytes: %u\n", ns->geom.pgaddrbytes); 763 printk("sector address bytes: %u\n", ns->geom.secaddrbytes); 764 printk("options: %#x\n", ns->options); 765 766 if ((ret = alloc_device(ns)) != 0) 767 return ret; 768 769 /* Allocate / initialize the internal buffer */ 770 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL); 771 if (!ns->buf.byte) { 772 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n", 773 ns->geom.pgszoob); 774 return -ENOMEM; 775 } 776 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob); 777 778 return 0; 779 } 780 781 /* 782 * Free the nandsim structure. 783 */ 784 static void free_nandsim(struct nandsim *ns) 785 { 786 kfree(ns->buf.byte); 787 free_device(ns); 788 789 return; 790 } 791 792 static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd) 793 { 794 char *w; 795 int zero_ok; 796 unsigned int erase_block_no; 797 loff_t offset; 798 799 if (!badblocks) 800 return 0; 801 w = badblocks; 802 do { 803 zero_ok = (*w == '0' ? 1 : 0); 804 erase_block_no = simple_strtoul(w, &w, 0); 805 if (!zero_ok && !erase_block_no) { 806 NS_ERR("invalid badblocks.\n"); 807 return -EINVAL; 808 } 809 offset = (loff_t)erase_block_no * ns->geom.secsz; 810 if (mtd_block_markbad(mtd, offset)) { 811 NS_ERR("invalid badblocks.\n"); 812 return -EINVAL; 813 } 814 if (*w == ',') 815 w += 1; 816 } while (*w); 817 return 0; 818 } 819 820 static int parse_weakblocks(void) 821 { 822 char *w; 823 int zero_ok; 824 unsigned int erase_block_no; 825 unsigned int max_erases; 826 struct weak_block *wb; 827 828 if (!weakblocks) 829 return 0; 830 w = weakblocks; 831 do { 832 zero_ok = (*w == '0' ? 1 : 0); 833 erase_block_no = simple_strtoul(w, &w, 0); 834 if (!zero_ok && !erase_block_no) { 835 NS_ERR("invalid weakblocks.\n"); 836 return -EINVAL; 837 } 838 max_erases = 3; 839 if (*w == ':') { 840 w += 1; 841 max_erases = simple_strtoul(w, &w, 0); 842 } 843 if (*w == ',') 844 w += 1; 845 wb = kzalloc(sizeof(*wb), GFP_KERNEL); 846 if (!wb) { 847 NS_ERR("unable to allocate memory.\n"); 848 return -ENOMEM; 849 } 850 wb->erase_block_no = erase_block_no; 851 wb->max_erases = max_erases; 852 list_add(&wb->list, &weak_blocks); 853 } while (*w); 854 return 0; 855 } 856 857 static int erase_error(unsigned int erase_block_no) 858 { 859 struct weak_block *wb; 860 861 list_for_each_entry(wb, &weak_blocks, list) 862 if (wb->erase_block_no == erase_block_no) { 863 if (wb->erases_done >= wb->max_erases) 864 return 1; 865 wb->erases_done += 1; 866 return 0; 867 } 868 return 0; 869 } 870 871 static int parse_weakpages(void) 872 { 873 char *w; 874 int zero_ok; 875 unsigned int page_no; 876 unsigned int max_writes; 877 struct weak_page *wp; 878 879 if (!weakpages) 880 return 0; 881 w = weakpages; 882 do { 883 zero_ok = (*w == '0' ? 1 : 0); 884 page_no = simple_strtoul(w, &w, 0); 885 if (!zero_ok && !page_no) { 886 NS_ERR("invalid weakpages.\n"); 887 return -EINVAL; 888 } 889 max_writes = 3; 890 if (*w == ':') { 891 w += 1; 892 max_writes = simple_strtoul(w, &w, 0); 893 } 894 if (*w == ',') 895 w += 1; 896 wp = kzalloc(sizeof(*wp), GFP_KERNEL); 897 if (!wp) { 898 NS_ERR("unable to allocate memory.\n"); 899 return -ENOMEM; 900 } 901 wp->page_no = page_no; 902 wp->max_writes = max_writes; 903 list_add(&wp->list, &weak_pages); 904 } while (*w); 905 return 0; 906 } 907 908 static int write_error(unsigned int page_no) 909 { 910 struct weak_page *wp; 911 912 list_for_each_entry(wp, &weak_pages, list) 913 if (wp->page_no == page_no) { 914 if (wp->writes_done >= wp->max_writes) 915 return 1; 916 wp->writes_done += 1; 917 return 0; 918 } 919 return 0; 920 } 921 922 static int parse_gravepages(void) 923 { 924 char *g; 925 int zero_ok; 926 unsigned int page_no; 927 unsigned int max_reads; 928 struct grave_page *gp; 929 930 if (!gravepages) 931 return 0; 932 g = gravepages; 933 do { 934 zero_ok = (*g == '0' ? 1 : 0); 935 page_no = simple_strtoul(g, &g, 0); 936 if (!zero_ok && !page_no) { 937 NS_ERR("invalid gravepagess.\n"); 938 return -EINVAL; 939 } 940 max_reads = 3; 941 if (*g == ':') { 942 g += 1; 943 max_reads = simple_strtoul(g, &g, 0); 944 } 945 if (*g == ',') 946 g += 1; 947 gp = kzalloc(sizeof(*gp), GFP_KERNEL); 948 if (!gp) { 949 NS_ERR("unable to allocate memory.\n"); 950 return -ENOMEM; 951 } 952 gp->page_no = page_no; 953 gp->max_reads = max_reads; 954 list_add(&gp->list, &grave_pages); 955 } while (*g); 956 return 0; 957 } 958 959 static int read_error(unsigned int page_no) 960 { 961 struct grave_page *gp; 962 963 list_for_each_entry(gp, &grave_pages, list) 964 if (gp->page_no == page_no) { 965 if (gp->reads_done >= gp->max_reads) 966 return 1; 967 gp->reads_done += 1; 968 return 0; 969 } 970 return 0; 971 } 972 973 static void free_lists(void) 974 { 975 struct list_head *pos, *n; 976 list_for_each_safe(pos, n, &weak_blocks) { 977 list_del(pos); 978 kfree(list_entry(pos, struct weak_block, list)); 979 } 980 list_for_each_safe(pos, n, &weak_pages) { 981 list_del(pos); 982 kfree(list_entry(pos, struct weak_page, list)); 983 } 984 list_for_each_safe(pos, n, &grave_pages) { 985 list_del(pos); 986 kfree(list_entry(pos, struct grave_page, list)); 987 } 988 kfree(erase_block_wear); 989 } 990 991 static int setup_wear_reporting(struct mtd_info *mtd) 992 { 993 size_t mem; 994 995 wear_eb_count = div_u64(mtd->size, mtd->erasesize); 996 mem = wear_eb_count * sizeof(unsigned long); 997 if (mem / sizeof(unsigned long) != wear_eb_count) { 998 NS_ERR("Too many erase blocks for wear reporting\n"); 999 return -ENOMEM; 1000 } 1001 erase_block_wear = kzalloc(mem, GFP_KERNEL); 1002 if (!erase_block_wear) { 1003 NS_ERR("Too many erase blocks for wear reporting\n"); 1004 return -ENOMEM; 1005 } 1006 return 0; 1007 } 1008 1009 static void update_wear(unsigned int erase_block_no) 1010 { 1011 if (!erase_block_wear) 1012 return; 1013 total_wear += 1; 1014 /* 1015 * TODO: Notify this through a debugfs entry, 1016 * instead of showing an error message. 1017 */ 1018 if (total_wear == 0) 1019 NS_ERR("Erase counter total overflow\n"); 1020 erase_block_wear[erase_block_no] += 1; 1021 if (erase_block_wear[erase_block_no] == 0) 1022 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no); 1023 } 1024 1025 /* 1026 * Returns the string representation of 'state' state. 1027 */ 1028 static char *get_state_name(uint32_t state) 1029 { 1030 switch (NS_STATE(state)) { 1031 case STATE_CMD_READ0: 1032 return "STATE_CMD_READ0"; 1033 case STATE_CMD_READ1: 1034 return "STATE_CMD_READ1"; 1035 case STATE_CMD_PAGEPROG: 1036 return "STATE_CMD_PAGEPROG"; 1037 case STATE_CMD_READOOB: 1038 return "STATE_CMD_READOOB"; 1039 case STATE_CMD_READSTART: 1040 return "STATE_CMD_READSTART"; 1041 case STATE_CMD_ERASE1: 1042 return "STATE_CMD_ERASE1"; 1043 case STATE_CMD_STATUS: 1044 return "STATE_CMD_STATUS"; 1045 case STATE_CMD_SEQIN: 1046 return "STATE_CMD_SEQIN"; 1047 case STATE_CMD_READID: 1048 return "STATE_CMD_READID"; 1049 case STATE_CMD_ERASE2: 1050 return "STATE_CMD_ERASE2"; 1051 case STATE_CMD_RESET: 1052 return "STATE_CMD_RESET"; 1053 case STATE_CMD_RNDOUT: 1054 return "STATE_CMD_RNDOUT"; 1055 case STATE_CMD_RNDOUTSTART: 1056 return "STATE_CMD_RNDOUTSTART"; 1057 case STATE_ADDR_PAGE: 1058 return "STATE_ADDR_PAGE"; 1059 case STATE_ADDR_SEC: 1060 return "STATE_ADDR_SEC"; 1061 case STATE_ADDR_ZERO: 1062 return "STATE_ADDR_ZERO"; 1063 case STATE_ADDR_COLUMN: 1064 return "STATE_ADDR_COLUMN"; 1065 case STATE_DATAIN: 1066 return "STATE_DATAIN"; 1067 case STATE_DATAOUT: 1068 return "STATE_DATAOUT"; 1069 case STATE_DATAOUT_ID: 1070 return "STATE_DATAOUT_ID"; 1071 case STATE_DATAOUT_STATUS: 1072 return "STATE_DATAOUT_STATUS"; 1073 case STATE_READY: 1074 return "STATE_READY"; 1075 case STATE_UNKNOWN: 1076 return "STATE_UNKNOWN"; 1077 } 1078 1079 NS_ERR("get_state_name: unknown state, BUG\n"); 1080 return NULL; 1081 } 1082 1083 /* 1084 * Check if command is valid. 1085 * 1086 * RETURNS: 1 if wrong command, 0 if right. 1087 */ 1088 static int check_command(int cmd) 1089 { 1090 switch (cmd) { 1091 1092 case NAND_CMD_READ0: 1093 case NAND_CMD_READ1: 1094 case NAND_CMD_READSTART: 1095 case NAND_CMD_PAGEPROG: 1096 case NAND_CMD_READOOB: 1097 case NAND_CMD_ERASE1: 1098 case NAND_CMD_STATUS: 1099 case NAND_CMD_SEQIN: 1100 case NAND_CMD_READID: 1101 case NAND_CMD_ERASE2: 1102 case NAND_CMD_RESET: 1103 case NAND_CMD_RNDOUT: 1104 case NAND_CMD_RNDOUTSTART: 1105 return 0; 1106 1107 default: 1108 return 1; 1109 } 1110 } 1111 1112 /* 1113 * Returns state after command is accepted by command number. 1114 */ 1115 static uint32_t get_state_by_command(unsigned command) 1116 { 1117 switch (command) { 1118 case NAND_CMD_READ0: 1119 return STATE_CMD_READ0; 1120 case NAND_CMD_READ1: 1121 return STATE_CMD_READ1; 1122 case NAND_CMD_PAGEPROG: 1123 return STATE_CMD_PAGEPROG; 1124 case NAND_CMD_READSTART: 1125 return STATE_CMD_READSTART; 1126 case NAND_CMD_READOOB: 1127 return STATE_CMD_READOOB; 1128 case NAND_CMD_ERASE1: 1129 return STATE_CMD_ERASE1; 1130 case NAND_CMD_STATUS: 1131 return STATE_CMD_STATUS; 1132 case NAND_CMD_SEQIN: 1133 return STATE_CMD_SEQIN; 1134 case NAND_CMD_READID: 1135 return STATE_CMD_READID; 1136 case NAND_CMD_ERASE2: 1137 return STATE_CMD_ERASE2; 1138 case NAND_CMD_RESET: 1139 return STATE_CMD_RESET; 1140 case NAND_CMD_RNDOUT: 1141 return STATE_CMD_RNDOUT; 1142 case NAND_CMD_RNDOUTSTART: 1143 return STATE_CMD_RNDOUTSTART; 1144 } 1145 1146 NS_ERR("get_state_by_command: unknown command, BUG\n"); 1147 return 0; 1148 } 1149 1150 /* 1151 * Move an address byte to the correspondent internal register. 1152 */ 1153 static inline void accept_addr_byte(struct nandsim *ns, u_char bt) 1154 { 1155 uint byte = (uint)bt; 1156 1157 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) 1158 ns->regs.column |= (byte << 8 * ns->regs.count); 1159 else { 1160 ns->regs.row |= (byte << 8 * (ns->regs.count - 1161 ns->geom.pgaddrbytes + 1162 ns->geom.secaddrbytes)); 1163 } 1164 1165 return; 1166 } 1167 1168 /* 1169 * Switch to STATE_READY state. 1170 */ 1171 static inline void switch_to_ready_state(struct nandsim *ns, u_char status) 1172 { 1173 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY)); 1174 1175 ns->state = STATE_READY; 1176 ns->nxstate = STATE_UNKNOWN; 1177 ns->op = NULL; 1178 ns->npstates = 0; 1179 ns->stateidx = 0; 1180 ns->regs.num = 0; 1181 ns->regs.count = 0; 1182 ns->regs.off = 0; 1183 ns->regs.row = 0; 1184 ns->regs.column = 0; 1185 ns->regs.status = status; 1186 } 1187 1188 /* 1189 * If the operation isn't known yet, try to find it in the global array 1190 * of supported operations. 1191 * 1192 * Operation can be unknown because of the following. 1193 * 1. New command was accepted and this is the first call to find the 1194 * correspondent states chain. In this case ns->npstates = 0; 1195 * 2. There are several operations which begin with the same command(s) 1196 * (for example program from the second half and read from the 1197 * second half operations both begin with the READ1 command). In this 1198 * case the ns->pstates[] array contains previous states. 1199 * 1200 * Thus, the function tries to find operation containing the following 1201 * states (if the 'flag' parameter is 0): 1202 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state 1203 * 1204 * If (one and only one) matching operation is found, it is accepted ( 1205 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is 1206 * zeroed). 1207 * 1208 * If there are several matches, the current state is pushed to the 1209 * ns->pstates. 1210 * 1211 * The operation can be unknown only while commands are input to the chip. 1212 * As soon as address command is accepted, the operation must be known. 1213 * In such situation the function is called with 'flag' != 0, and the 1214 * operation is searched using the following pattern: 1215 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input> 1216 * 1217 * It is supposed that this pattern must either match one operation or 1218 * none. There can't be ambiguity in that case. 1219 * 1220 * If no matches found, the function does the following: 1221 * 1. if there are saved states present, try to ignore them and search 1222 * again only using the last command. If nothing was found, switch 1223 * to the STATE_READY state. 1224 * 2. if there are no saved states, switch to the STATE_READY state. 1225 * 1226 * RETURNS: -2 - no matched operations found. 1227 * -1 - several matches. 1228 * 0 - operation is found. 1229 */ 1230 static int find_operation(struct nandsim *ns, uint32_t flag) 1231 { 1232 int opsfound = 0; 1233 int i, j, idx = 0; 1234 1235 for (i = 0; i < NS_OPER_NUM; i++) { 1236 1237 int found = 1; 1238 1239 if (!(ns->options & ops[i].reqopts)) 1240 /* Ignore operations we can't perform */ 1241 continue; 1242 1243 if (flag) { 1244 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK)) 1245 continue; 1246 } else { 1247 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates])) 1248 continue; 1249 } 1250 1251 for (j = 0; j < ns->npstates; j++) 1252 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j]) 1253 && (ns->options & ops[idx].reqopts)) { 1254 found = 0; 1255 break; 1256 } 1257 1258 if (found) { 1259 idx = i; 1260 opsfound += 1; 1261 } 1262 } 1263 1264 if (opsfound == 1) { 1265 /* Exact match */ 1266 ns->op = &ops[idx].states[0]; 1267 if (flag) { 1268 /* 1269 * In this case the find_operation function was 1270 * called when address has just began input. But it isn't 1271 * yet fully input and the current state must 1272 * not be one of STATE_ADDR_*, but the STATE_ADDR_* 1273 * state must be the next state (ns->nxstate). 1274 */ 1275 ns->stateidx = ns->npstates - 1; 1276 } else { 1277 ns->stateidx = ns->npstates; 1278 } 1279 ns->npstates = 0; 1280 ns->state = ns->op[ns->stateidx]; 1281 ns->nxstate = ns->op[ns->stateidx + 1]; 1282 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n", 1283 idx, get_state_name(ns->state), get_state_name(ns->nxstate)); 1284 return 0; 1285 } 1286 1287 if (opsfound == 0) { 1288 /* Nothing was found. Try to ignore previous commands (if any) and search again */ 1289 if (ns->npstates != 0) { 1290 NS_DBG("find_operation: no operation found, try again with state %s\n", 1291 get_state_name(ns->state)); 1292 ns->npstates = 0; 1293 return find_operation(ns, 0); 1294 1295 } 1296 NS_DBG("find_operation: no operations found\n"); 1297 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 1298 return -2; 1299 } 1300 1301 if (flag) { 1302 /* This shouldn't happen */ 1303 NS_DBG("find_operation: BUG, operation must be known if address is input\n"); 1304 return -2; 1305 } 1306 1307 NS_DBG("find_operation: there is still ambiguity\n"); 1308 1309 ns->pstates[ns->npstates++] = ns->state; 1310 1311 return -1; 1312 } 1313 1314 static void put_pages(struct nandsim *ns) 1315 { 1316 int i; 1317 1318 for (i = 0; i < ns->held_cnt; i++) 1319 put_page(ns->held_pages[i]); 1320 } 1321 1322 /* Get page cache pages in advance to provide NOFS memory allocation */ 1323 static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos) 1324 { 1325 pgoff_t index, start_index, end_index; 1326 struct page *page; 1327 struct address_space *mapping = file->f_mapping; 1328 1329 start_index = pos >> PAGE_SHIFT; 1330 end_index = (pos + count - 1) >> PAGE_SHIFT; 1331 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES) 1332 return -EINVAL; 1333 ns->held_cnt = 0; 1334 for (index = start_index; index <= end_index; index++) { 1335 page = find_get_page(mapping, index); 1336 if (page == NULL) { 1337 page = find_or_create_page(mapping, index, GFP_NOFS); 1338 if (page == NULL) { 1339 write_inode_now(mapping->host, 1); 1340 page = find_or_create_page(mapping, index, GFP_NOFS); 1341 } 1342 if (page == NULL) { 1343 put_pages(ns); 1344 return -ENOMEM; 1345 } 1346 unlock_page(page); 1347 } 1348 ns->held_pages[ns->held_cnt++] = page; 1349 } 1350 return 0; 1351 } 1352 1353 static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos) 1354 { 1355 ssize_t tx; 1356 int err; 1357 unsigned int noreclaim_flag; 1358 1359 err = get_pages(ns, file, count, pos); 1360 if (err) 1361 return err; 1362 noreclaim_flag = memalloc_noreclaim_save(); 1363 tx = kernel_read(file, buf, count, &pos); 1364 memalloc_noreclaim_restore(noreclaim_flag); 1365 put_pages(ns); 1366 return tx; 1367 } 1368 1369 static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos) 1370 { 1371 ssize_t tx; 1372 int err; 1373 unsigned int noreclaim_flag; 1374 1375 err = get_pages(ns, file, count, pos); 1376 if (err) 1377 return err; 1378 noreclaim_flag = memalloc_noreclaim_save(); 1379 tx = kernel_write(file, buf, count, &pos); 1380 memalloc_noreclaim_restore(noreclaim_flag); 1381 put_pages(ns); 1382 return tx; 1383 } 1384 1385 /* 1386 * Returns a pointer to the current page. 1387 */ 1388 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns) 1389 { 1390 return &(ns->pages[ns->regs.row]); 1391 } 1392 1393 /* 1394 * Retuns a pointer to the current byte, within the current page. 1395 */ 1396 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns) 1397 { 1398 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off; 1399 } 1400 1401 static int do_read_error(struct nandsim *ns, int num) 1402 { 1403 unsigned int page_no = ns->regs.row; 1404 1405 if (read_error(page_no)) { 1406 prandom_bytes(ns->buf.byte, num); 1407 NS_WARN("simulating read error in page %u\n", page_no); 1408 return 1; 1409 } 1410 return 0; 1411 } 1412 1413 static void do_bit_flips(struct nandsim *ns, int num) 1414 { 1415 if (bitflips && prandom_u32() < (1 << 22)) { 1416 int flips = 1; 1417 if (bitflips > 1) 1418 flips = (prandom_u32() % (int) bitflips) + 1; 1419 while (flips--) { 1420 int pos = prandom_u32() % (num * 8); 1421 ns->buf.byte[pos / 8] ^= (1 << (pos % 8)); 1422 NS_WARN("read_page: flipping bit %d in page %d " 1423 "reading from %d ecc: corrected=%u failed=%u\n", 1424 pos, ns->regs.row, ns->regs.column + ns->regs.off, 1425 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed); 1426 } 1427 } 1428 } 1429 1430 /* 1431 * Fill the NAND buffer with data read from the specified page. 1432 */ 1433 static void read_page(struct nandsim *ns, int num) 1434 { 1435 union ns_mem *mypage; 1436 1437 if (ns->cfile) { 1438 if (!test_bit(ns->regs.row, ns->pages_written)) { 1439 NS_DBG("read_page: page %d not written\n", ns->regs.row); 1440 memset(ns->buf.byte, 0xFF, num); 1441 } else { 1442 loff_t pos; 1443 ssize_t tx; 1444 1445 NS_DBG("read_page: page %d written, reading from %d\n", 1446 ns->regs.row, ns->regs.column + ns->regs.off); 1447 if (do_read_error(ns, num)) 1448 return; 1449 pos = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off; 1450 tx = read_file(ns, ns->cfile, ns->buf.byte, num, pos); 1451 if (tx != num) { 1452 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx); 1453 return; 1454 } 1455 do_bit_flips(ns, num); 1456 } 1457 return; 1458 } 1459 1460 mypage = NS_GET_PAGE(ns); 1461 if (mypage->byte == NULL) { 1462 NS_DBG("read_page: page %d not allocated\n", ns->regs.row); 1463 memset(ns->buf.byte, 0xFF, num); 1464 } else { 1465 NS_DBG("read_page: page %d allocated, reading from %d\n", 1466 ns->regs.row, ns->regs.column + ns->regs.off); 1467 if (do_read_error(ns, num)) 1468 return; 1469 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num); 1470 do_bit_flips(ns, num); 1471 } 1472 } 1473 1474 /* 1475 * Erase all pages in the specified sector. 1476 */ 1477 static void erase_sector(struct nandsim *ns) 1478 { 1479 union ns_mem *mypage; 1480 int i; 1481 1482 if (ns->cfile) { 1483 for (i = 0; i < ns->geom.pgsec; i++) 1484 if (__test_and_clear_bit(ns->regs.row + i, 1485 ns->pages_written)) { 1486 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i); 1487 } 1488 return; 1489 } 1490 1491 mypage = NS_GET_PAGE(ns); 1492 for (i = 0; i < ns->geom.pgsec; i++) { 1493 if (mypage->byte != NULL) { 1494 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i); 1495 kmem_cache_free(ns->nand_pages_slab, mypage->byte); 1496 mypage->byte = NULL; 1497 } 1498 mypage++; 1499 } 1500 } 1501 1502 /* 1503 * Program the specified page with the contents from the NAND buffer. 1504 */ 1505 static int prog_page(struct nandsim *ns, int num) 1506 { 1507 int i; 1508 union ns_mem *mypage; 1509 u_char *pg_off; 1510 1511 if (ns->cfile) { 1512 loff_t off; 1513 ssize_t tx; 1514 int all; 1515 1516 NS_DBG("prog_page: writing page %d\n", ns->regs.row); 1517 pg_off = ns->file_buf + ns->regs.column + ns->regs.off; 1518 off = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off; 1519 if (!test_bit(ns->regs.row, ns->pages_written)) { 1520 all = 1; 1521 memset(ns->file_buf, 0xff, ns->geom.pgszoob); 1522 } else { 1523 all = 0; 1524 tx = read_file(ns, ns->cfile, pg_off, num, off); 1525 if (tx != num) { 1526 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx); 1527 return -1; 1528 } 1529 } 1530 for (i = 0; i < num; i++) 1531 pg_off[i] &= ns->buf.byte[i]; 1532 if (all) { 1533 loff_t pos = (loff_t)ns->regs.row * ns->geom.pgszoob; 1534 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, pos); 1535 if (tx != ns->geom.pgszoob) { 1536 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx); 1537 return -1; 1538 } 1539 __set_bit(ns->regs.row, ns->pages_written); 1540 } else { 1541 tx = write_file(ns, ns->cfile, pg_off, num, off); 1542 if (tx != num) { 1543 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx); 1544 return -1; 1545 } 1546 } 1547 return 0; 1548 } 1549 1550 mypage = NS_GET_PAGE(ns); 1551 if (mypage->byte == NULL) { 1552 NS_DBG("prog_page: allocating page %d\n", ns->regs.row); 1553 /* 1554 * We allocate memory with GFP_NOFS because a flash FS may 1555 * utilize this. If it is holding an FS lock, then gets here, 1556 * then kernel memory alloc runs writeback which goes to the FS 1557 * again and deadlocks. This was seen in practice. 1558 */ 1559 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS); 1560 if (mypage->byte == NULL) { 1561 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row); 1562 return -1; 1563 } 1564 memset(mypage->byte, 0xFF, ns->geom.pgszoob); 1565 } 1566 1567 pg_off = NS_PAGE_BYTE_OFF(ns); 1568 for (i = 0; i < num; i++) 1569 pg_off[i] &= ns->buf.byte[i]; 1570 1571 return 0; 1572 } 1573 1574 /* 1575 * If state has any action bit, perform this action. 1576 * 1577 * RETURNS: 0 if success, -1 if error. 1578 */ 1579 static int do_state_action(struct nandsim *ns, uint32_t action) 1580 { 1581 int num; 1582 int busdiv = ns->busw == 8 ? 1 : 2; 1583 unsigned int erase_block_no, page_no; 1584 1585 action &= ACTION_MASK; 1586 1587 /* Check that page address input is correct */ 1588 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) { 1589 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row); 1590 return -1; 1591 } 1592 1593 switch (action) { 1594 1595 case ACTION_CPY: 1596 /* 1597 * Copy page data to the internal buffer. 1598 */ 1599 1600 /* Column shouldn't be very large */ 1601 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) { 1602 NS_ERR("do_state_action: column number is too large\n"); 1603 break; 1604 } 1605 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; 1606 read_page(ns, num); 1607 1608 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n", 1609 num, NS_RAW_OFFSET(ns) + ns->regs.off); 1610 1611 if (ns->regs.off == 0) 1612 NS_LOG("read page %d\n", ns->regs.row); 1613 else if (ns->regs.off < ns->geom.pgsz) 1614 NS_LOG("read page %d (second half)\n", ns->regs.row); 1615 else 1616 NS_LOG("read OOB of page %d\n", ns->regs.row); 1617 1618 NS_UDELAY(access_delay); 1619 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv); 1620 1621 break; 1622 1623 case ACTION_SECERASE: 1624 /* 1625 * Erase sector. 1626 */ 1627 1628 if (ns->lines.wp) { 1629 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n"); 1630 return -1; 1631 } 1632 1633 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec 1634 || (ns->regs.row & ~(ns->geom.secsz - 1))) { 1635 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row); 1636 return -1; 1637 } 1638 1639 ns->regs.row = (ns->regs.row << 1640 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column; 1641 ns->regs.column = 0; 1642 1643 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift); 1644 1645 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n", 1646 ns->regs.row, NS_RAW_OFFSET(ns)); 1647 NS_LOG("erase sector %u\n", erase_block_no); 1648 1649 erase_sector(ns); 1650 1651 NS_MDELAY(erase_delay); 1652 1653 if (erase_block_wear) 1654 update_wear(erase_block_no); 1655 1656 if (erase_error(erase_block_no)) { 1657 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no); 1658 return -1; 1659 } 1660 1661 break; 1662 1663 case ACTION_PRGPAGE: 1664 /* 1665 * Program page - move internal buffer data to the page. 1666 */ 1667 1668 if (ns->lines.wp) { 1669 NS_WARN("do_state_action: device is write-protected, programm\n"); 1670 return -1; 1671 } 1672 1673 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; 1674 if (num != ns->regs.count) { 1675 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n", 1676 ns->regs.count, num); 1677 return -1; 1678 } 1679 1680 if (prog_page(ns, num) == -1) 1681 return -1; 1682 1683 page_no = ns->regs.row; 1684 1685 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n", 1686 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off); 1687 NS_LOG("programm page %d\n", ns->regs.row); 1688 1689 NS_UDELAY(programm_delay); 1690 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv); 1691 1692 if (write_error(page_no)) { 1693 NS_WARN("simulating write failure in page %u\n", page_no); 1694 return -1; 1695 } 1696 1697 break; 1698 1699 case ACTION_ZEROOFF: 1700 NS_DBG("do_state_action: set internal offset to 0\n"); 1701 ns->regs.off = 0; 1702 break; 1703 1704 case ACTION_HALFOFF: 1705 if (!(ns->options & OPT_PAGE512_8BIT)) { 1706 NS_ERR("do_state_action: BUG! can't skip half of page for non-512" 1707 "byte page size 8x chips\n"); 1708 return -1; 1709 } 1710 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2); 1711 ns->regs.off = ns->geom.pgsz/2; 1712 break; 1713 1714 case ACTION_OOBOFF: 1715 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz); 1716 ns->regs.off = ns->geom.pgsz; 1717 break; 1718 1719 default: 1720 NS_DBG("do_state_action: BUG! unknown action\n"); 1721 } 1722 1723 return 0; 1724 } 1725 1726 /* 1727 * Switch simulator's state. 1728 */ 1729 static void switch_state(struct nandsim *ns) 1730 { 1731 if (ns->op) { 1732 /* 1733 * The current operation have already been identified. 1734 * Just follow the states chain. 1735 */ 1736 1737 ns->stateidx += 1; 1738 ns->state = ns->nxstate; 1739 ns->nxstate = ns->op[ns->stateidx + 1]; 1740 1741 NS_DBG("switch_state: operation is known, switch to the next state, " 1742 "state: %s, nxstate: %s\n", 1743 get_state_name(ns->state), get_state_name(ns->nxstate)); 1744 1745 /* See, whether we need to do some action */ 1746 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { 1747 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 1748 return; 1749 } 1750 1751 } else { 1752 /* 1753 * We don't yet know which operation we perform. 1754 * Try to identify it. 1755 */ 1756 1757 /* 1758 * The only event causing the switch_state function to 1759 * be called with yet unknown operation is new command. 1760 */ 1761 ns->state = get_state_by_command(ns->regs.command); 1762 1763 NS_DBG("switch_state: operation is unknown, try to find it\n"); 1764 1765 if (find_operation(ns, 0) != 0) 1766 return; 1767 1768 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { 1769 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 1770 return; 1771 } 1772 } 1773 1774 /* For 16x devices column means the page offset in words */ 1775 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) { 1776 NS_DBG("switch_state: double the column number for 16x device\n"); 1777 ns->regs.column <<= 1; 1778 } 1779 1780 if (NS_STATE(ns->nxstate) == STATE_READY) { 1781 /* 1782 * The current state is the last. Return to STATE_READY 1783 */ 1784 1785 u_char status = NS_STATUS_OK(ns); 1786 1787 /* In case of data states, see if all bytes were input/output */ 1788 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) 1789 && ns->regs.count != ns->regs.num) { 1790 NS_WARN("switch_state: not all bytes were processed, %d left\n", 1791 ns->regs.num - ns->regs.count); 1792 status = NS_STATUS_FAILED(ns); 1793 } 1794 1795 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n"); 1796 1797 switch_to_ready_state(ns, status); 1798 1799 return; 1800 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) { 1801 /* 1802 * If the next state is data input/output, switch to it now 1803 */ 1804 1805 ns->state = ns->nxstate; 1806 ns->nxstate = ns->op[++ns->stateidx + 1]; 1807 ns->regs.num = ns->regs.count = 0; 1808 1809 NS_DBG("switch_state: the next state is data I/O, switch, " 1810 "state: %s, nxstate: %s\n", 1811 get_state_name(ns->state), get_state_name(ns->nxstate)); 1812 1813 /* 1814 * Set the internal register to the count of bytes which 1815 * are expected to be input or output 1816 */ 1817 switch (NS_STATE(ns->state)) { 1818 case STATE_DATAIN: 1819 case STATE_DATAOUT: 1820 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column; 1821 break; 1822 1823 case STATE_DATAOUT_ID: 1824 ns->regs.num = ns->geom.idbytes; 1825 break; 1826 1827 case STATE_DATAOUT_STATUS: 1828 ns->regs.count = ns->regs.num = 0; 1829 break; 1830 1831 default: 1832 NS_ERR("switch_state: BUG! unknown data state\n"); 1833 } 1834 1835 } else if (ns->nxstate & STATE_ADDR_MASK) { 1836 /* 1837 * If the next state is address input, set the internal 1838 * register to the number of expected address bytes 1839 */ 1840 1841 ns->regs.count = 0; 1842 1843 switch (NS_STATE(ns->nxstate)) { 1844 case STATE_ADDR_PAGE: 1845 ns->regs.num = ns->geom.pgaddrbytes; 1846 1847 break; 1848 case STATE_ADDR_SEC: 1849 ns->regs.num = ns->geom.secaddrbytes; 1850 break; 1851 1852 case STATE_ADDR_ZERO: 1853 ns->regs.num = 1; 1854 break; 1855 1856 case STATE_ADDR_COLUMN: 1857 /* Column address is always 2 bytes */ 1858 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes; 1859 break; 1860 1861 default: 1862 NS_ERR("switch_state: BUG! unknown address state\n"); 1863 } 1864 } else { 1865 /* 1866 * Just reset internal counters. 1867 */ 1868 1869 ns->regs.num = 0; 1870 ns->regs.count = 0; 1871 } 1872 } 1873 1874 static u_char ns_nand_read_byte(struct mtd_info *mtd) 1875 { 1876 struct nand_chip *chip = mtd_to_nand(mtd); 1877 struct nandsim *ns = nand_get_controller_data(chip); 1878 u_char outb = 0x00; 1879 1880 /* Sanity and correctness checks */ 1881 if (!ns->lines.ce) { 1882 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb); 1883 return outb; 1884 } 1885 if (ns->lines.ale || ns->lines.cle) { 1886 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb); 1887 return outb; 1888 } 1889 if (!(ns->state & STATE_DATAOUT_MASK)) { 1890 NS_WARN("read_byte: unexpected data output cycle, state is %s " 1891 "return %#x\n", get_state_name(ns->state), (uint)outb); 1892 return outb; 1893 } 1894 1895 /* Status register may be read as many times as it is wanted */ 1896 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) { 1897 NS_DBG("read_byte: return %#x status\n", ns->regs.status); 1898 return ns->regs.status; 1899 } 1900 1901 /* Check if there is any data in the internal buffer which may be read */ 1902 if (ns->regs.count == ns->regs.num) { 1903 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb); 1904 return outb; 1905 } 1906 1907 switch (NS_STATE(ns->state)) { 1908 case STATE_DATAOUT: 1909 if (ns->busw == 8) { 1910 outb = ns->buf.byte[ns->regs.count]; 1911 ns->regs.count += 1; 1912 } else { 1913 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]); 1914 ns->regs.count += 2; 1915 } 1916 break; 1917 case STATE_DATAOUT_ID: 1918 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num); 1919 outb = ns->ids[ns->regs.count]; 1920 ns->regs.count += 1; 1921 break; 1922 default: 1923 BUG(); 1924 } 1925 1926 if (ns->regs.count == ns->regs.num) { 1927 NS_DBG("read_byte: all bytes were read\n"); 1928 1929 if (NS_STATE(ns->nxstate) == STATE_READY) 1930 switch_state(ns); 1931 } 1932 1933 return outb; 1934 } 1935 1936 static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte) 1937 { 1938 struct nand_chip *chip = mtd_to_nand(mtd); 1939 struct nandsim *ns = nand_get_controller_data(chip); 1940 1941 /* Sanity and correctness checks */ 1942 if (!ns->lines.ce) { 1943 NS_ERR("write_byte: chip is disabled, ignore write\n"); 1944 return; 1945 } 1946 if (ns->lines.ale && ns->lines.cle) { 1947 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n"); 1948 return; 1949 } 1950 1951 if (ns->lines.cle == 1) { 1952 /* 1953 * The byte written is a command. 1954 */ 1955 1956 if (byte == NAND_CMD_RESET) { 1957 NS_LOG("reset chip\n"); 1958 switch_to_ready_state(ns, NS_STATUS_OK(ns)); 1959 return; 1960 } 1961 1962 /* Check that the command byte is correct */ 1963 if (check_command(byte)) { 1964 NS_ERR("write_byte: unknown command %#x\n", (uint)byte); 1965 return; 1966 } 1967 1968 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS 1969 || NS_STATE(ns->state) == STATE_DATAOUT) { 1970 int row = ns->regs.row; 1971 1972 switch_state(ns); 1973 if (byte == NAND_CMD_RNDOUT) 1974 ns->regs.row = row; 1975 } 1976 1977 /* Check if chip is expecting command */ 1978 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) { 1979 /* Do not warn if only 2 id bytes are read */ 1980 if (!(ns->regs.command == NAND_CMD_READID && 1981 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) { 1982 /* 1983 * We are in situation when something else (not command) 1984 * was expected but command was input. In this case ignore 1985 * previous command(s)/state(s) and accept the last one. 1986 */ 1987 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, " 1988 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate)); 1989 } 1990 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 1991 } 1992 1993 NS_DBG("command byte corresponding to %s state accepted\n", 1994 get_state_name(get_state_by_command(byte))); 1995 ns->regs.command = byte; 1996 switch_state(ns); 1997 1998 } else if (ns->lines.ale == 1) { 1999 /* 2000 * The byte written is an address. 2001 */ 2002 2003 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) { 2004 2005 NS_DBG("write_byte: operation isn't known yet, identify it\n"); 2006 2007 if (find_operation(ns, 1) < 0) 2008 return; 2009 2010 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) { 2011 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2012 return; 2013 } 2014 2015 ns->regs.count = 0; 2016 switch (NS_STATE(ns->nxstate)) { 2017 case STATE_ADDR_PAGE: 2018 ns->regs.num = ns->geom.pgaddrbytes; 2019 break; 2020 case STATE_ADDR_SEC: 2021 ns->regs.num = ns->geom.secaddrbytes; 2022 break; 2023 case STATE_ADDR_ZERO: 2024 ns->regs.num = 1; 2025 break; 2026 default: 2027 BUG(); 2028 } 2029 } 2030 2031 /* Check that chip is expecting address */ 2032 if (!(ns->nxstate & STATE_ADDR_MASK)) { 2033 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, " 2034 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate)); 2035 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2036 return; 2037 } 2038 2039 /* Check if this is expected byte */ 2040 if (ns->regs.count == ns->regs.num) { 2041 NS_ERR("write_byte: no more address bytes expected\n"); 2042 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2043 return; 2044 } 2045 2046 accept_addr_byte(ns, byte); 2047 2048 ns->regs.count += 1; 2049 2050 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n", 2051 (uint)byte, ns->regs.count, ns->regs.num); 2052 2053 if (ns->regs.count == ns->regs.num) { 2054 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column); 2055 switch_state(ns); 2056 } 2057 2058 } else { 2059 /* 2060 * The byte written is an input data. 2061 */ 2062 2063 /* Check that chip is expecting data input */ 2064 if (!(ns->state & STATE_DATAIN_MASK)) { 2065 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, " 2066 "switch to %s\n", (uint)byte, 2067 get_state_name(ns->state), get_state_name(STATE_READY)); 2068 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2069 return; 2070 } 2071 2072 /* Check if this is expected byte */ 2073 if (ns->regs.count == ns->regs.num) { 2074 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n", 2075 ns->regs.num); 2076 return; 2077 } 2078 2079 if (ns->busw == 8) { 2080 ns->buf.byte[ns->regs.count] = byte; 2081 ns->regs.count += 1; 2082 } else { 2083 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte); 2084 ns->regs.count += 2; 2085 } 2086 } 2087 2088 return; 2089 } 2090 2091 static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask) 2092 { 2093 struct nand_chip *chip = mtd_to_nand(mtd); 2094 struct nandsim *ns = nand_get_controller_data(chip); 2095 2096 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0; 2097 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0; 2098 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0; 2099 2100 if (cmd != NAND_CMD_NONE) 2101 ns_nand_write_byte(mtd, cmd); 2102 } 2103 2104 static int ns_device_ready(struct mtd_info *mtd) 2105 { 2106 NS_DBG("device_ready\n"); 2107 return 1; 2108 } 2109 2110 static uint16_t ns_nand_read_word(struct mtd_info *mtd) 2111 { 2112 struct nand_chip *chip = mtd_to_nand(mtd); 2113 2114 NS_DBG("read_word\n"); 2115 2116 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8); 2117 } 2118 2119 static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 2120 { 2121 struct nand_chip *chip = mtd_to_nand(mtd); 2122 struct nandsim *ns = nand_get_controller_data(chip); 2123 2124 /* Check that chip is expecting data input */ 2125 if (!(ns->state & STATE_DATAIN_MASK)) { 2126 NS_ERR("write_buf: data input isn't expected, state is %s, " 2127 "switch to STATE_READY\n", get_state_name(ns->state)); 2128 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2129 return; 2130 } 2131 2132 /* Check if these are expected bytes */ 2133 if (ns->regs.count + len > ns->regs.num) { 2134 NS_ERR("write_buf: too many input bytes\n"); 2135 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2136 return; 2137 } 2138 2139 memcpy(ns->buf.byte + ns->regs.count, buf, len); 2140 ns->regs.count += len; 2141 2142 if (ns->regs.count == ns->regs.num) { 2143 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count); 2144 } 2145 } 2146 2147 static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 2148 { 2149 struct nand_chip *chip = mtd_to_nand(mtd); 2150 struct nandsim *ns = nand_get_controller_data(chip); 2151 2152 /* Sanity and correctness checks */ 2153 if (!ns->lines.ce) { 2154 NS_ERR("read_buf: chip is disabled\n"); 2155 return; 2156 } 2157 if (ns->lines.ale || ns->lines.cle) { 2158 NS_ERR("read_buf: ALE or CLE pin is high\n"); 2159 return; 2160 } 2161 if (!(ns->state & STATE_DATAOUT_MASK)) { 2162 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n", 2163 get_state_name(ns->state)); 2164 return; 2165 } 2166 2167 if (NS_STATE(ns->state) != STATE_DATAOUT) { 2168 int i; 2169 2170 for (i = 0; i < len; i++) 2171 buf[i] = mtd_to_nand(mtd)->read_byte(mtd); 2172 2173 return; 2174 } 2175 2176 /* Check if these are expected bytes */ 2177 if (ns->regs.count + len > ns->regs.num) { 2178 NS_ERR("read_buf: too many bytes to read\n"); 2179 switch_to_ready_state(ns, NS_STATUS_FAILED(ns)); 2180 return; 2181 } 2182 2183 memcpy(buf, ns->buf.byte + ns->regs.count, len); 2184 ns->regs.count += len; 2185 2186 if (ns->regs.count == ns->regs.num) { 2187 if (NS_STATE(ns->nxstate) == STATE_READY) 2188 switch_state(ns); 2189 } 2190 2191 return; 2192 } 2193 2194 /* 2195 * Module initialization function 2196 */ 2197 static int __init ns_init_module(void) 2198 { 2199 struct nand_chip *chip; 2200 struct nandsim *nand; 2201 int retval = -ENOMEM, i; 2202 2203 if (bus_width != 8 && bus_width != 16) { 2204 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width); 2205 return -EINVAL; 2206 } 2207 2208 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */ 2209 chip = kzalloc(sizeof(struct nand_chip) + sizeof(struct nandsim), 2210 GFP_KERNEL); 2211 if (!chip) { 2212 NS_ERR("unable to allocate core structures.\n"); 2213 return -ENOMEM; 2214 } 2215 nsmtd = nand_to_mtd(chip); 2216 nand = (struct nandsim *)(chip + 1); 2217 nand_set_controller_data(chip, (void *)nand); 2218 2219 /* 2220 * Register simulator's callbacks. 2221 */ 2222 chip->cmd_ctrl = ns_hwcontrol; 2223 chip->read_byte = ns_nand_read_byte; 2224 chip->dev_ready = ns_device_ready; 2225 chip->write_buf = ns_nand_write_buf; 2226 chip->read_buf = ns_nand_read_buf; 2227 chip->read_word = ns_nand_read_word; 2228 chip->ecc.mode = NAND_ECC_SOFT; 2229 chip->ecc.algo = NAND_ECC_HAMMING; 2230 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */ 2231 /* and 'badblocks' parameters to work */ 2232 chip->options |= NAND_SKIP_BBTSCAN; 2233 2234 switch (bbt) { 2235 case 2: 2236 chip->bbt_options |= NAND_BBT_NO_OOB; 2237 case 1: 2238 chip->bbt_options |= NAND_BBT_USE_FLASH; 2239 case 0: 2240 break; 2241 default: 2242 NS_ERR("bbt has to be 0..2\n"); 2243 retval = -EINVAL; 2244 goto error; 2245 } 2246 /* 2247 * Perform minimum nandsim structure initialization to handle 2248 * the initial ID read command correctly 2249 */ 2250 if (id_bytes[6] != 0xFF || id_bytes[7] != 0xFF) 2251 nand->geom.idbytes = 8; 2252 else if (id_bytes[4] != 0xFF || id_bytes[5] != 0xFF) 2253 nand->geom.idbytes = 6; 2254 else if (id_bytes[2] != 0xFF || id_bytes[3] != 0xFF) 2255 nand->geom.idbytes = 4; 2256 else 2257 nand->geom.idbytes = 2; 2258 nand->regs.status = NS_STATUS_OK(nand); 2259 nand->nxstate = STATE_UNKNOWN; 2260 nand->options |= OPT_PAGE512; /* temporary value */ 2261 memcpy(nand->ids, id_bytes, sizeof(nand->ids)); 2262 if (bus_width == 16) { 2263 nand->busw = 16; 2264 chip->options |= NAND_BUSWIDTH_16; 2265 } 2266 2267 nsmtd->owner = THIS_MODULE; 2268 2269 if ((retval = parse_weakblocks()) != 0) 2270 goto error; 2271 2272 if ((retval = parse_weakpages()) != 0) 2273 goto error; 2274 2275 if ((retval = parse_gravepages()) != 0) 2276 goto error; 2277 2278 retval = nand_scan_ident(nsmtd, 1, NULL); 2279 if (retval) { 2280 NS_ERR("cannot scan NAND Simulator device\n"); 2281 goto error; 2282 } 2283 2284 if (bch) { 2285 unsigned int eccsteps, eccbytes; 2286 if (!mtd_nand_has_bch()) { 2287 NS_ERR("BCH ECC support is disabled\n"); 2288 retval = -EINVAL; 2289 goto error; 2290 } 2291 /* use 512-byte ecc blocks */ 2292 eccsteps = nsmtd->writesize/512; 2293 eccbytes = (bch*13+7)/8; 2294 /* do not bother supporting small page devices */ 2295 if ((nsmtd->oobsize < 64) || !eccsteps) { 2296 NS_ERR("bch not available on small page devices\n"); 2297 retval = -EINVAL; 2298 goto error; 2299 } 2300 if ((eccbytes*eccsteps+2) > nsmtd->oobsize) { 2301 NS_ERR("invalid bch value %u\n", bch); 2302 retval = -EINVAL; 2303 goto error; 2304 } 2305 chip->ecc.mode = NAND_ECC_SOFT; 2306 chip->ecc.algo = NAND_ECC_BCH; 2307 chip->ecc.size = 512; 2308 chip->ecc.strength = bch; 2309 chip->ecc.bytes = eccbytes; 2310 NS_INFO("using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size); 2311 } 2312 2313 retval = nand_scan_tail(nsmtd); 2314 if (retval) { 2315 NS_ERR("can't register NAND Simulator\n"); 2316 goto error; 2317 } 2318 2319 if (overridesize) { 2320 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize; 2321 if (new_size >> overridesize != nsmtd->erasesize) { 2322 NS_ERR("overridesize is too big\n"); 2323 retval = -EINVAL; 2324 goto err_exit; 2325 } 2326 /* N.B. This relies on nand_scan not doing anything with the size before we change it */ 2327 nsmtd->size = new_size; 2328 chip->chipsize = new_size; 2329 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1; 2330 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 2331 } 2332 2333 if ((retval = setup_wear_reporting(nsmtd)) != 0) 2334 goto err_exit; 2335 2336 if ((retval = init_nandsim(nsmtd)) != 0) 2337 goto err_exit; 2338 2339 if ((retval = chip->scan_bbt(nsmtd)) != 0) 2340 goto err_exit; 2341 2342 if ((retval = parse_badblocks(nand, nsmtd)) != 0) 2343 goto err_exit; 2344 2345 /* Register NAND partitions */ 2346 retval = mtd_device_register(nsmtd, &nand->partitions[0], 2347 nand->nbparts); 2348 if (retval != 0) 2349 goto err_exit; 2350 2351 if ((retval = nandsim_debugfs_create(nand)) != 0) 2352 goto err_exit; 2353 2354 return 0; 2355 2356 err_exit: 2357 free_nandsim(nand); 2358 nand_release(nsmtd); 2359 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i) 2360 kfree(nand->partitions[i].name); 2361 error: 2362 kfree(chip); 2363 free_lists(); 2364 2365 return retval; 2366 } 2367 2368 module_init(ns_init_module); 2369 2370 /* 2371 * Module clean-up function 2372 */ 2373 static void __exit ns_cleanup_module(void) 2374 { 2375 struct nand_chip *chip = mtd_to_nand(nsmtd); 2376 struct nandsim *ns = nand_get_controller_data(chip); 2377 int i; 2378 2379 free_nandsim(ns); /* Free nandsim private resources */ 2380 nand_release(nsmtd); /* Unregister driver */ 2381 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i) 2382 kfree(ns->partitions[i].name); 2383 kfree(mtd_to_nand(nsmtd)); /* Free other structures */ 2384 free_lists(); 2385 } 2386 2387 module_exit(ns_cleanup_module); 2388 2389 MODULE_LICENSE ("GPL"); 2390 MODULE_AUTHOR ("Artem B. Bityuckiy"); 2391 MODULE_DESCRIPTION ("The NAND flash simulator"); 2392