1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Overview: 4 * This is the generic MTD driver for NAND flash devices. It should be 5 * capable of working with almost all NAND chips currently available. 6 * 7 * Additional technical information is available on 8 * http://www.linux-mtd.infradead.org/doc/nand.html 9 * 10 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 12 * 13 * Credits: 14 * David Woodhouse for adding multichip support 15 * 16 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 17 * rework for 2K page size chips 18 * 19 * TODO: 20 * Enable cached programming for 2k page size chips 21 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * if we have HW ECC support. 23 * BBT table is not serialized, has to be fixed 24 */ 25 26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 27 28 #include <linux/module.h> 29 #include <linux/delay.h> 30 #include <linux/errno.h> 31 #include <linux/err.h> 32 #include <linux/sched.h> 33 #include <linux/slab.h> 34 #include <linux/mm.h> 35 #include <linux/types.h> 36 #include <linux/mtd/mtd.h> 37 #include <linux/mtd/nand.h> 38 #include <linux/mtd/nand-ecc-sw-hamming.h> 39 #include <linux/mtd/nand-ecc-sw-bch.h> 40 #include <linux/interrupt.h> 41 #include <linux/bitops.h> 42 #include <linux/io.h> 43 #include <linux/mtd/partitions.h> 44 #include <linux/of.h> 45 #include <linux/gpio/consumer.h> 46 47 #include "internals.h" 48 49 static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page, 50 struct mtd_pairing_info *info) 51 { 52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; 53 int dist = 3; 54 55 if (page == lastpage) 56 dist = 2; 57 58 if (!page || (page & 1)) { 59 info->group = 0; 60 info->pair = (page + 1) / 2; 61 } else { 62 info->group = 1; 63 info->pair = (page + 1 - dist) / 2; 64 } 65 66 return 0; 67 } 68 69 static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd, 70 const struct mtd_pairing_info *info) 71 { 72 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2; 73 int page = info->pair * 2; 74 int dist = 3; 75 76 if (!info->group && !info->pair) 77 return 0; 78 79 if (info->pair == lastpair && info->group) 80 dist = 2; 81 82 if (!info->group) 83 page--; 84 else if (info->pair) 85 page += dist - 1; 86 87 if (page >= mtd->erasesize / mtd->writesize) 88 return -EINVAL; 89 90 return page; 91 } 92 93 const struct mtd_pairing_scheme dist3_pairing_scheme = { 94 .ngroups = 2, 95 .get_info = nand_pairing_dist3_get_info, 96 .get_wunit = nand_pairing_dist3_get_wunit, 97 }; 98 99 static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len) 100 { 101 int ret = 0; 102 103 /* Start address must align on block boundary */ 104 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 105 pr_debug("%s: unaligned address\n", __func__); 106 ret = -EINVAL; 107 } 108 109 /* Length must align on block boundary */ 110 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 111 pr_debug("%s: length not block aligned\n", __func__); 112 ret = -EINVAL; 113 } 114 115 return ret; 116 } 117 118 /** 119 * nand_extract_bits - Copy unaligned bits from one buffer to another one 120 * @dst: destination buffer 121 * @dst_off: bit offset at which the writing starts 122 * @src: source buffer 123 * @src_off: bit offset at which the reading starts 124 * @nbits: number of bits to copy from @src to @dst 125 * 126 * Copy bits from one memory region to another (overlap authorized). 127 */ 128 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src, 129 unsigned int src_off, unsigned int nbits) 130 { 131 unsigned int tmp, n; 132 133 dst += dst_off / 8; 134 dst_off %= 8; 135 src += src_off / 8; 136 src_off %= 8; 137 138 while (nbits) { 139 n = min3(8 - dst_off, 8 - src_off, nbits); 140 141 tmp = (*src >> src_off) & GENMASK(n - 1, 0); 142 *dst &= ~GENMASK(n - 1 + dst_off, dst_off); 143 *dst |= tmp << dst_off; 144 145 dst_off += n; 146 if (dst_off >= 8) { 147 dst++; 148 dst_off -= 8; 149 } 150 151 src_off += n; 152 if (src_off >= 8) { 153 src++; 154 src_off -= 8; 155 } 156 157 nbits -= n; 158 } 159 } 160 EXPORT_SYMBOL_GPL(nand_extract_bits); 161 162 /** 163 * nand_select_target() - Select a NAND target (A.K.A. die) 164 * @chip: NAND chip object 165 * @cs: the CS line to select. Note that this CS id is always from the chip 166 * PoV, not the controller one 167 * 168 * Select a NAND target so that further operations executed on @chip go to the 169 * selected NAND target. 170 */ 171 void nand_select_target(struct nand_chip *chip, unsigned int cs) 172 { 173 /* 174 * cs should always lie between 0 and nanddev_ntargets(), when that's 175 * not the case it's a bug and the caller should be fixed. 176 */ 177 if (WARN_ON(cs > nanddev_ntargets(&chip->base))) 178 return; 179 180 chip->cur_cs = cs; 181 182 if (chip->legacy.select_chip) 183 chip->legacy.select_chip(chip, cs); 184 } 185 EXPORT_SYMBOL_GPL(nand_select_target); 186 187 /** 188 * nand_deselect_target() - Deselect the currently selected target 189 * @chip: NAND chip object 190 * 191 * Deselect the currently selected NAND target. The result of operations 192 * executed on @chip after the target has been deselected is undefined. 193 */ 194 void nand_deselect_target(struct nand_chip *chip) 195 { 196 if (chip->legacy.select_chip) 197 chip->legacy.select_chip(chip, -1); 198 199 chip->cur_cs = -1; 200 } 201 EXPORT_SYMBOL_GPL(nand_deselect_target); 202 203 /** 204 * nand_release_device - [GENERIC] release chip 205 * @chip: NAND chip object 206 * 207 * Release chip lock and wake up anyone waiting on the device. 208 */ 209 static void nand_release_device(struct nand_chip *chip) 210 { 211 /* Release the controller and the chip */ 212 mutex_unlock(&chip->controller->lock); 213 mutex_unlock(&chip->lock); 214 } 215 216 /** 217 * nand_bbm_get_next_page - Get the next page for bad block markers 218 * @chip: NAND chip object 219 * @page: First page to start checking for bad block marker usage 220 * 221 * Returns an integer that corresponds to the page offset within a block, for 222 * a page that is used to store bad block markers. If no more pages are 223 * available, -EINVAL is returned. 224 */ 225 int nand_bbm_get_next_page(struct nand_chip *chip, int page) 226 { 227 struct mtd_info *mtd = nand_to_mtd(chip); 228 int last_page = ((mtd->erasesize - mtd->writesize) >> 229 chip->page_shift) & chip->pagemask; 230 unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE 231 | NAND_BBM_LASTPAGE; 232 233 if (page == 0 && !(chip->options & bbm_flags)) 234 return 0; 235 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) 236 return 0; 237 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) 238 return 1; 239 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) 240 return last_page; 241 242 return -EINVAL; 243 } 244 245 /** 246 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 247 * @chip: NAND chip object 248 * @ofs: offset from device start 249 * 250 * Check, if the block is bad. 251 */ 252 static int nand_block_bad(struct nand_chip *chip, loff_t ofs) 253 { 254 int first_page, page_offset; 255 int res; 256 u8 bad; 257 258 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; 259 page_offset = nand_bbm_get_next_page(chip, 0); 260 261 while (page_offset >= 0) { 262 res = chip->ecc.read_oob(chip, first_page + page_offset); 263 if (res < 0) 264 return res; 265 266 bad = chip->oob_poi[chip->badblockpos]; 267 268 if (likely(chip->badblockbits == 8)) 269 res = bad != 0xFF; 270 else 271 res = hweight8(bad) < chip->badblockbits; 272 if (res) 273 return res; 274 275 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 276 } 277 278 return 0; 279 } 280 281 /** 282 * nand_region_is_secured() - Check if the region is secured 283 * @chip: NAND chip object 284 * @offset: Offset of the region to check 285 * @size: Size of the region to check 286 * 287 * Checks if the region is secured by comparing the offset and size with the 288 * list of secure regions obtained from DT. Returns true if the region is 289 * secured else false. 290 */ 291 static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size) 292 { 293 int i; 294 295 /* Skip touching the secure regions if present */ 296 for (i = 0; i < chip->nr_secure_regions; i++) { 297 const struct nand_secure_region *region = &chip->secure_regions[i]; 298 299 if (offset + size <= region->offset || 300 offset >= region->offset + region->size) 301 continue; 302 303 pr_debug("%s: Region 0x%llx - 0x%llx is secured!", 304 __func__, offset, offset + size); 305 306 return true; 307 } 308 309 return false; 310 } 311 312 static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) 313 { 314 struct mtd_info *mtd = nand_to_mtd(chip); 315 316 if (chip->options & NAND_NO_BBM_QUIRK) 317 return 0; 318 319 /* Check if the region is secured */ 320 if (nand_region_is_secured(chip, ofs, mtd->erasesize)) 321 return -EIO; 322 323 if (mtd_check_expert_analysis_mode()) 324 return 0; 325 326 if (chip->legacy.block_bad) 327 return chip->legacy.block_bad(chip, ofs); 328 329 return nand_block_bad(chip, ofs); 330 } 331 332 /** 333 * nand_get_device - [GENERIC] Get chip for selected access 334 * @chip: NAND chip structure 335 * 336 * Lock the device and its controller for exclusive access 337 */ 338 static void nand_get_device(struct nand_chip *chip) 339 { 340 /* Wait until the device is resumed. */ 341 while (1) { 342 mutex_lock(&chip->lock); 343 if (!chip->suspended) { 344 mutex_lock(&chip->controller->lock); 345 return; 346 } 347 mutex_unlock(&chip->lock); 348 349 wait_event(chip->resume_wq, !chip->suspended); 350 } 351 } 352 353 /** 354 * nand_check_wp - [GENERIC] check if the chip is write protected 355 * @chip: NAND chip object 356 * 357 * Check, if the device is write protected. The function expects, that the 358 * device is already selected. 359 */ 360 static int nand_check_wp(struct nand_chip *chip) 361 { 362 u8 status; 363 int ret; 364 365 /* Broken xD cards report WP despite being writable */ 366 if (chip->options & NAND_BROKEN_XD) 367 return 0; 368 369 /* Check the WP bit */ 370 ret = nand_status_op(chip, &status); 371 if (ret) 372 return ret; 373 374 return status & NAND_STATUS_WP ? 0 : 1; 375 } 376 377 /** 378 * nand_fill_oob - [INTERN] Transfer client buffer to oob 379 * @chip: NAND chip object 380 * @oob: oob data buffer 381 * @len: oob data write length 382 * @ops: oob ops structure 383 */ 384 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, 385 struct mtd_oob_ops *ops) 386 { 387 struct mtd_info *mtd = nand_to_mtd(chip); 388 int ret; 389 390 /* 391 * Initialise to all 0xFF, to avoid the possibility of left over OOB 392 * data from a previous OOB read. 393 */ 394 memset(chip->oob_poi, 0xff, mtd->oobsize); 395 396 switch (ops->mode) { 397 398 case MTD_OPS_PLACE_OOB: 399 case MTD_OPS_RAW: 400 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 401 return oob + len; 402 403 case MTD_OPS_AUTO_OOB: 404 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, 405 ops->ooboffs, len); 406 BUG_ON(ret); 407 return oob + len; 408 409 default: 410 BUG(); 411 } 412 return NULL; 413 } 414 415 /** 416 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 417 * @chip: NAND chip object 418 * @to: offset to write to 419 * @ops: oob operation description structure 420 * 421 * NAND write out-of-band. 422 */ 423 static int nand_do_write_oob(struct nand_chip *chip, loff_t to, 424 struct mtd_oob_ops *ops) 425 { 426 struct mtd_info *mtd = nand_to_mtd(chip); 427 int chipnr, page, status, len, ret; 428 429 pr_debug("%s: to = 0x%08x, len = %i\n", 430 __func__, (unsigned int)to, (int)ops->ooblen); 431 432 len = mtd_oobavail(mtd, ops); 433 434 /* Do not allow write past end of page */ 435 if ((ops->ooboffs + ops->ooblen) > len) { 436 pr_debug("%s: attempt to write past end of page\n", 437 __func__); 438 return -EINVAL; 439 } 440 441 /* Check if the region is secured */ 442 if (nand_region_is_secured(chip, to, ops->ooblen)) 443 return -EIO; 444 445 chipnr = (int)(to >> chip->chip_shift); 446 447 /* 448 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 449 * of my DiskOnChip 2000 test units) will clear the whole data page too 450 * if we don't do this. I have no clue why, but I seem to have 'fixed' 451 * it in the doc2000 driver in August 1999. dwmw2. 452 */ 453 ret = nand_reset(chip, chipnr); 454 if (ret) 455 return ret; 456 457 nand_select_target(chip, chipnr); 458 459 /* Shift to get page */ 460 page = (int)(to >> chip->page_shift); 461 462 /* Check, if it is write protected */ 463 if (nand_check_wp(chip)) { 464 nand_deselect_target(chip); 465 return -EROFS; 466 } 467 468 /* Invalidate the page cache, if we write to the cached page */ 469 if (page == chip->pagecache.page) 470 chip->pagecache.page = -1; 471 472 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); 473 474 if (ops->mode == MTD_OPS_RAW) 475 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); 476 else 477 status = chip->ecc.write_oob(chip, page & chip->pagemask); 478 479 nand_deselect_target(chip); 480 481 if (status) 482 return status; 483 484 ops->oobretlen = ops->ooblen; 485 486 return 0; 487 } 488 489 /** 490 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 491 * @chip: NAND chip object 492 * @ofs: offset from device start 493 * 494 * This is the default implementation, which can be overridden by a hardware 495 * specific driver. It provides the details for writing a bad block marker to a 496 * block. 497 */ 498 static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs) 499 { 500 struct mtd_info *mtd = nand_to_mtd(chip); 501 struct mtd_oob_ops ops; 502 uint8_t buf[2] = { 0, 0 }; 503 int ret = 0, res, page_offset; 504 505 memset(&ops, 0, sizeof(ops)); 506 ops.oobbuf = buf; 507 ops.ooboffs = chip->badblockpos; 508 if (chip->options & NAND_BUSWIDTH_16) { 509 ops.ooboffs &= ~0x01; 510 ops.len = ops.ooblen = 2; 511 } else { 512 ops.len = ops.ooblen = 1; 513 } 514 ops.mode = MTD_OPS_PLACE_OOB; 515 516 page_offset = nand_bbm_get_next_page(chip, 0); 517 518 while (page_offset >= 0) { 519 res = nand_do_write_oob(chip, 520 ofs + (page_offset * mtd->writesize), 521 &ops); 522 523 if (!ret) 524 ret = res; 525 526 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 527 } 528 529 return ret; 530 } 531 532 /** 533 * nand_markbad_bbm - mark a block by updating the BBM 534 * @chip: NAND chip object 535 * @ofs: offset of the block to mark bad 536 */ 537 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs) 538 { 539 if (chip->legacy.block_markbad) 540 return chip->legacy.block_markbad(chip, ofs); 541 542 return nand_default_block_markbad(chip, ofs); 543 } 544 545 /** 546 * nand_block_markbad_lowlevel - mark a block bad 547 * @chip: NAND chip object 548 * @ofs: offset from device start 549 * 550 * This function performs the generic NAND bad block marking steps (i.e., bad 551 * block table(s) and/or marker(s)). We only allow the hardware driver to 552 * specify how to write bad block markers to OOB (chip->legacy.block_markbad). 553 * 554 * We try operations in the following order: 555 * 556 * (1) erase the affected block, to allow OOB marker to be written cleanly 557 * (2) write bad block marker to OOB area of affected block (unless flag 558 * NAND_BBT_NO_OOB_BBM is present) 559 * (3) update the BBT 560 * 561 * Note that we retain the first error encountered in (2) or (3), finish the 562 * procedures, and dump the error in the end. 563 */ 564 static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs) 565 { 566 struct mtd_info *mtd = nand_to_mtd(chip); 567 int res, ret = 0; 568 569 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 570 struct erase_info einfo; 571 572 /* Attempt erase before marking OOB */ 573 memset(&einfo, 0, sizeof(einfo)); 574 einfo.addr = ofs; 575 einfo.len = 1ULL << chip->phys_erase_shift; 576 nand_erase_nand(chip, &einfo, 0); 577 578 /* Write bad block marker to OOB */ 579 nand_get_device(chip); 580 581 ret = nand_markbad_bbm(chip, ofs); 582 nand_release_device(chip); 583 } 584 585 /* Mark block bad in BBT */ 586 if (chip->bbt) { 587 res = nand_markbad_bbt(chip, ofs); 588 if (!ret) 589 ret = res; 590 } 591 592 if (!ret) 593 mtd->ecc_stats.badblocks++; 594 595 return ret; 596 } 597 598 /** 599 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. 600 * @mtd: MTD device structure 601 * @ofs: offset from device start 602 * 603 * Check if the block is marked as reserved. 604 */ 605 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 606 { 607 struct nand_chip *chip = mtd_to_nand(mtd); 608 609 if (!chip->bbt) 610 return 0; 611 /* Return info from the table */ 612 return nand_isreserved_bbt(chip, ofs); 613 } 614 615 /** 616 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 617 * @chip: NAND chip object 618 * @ofs: offset from device start 619 * @allowbbt: 1, if its allowed to access the bbt area 620 * 621 * Check, if the block is bad. Either by reading the bad block table or 622 * calling of the scan function. 623 */ 624 static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt) 625 { 626 /* Return info from the table */ 627 if (chip->bbt) 628 return nand_isbad_bbt(chip, ofs, allowbbt); 629 630 return nand_isbad_bbm(chip, ofs); 631 } 632 633 /** 634 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1 635 * @chip: NAND chip structure 636 * @timeout_ms: Timeout in ms 637 * 638 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1. 639 * If that does not happen whitin the specified timeout, -ETIMEDOUT is 640 * returned. 641 * 642 * This helper is intended to be used when the controller does not have access 643 * to the NAND R/B pin. 644 * 645 * Be aware that calling this helper from an ->exec_op() implementation means 646 * ->exec_op() must be re-entrant. 647 * 648 * Return 0 if the NAND chip is ready, a negative error otherwise. 649 */ 650 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms) 651 { 652 const struct nand_interface_config *conf; 653 u8 status = 0; 654 int ret; 655 656 if (!nand_has_exec_op(chip)) 657 return -ENOTSUPP; 658 659 /* Wait tWB before polling the STATUS reg. */ 660 conf = nand_get_interface_config(chip); 661 ndelay(NAND_COMMON_TIMING_NS(conf, tWB_max)); 662 663 ret = nand_status_op(chip, NULL); 664 if (ret) 665 return ret; 666 667 /* 668 * +1 below is necessary because if we are now in the last fraction 669 * of jiffy and msecs_to_jiffies is 1 then we will wait only that 670 * small jiffy fraction - possibly leading to false timeout 671 */ 672 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 673 do { 674 ret = nand_read_data_op(chip, &status, sizeof(status), true, 675 false); 676 if (ret) 677 break; 678 679 if (status & NAND_STATUS_READY) 680 break; 681 682 /* 683 * Typical lowest execution time for a tR on most NANDs is 10us, 684 * use this as polling delay before doing something smarter (ie. 685 * deriving a delay from the timeout value, timeout_ms/ratio). 686 */ 687 udelay(10); 688 } while (time_before(jiffies, timeout_ms)); 689 690 /* 691 * We have to exit READ_STATUS mode in order to read real data on the 692 * bus in case the WAITRDY instruction is preceding a DATA_IN 693 * instruction. 694 */ 695 nand_exit_status_op(chip); 696 697 if (ret) 698 return ret; 699 700 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; 701 }; 702 EXPORT_SYMBOL_GPL(nand_soft_waitrdy); 703 704 /** 705 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready 706 * @chip: NAND chip structure 707 * @gpiod: GPIO descriptor of R/B pin 708 * @timeout_ms: Timeout in ms 709 * 710 * Poll the R/B GPIO pin until it becomes ready. If that does not happen 711 * whitin the specified timeout, -ETIMEDOUT is returned. 712 * 713 * This helper is intended to be used when the controller has access to the 714 * NAND R/B pin over GPIO. 715 * 716 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise. 717 */ 718 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 719 unsigned long timeout_ms) 720 { 721 722 /* 723 * Wait until R/B pin indicates chip is ready or timeout occurs. 724 * +1 below is necessary because if we are now in the last fraction 725 * of jiffy and msecs_to_jiffies is 1 then we will wait only that 726 * small jiffy fraction - possibly leading to false timeout. 727 */ 728 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 729 do { 730 if (gpiod_get_value_cansleep(gpiod)) 731 return 0; 732 733 cond_resched(); 734 } while (time_before(jiffies, timeout_ms)); 735 736 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT; 737 }; 738 EXPORT_SYMBOL_GPL(nand_gpio_waitrdy); 739 740 /** 741 * panic_nand_wait - [GENERIC] wait until the command is done 742 * @chip: NAND chip structure 743 * @timeo: timeout 744 * 745 * Wait for command done. This is a helper function for nand_wait used when 746 * we are in interrupt context. May happen when in panic and trying to write 747 * an oops through mtdoops. 748 */ 749 void panic_nand_wait(struct nand_chip *chip, unsigned long timeo) 750 { 751 int i; 752 for (i = 0; i < timeo; i++) { 753 if (chip->legacy.dev_ready) { 754 if (chip->legacy.dev_ready(chip)) 755 break; 756 } else { 757 int ret; 758 u8 status; 759 760 ret = nand_read_data_op(chip, &status, sizeof(status), 761 true, false); 762 if (ret) 763 return; 764 765 if (status & NAND_STATUS_READY) 766 break; 767 } 768 mdelay(1); 769 } 770 } 771 772 static bool nand_supports_get_features(struct nand_chip *chip, int addr) 773 { 774 return (chip->parameters.supports_set_get_features && 775 test_bit(addr, chip->parameters.get_feature_list)); 776 } 777 778 static bool nand_supports_set_features(struct nand_chip *chip, int addr) 779 { 780 return (chip->parameters.supports_set_get_features && 781 test_bit(addr, chip->parameters.set_feature_list)); 782 } 783 784 /** 785 * nand_reset_interface - Reset data interface and timings 786 * @chip: The NAND chip 787 * @chipnr: Internal die id 788 * 789 * Reset the Data interface and timings to ONFI mode 0. 790 * 791 * Returns 0 for success or negative error code otherwise. 792 */ 793 static int nand_reset_interface(struct nand_chip *chip, int chipnr) 794 { 795 const struct nand_controller_ops *ops = chip->controller->ops; 796 int ret; 797 798 if (!nand_controller_can_setup_interface(chip)) 799 return 0; 800 801 /* 802 * The ONFI specification says: 803 * " 804 * To transition from NV-DDR or NV-DDR2 to the SDR data 805 * interface, the host shall use the Reset (FFh) command 806 * using SDR timing mode 0. A device in any timing mode is 807 * required to recognize Reset (FFh) command issued in SDR 808 * timing mode 0. 809 * " 810 * 811 * Configure the data interface in SDR mode and set the 812 * timings to timing mode 0. 813 */ 814 815 chip->current_interface_config = nand_get_reset_interface_config(); 816 ret = ops->setup_interface(chip, chipnr, 817 chip->current_interface_config); 818 if (ret) 819 pr_err("Failed to configure data interface to SDR timing mode 0\n"); 820 821 return ret; 822 } 823 824 /** 825 * nand_setup_interface - Setup the best data interface and timings 826 * @chip: The NAND chip 827 * @chipnr: Internal die id 828 * 829 * Configure what has been reported to be the best data interface and NAND 830 * timings supported by the chip and the driver. 831 * 832 * Returns 0 for success or negative error code otherwise. 833 */ 834 static int nand_setup_interface(struct nand_chip *chip, int chipnr) 835 { 836 const struct nand_controller_ops *ops = chip->controller->ops; 837 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }, request; 838 int ret; 839 840 if (!nand_controller_can_setup_interface(chip)) 841 return 0; 842 843 /* 844 * A nand_reset_interface() put both the NAND chip and the NAND 845 * controller in timings mode 0. If the default mode for this chip is 846 * also 0, no need to proceed to the change again. Plus, at probe time, 847 * nand_setup_interface() uses ->set/get_features() which would 848 * fail anyway as the parameter page is not available yet. 849 */ 850 if (!chip->best_interface_config) 851 return 0; 852 853 request = chip->best_interface_config->timings.mode; 854 if (nand_interface_is_sdr(chip->best_interface_config)) 855 request |= ONFI_DATA_INTERFACE_SDR; 856 else 857 request |= ONFI_DATA_INTERFACE_NVDDR; 858 tmode_param[0] = request; 859 860 /* Change the mode on the chip side (if supported by the NAND chip) */ 861 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { 862 nand_select_target(chip, chipnr); 863 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 864 tmode_param); 865 nand_deselect_target(chip); 866 if (ret) 867 return ret; 868 } 869 870 /* Change the mode on the controller side */ 871 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config); 872 if (ret) 873 return ret; 874 875 /* Check the mode has been accepted by the chip, if supported */ 876 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) 877 goto update_interface_config; 878 879 memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); 880 nand_select_target(chip, chipnr); 881 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 882 tmode_param); 883 nand_deselect_target(chip); 884 if (ret) 885 goto err_reset_chip; 886 887 if (request != tmode_param[0]) { 888 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n", 889 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR", 890 chip->best_interface_config->timings.mode); 891 pr_debug("NAND chip would work in %s timing mode %d\n", 892 tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR", 893 (unsigned int)ONFI_TIMING_MODE_PARAM(tmode_param[0])); 894 goto err_reset_chip; 895 } 896 897 update_interface_config: 898 chip->current_interface_config = chip->best_interface_config; 899 900 return 0; 901 902 err_reset_chip: 903 /* 904 * Fallback to mode 0 if the chip explicitly did not ack the chosen 905 * timing mode. 906 */ 907 nand_reset_interface(chip, chipnr); 908 nand_select_target(chip, chipnr); 909 nand_reset_op(chip); 910 nand_deselect_target(chip); 911 912 return ret; 913 } 914 915 /** 916 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the 917 * NAND controller and the NAND chip support 918 * @chip: the NAND chip 919 * @iface: the interface configuration (can eventually be updated) 920 * @spec_timings: specific timings, when not fitting the ONFI specification 921 * 922 * If specific timings are provided, use them. Otherwise, retrieve supported 923 * timing modes from ONFI information. 924 */ 925 int nand_choose_best_sdr_timings(struct nand_chip *chip, 926 struct nand_interface_config *iface, 927 struct nand_sdr_timings *spec_timings) 928 { 929 const struct nand_controller_ops *ops = chip->controller->ops; 930 int best_mode = 0, mode, ret = -EOPNOTSUPP; 931 932 iface->type = NAND_SDR_IFACE; 933 934 if (spec_timings) { 935 iface->timings.sdr = *spec_timings; 936 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings); 937 938 /* Verify the controller supports the requested interface */ 939 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 940 iface); 941 if (!ret) { 942 chip->best_interface_config = iface; 943 return ret; 944 } 945 946 /* Fallback to slower modes */ 947 best_mode = iface->timings.mode; 948 } else if (chip->parameters.onfi) { 949 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1; 950 } 951 952 for (mode = best_mode; mode >= 0; mode--) { 953 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode); 954 955 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 956 iface); 957 if (!ret) { 958 chip->best_interface_config = iface; 959 break; 960 } 961 } 962 963 return ret; 964 } 965 966 /** 967 * nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the 968 * NAND controller and the NAND chip support 969 * @chip: the NAND chip 970 * @iface: the interface configuration (can eventually be updated) 971 * @spec_timings: specific timings, when not fitting the ONFI specification 972 * 973 * If specific timings are provided, use them. Otherwise, retrieve supported 974 * timing modes from ONFI information. 975 */ 976 int nand_choose_best_nvddr_timings(struct nand_chip *chip, 977 struct nand_interface_config *iface, 978 struct nand_nvddr_timings *spec_timings) 979 { 980 const struct nand_controller_ops *ops = chip->controller->ops; 981 int best_mode = 0, mode, ret = -EOPNOTSUPP; 982 983 iface->type = NAND_NVDDR_IFACE; 984 985 if (spec_timings) { 986 iface->timings.nvddr = *spec_timings; 987 iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings); 988 989 /* Verify the controller supports the requested interface */ 990 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 991 iface); 992 if (!ret) { 993 chip->best_interface_config = iface; 994 return ret; 995 } 996 997 /* Fallback to slower modes */ 998 best_mode = iface->timings.mode; 999 } else if (chip->parameters.onfi) { 1000 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1; 1001 } 1002 1003 for (mode = best_mode; mode >= 0; mode--) { 1004 onfi_fill_interface_config(chip, iface, NAND_NVDDR_IFACE, mode); 1005 1006 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY, 1007 iface); 1008 if (!ret) { 1009 chip->best_interface_config = iface; 1010 break; 1011 } 1012 } 1013 1014 return ret; 1015 } 1016 1017 /** 1018 * nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both 1019 * NAND controller and the NAND chip support 1020 * @chip: the NAND chip 1021 * @iface: the interface configuration (can eventually be updated) 1022 * 1023 * If specific timings are provided, use them. Otherwise, retrieve supported 1024 * timing modes from ONFI information. 1025 */ 1026 static int nand_choose_best_timings(struct nand_chip *chip, 1027 struct nand_interface_config *iface) 1028 { 1029 int ret; 1030 1031 /* Try the fastest timings: NV-DDR */ 1032 ret = nand_choose_best_nvddr_timings(chip, iface, NULL); 1033 if (!ret) 1034 return 0; 1035 1036 /* Fallback to SDR timings otherwise */ 1037 return nand_choose_best_sdr_timings(chip, iface, NULL); 1038 } 1039 1040 /** 1041 * nand_choose_interface_config - find the best data interface and timings 1042 * @chip: The NAND chip 1043 * 1044 * Find the best data interface and NAND timings supported by the chip 1045 * and the driver. Eventually let the NAND manufacturer driver propose his own 1046 * set of timings. 1047 * 1048 * After this function nand_chip->interface_config is initialized with the best 1049 * timing mode available. 1050 * 1051 * Returns 0 for success or negative error code otherwise. 1052 */ 1053 static int nand_choose_interface_config(struct nand_chip *chip) 1054 { 1055 struct nand_interface_config *iface; 1056 int ret; 1057 1058 if (!nand_controller_can_setup_interface(chip)) 1059 return 0; 1060 1061 iface = kzalloc(sizeof(*iface), GFP_KERNEL); 1062 if (!iface) 1063 return -ENOMEM; 1064 1065 if (chip->ops.choose_interface_config) 1066 ret = chip->ops.choose_interface_config(chip, iface); 1067 else 1068 ret = nand_choose_best_timings(chip, iface); 1069 1070 if (ret) 1071 kfree(iface); 1072 1073 return ret; 1074 } 1075 1076 /** 1077 * nand_fill_column_cycles - fill the column cycles of an address 1078 * @chip: The NAND chip 1079 * @addrs: Array of address cycles to fill 1080 * @offset_in_page: The offset in the page 1081 * 1082 * Fills the first or the first two bytes of the @addrs field depending 1083 * on the NAND bus width and the page size. 1084 * 1085 * Returns the number of cycles needed to encode the column, or a negative 1086 * error code in case one of the arguments is invalid. 1087 */ 1088 static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs, 1089 unsigned int offset_in_page) 1090 { 1091 struct mtd_info *mtd = nand_to_mtd(chip); 1092 1093 /* Make sure the offset is less than the actual page size. */ 1094 if (offset_in_page > mtd->writesize + mtd->oobsize) 1095 return -EINVAL; 1096 1097 /* 1098 * On small page NANDs, there's a dedicated command to access the OOB 1099 * area, and the column address is relative to the start of the OOB 1100 * area, not the start of the page. Asjust the address accordingly. 1101 */ 1102 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) 1103 offset_in_page -= mtd->writesize; 1104 1105 /* 1106 * The offset in page is expressed in bytes, if the NAND bus is 16-bit 1107 * wide, then it must be divided by 2. 1108 */ 1109 if (chip->options & NAND_BUSWIDTH_16) { 1110 if (WARN_ON(offset_in_page % 2)) 1111 return -EINVAL; 1112 1113 offset_in_page /= 2; 1114 } 1115 1116 addrs[0] = offset_in_page; 1117 1118 /* 1119 * Small page NANDs use 1 cycle for the columns, while large page NANDs 1120 * need 2 1121 */ 1122 if (mtd->writesize <= 512) 1123 return 1; 1124 1125 addrs[1] = offset_in_page >> 8; 1126 1127 return 2; 1128 } 1129 1130 static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1131 unsigned int offset_in_page, void *buf, 1132 unsigned int len) 1133 { 1134 const struct nand_interface_config *conf = 1135 nand_get_interface_config(chip); 1136 struct mtd_info *mtd = nand_to_mtd(chip); 1137 u8 addrs[4]; 1138 struct nand_op_instr instrs[] = { 1139 NAND_OP_CMD(NAND_CMD_READ0, 0), 1140 NAND_OP_ADDR(3, addrs, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1141 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1142 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1143 NAND_OP_DATA_IN(len, buf, 0), 1144 }; 1145 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1146 int ret; 1147 1148 /* Drop the DATA_IN instruction if len is set to 0. */ 1149 if (!len) 1150 op.ninstrs--; 1151 1152 if (offset_in_page >= mtd->writesize) 1153 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1154 else if (offset_in_page >= 256 && 1155 !(chip->options & NAND_BUSWIDTH_16)) 1156 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1157 1158 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1159 if (ret < 0) 1160 return ret; 1161 1162 addrs[1] = page; 1163 addrs[2] = page >> 8; 1164 1165 if (chip->options & NAND_ROW_ADDR_3) { 1166 addrs[3] = page >> 16; 1167 instrs[1].ctx.addr.naddrs++; 1168 } 1169 1170 return nand_exec_op(chip, &op); 1171 } 1172 1173 static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1174 unsigned int offset_in_page, void *buf, 1175 unsigned int len) 1176 { 1177 const struct nand_interface_config *conf = 1178 nand_get_interface_config(chip); 1179 u8 addrs[5]; 1180 struct nand_op_instr instrs[] = { 1181 NAND_OP_CMD(NAND_CMD_READ0, 0), 1182 NAND_OP_ADDR(4, addrs, 0), 1183 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1184 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1185 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1186 NAND_OP_DATA_IN(len, buf, 0), 1187 }; 1188 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1189 int ret; 1190 1191 /* Drop the DATA_IN instruction if len is set to 0. */ 1192 if (!len) 1193 op.ninstrs--; 1194 1195 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1196 if (ret < 0) 1197 return ret; 1198 1199 addrs[2] = page; 1200 addrs[3] = page >> 8; 1201 1202 if (chip->options & NAND_ROW_ADDR_3) { 1203 addrs[4] = page >> 16; 1204 instrs[1].ctx.addr.naddrs++; 1205 } 1206 1207 return nand_exec_op(chip, &op); 1208 } 1209 1210 static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page, 1211 unsigned int offset_in_page, void *buf, 1212 unsigned int len, bool check_only) 1213 { 1214 const struct nand_interface_config *conf = 1215 nand_get_interface_config(chip); 1216 u8 addrs[5]; 1217 struct nand_op_instr start_instrs[] = { 1218 NAND_OP_CMD(NAND_CMD_READ0, 0), 1219 NAND_OP_ADDR(4, addrs, 0), 1220 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1221 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 0), 1222 NAND_OP_CMD(NAND_CMD_READCACHESEQ, NAND_COMMON_TIMING_NS(conf, tWB_max)), 1223 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1224 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1225 NAND_OP_DATA_IN(len, buf, 0), 1226 }; 1227 struct nand_op_instr cont_instrs[] = { 1228 NAND_OP_CMD(page == chip->cont_read.last_page ? 1229 NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ, 1230 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1231 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1232 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1233 NAND_OP_DATA_IN(len, buf, 0), 1234 }; 1235 struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs); 1236 struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs); 1237 int ret; 1238 1239 if (!len) { 1240 start_op.ninstrs--; 1241 cont_op.ninstrs--; 1242 } 1243 1244 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1245 if (ret < 0) 1246 return ret; 1247 1248 addrs[2] = page; 1249 addrs[3] = page >> 8; 1250 1251 if (chip->options & NAND_ROW_ADDR_3) { 1252 addrs[4] = page >> 16; 1253 start_instrs[1].ctx.addr.naddrs++; 1254 } 1255 1256 /* Check if cache reads are supported */ 1257 if (check_only) { 1258 if (nand_check_op(chip, &start_op) || nand_check_op(chip, &cont_op)) 1259 return -EOPNOTSUPP; 1260 1261 return 0; 1262 } 1263 1264 if (page == chip->cont_read.first_page) 1265 return nand_exec_op(chip, &start_op); 1266 else 1267 return nand_exec_op(chip, &cont_op); 1268 } 1269 1270 static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page) 1271 { 1272 return chip->cont_read.ongoing && 1273 page >= chip->cont_read.first_page && 1274 page <= chip->cont_read.last_page; 1275 } 1276 1277 /** 1278 * nand_read_page_op - Do a READ PAGE operation 1279 * @chip: The NAND chip 1280 * @page: page to read 1281 * @offset_in_page: offset within the page 1282 * @buf: buffer used to store the data 1283 * @len: length of the buffer 1284 * 1285 * This function issues a READ PAGE operation. 1286 * This function does not select/unselect the CS line. 1287 * 1288 * Returns 0 on success, a negative error code otherwise. 1289 */ 1290 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1291 unsigned int offset_in_page, void *buf, unsigned int len) 1292 { 1293 struct mtd_info *mtd = nand_to_mtd(chip); 1294 1295 if (len && !buf) 1296 return -EINVAL; 1297 1298 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1299 return -EINVAL; 1300 1301 if (nand_has_exec_op(chip)) { 1302 if (mtd->writesize > 512) { 1303 if (rawnand_cont_read_ongoing(chip, page)) 1304 return nand_lp_exec_cont_read_page_op(chip, page, 1305 offset_in_page, 1306 buf, len, false); 1307 else 1308 return nand_lp_exec_read_page_op(chip, page, 1309 offset_in_page, buf, 1310 len); 1311 } 1312 1313 return nand_sp_exec_read_page_op(chip, page, offset_in_page, 1314 buf, len); 1315 } 1316 1317 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page); 1318 if (len) 1319 chip->legacy.read_buf(chip, buf, len); 1320 1321 return 0; 1322 } 1323 EXPORT_SYMBOL_GPL(nand_read_page_op); 1324 1325 /** 1326 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation 1327 * @chip: The NAND chip 1328 * @page: parameter page to read 1329 * @buf: buffer used to store the data 1330 * @len: length of the buffer 1331 * 1332 * This function issues a READ PARAMETER PAGE operation. 1333 * This function does not select/unselect the CS line. 1334 * 1335 * Returns 0 on success, a negative error code otherwise. 1336 */ 1337 int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf, 1338 unsigned int len) 1339 { 1340 unsigned int i; 1341 u8 *p = buf; 1342 1343 if (len && !buf) 1344 return -EINVAL; 1345 1346 if (nand_has_exec_op(chip)) { 1347 const struct nand_interface_config *conf = 1348 nand_get_interface_config(chip); 1349 struct nand_op_instr instrs[] = { 1350 NAND_OP_CMD(NAND_CMD_PARAM, 0), 1351 NAND_OP_ADDR(1, &page, 1352 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1353 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 1354 NAND_COMMON_TIMING_NS(conf, tRR_min)), 1355 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1356 }; 1357 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1358 1359 /* Drop the DATA_IN instruction if len is set to 0. */ 1360 if (!len) 1361 op.ninstrs--; 1362 1363 return nand_exec_op(chip, &op); 1364 } 1365 1366 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1); 1367 for (i = 0; i < len; i++) 1368 p[i] = chip->legacy.read_byte(chip); 1369 1370 return 0; 1371 } 1372 1373 /** 1374 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation 1375 * @chip: The NAND chip 1376 * @offset_in_page: offset within the page 1377 * @buf: buffer used to store the data 1378 * @len: length of the buffer 1379 * @force_8bit: force 8-bit bus access 1380 * 1381 * This function issues a CHANGE READ COLUMN operation. 1382 * This function does not select/unselect the CS line. 1383 * 1384 * Returns 0 on success, a negative error code otherwise. 1385 */ 1386 int nand_change_read_column_op(struct nand_chip *chip, 1387 unsigned int offset_in_page, void *buf, 1388 unsigned int len, bool force_8bit) 1389 { 1390 struct mtd_info *mtd = nand_to_mtd(chip); 1391 1392 if (len && !buf) 1393 return -EINVAL; 1394 1395 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1396 return -EINVAL; 1397 1398 /* Small page NANDs do not support column change. */ 1399 if (mtd->writesize <= 512) 1400 return -ENOTSUPP; 1401 1402 if (nand_has_exec_op(chip)) { 1403 const struct nand_interface_config *conf = 1404 nand_get_interface_config(chip); 1405 u8 addrs[2] = {}; 1406 struct nand_op_instr instrs[] = { 1407 NAND_OP_CMD(NAND_CMD_RNDOUT, 0), 1408 NAND_OP_ADDR(2, addrs, 0), 1409 NAND_OP_CMD(NAND_CMD_RNDOUTSTART, 1410 NAND_COMMON_TIMING_NS(conf, tCCS_min)), 1411 NAND_OP_DATA_IN(len, buf, 0), 1412 }; 1413 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1414 int ret; 1415 1416 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1417 if (ret < 0) 1418 return ret; 1419 1420 /* Drop the DATA_IN instruction if len is set to 0. */ 1421 if (!len) 1422 op.ninstrs--; 1423 1424 instrs[3].ctx.data.force_8bit = force_8bit; 1425 1426 return nand_exec_op(chip, &op); 1427 } 1428 1429 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1); 1430 if (len) 1431 chip->legacy.read_buf(chip, buf, len); 1432 1433 return 0; 1434 } 1435 EXPORT_SYMBOL_GPL(nand_change_read_column_op); 1436 1437 /** 1438 * nand_read_oob_op - Do a READ OOB operation 1439 * @chip: The NAND chip 1440 * @page: page to read 1441 * @offset_in_oob: offset within the OOB area 1442 * @buf: buffer used to store the data 1443 * @len: length of the buffer 1444 * 1445 * This function issues a READ OOB operation. 1446 * This function does not select/unselect the CS line. 1447 * 1448 * Returns 0 on success, a negative error code otherwise. 1449 */ 1450 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1451 unsigned int offset_in_oob, void *buf, unsigned int len) 1452 { 1453 struct mtd_info *mtd = nand_to_mtd(chip); 1454 1455 if (len && !buf) 1456 return -EINVAL; 1457 1458 if (offset_in_oob + len > mtd->oobsize) 1459 return -EINVAL; 1460 1461 if (nand_has_exec_op(chip)) 1462 return nand_read_page_op(chip, page, 1463 mtd->writesize + offset_in_oob, 1464 buf, len); 1465 1466 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page); 1467 if (len) 1468 chip->legacy.read_buf(chip, buf, len); 1469 1470 return 0; 1471 } 1472 EXPORT_SYMBOL_GPL(nand_read_oob_op); 1473 1474 static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page, 1475 unsigned int offset_in_page, const void *buf, 1476 unsigned int len, bool prog) 1477 { 1478 const struct nand_interface_config *conf = 1479 nand_get_interface_config(chip); 1480 struct mtd_info *mtd = nand_to_mtd(chip); 1481 u8 addrs[5] = {}; 1482 struct nand_op_instr instrs[] = { 1483 /* 1484 * The first instruction will be dropped if we're dealing 1485 * with a large page NAND and adjusted if we're dealing 1486 * with a small page NAND and the page offset is > 255. 1487 */ 1488 NAND_OP_CMD(NAND_CMD_READ0, 0), 1489 NAND_OP_CMD(NAND_CMD_SEQIN, 0), 1490 NAND_OP_ADDR(0, addrs, NAND_COMMON_TIMING_NS(conf, tADL_min)), 1491 NAND_OP_DATA_OUT(len, buf, 0), 1492 NAND_OP_CMD(NAND_CMD_PAGEPROG, 1493 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1494 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0), 1495 }; 1496 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1497 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page); 1498 1499 if (naddrs < 0) 1500 return naddrs; 1501 1502 addrs[naddrs++] = page; 1503 addrs[naddrs++] = page >> 8; 1504 if (chip->options & NAND_ROW_ADDR_3) 1505 addrs[naddrs++] = page >> 16; 1506 1507 instrs[2].ctx.addr.naddrs = naddrs; 1508 1509 /* Drop the last two instructions if we're not programming the page. */ 1510 if (!prog) { 1511 op.ninstrs -= 2; 1512 /* Also drop the DATA_OUT instruction if empty. */ 1513 if (!len) 1514 op.ninstrs--; 1515 } 1516 1517 if (mtd->writesize <= 512) { 1518 /* 1519 * Small pages need some more tweaking: we have to adjust the 1520 * first instruction depending on the page offset we're trying 1521 * to access. 1522 */ 1523 if (offset_in_page >= mtd->writesize) 1524 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1525 else if (offset_in_page >= 256 && 1526 !(chip->options & NAND_BUSWIDTH_16)) 1527 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1528 } else { 1529 /* 1530 * Drop the first command if we're dealing with a large page 1531 * NAND. 1532 */ 1533 op.instrs++; 1534 op.ninstrs--; 1535 } 1536 1537 return nand_exec_op(chip, &op); 1538 } 1539 1540 /** 1541 * nand_prog_page_begin_op - starts a PROG PAGE operation 1542 * @chip: The NAND chip 1543 * @page: page to write 1544 * @offset_in_page: offset within the page 1545 * @buf: buffer containing the data to write to the page 1546 * @len: length of the buffer 1547 * 1548 * This function issues the first half of a PROG PAGE operation. 1549 * This function does not select/unselect the CS line. 1550 * 1551 * Returns 0 on success, a negative error code otherwise. 1552 */ 1553 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1554 unsigned int offset_in_page, const void *buf, 1555 unsigned int len) 1556 { 1557 struct mtd_info *mtd = nand_to_mtd(chip); 1558 1559 if (len && !buf) 1560 return -EINVAL; 1561 1562 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1563 return -EINVAL; 1564 1565 if (nand_has_exec_op(chip)) 1566 return nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1567 len, false); 1568 1569 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page); 1570 1571 if (buf) 1572 chip->legacy.write_buf(chip, buf, len); 1573 1574 return 0; 1575 } 1576 EXPORT_SYMBOL_GPL(nand_prog_page_begin_op); 1577 1578 /** 1579 * nand_prog_page_end_op - ends a PROG PAGE operation 1580 * @chip: The NAND chip 1581 * 1582 * This function issues the second half of a PROG PAGE operation. 1583 * This function does not select/unselect the CS line. 1584 * 1585 * Returns 0 on success, a negative error code otherwise. 1586 */ 1587 int nand_prog_page_end_op(struct nand_chip *chip) 1588 { 1589 int ret; 1590 u8 status; 1591 1592 if (nand_has_exec_op(chip)) { 1593 const struct nand_interface_config *conf = 1594 nand_get_interface_config(chip); 1595 struct nand_op_instr instrs[] = { 1596 NAND_OP_CMD(NAND_CMD_PAGEPROG, 1597 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1598 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 1599 0), 1600 }; 1601 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1602 1603 ret = nand_exec_op(chip, &op); 1604 if (ret) 1605 return ret; 1606 1607 ret = nand_status_op(chip, &status); 1608 if (ret) 1609 return ret; 1610 } else { 1611 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1612 ret = chip->legacy.waitfunc(chip); 1613 if (ret < 0) 1614 return ret; 1615 1616 status = ret; 1617 } 1618 1619 if (status & NAND_STATUS_FAIL) 1620 return -EIO; 1621 1622 return 0; 1623 } 1624 EXPORT_SYMBOL_GPL(nand_prog_page_end_op); 1625 1626 /** 1627 * nand_prog_page_op - Do a full PROG PAGE operation 1628 * @chip: The NAND chip 1629 * @page: page to write 1630 * @offset_in_page: offset within the page 1631 * @buf: buffer containing the data to write to the page 1632 * @len: length of the buffer 1633 * 1634 * This function issues a full PROG PAGE operation. 1635 * This function does not select/unselect the CS line. 1636 * 1637 * Returns 0 on success, a negative error code otherwise. 1638 */ 1639 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1640 unsigned int offset_in_page, const void *buf, 1641 unsigned int len) 1642 { 1643 struct mtd_info *mtd = nand_to_mtd(chip); 1644 u8 status; 1645 int ret; 1646 1647 if (!len || !buf) 1648 return -EINVAL; 1649 1650 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1651 return -EINVAL; 1652 1653 if (nand_has_exec_op(chip)) { 1654 ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1655 len, true); 1656 if (ret) 1657 return ret; 1658 1659 ret = nand_status_op(chip, &status); 1660 if (ret) 1661 return ret; 1662 } else { 1663 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, 1664 page); 1665 chip->legacy.write_buf(chip, buf, len); 1666 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1667 ret = chip->legacy.waitfunc(chip); 1668 if (ret < 0) 1669 return ret; 1670 1671 status = ret; 1672 } 1673 1674 if (status & NAND_STATUS_FAIL) 1675 return -EIO; 1676 1677 return 0; 1678 } 1679 EXPORT_SYMBOL_GPL(nand_prog_page_op); 1680 1681 /** 1682 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation 1683 * @chip: The NAND chip 1684 * @offset_in_page: offset within the page 1685 * @buf: buffer containing the data to send to the NAND 1686 * @len: length of the buffer 1687 * @force_8bit: force 8-bit bus access 1688 * 1689 * This function issues a CHANGE WRITE COLUMN operation. 1690 * This function does not select/unselect the CS line. 1691 * 1692 * Returns 0 on success, a negative error code otherwise. 1693 */ 1694 int nand_change_write_column_op(struct nand_chip *chip, 1695 unsigned int offset_in_page, 1696 const void *buf, unsigned int len, 1697 bool force_8bit) 1698 { 1699 struct mtd_info *mtd = nand_to_mtd(chip); 1700 1701 if (len && !buf) 1702 return -EINVAL; 1703 1704 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1705 return -EINVAL; 1706 1707 /* Small page NANDs do not support column change. */ 1708 if (mtd->writesize <= 512) 1709 return -ENOTSUPP; 1710 1711 if (nand_has_exec_op(chip)) { 1712 const struct nand_interface_config *conf = 1713 nand_get_interface_config(chip); 1714 u8 addrs[2]; 1715 struct nand_op_instr instrs[] = { 1716 NAND_OP_CMD(NAND_CMD_RNDIN, 0), 1717 NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)), 1718 NAND_OP_DATA_OUT(len, buf, 0), 1719 }; 1720 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1721 int ret; 1722 1723 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1724 if (ret < 0) 1725 return ret; 1726 1727 instrs[2].ctx.data.force_8bit = force_8bit; 1728 1729 /* Drop the DATA_OUT instruction if len is set to 0. */ 1730 if (!len) 1731 op.ninstrs--; 1732 1733 return nand_exec_op(chip, &op); 1734 } 1735 1736 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1); 1737 if (len) 1738 chip->legacy.write_buf(chip, buf, len); 1739 1740 return 0; 1741 } 1742 EXPORT_SYMBOL_GPL(nand_change_write_column_op); 1743 1744 /** 1745 * nand_readid_op - Do a READID operation 1746 * @chip: The NAND chip 1747 * @addr: address cycle to pass after the READID command 1748 * @buf: buffer used to store the ID 1749 * @len: length of the buffer 1750 * 1751 * This function sends a READID command and reads back the ID returned by the 1752 * NAND. 1753 * This function does not select/unselect the CS line. 1754 * 1755 * Returns 0 on success, a negative error code otherwise. 1756 */ 1757 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1758 unsigned int len) 1759 { 1760 unsigned int i; 1761 u8 *id = buf, *ddrbuf = NULL; 1762 1763 if (len && !buf) 1764 return -EINVAL; 1765 1766 if (nand_has_exec_op(chip)) { 1767 const struct nand_interface_config *conf = 1768 nand_get_interface_config(chip); 1769 struct nand_op_instr instrs[] = { 1770 NAND_OP_CMD(NAND_CMD_READID, 0), 1771 NAND_OP_ADDR(1, &addr, 1772 NAND_COMMON_TIMING_NS(conf, tADL_min)), 1773 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1774 }; 1775 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1776 int ret; 1777 1778 /* READ_ID data bytes are received twice in NV-DDR mode */ 1779 if (len && nand_interface_is_nvddr(conf)) { 1780 ddrbuf = kzalloc(len * 2, GFP_KERNEL); 1781 if (!ddrbuf) 1782 return -ENOMEM; 1783 1784 instrs[2].ctx.data.len *= 2; 1785 instrs[2].ctx.data.buf.in = ddrbuf; 1786 } 1787 1788 /* Drop the DATA_IN instruction if len is set to 0. */ 1789 if (!len) 1790 op.ninstrs--; 1791 1792 ret = nand_exec_op(chip, &op); 1793 if (!ret && len && nand_interface_is_nvddr(conf)) { 1794 for (i = 0; i < len; i++) 1795 id[i] = ddrbuf[i * 2]; 1796 } 1797 1798 kfree(ddrbuf); 1799 1800 return ret; 1801 } 1802 1803 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1); 1804 1805 for (i = 0; i < len; i++) 1806 id[i] = chip->legacy.read_byte(chip); 1807 1808 return 0; 1809 } 1810 EXPORT_SYMBOL_GPL(nand_readid_op); 1811 1812 /** 1813 * nand_status_op - Do a STATUS operation 1814 * @chip: The NAND chip 1815 * @status: out variable to store the NAND status 1816 * 1817 * This function sends a STATUS command and reads back the status returned by 1818 * the NAND. 1819 * This function does not select/unselect the CS line. 1820 * 1821 * Returns 0 on success, a negative error code otherwise. 1822 */ 1823 int nand_status_op(struct nand_chip *chip, u8 *status) 1824 { 1825 if (nand_has_exec_op(chip)) { 1826 const struct nand_interface_config *conf = 1827 nand_get_interface_config(chip); 1828 u8 ddrstatus[2]; 1829 struct nand_op_instr instrs[] = { 1830 NAND_OP_CMD(NAND_CMD_STATUS, 1831 NAND_COMMON_TIMING_NS(conf, tADL_min)), 1832 NAND_OP_8BIT_DATA_IN(1, status, 0), 1833 }; 1834 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1835 int ret; 1836 1837 /* The status data byte will be received twice in NV-DDR mode */ 1838 if (status && nand_interface_is_nvddr(conf)) { 1839 instrs[1].ctx.data.len *= 2; 1840 instrs[1].ctx.data.buf.in = ddrstatus; 1841 } 1842 1843 if (!status) 1844 op.ninstrs--; 1845 1846 ret = nand_exec_op(chip, &op); 1847 if (!ret && status && nand_interface_is_nvddr(conf)) 1848 *status = ddrstatus[0]; 1849 1850 return ret; 1851 } 1852 1853 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1); 1854 if (status) 1855 *status = chip->legacy.read_byte(chip); 1856 1857 return 0; 1858 } 1859 EXPORT_SYMBOL_GPL(nand_status_op); 1860 1861 /** 1862 * nand_exit_status_op - Exit a STATUS operation 1863 * @chip: The NAND chip 1864 * 1865 * This function sends a READ0 command to cancel the effect of the STATUS 1866 * command to avoid reading only the status until a new read command is sent. 1867 * 1868 * This function does not select/unselect the CS line. 1869 * 1870 * Returns 0 on success, a negative error code otherwise. 1871 */ 1872 int nand_exit_status_op(struct nand_chip *chip) 1873 { 1874 if (nand_has_exec_op(chip)) { 1875 struct nand_op_instr instrs[] = { 1876 NAND_OP_CMD(NAND_CMD_READ0, 0), 1877 }; 1878 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1879 1880 return nand_exec_op(chip, &op); 1881 } 1882 1883 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1); 1884 1885 return 0; 1886 } 1887 EXPORT_SYMBOL_GPL(nand_exit_status_op); 1888 1889 /** 1890 * nand_erase_op - Do an erase operation 1891 * @chip: The NAND chip 1892 * @eraseblock: block to erase 1893 * 1894 * This function sends an ERASE command and waits for the NAND to be ready 1895 * before returning. 1896 * This function does not select/unselect the CS line. 1897 * 1898 * Returns 0 on success, a negative error code otherwise. 1899 */ 1900 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock) 1901 { 1902 unsigned int page = eraseblock << 1903 (chip->phys_erase_shift - chip->page_shift); 1904 int ret; 1905 u8 status; 1906 1907 if (nand_has_exec_op(chip)) { 1908 const struct nand_interface_config *conf = 1909 nand_get_interface_config(chip); 1910 u8 addrs[3] = { page, page >> 8, page >> 16 }; 1911 struct nand_op_instr instrs[] = { 1912 NAND_OP_CMD(NAND_CMD_ERASE1, 0), 1913 NAND_OP_ADDR(2, addrs, 0), 1914 NAND_OP_CMD(NAND_CMD_ERASE2, 1915 NAND_COMMON_TIMING_NS(conf, tWB_max)), 1916 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max), 1917 0), 1918 }; 1919 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1920 1921 if (chip->options & NAND_ROW_ADDR_3) 1922 instrs[1].ctx.addr.naddrs++; 1923 1924 ret = nand_exec_op(chip, &op); 1925 if (ret) 1926 return ret; 1927 1928 ret = nand_status_op(chip, &status); 1929 if (ret) 1930 return ret; 1931 } else { 1932 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page); 1933 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1); 1934 1935 ret = chip->legacy.waitfunc(chip); 1936 if (ret < 0) 1937 return ret; 1938 1939 status = ret; 1940 } 1941 1942 if (status & NAND_STATUS_FAIL) 1943 return -EIO; 1944 1945 return 0; 1946 } 1947 EXPORT_SYMBOL_GPL(nand_erase_op); 1948 1949 /** 1950 * nand_set_features_op - Do a SET FEATURES operation 1951 * @chip: The NAND chip 1952 * @feature: feature id 1953 * @data: 4 bytes of data 1954 * 1955 * This function sends a SET FEATURES command and waits for the NAND to be 1956 * ready before returning. 1957 * This function does not select/unselect the CS line. 1958 * 1959 * Returns 0 on success, a negative error code otherwise. 1960 */ 1961 static int nand_set_features_op(struct nand_chip *chip, u8 feature, 1962 const void *data) 1963 { 1964 const u8 *params = data; 1965 int i, ret; 1966 1967 if (nand_has_exec_op(chip)) { 1968 const struct nand_interface_config *conf = 1969 nand_get_interface_config(chip); 1970 struct nand_op_instr instrs[] = { 1971 NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0), 1972 NAND_OP_ADDR(1, &feature, NAND_COMMON_TIMING_NS(conf, 1973 tADL_min)), 1974 NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data, 1975 NAND_COMMON_TIMING_NS(conf, 1976 tWB_max)), 1977 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max), 1978 0), 1979 }; 1980 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1981 1982 return nand_exec_op(chip, &op); 1983 } 1984 1985 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1); 1986 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1987 chip->legacy.write_byte(chip, params[i]); 1988 1989 ret = chip->legacy.waitfunc(chip); 1990 if (ret < 0) 1991 return ret; 1992 1993 if (ret & NAND_STATUS_FAIL) 1994 return -EIO; 1995 1996 return 0; 1997 } 1998 1999 /** 2000 * nand_get_features_op - Do a GET FEATURES operation 2001 * @chip: The NAND chip 2002 * @feature: feature id 2003 * @data: 4 bytes of data 2004 * 2005 * This function sends a GET FEATURES command and waits for the NAND to be 2006 * ready before returning. 2007 * This function does not select/unselect the CS line. 2008 * 2009 * Returns 0 on success, a negative error code otherwise. 2010 */ 2011 static int nand_get_features_op(struct nand_chip *chip, u8 feature, 2012 void *data) 2013 { 2014 u8 *params = data, ddrbuf[ONFI_SUBFEATURE_PARAM_LEN * 2]; 2015 int i; 2016 2017 if (nand_has_exec_op(chip)) { 2018 const struct nand_interface_config *conf = 2019 nand_get_interface_config(chip); 2020 struct nand_op_instr instrs[] = { 2021 NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0), 2022 NAND_OP_ADDR(1, &feature, 2023 NAND_COMMON_TIMING_NS(conf, tWB_max)), 2024 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max), 2025 NAND_COMMON_TIMING_NS(conf, tRR_min)), 2026 NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN, 2027 data, 0), 2028 }; 2029 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2030 int ret; 2031 2032 /* GET_FEATURE data bytes are received twice in NV-DDR mode */ 2033 if (nand_interface_is_nvddr(conf)) { 2034 instrs[3].ctx.data.len *= 2; 2035 instrs[3].ctx.data.buf.in = ddrbuf; 2036 } 2037 2038 ret = nand_exec_op(chip, &op); 2039 if (nand_interface_is_nvddr(conf)) { 2040 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; i++) 2041 params[i] = ddrbuf[i * 2]; 2042 } 2043 2044 return ret; 2045 } 2046 2047 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1); 2048 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 2049 params[i] = chip->legacy.read_byte(chip); 2050 2051 return 0; 2052 } 2053 2054 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms, 2055 unsigned int delay_ns) 2056 { 2057 if (nand_has_exec_op(chip)) { 2058 struct nand_op_instr instrs[] = { 2059 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms), 2060 PSEC_TO_NSEC(delay_ns)), 2061 }; 2062 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2063 2064 return nand_exec_op(chip, &op); 2065 } 2066 2067 /* Apply delay or wait for ready/busy pin */ 2068 if (!chip->legacy.dev_ready) 2069 udelay(chip->legacy.chip_delay); 2070 else 2071 nand_wait_ready(chip); 2072 2073 return 0; 2074 } 2075 2076 /** 2077 * nand_reset_op - Do a reset operation 2078 * @chip: The NAND chip 2079 * 2080 * This function sends a RESET command and waits for the NAND to be ready 2081 * before returning. 2082 * This function does not select/unselect the CS line. 2083 * 2084 * Returns 0 on success, a negative error code otherwise. 2085 */ 2086 int nand_reset_op(struct nand_chip *chip) 2087 { 2088 if (nand_has_exec_op(chip)) { 2089 const struct nand_interface_config *conf = 2090 nand_get_interface_config(chip); 2091 struct nand_op_instr instrs[] = { 2092 NAND_OP_CMD(NAND_CMD_RESET, 2093 NAND_COMMON_TIMING_NS(conf, tWB_max)), 2094 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tRST_max), 2095 0), 2096 }; 2097 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2098 2099 return nand_exec_op(chip, &op); 2100 } 2101 2102 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1); 2103 2104 return 0; 2105 } 2106 EXPORT_SYMBOL_GPL(nand_reset_op); 2107 2108 /** 2109 * nand_read_data_op - Read data from the NAND 2110 * @chip: The NAND chip 2111 * @buf: buffer used to store the data 2112 * @len: length of the buffer 2113 * @force_8bit: force 8-bit bus access 2114 * @check_only: do not actually run the command, only checks if the 2115 * controller driver supports it 2116 * 2117 * This function does a raw data read on the bus. Usually used after launching 2118 * another NAND operation like nand_read_page_op(). 2119 * This function does not select/unselect the CS line. 2120 * 2121 * Returns 0 on success, a negative error code otherwise. 2122 */ 2123 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 2124 bool force_8bit, bool check_only) 2125 { 2126 if (!len || !buf) 2127 return -EINVAL; 2128 2129 if (nand_has_exec_op(chip)) { 2130 const struct nand_interface_config *conf = 2131 nand_get_interface_config(chip); 2132 struct nand_op_instr instrs[] = { 2133 NAND_OP_DATA_IN(len, buf, 0), 2134 }; 2135 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2136 u8 *ddrbuf = NULL; 2137 int ret, i; 2138 2139 instrs[0].ctx.data.force_8bit = force_8bit; 2140 2141 /* 2142 * Parameter payloads (ID, status, features, etc) do not go 2143 * through the same pipeline as regular data, hence the 2144 * force_8bit flag must be set and this also indicates that in 2145 * case NV-DDR timings are being used the data will be received 2146 * twice. 2147 */ 2148 if (force_8bit && nand_interface_is_nvddr(conf)) { 2149 ddrbuf = kzalloc(len * 2, GFP_KERNEL); 2150 if (!ddrbuf) 2151 return -ENOMEM; 2152 2153 instrs[0].ctx.data.len *= 2; 2154 instrs[0].ctx.data.buf.in = ddrbuf; 2155 } 2156 2157 if (check_only) { 2158 ret = nand_check_op(chip, &op); 2159 kfree(ddrbuf); 2160 return ret; 2161 } 2162 2163 ret = nand_exec_op(chip, &op); 2164 if (!ret && force_8bit && nand_interface_is_nvddr(conf)) { 2165 u8 *dst = buf; 2166 2167 for (i = 0; i < len; i++) 2168 dst[i] = ddrbuf[i * 2]; 2169 } 2170 2171 kfree(ddrbuf); 2172 2173 return ret; 2174 } 2175 2176 if (check_only) 2177 return 0; 2178 2179 if (force_8bit) { 2180 u8 *p = buf; 2181 unsigned int i; 2182 2183 for (i = 0; i < len; i++) 2184 p[i] = chip->legacy.read_byte(chip); 2185 } else { 2186 chip->legacy.read_buf(chip, buf, len); 2187 } 2188 2189 return 0; 2190 } 2191 EXPORT_SYMBOL_GPL(nand_read_data_op); 2192 2193 /** 2194 * nand_write_data_op - Write data from the NAND 2195 * @chip: The NAND chip 2196 * @buf: buffer containing the data to send on the bus 2197 * @len: length of the buffer 2198 * @force_8bit: force 8-bit bus access 2199 * 2200 * This function does a raw data write on the bus. Usually used after launching 2201 * another NAND operation like nand_write_page_begin_op(). 2202 * This function does not select/unselect the CS line. 2203 * 2204 * Returns 0 on success, a negative error code otherwise. 2205 */ 2206 int nand_write_data_op(struct nand_chip *chip, const void *buf, 2207 unsigned int len, bool force_8bit) 2208 { 2209 if (!len || !buf) 2210 return -EINVAL; 2211 2212 if (nand_has_exec_op(chip)) { 2213 struct nand_op_instr instrs[] = { 2214 NAND_OP_DATA_OUT(len, buf, 0), 2215 }; 2216 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 2217 2218 instrs[0].ctx.data.force_8bit = force_8bit; 2219 2220 return nand_exec_op(chip, &op); 2221 } 2222 2223 if (force_8bit) { 2224 const u8 *p = buf; 2225 unsigned int i; 2226 2227 for (i = 0; i < len; i++) 2228 chip->legacy.write_byte(chip, p[i]); 2229 } else { 2230 chip->legacy.write_buf(chip, buf, len); 2231 } 2232 2233 return 0; 2234 } 2235 EXPORT_SYMBOL_GPL(nand_write_data_op); 2236 2237 /** 2238 * struct nand_op_parser_ctx - Context used by the parser 2239 * @instrs: array of all the instructions that must be addressed 2240 * @ninstrs: length of the @instrs array 2241 * @subop: Sub-operation to be passed to the NAND controller 2242 * 2243 * This structure is used by the core to split NAND operations into 2244 * sub-operations that can be handled by the NAND controller. 2245 */ 2246 struct nand_op_parser_ctx { 2247 const struct nand_op_instr *instrs; 2248 unsigned int ninstrs; 2249 struct nand_subop subop; 2250 }; 2251 2252 /** 2253 * nand_op_parser_must_split_instr - Checks if an instruction must be split 2254 * @pat: the parser pattern element that matches @instr 2255 * @instr: pointer to the instruction to check 2256 * @start_offset: this is an in/out parameter. If @instr has already been 2257 * split, then @start_offset is the offset from which to start 2258 * (either an address cycle or an offset in the data buffer). 2259 * Conversely, if the function returns true (ie. instr must be 2260 * split), this parameter is updated to point to the first 2261 * data/address cycle that has not been taken care of. 2262 * 2263 * Some NAND controllers are limited and cannot send X address cycles with a 2264 * unique operation, or cannot read/write more than Y bytes at the same time. 2265 * In this case, split the instruction that does not fit in a single 2266 * controller-operation into two or more chunks. 2267 * 2268 * Returns true if the instruction must be split, false otherwise. 2269 * The @start_offset parameter is also updated to the offset at which the next 2270 * bundle of instruction must start (if an address or a data instruction). 2271 */ 2272 static bool 2273 nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat, 2274 const struct nand_op_instr *instr, 2275 unsigned int *start_offset) 2276 { 2277 switch (pat->type) { 2278 case NAND_OP_ADDR_INSTR: 2279 if (!pat->ctx.addr.maxcycles) 2280 break; 2281 2282 if (instr->ctx.addr.naddrs - *start_offset > 2283 pat->ctx.addr.maxcycles) { 2284 *start_offset += pat->ctx.addr.maxcycles; 2285 return true; 2286 } 2287 break; 2288 2289 case NAND_OP_DATA_IN_INSTR: 2290 case NAND_OP_DATA_OUT_INSTR: 2291 if (!pat->ctx.data.maxlen) 2292 break; 2293 2294 if (instr->ctx.data.len - *start_offset > 2295 pat->ctx.data.maxlen) { 2296 *start_offset += pat->ctx.data.maxlen; 2297 return true; 2298 } 2299 break; 2300 2301 default: 2302 break; 2303 } 2304 2305 return false; 2306 } 2307 2308 /** 2309 * nand_op_parser_match_pat - Checks if a pattern matches the instructions 2310 * remaining in the parser context 2311 * @pat: the pattern to test 2312 * @ctx: the parser context structure to match with the pattern @pat 2313 * 2314 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx. 2315 * Returns true if this is the case, false ortherwise. When true is returned, 2316 * @ctx->subop is updated with the set of instructions to be passed to the 2317 * controller driver. 2318 */ 2319 static bool 2320 nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat, 2321 struct nand_op_parser_ctx *ctx) 2322 { 2323 unsigned int instr_offset = ctx->subop.first_instr_start_off; 2324 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; 2325 const struct nand_op_instr *instr = ctx->subop.instrs; 2326 unsigned int i, ninstrs; 2327 2328 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { 2329 /* 2330 * The pattern instruction does not match the operation 2331 * instruction. If the instruction is marked optional in the 2332 * pattern definition, we skip the pattern element and continue 2333 * to the next one. If the element is mandatory, there's no 2334 * match and we can return false directly. 2335 */ 2336 if (instr->type != pat->elems[i].type) { 2337 if (!pat->elems[i].optional) 2338 return false; 2339 2340 continue; 2341 } 2342 2343 /* 2344 * Now check the pattern element constraints. If the pattern is 2345 * not able to handle the whole instruction in a single step, 2346 * we have to split it. 2347 * The last_instr_end_off value comes back updated to point to 2348 * the position where we have to split the instruction (the 2349 * start of the next subop chunk). 2350 */ 2351 if (nand_op_parser_must_split_instr(&pat->elems[i], instr, 2352 &instr_offset)) { 2353 ninstrs++; 2354 i++; 2355 break; 2356 } 2357 2358 instr++; 2359 ninstrs++; 2360 instr_offset = 0; 2361 } 2362 2363 /* 2364 * This can happen if all instructions of a pattern are optional. 2365 * Still, if there's not at least one instruction handled by this 2366 * pattern, this is not a match, and we should try the next one (if 2367 * any). 2368 */ 2369 if (!ninstrs) 2370 return false; 2371 2372 /* 2373 * We had a match on the pattern head, but the pattern may be longer 2374 * than the instructions we're asked to execute. We need to make sure 2375 * there's no mandatory elements in the pattern tail. 2376 */ 2377 for (; i < pat->nelems; i++) { 2378 if (!pat->elems[i].optional) 2379 return false; 2380 } 2381 2382 /* 2383 * We have a match: update the subop structure accordingly and return 2384 * true. 2385 */ 2386 ctx->subop.ninstrs = ninstrs; 2387 ctx->subop.last_instr_end_off = instr_offset; 2388 2389 return true; 2390 } 2391 2392 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) 2393 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2394 { 2395 const struct nand_op_instr *instr; 2396 char *prefix = " "; 2397 unsigned int i; 2398 2399 pr_debug("executing subop (CS%d):\n", ctx->subop.cs); 2400 2401 for (i = 0; i < ctx->ninstrs; i++) { 2402 instr = &ctx->instrs[i]; 2403 2404 if (instr == &ctx->subop.instrs[0]) 2405 prefix = " ->"; 2406 2407 nand_op_trace(prefix, instr); 2408 2409 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) 2410 prefix = " "; 2411 } 2412 } 2413 #else 2414 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2415 { 2416 /* NOP */ 2417 } 2418 #endif 2419 2420 static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a, 2421 const struct nand_op_parser_ctx *b) 2422 { 2423 if (a->subop.ninstrs < b->subop.ninstrs) 2424 return -1; 2425 else if (a->subop.ninstrs > b->subop.ninstrs) 2426 return 1; 2427 2428 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off) 2429 return -1; 2430 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off) 2431 return 1; 2432 2433 return 0; 2434 } 2435 2436 /** 2437 * nand_op_parser_exec_op - exec_op parser 2438 * @chip: the NAND chip 2439 * @parser: patterns description provided by the controller driver 2440 * @op: the NAND operation to address 2441 * @check_only: when true, the function only checks if @op can be handled but 2442 * does not execute the operation 2443 * 2444 * Helper function designed to ease integration of NAND controller drivers that 2445 * only support a limited set of instruction sequences. The supported sequences 2446 * are described in @parser, and the framework takes care of splitting @op into 2447 * multiple sub-operations (if required) and pass them back to the ->exec() 2448 * callback of the matching pattern if @check_only is set to false. 2449 * 2450 * NAND controller drivers should call this function from their own ->exec_op() 2451 * implementation. 2452 * 2453 * Returns 0 on success, a negative error code otherwise. A failure can be 2454 * caused by an unsupported operation (none of the supported patterns is able 2455 * to handle the requested operation), or an error returned by one of the 2456 * matching pattern->exec() hook. 2457 */ 2458 int nand_op_parser_exec_op(struct nand_chip *chip, 2459 const struct nand_op_parser *parser, 2460 const struct nand_operation *op, bool check_only) 2461 { 2462 struct nand_op_parser_ctx ctx = { 2463 .subop.cs = op->cs, 2464 .subop.instrs = op->instrs, 2465 .instrs = op->instrs, 2466 .ninstrs = op->ninstrs, 2467 }; 2468 unsigned int i; 2469 2470 while (ctx.subop.instrs < op->instrs + op->ninstrs) { 2471 const struct nand_op_parser_pattern *pattern; 2472 struct nand_op_parser_ctx best_ctx; 2473 int ret, best_pattern = -1; 2474 2475 for (i = 0; i < parser->npatterns; i++) { 2476 struct nand_op_parser_ctx test_ctx = ctx; 2477 2478 pattern = &parser->patterns[i]; 2479 if (!nand_op_parser_match_pat(pattern, &test_ctx)) 2480 continue; 2481 2482 if (best_pattern >= 0 && 2483 nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0) 2484 continue; 2485 2486 best_pattern = i; 2487 best_ctx = test_ctx; 2488 } 2489 2490 if (best_pattern < 0) { 2491 pr_debug("->exec_op() parser: pattern not found!\n"); 2492 return -ENOTSUPP; 2493 } 2494 2495 ctx = best_ctx; 2496 nand_op_parser_trace(&ctx); 2497 2498 if (!check_only) { 2499 pattern = &parser->patterns[best_pattern]; 2500 ret = pattern->exec(chip, &ctx.subop); 2501 if (ret) 2502 return ret; 2503 } 2504 2505 /* 2506 * Update the context structure by pointing to the start of the 2507 * next subop. 2508 */ 2509 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs; 2510 if (ctx.subop.last_instr_end_off) 2511 ctx.subop.instrs -= 1; 2512 2513 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off; 2514 } 2515 2516 return 0; 2517 } 2518 EXPORT_SYMBOL_GPL(nand_op_parser_exec_op); 2519 2520 static bool nand_instr_is_data(const struct nand_op_instr *instr) 2521 { 2522 return instr && (instr->type == NAND_OP_DATA_IN_INSTR || 2523 instr->type == NAND_OP_DATA_OUT_INSTR); 2524 } 2525 2526 static bool nand_subop_instr_is_valid(const struct nand_subop *subop, 2527 unsigned int instr_idx) 2528 { 2529 return subop && instr_idx < subop->ninstrs; 2530 } 2531 2532 static unsigned int nand_subop_get_start_off(const struct nand_subop *subop, 2533 unsigned int instr_idx) 2534 { 2535 if (instr_idx) 2536 return 0; 2537 2538 return subop->first_instr_start_off; 2539 } 2540 2541 /** 2542 * nand_subop_get_addr_start_off - Get the start offset in an address array 2543 * @subop: The entire sub-operation 2544 * @instr_idx: Index of the instruction inside the sub-operation 2545 * 2546 * During driver development, one could be tempted to directly use the 2547 * ->addr.addrs field of address instructions. This is wrong as address 2548 * instructions might be split. 2549 * 2550 * Given an address instruction, returns the offset of the first cycle to issue. 2551 */ 2552 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 2553 unsigned int instr_idx) 2554 { 2555 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2556 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2557 return 0; 2558 2559 return nand_subop_get_start_off(subop, instr_idx); 2560 } 2561 EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off); 2562 2563 /** 2564 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert 2565 * @subop: The entire sub-operation 2566 * @instr_idx: Index of the instruction inside the sub-operation 2567 * 2568 * During driver development, one could be tempted to directly use the 2569 * ->addr->naddrs field of a data instruction. This is wrong as instructions 2570 * might be split. 2571 * 2572 * Given an address instruction, returns the number of address cycle to issue. 2573 */ 2574 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 2575 unsigned int instr_idx) 2576 { 2577 int start_off, end_off; 2578 2579 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2580 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2581 return 0; 2582 2583 start_off = nand_subop_get_addr_start_off(subop, instr_idx); 2584 2585 if (instr_idx == subop->ninstrs - 1 && 2586 subop->last_instr_end_off) 2587 end_off = subop->last_instr_end_off; 2588 else 2589 end_off = subop->instrs[instr_idx].ctx.addr.naddrs; 2590 2591 return end_off - start_off; 2592 } 2593 EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc); 2594 2595 /** 2596 * nand_subop_get_data_start_off - Get the start offset in a data array 2597 * @subop: The entire sub-operation 2598 * @instr_idx: Index of the instruction inside the sub-operation 2599 * 2600 * During driver development, one could be tempted to directly use the 2601 * ->data->buf.{in,out} field of data instructions. This is wrong as data 2602 * instructions might be split. 2603 * 2604 * Given a data instruction, returns the offset to start from. 2605 */ 2606 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 2607 unsigned int instr_idx) 2608 { 2609 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2610 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2611 return 0; 2612 2613 return nand_subop_get_start_off(subop, instr_idx); 2614 } 2615 EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off); 2616 2617 /** 2618 * nand_subop_get_data_len - Get the number of bytes to retrieve 2619 * @subop: The entire sub-operation 2620 * @instr_idx: Index of the instruction inside the sub-operation 2621 * 2622 * During driver development, one could be tempted to directly use the 2623 * ->data->len field of a data instruction. This is wrong as data instructions 2624 * might be split. 2625 * 2626 * Returns the length of the chunk of data to send/receive. 2627 */ 2628 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 2629 unsigned int instr_idx) 2630 { 2631 int start_off = 0, end_off; 2632 2633 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2634 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2635 return 0; 2636 2637 start_off = nand_subop_get_data_start_off(subop, instr_idx); 2638 2639 if (instr_idx == subop->ninstrs - 1 && 2640 subop->last_instr_end_off) 2641 end_off = subop->last_instr_end_off; 2642 else 2643 end_off = subop->instrs[instr_idx].ctx.data.len; 2644 2645 return end_off - start_off; 2646 } 2647 EXPORT_SYMBOL_GPL(nand_subop_get_data_len); 2648 2649 /** 2650 * nand_reset - Reset and initialize a NAND device 2651 * @chip: The NAND chip 2652 * @chipnr: Internal die id 2653 * 2654 * Save the timings data structure, then apply SDR timings mode 0 (see 2655 * nand_reset_interface for details), do the reset operation, and apply 2656 * back the previous timings. 2657 * 2658 * Returns 0 on success, a negative error code otherwise. 2659 */ 2660 int nand_reset(struct nand_chip *chip, int chipnr) 2661 { 2662 int ret; 2663 2664 ret = nand_reset_interface(chip, chipnr); 2665 if (ret) 2666 return ret; 2667 2668 /* 2669 * The CS line has to be released before we can apply the new NAND 2670 * interface settings, hence this weird nand_select_target() 2671 * nand_deselect_target() dance. 2672 */ 2673 nand_select_target(chip, chipnr); 2674 ret = nand_reset_op(chip); 2675 nand_deselect_target(chip); 2676 if (ret) 2677 return ret; 2678 2679 ret = nand_setup_interface(chip, chipnr); 2680 if (ret) 2681 return ret; 2682 2683 return 0; 2684 } 2685 EXPORT_SYMBOL_GPL(nand_reset); 2686 2687 /** 2688 * nand_get_features - wrapper to perform a GET_FEATURE 2689 * @chip: NAND chip info structure 2690 * @addr: feature address 2691 * @subfeature_param: the subfeature parameters, a four bytes array 2692 * 2693 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2694 * operation cannot be handled. 2695 */ 2696 int nand_get_features(struct nand_chip *chip, int addr, 2697 u8 *subfeature_param) 2698 { 2699 if (!nand_supports_get_features(chip, addr)) 2700 return -ENOTSUPP; 2701 2702 if (chip->legacy.get_features) 2703 return chip->legacy.get_features(chip, addr, subfeature_param); 2704 2705 return nand_get_features_op(chip, addr, subfeature_param); 2706 } 2707 2708 /** 2709 * nand_set_features - wrapper to perform a SET_FEATURE 2710 * @chip: NAND chip info structure 2711 * @addr: feature address 2712 * @subfeature_param: the subfeature parameters, a four bytes array 2713 * 2714 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2715 * operation cannot be handled. 2716 */ 2717 int nand_set_features(struct nand_chip *chip, int addr, 2718 u8 *subfeature_param) 2719 { 2720 if (!nand_supports_set_features(chip, addr)) 2721 return -ENOTSUPP; 2722 2723 if (chip->legacy.set_features) 2724 return chip->legacy.set_features(chip, addr, subfeature_param); 2725 2726 return nand_set_features_op(chip, addr, subfeature_param); 2727 } 2728 2729 /** 2730 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data 2731 * @buf: buffer to test 2732 * @len: buffer length 2733 * @bitflips_threshold: maximum number of bitflips 2734 * 2735 * Check if a buffer contains only 0xff, which means the underlying region 2736 * has been erased and is ready to be programmed. 2737 * The bitflips_threshold specify the maximum number of bitflips before 2738 * considering the region is not erased. 2739 * Note: The logic of this function has been extracted from the memweight 2740 * implementation, except that nand_check_erased_buf function exit before 2741 * testing the whole buffer if the number of bitflips exceed the 2742 * bitflips_threshold value. 2743 * 2744 * Returns a positive number of bitflips less than or equal to 2745 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 2746 * threshold. 2747 */ 2748 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) 2749 { 2750 const unsigned char *bitmap = buf; 2751 int bitflips = 0; 2752 int weight; 2753 2754 for (; len && ((uintptr_t)bitmap) % sizeof(long); 2755 len--, bitmap++) { 2756 weight = hweight8(*bitmap); 2757 bitflips += BITS_PER_BYTE - weight; 2758 if (unlikely(bitflips > bitflips_threshold)) 2759 return -EBADMSG; 2760 } 2761 2762 for (; len >= sizeof(long); 2763 len -= sizeof(long), bitmap += sizeof(long)) { 2764 unsigned long d = *((unsigned long *)bitmap); 2765 if (d == ~0UL) 2766 continue; 2767 weight = hweight_long(d); 2768 bitflips += BITS_PER_LONG - weight; 2769 if (unlikely(bitflips > bitflips_threshold)) 2770 return -EBADMSG; 2771 } 2772 2773 for (; len > 0; len--, bitmap++) { 2774 weight = hweight8(*bitmap); 2775 bitflips += BITS_PER_BYTE - weight; 2776 if (unlikely(bitflips > bitflips_threshold)) 2777 return -EBADMSG; 2778 } 2779 2780 return bitflips; 2781 } 2782 2783 /** 2784 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only 2785 * 0xff data 2786 * @data: data buffer to test 2787 * @datalen: data length 2788 * @ecc: ECC buffer 2789 * @ecclen: ECC length 2790 * @extraoob: extra OOB buffer 2791 * @extraooblen: extra OOB length 2792 * @bitflips_threshold: maximum number of bitflips 2793 * 2794 * Check if a data buffer and its associated ECC and OOB data contains only 2795 * 0xff pattern, which means the underlying region has been erased and is 2796 * ready to be programmed. 2797 * The bitflips_threshold specify the maximum number of bitflips before 2798 * considering the region as not erased. 2799 * 2800 * Note: 2801 * 1/ ECC algorithms are working on pre-defined block sizes which are usually 2802 * different from the NAND page size. When fixing bitflips, ECC engines will 2803 * report the number of errors per chunk, and the NAND core infrastructure 2804 * expect you to return the maximum number of bitflips for the whole page. 2805 * This is why you should always use this function on a single chunk and 2806 * not on the whole page. After checking each chunk you should update your 2807 * max_bitflips value accordingly. 2808 * 2/ When checking for bitflips in erased pages you should not only check 2809 * the payload data but also their associated ECC data, because a user might 2810 * have programmed almost all bits to 1 but a few. In this case, we 2811 * shouldn't consider the chunk as erased, and checking ECC bytes prevent 2812 * this case. 2813 * 3/ The extraoob argument is optional, and should be used if some of your OOB 2814 * data are protected by the ECC engine. 2815 * It could also be used if you support subpages and want to attach some 2816 * extra OOB data to an ECC chunk. 2817 * 2818 * Returns a positive number of bitflips less than or equal to 2819 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 2820 * threshold. In case of success, the passed buffers are filled with 0xff. 2821 */ 2822 int nand_check_erased_ecc_chunk(void *data, int datalen, 2823 void *ecc, int ecclen, 2824 void *extraoob, int extraooblen, 2825 int bitflips_threshold) 2826 { 2827 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; 2828 2829 data_bitflips = nand_check_erased_buf(data, datalen, 2830 bitflips_threshold); 2831 if (data_bitflips < 0) 2832 return data_bitflips; 2833 2834 bitflips_threshold -= data_bitflips; 2835 2836 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); 2837 if (ecc_bitflips < 0) 2838 return ecc_bitflips; 2839 2840 bitflips_threshold -= ecc_bitflips; 2841 2842 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, 2843 bitflips_threshold); 2844 if (extraoob_bitflips < 0) 2845 return extraoob_bitflips; 2846 2847 if (data_bitflips) 2848 memset(data, 0xff, datalen); 2849 2850 if (ecc_bitflips) 2851 memset(ecc, 0xff, ecclen); 2852 2853 if (extraoob_bitflips) 2854 memset(extraoob, 0xff, extraooblen); 2855 2856 return data_bitflips + ecc_bitflips + extraoob_bitflips; 2857 } 2858 EXPORT_SYMBOL(nand_check_erased_ecc_chunk); 2859 2860 /** 2861 * nand_read_page_raw_notsupp - dummy read raw page function 2862 * @chip: nand chip info structure 2863 * @buf: buffer to store read data 2864 * @oob_required: caller requires OOB data read to chip->oob_poi 2865 * @page: page number to read 2866 * 2867 * Returns -ENOTSUPP unconditionally. 2868 */ 2869 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf, 2870 int oob_required, int page) 2871 { 2872 return -ENOTSUPP; 2873 } 2874 2875 /** 2876 * nand_read_page_raw - [INTERN] read raw page data without ecc 2877 * @chip: nand chip info structure 2878 * @buf: buffer to store read data 2879 * @oob_required: caller requires OOB data read to chip->oob_poi 2880 * @page: page number to read 2881 * 2882 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2883 */ 2884 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 2885 int page) 2886 { 2887 struct mtd_info *mtd = nand_to_mtd(chip); 2888 int ret; 2889 2890 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); 2891 if (ret) 2892 return ret; 2893 2894 if (oob_required) { 2895 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, 2896 false, false); 2897 if (ret) 2898 return ret; 2899 } 2900 2901 return 0; 2902 } 2903 EXPORT_SYMBOL(nand_read_page_raw); 2904 2905 /** 2906 * nand_monolithic_read_page_raw - Monolithic page read in raw mode 2907 * @chip: NAND chip info structure 2908 * @buf: buffer to store read data 2909 * @oob_required: caller requires OOB data read to chip->oob_poi 2910 * @page: page number to read 2911 * 2912 * This is a raw page read, ie. without any error detection/correction. 2913 * Monolithic means we are requesting all the relevant data (main plus 2914 * eventually OOB) to be loaded in the NAND cache and sent over the 2915 * bus (from the NAND chip to the NAND controller) in a single 2916 * operation. This is an alternative to nand_read_page_raw(), which 2917 * first reads the main data, and if the OOB data is requested too, 2918 * then reads more data on the bus. 2919 */ 2920 int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf, 2921 int oob_required, int page) 2922 { 2923 struct mtd_info *mtd = nand_to_mtd(chip); 2924 unsigned int size = mtd->writesize; 2925 u8 *read_buf = buf; 2926 int ret; 2927 2928 if (oob_required) { 2929 size += mtd->oobsize; 2930 2931 if (buf != chip->data_buf) 2932 read_buf = nand_get_data_buf(chip); 2933 } 2934 2935 ret = nand_read_page_op(chip, page, 0, read_buf, size); 2936 if (ret) 2937 return ret; 2938 2939 if (buf != chip->data_buf) 2940 memcpy(buf, read_buf, mtd->writesize); 2941 2942 return 0; 2943 } 2944 EXPORT_SYMBOL(nand_monolithic_read_page_raw); 2945 2946 /** 2947 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 2948 * @chip: nand chip info structure 2949 * @buf: buffer to store read data 2950 * @oob_required: caller requires OOB data read to chip->oob_poi 2951 * @page: page number to read 2952 * 2953 * We need a special oob layout and handling even when OOB isn't used. 2954 */ 2955 static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf, 2956 int oob_required, int page) 2957 { 2958 struct mtd_info *mtd = nand_to_mtd(chip); 2959 int eccsize = chip->ecc.size; 2960 int eccbytes = chip->ecc.bytes; 2961 uint8_t *oob = chip->oob_poi; 2962 int steps, size, ret; 2963 2964 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2965 if (ret) 2966 return ret; 2967 2968 for (steps = chip->ecc.steps; steps > 0; steps--) { 2969 ret = nand_read_data_op(chip, buf, eccsize, false, false); 2970 if (ret) 2971 return ret; 2972 2973 buf += eccsize; 2974 2975 if (chip->ecc.prepad) { 2976 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 2977 false, false); 2978 if (ret) 2979 return ret; 2980 2981 oob += chip->ecc.prepad; 2982 } 2983 2984 ret = nand_read_data_op(chip, oob, eccbytes, false, false); 2985 if (ret) 2986 return ret; 2987 2988 oob += eccbytes; 2989 2990 if (chip->ecc.postpad) { 2991 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 2992 false, false); 2993 if (ret) 2994 return ret; 2995 2996 oob += chip->ecc.postpad; 2997 } 2998 } 2999 3000 size = mtd->oobsize - (oob - chip->oob_poi); 3001 if (size) { 3002 ret = nand_read_data_op(chip, oob, size, false, false); 3003 if (ret) 3004 return ret; 3005 } 3006 3007 return 0; 3008 } 3009 3010 /** 3011 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 3012 * @chip: nand chip info structure 3013 * @buf: buffer to store read data 3014 * @oob_required: caller requires OOB data read to chip->oob_poi 3015 * @page: page number to read 3016 */ 3017 static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf, 3018 int oob_required, int page) 3019 { 3020 struct mtd_info *mtd = nand_to_mtd(chip); 3021 int i, eccsize = chip->ecc.size, ret; 3022 int eccbytes = chip->ecc.bytes; 3023 int eccsteps = chip->ecc.steps; 3024 uint8_t *p = buf; 3025 uint8_t *ecc_calc = chip->ecc.calc_buf; 3026 uint8_t *ecc_code = chip->ecc.code_buf; 3027 unsigned int max_bitflips = 0; 3028 3029 chip->ecc.read_page_raw(chip, buf, 1, page); 3030 3031 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 3032 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3033 3034 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3035 chip->ecc.total); 3036 if (ret) 3037 return ret; 3038 3039 eccsteps = chip->ecc.steps; 3040 p = buf; 3041 3042 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3043 int stat; 3044 3045 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 3046 if (stat < 0) { 3047 mtd->ecc_stats.failed++; 3048 } else { 3049 mtd->ecc_stats.corrected += stat; 3050 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3051 } 3052 } 3053 return max_bitflips; 3054 } 3055 3056 /** 3057 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 3058 * @chip: nand chip info structure 3059 * @data_offs: offset of requested data within the page 3060 * @readlen: data length 3061 * @bufpoi: buffer to store read data 3062 * @page: page number to read 3063 */ 3064 static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs, 3065 uint32_t readlen, uint8_t *bufpoi, int page) 3066 { 3067 struct mtd_info *mtd = nand_to_mtd(chip); 3068 int start_step, end_step, num_steps, ret; 3069 uint8_t *p; 3070 int data_col_addr, i, gaps = 0; 3071 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 3072 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 3073 int index, section = 0; 3074 unsigned int max_bitflips = 0; 3075 struct mtd_oob_region oobregion = { }; 3076 3077 /* Column address within the page aligned to ECC size (256bytes) */ 3078 start_step = data_offs / chip->ecc.size; 3079 end_step = (data_offs + readlen - 1) / chip->ecc.size; 3080 num_steps = end_step - start_step + 1; 3081 index = start_step * chip->ecc.bytes; 3082 3083 /* Data size aligned to ECC ecc.size */ 3084 datafrag_len = num_steps * chip->ecc.size; 3085 eccfrag_len = num_steps * chip->ecc.bytes; 3086 3087 data_col_addr = start_step * chip->ecc.size; 3088 /* If we read not a page aligned data */ 3089 p = bufpoi + data_col_addr; 3090 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len); 3091 if (ret) 3092 return ret; 3093 3094 /* Calculate ECC */ 3095 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 3096 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); 3097 3098 /* 3099 * The performance is faster if we position offsets according to 3100 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 3101 */ 3102 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); 3103 if (ret) 3104 return ret; 3105 3106 if (oobregion.length < eccfrag_len) 3107 gaps = 1; 3108 3109 if (gaps) { 3110 ret = nand_change_read_column_op(chip, mtd->writesize, 3111 chip->oob_poi, mtd->oobsize, 3112 false); 3113 if (ret) 3114 return ret; 3115 } else { 3116 /* 3117 * Send the command to read the particular ECC bytes take care 3118 * about buswidth alignment in read_buf. 3119 */ 3120 aligned_pos = oobregion.offset & ~(busw - 1); 3121 aligned_len = eccfrag_len; 3122 if (oobregion.offset & (busw - 1)) 3123 aligned_len++; 3124 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & 3125 (busw - 1)) 3126 aligned_len++; 3127 3128 ret = nand_change_read_column_op(chip, 3129 mtd->writesize + aligned_pos, 3130 &chip->oob_poi[aligned_pos], 3131 aligned_len, false); 3132 if (ret) 3133 return ret; 3134 } 3135 3136 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, 3137 chip->oob_poi, index, eccfrag_len); 3138 if (ret) 3139 return ret; 3140 3141 p = bufpoi + data_col_addr; 3142 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 3143 int stat; 3144 3145 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], 3146 &chip->ecc.calc_buf[i]); 3147 if (stat == -EBADMSG && 3148 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3149 /* check for empty pages with bitflips */ 3150 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 3151 &chip->ecc.code_buf[i], 3152 chip->ecc.bytes, 3153 NULL, 0, 3154 chip->ecc.strength); 3155 } 3156 3157 if (stat < 0) { 3158 mtd->ecc_stats.failed++; 3159 } else { 3160 mtd->ecc_stats.corrected += stat; 3161 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3162 } 3163 } 3164 return max_bitflips; 3165 } 3166 3167 /** 3168 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 3169 * @chip: nand chip info structure 3170 * @buf: buffer to store read data 3171 * @oob_required: caller requires OOB data read to chip->oob_poi 3172 * @page: page number to read 3173 * 3174 * Not for syndrome calculating ECC controllers which need a special oob layout. 3175 */ 3176 static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf, 3177 int oob_required, int page) 3178 { 3179 struct mtd_info *mtd = nand_to_mtd(chip); 3180 int i, eccsize = chip->ecc.size, ret; 3181 int eccbytes = chip->ecc.bytes; 3182 int eccsteps = chip->ecc.steps; 3183 uint8_t *p = buf; 3184 uint8_t *ecc_calc = chip->ecc.calc_buf; 3185 uint8_t *ecc_code = chip->ecc.code_buf; 3186 unsigned int max_bitflips = 0; 3187 3188 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3189 if (ret) 3190 return ret; 3191 3192 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3193 chip->ecc.hwctl(chip, NAND_ECC_READ); 3194 3195 ret = nand_read_data_op(chip, p, eccsize, false, false); 3196 if (ret) 3197 return ret; 3198 3199 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3200 } 3201 3202 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, 3203 false); 3204 if (ret) 3205 return ret; 3206 3207 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3208 chip->ecc.total); 3209 if (ret) 3210 return ret; 3211 3212 eccsteps = chip->ecc.steps; 3213 p = buf; 3214 3215 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3216 int stat; 3217 3218 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 3219 if (stat == -EBADMSG && 3220 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3221 /* check for empty pages with bitflips */ 3222 stat = nand_check_erased_ecc_chunk(p, eccsize, 3223 &ecc_code[i], eccbytes, 3224 NULL, 0, 3225 chip->ecc.strength); 3226 } 3227 3228 if (stat < 0) { 3229 mtd->ecc_stats.failed++; 3230 } else { 3231 mtd->ecc_stats.corrected += stat; 3232 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3233 } 3234 } 3235 return max_bitflips; 3236 } 3237 3238 /** 3239 * nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC 3240 * data read from OOB area 3241 * @chip: nand chip info structure 3242 * @buf: buffer to store read data 3243 * @oob_required: caller requires OOB data read to chip->oob_poi 3244 * @page: page number to read 3245 * 3246 * Hardware ECC for large page chips, which requires the ECC data to be 3247 * extracted from the OOB before the actual data is read. 3248 */ 3249 int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf, 3250 int oob_required, int page) 3251 { 3252 struct mtd_info *mtd = nand_to_mtd(chip); 3253 int i, eccsize = chip->ecc.size, ret; 3254 int eccbytes = chip->ecc.bytes; 3255 int eccsteps = chip->ecc.steps; 3256 uint8_t *p = buf; 3257 uint8_t *ecc_code = chip->ecc.code_buf; 3258 unsigned int max_bitflips = 0; 3259 3260 /* Read the OOB area first */ 3261 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3262 if (ret) 3263 return ret; 3264 3265 /* Move read cursor to start of page */ 3266 ret = nand_change_read_column_op(chip, 0, NULL, 0, false); 3267 if (ret) 3268 return ret; 3269 3270 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3271 chip->ecc.total); 3272 if (ret) 3273 return ret; 3274 3275 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3276 int stat; 3277 3278 chip->ecc.hwctl(chip, NAND_ECC_READ); 3279 3280 ret = nand_read_data_op(chip, p, eccsize, false, false); 3281 if (ret) 3282 return ret; 3283 3284 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL); 3285 if (stat == -EBADMSG && 3286 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3287 /* check for empty pages with bitflips */ 3288 stat = nand_check_erased_ecc_chunk(p, eccsize, 3289 &ecc_code[i], 3290 eccbytes, NULL, 0, 3291 chip->ecc.strength); 3292 } 3293 3294 if (stat < 0) { 3295 mtd->ecc_stats.failed++; 3296 } else { 3297 mtd->ecc_stats.corrected += stat; 3298 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3299 } 3300 } 3301 return max_bitflips; 3302 } 3303 EXPORT_SYMBOL_GPL(nand_read_page_hwecc_oob_first); 3304 3305 /** 3306 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 3307 * @chip: nand chip info structure 3308 * @buf: buffer to store read data 3309 * @oob_required: caller requires OOB data read to chip->oob_poi 3310 * @page: page number to read 3311 * 3312 * The hw generator calculates the error syndrome automatically. Therefore we 3313 * need a special oob layout and handling. 3314 */ 3315 static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, 3316 int oob_required, int page) 3317 { 3318 struct mtd_info *mtd = nand_to_mtd(chip); 3319 int ret, i, eccsize = chip->ecc.size; 3320 int eccbytes = chip->ecc.bytes; 3321 int eccsteps = chip->ecc.steps; 3322 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 3323 uint8_t *p = buf; 3324 uint8_t *oob = chip->oob_poi; 3325 unsigned int max_bitflips = 0; 3326 3327 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3328 if (ret) 3329 return ret; 3330 3331 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3332 int stat; 3333 3334 chip->ecc.hwctl(chip, NAND_ECC_READ); 3335 3336 ret = nand_read_data_op(chip, p, eccsize, false, false); 3337 if (ret) 3338 return ret; 3339 3340 if (chip->ecc.prepad) { 3341 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 3342 false, false); 3343 if (ret) 3344 return ret; 3345 3346 oob += chip->ecc.prepad; 3347 } 3348 3349 chip->ecc.hwctl(chip, NAND_ECC_READSYN); 3350 3351 ret = nand_read_data_op(chip, oob, eccbytes, false, false); 3352 if (ret) 3353 return ret; 3354 3355 stat = chip->ecc.correct(chip, p, oob, NULL); 3356 3357 oob += eccbytes; 3358 3359 if (chip->ecc.postpad) { 3360 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 3361 false, false); 3362 if (ret) 3363 return ret; 3364 3365 oob += chip->ecc.postpad; 3366 } 3367 3368 if (stat == -EBADMSG && 3369 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3370 /* check for empty pages with bitflips */ 3371 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 3372 oob - eccpadbytes, 3373 eccpadbytes, 3374 NULL, 0, 3375 chip->ecc.strength); 3376 } 3377 3378 if (stat < 0) { 3379 mtd->ecc_stats.failed++; 3380 } else { 3381 mtd->ecc_stats.corrected += stat; 3382 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3383 } 3384 } 3385 3386 /* Calculate remaining oob bytes */ 3387 i = mtd->oobsize - (oob - chip->oob_poi); 3388 if (i) { 3389 ret = nand_read_data_op(chip, oob, i, false, false); 3390 if (ret) 3391 return ret; 3392 } 3393 3394 return max_bitflips; 3395 } 3396 3397 /** 3398 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 3399 * @chip: NAND chip object 3400 * @oob: oob destination address 3401 * @ops: oob ops structure 3402 * @len: size of oob to transfer 3403 */ 3404 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 3405 struct mtd_oob_ops *ops, size_t len) 3406 { 3407 struct mtd_info *mtd = nand_to_mtd(chip); 3408 int ret; 3409 3410 switch (ops->mode) { 3411 3412 case MTD_OPS_PLACE_OOB: 3413 case MTD_OPS_RAW: 3414 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 3415 return oob + len; 3416 3417 case MTD_OPS_AUTO_OOB: 3418 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, 3419 ops->ooboffs, len); 3420 BUG_ON(ret); 3421 return oob + len; 3422 3423 default: 3424 BUG(); 3425 } 3426 return NULL; 3427 } 3428 3429 static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page, 3430 u32 readlen, int col) 3431 { 3432 struct mtd_info *mtd = nand_to_mtd(chip); 3433 3434 if (!chip->controller->supported_op.cont_read) 3435 return; 3436 3437 if ((col && col + readlen < (3 * mtd->writesize)) || 3438 (!col && readlen < (2 * mtd->writesize))) { 3439 chip->cont_read.ongoing = false; 3440 return; 3441 } 3442 3443 chip->cont_read.ongoing = true; 3444 chip->cont_read.first_page = page; 3445 if (col) 3446 chip->cont_read.first_page++; 3447 chip->cont_read.last_page = page + ((readlen >> chip->page_shift) & chip->pagemask); 3448 } 3449 3450 /** 3451 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 3452 * @chip: NAND chip object 3453 * @retry_mode: the retry mode to use 3454 * 3455 * Some vendors supply a special command to shift the Vt threshold, to be used 3456 * when there are too many bitflips in a page (i.e., ECC error). After setting 3457 * a new threshold, the host should retry reading the page. 3458 */ 3459 static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode) 3460 { 3461 pr_debug("setting READ RETRY mode %d\n", retry_mode); 3462 3463 if (retry_mode >= chip->read_retries) 3464 return -EINVAL; 3465 3466 if (!chip->ops.setup_read_retry) 3467 return -EOPNOTSUPP; 3468 3469 return chip->ops.setup_read_retry(chip, retry_mode); 3470 } 3471 3472 static void nand_wait_readrdy(struct nand_chip *chip) 3473 { 3474 const struct nand_interface_config *conf; 3475 3476 if (!(chip->options & NAND_NEED_READRDY)) 3477 return; 3478 3479 conf = nand_get_interface_config(chip); 3480 WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0)); 3481 } 3482 3483 /** 3484 * nand_do_read_ops - [INTERN] Read data with ECC 3485 * @chip: NAND chip object 3486 * @from: offset to read from 3487 * @ops: oob ops structure 3488 * 3489 * Internal function. Called with chip held. 3490 */ 3491 static int nand_do_read_ops(struct nand_chip *chip, loff_t from, 3492 struct mtd_oob_ops *ops) 3493 { 3494 int chipnr, page, realpage, col, bytes, aligned, oob_required; 3495 struct mtd_info *mtd = nand_to_mtd(chip); 3496 int ret = 0; 3497 uint32_t readlen = ops->len; 3498 uint32_t oobreadlen = ops->ooblen; 3499 uint32_t max_oobsize = mtd_oobavail(mtd, ops); 3500 3501 uint8_t *bufpoi, *oob, *buf; 3502 int use_bounce_buf; 3503 unsigned int max_bitflips = 0; 3504 int retry_mode = 0; 3505 bool ecc_fail = false; 3506 3507 /* Check if the region is secured */ 3508 if (nand_region_is_secured(chip, from, readlen)) 3509 return -EIO; 3510 3511 chipnr = (int)(from >> chip->chip_shift); 3512 nand_select_target(chip, chipnr); 3513 3514 realpage = (int)(from >> chip->page_shift); 3515 page = realpage & chip->pagemask; 3516 3517 col = (int)(from & (mtd->writesize - 1)); 3518 3519 buf = ops->datbuf; 3520 oob = ops->oobbuf; 3521 oob_required = oob ? 1 : 0; 3522 3523 rawnand_enable_cont_reads(chip, page, readlen, col); 3524 3525 while (1) { 3526 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats; 3527 3528 bytes = min(mtd->writesize - col, readlen); 3529 aligned = (bytes == mtd->writesize); 3530 3531 if (!aligned) 3532 use_bounce_buf = 1; 3533 else if (chip->options & NAND_USES_DMA) 3534 use_bounce_buf = !virt_addr_valid(buf) || 3535 !IS_ALIGNED((unsigned long)buf, 3536 chip->buf_align); 3537 else 3538 use_bounce_buf = 0; 3539 3540 /* Is the current page in the buffer? */ 3541 if (realpage != chip->pagecache.page || oob) { 3542 bufpoi = use_bounce_buf ? chip->data_buf : buf; 3543 3544 if (use_bounce_buf && aligned) 3545 pr_debug("%s: using read bounce buffer for buf@%p\n", 3546 __func__, buf); 3547 3548 read_retry: 3549 /* 3550 * Now read the page into the buffer. Absent an error, 3551 * the read methods return max bitflips per ecc step. 3552 */ 3553 if (unlikely(ops->mode == MTD_OPS_RAW)) 3554 ret = chip->ecc.read_page_raw(chip, bufpoi, 3555 oob_required, 3556 page); 3557 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 3558 !oob) 3559 ret = chip->ecc.read_subpage(chip, col, bytes, 3560 bufpoi, page); 3561 else 3562 ret = chip->ecc.read_page(chip, bufpoi, 3563 oob_required, page); 3564 if (ret < 0) { 3565 if (use_bounce_buf) 3566 /* Invalidate page cache */ 3567 chip->pagecache.page = -1; 3568 break; 3569 } 3570 3571 /* 3572 * Copy back the data in the initial buffer when reading 3573 * partial pages or when a bounce buffer is required. 3574 */ 3575 if (use_bounce_buf) { 3576 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 3577 !(mtd->ecc_stats.failed - ecc_stats.failed) && 3578 (ops->mode != MTD_OPS_RAW)) { 3579 chip->pagecache.page = realpage; 3580 chip->pagecache.bitflips = ret; 3581 } else { 3582 /* Invalidate page cache */ 3583 chip->pagecache.page = -1; 3584 } 3585 memcpy(buf, bufpoi + col, bytes); 3586 } 3587 3588 if (unlikely(oob)) { 3589 int toread = min(oobreadlen, max_oobsize); 3590 3591 if (toread) { 3592 oob = nand_transfer_oob(chip, oob, ops, 3593 toread); 3594 oobreadlen -= toread; 3595 } 3596 } 3597 3598 nand_wait_readrdy(chip); 3599 3600 if (mtd->ecc_stats.failed - ecc_stats.failed) { 3601 if (retry_mode + 1 < chip->read_retries) { 3602 retry_mode++; 3603 ret = nand_setup_read_retry(chip, 3604 retry_mode); 3605 if (ret < 0) 3606 break; 3607 3608 /* Reset ecc_stats; retry */ 3609 mtd->ecc_stats = ecc_stats; 3610 goto read_retry; 3611 } else { 3612 /* No more retry modes; real failure */ 3613 ecc_fail = true; 3614 } 3615 } 3616 3617 buf += bytes; 3618 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3619 } else { 3620 memcpy(buf, chip->data_buf + col, bytes); 3621 buf += bytes; 3622 max_bitflips = max_t(unsigned int, max_bitflips, 3623 chip->pagecache.bitflips); 3624 } 3625 3626 readlen -= bytes; 3627 3628 /* Reset to retry mode 0 */ 3629 if (retry_mode) { 3630 ret = nand_setup_read_retry(chip, 0); 3631 if (ret < 0) 3632 break; 3633 retry_mode = 0; 3634 } 3635 3636 if (!readlen) 3637 break; 3638 3639 /* For subsequent reads align to page boundary */ 3640 col = 0; 3641 /* Increment page address */ 3642 realpage++; 3643 3644 page = realpage & chip->pagemask; 3645 /* Check, if we cross a chip boundary */ 3646 if (!page) { 3647 chipnr++; 3648 nand_deselect_target(chip); 3649 nand_select_target(chip, chipnr); 3650 } 3651 } 3652 nand_deselect_target(chip); 3653 3654 ops->retlen = ops->len - (size_t) readlen; 3655 if (oob) 3656 ops->oobretlen = ops->ooblen - oobreadlen; 3657 3658 if (ret < 0) 3659 return ret; 3660 3661 if (ecc_fail) 3662 return -EBADMSG; 3663 3664 return max_bitflips; 3665 } 3666 3667 /** 3668 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 3669 * @chip: nand chip info structure 3670 * @page: page number to read 3671 */ 3672 int nand_read_oob_std(struct nand_chip *chip, int page) 3673 { 3674 struct mtd_info *mtd = nand_to_mtd(chip); 3675 3676 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3677 } 3678 EXPORT_SYMBOL(nand_read_oob_std); 3679 3680 /** 3681 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 3682 * with syndromes 3683 * @chip: nand chip info structure 3684 * @page: page number to read 3685 */ 3686 static int nand_read_oob_syndrome(struct nand_chip *chip, int page) 3687 { 3688 struct mtd_info *mtd = nand_to_mtd(chip); 3689 int length = mtd->oobsize; 3690 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3691 int eccsize = chip->ecc.size; 3692 uint8_t *bufpoi = chip->oob_poi; 3693 int i, toread, sndrnd = 0, pos, ret; 3694 3695 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); 3696 if (ret) 3697 return ret; 3698 3699 for (i = 0; i < chip->ecc.steps; i++) { 3700 if (sndrnd) { 3701 int ret; 3702 3703 pos = eccsize + i * (eccsize + chunk); 3704 if (mtd->writesize > 512) 3705 ret = nand_change_read_column_op(chip, pos, 3706 NULL, 0, 3707 false); 3708 else 3709 ret = nand_read_page_op(chip, page, pos, NULL, 3710 0); 3711 3712 if (ret) 3713 return ret; 3714 } else 3715 sndrnd = 1; 3716 toread = min_t(int, length, chunk); 3717 3718 ret = nand_read_data_op(chip, bufpoi, toread, false, false); 3719 if (ret) 3720 return ret; 3721 3722 bufpoi += toread; 3723 length -= toread; 3724 } 3725 if (length > 0) { 3726 ret = nand_read_data_op(chip, bufpoi, length, false, false); 3727 if (ret) 3728 return ret; 3729 } 3730 3731 return 0; 3732 } 3733 3734 /** 3735 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 3736 * @chip: nand chip info structure 3737 * @page: page number to write 3738 */ 3739 int nand_write_oob_std(struct nand_chip *chip, int page) 3740 { 3741 struct mtd_info *mtd = nand_to_mtd(chip); 3742 3743 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 3744 mtd->oobsize); 3745 } 3746 EXPORT_SYMBOL(nand_write_oob_std); 3747 3748 /** 3749 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 3750 * with syndrome - only for large page flash 3751 * @chip: nand chip info structure 3752 * @page: page number to write 3753 */ 3754 static int nand_write_oob_syndrome(struct nand_chip *chip, int page) 3755 { 3756 struct mtd_info *mtd = nand_to_mtd(chip); 3757 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3758 int eccsize = chip->ecc.size, length = mtd->oobsize; 3759 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; 3760 const uint8_t *bufpoi = chip->oob_poi; 3761 3762 /* 3763 * data-ecc-data-ecc ... ecc-oob 3764 * or 3765 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 3766 */ 3767 if (!chip->ecc.prepad && !chip->ecc.postpad) { 3768 pos = steps * (eccsize + chunk); 3769 steps = 0; 3770 } else 3771 pos = eccsize; 3772 3773 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0); 3774 if (ret) 3775 return ret; 3776 3777 for (i = 0; i < steps; i++) { 3778 if (sndcmd) { 3779 if (mtd->writesize <= 512) { 3780 uint32_t fill = 0xFFFFFFFF; 3781 3782 len = eccsize; 3783 while (len > 0) { 3784 int num = min_t(int, len, 4); 3785 3786 ret = nand_write_data_op(chip, &fill, 3787 num, false); 3788 if (ret) 3789 return ret; 3790 3791 len -= num; 3792 } 3793 } else { 3794 pos = eccsize + i * (eccsize + chunk); 3795 ret = nand_change_write_column_op(chip, pos, 3796 NULL, 0, 3797 false); 3798 if (ret) 3799 return ret; 3800 } 3801 } else 3802 sndcmd = 1; 3803 len = min_t(int, length, chunk); 3804 3805 ret = nand_write_data_op(chip, bufpoi, len, false); 3806 if (ret) 3807 return ret; 3808 3809 bufpoi += len; 3810 length -= len; 3811 } 3812 if (length > 0) { 3813 ret = nand_write_data_op(chip, bufpoi, length, false); 3814 if (ret) 3815 return ret; 3816 } 3817 3818 return nand_prog_page_end_op(chip); 3819 } 3820 3821 /** 3822 * nand_do_read_oob - [INTERN] NAND read out-of-band 3823 * @chip: NAND chip object 3824 * @from: offset to read from 3825 * @ops: oob operations description structure 3826 * 3827 * NAND read out-of-band data from the spare area. 3828 */ 3829 static int nand_do_read_oob(struct nand_chip *chip, loff_t from, 3830 struct mtd_oob_ops *ops) 3831 { 3832 struct mtd_info *mtd = nand_to_mtd(chip); 3833 unsigned int max_bitflips = 0; 3834 int page, realpage, chipnr; 3835 struct mtd_ecc_stats stats; 3836 int readlen = ops->ooblen; 3837 int len; 3838 uint8_t *buf = ops->oobbuf; 3839 int ret = 0; 3840 3841 pr_debug("%s: from = 0x%08Lx, len = %i\n", 3842 __func__, (unsigned long long)from, readlen); 3843 3844 /* Check if the region is secured */ 3845 if (nand_region_is_secured(chip, from, readlen)) 3846 return -EIO; 3847 3848 stats = mtd->ecc_stats; 3849 3850 len = mtd_oobavail(mtd, ops); 3851 3852 chipnr = (int)(from >> chip->chip_shift); 3853 nand_select_target(chip, chipnr); 3854 3855 /* Shift to get page */ 3856 realpage = (int)(from >> chip->page_shift); 3857 page = realpage & chip->pagemask; 3858 3859 while (1) { 3860 if (ops->mode == MTD_OPS_RAW) 3861 ret = chip->ecc.read_oob_raw(chip, page); 3862 else 3863 ret = chip->ecc.read_oob(chip, page); 3864 3865 if (ret < 0) 3866 break; 3867 3868 len = min(len, readlen); 3869 buf = nand_transfer_oob(chip, buf, ops, len); 3870 3871 nand_wait_readrdy(chip); 3872 3873 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3874 3875 readlen -= len; 3876 if (!readlen) 3877 break; 3878 3879 /* Increment page address */ 3880 realpage++; 3881 3882 page = realpage & chip->pagemask; 3883 /* Check, if we cross a chip boundary */ 3884 if (!page) { 3885 chipnr++; 3886 nand_deselect_target(chip); 3887 nand_select_target(chip, chipnr); 3888 } 3889 } 3890 nand_deselect_target(chip); 3891 3892 ops->oobretlen = ops->ooblen - readlen; 3893 3894 if (ret < 0) 3895 return ret; 3896 3897 if (mtd->ecc_stats.failed - stats.failed) 3898 return -EBADMSG; 3899 3900 return max_bitflips; 3901 } 3902 3903 /** 3904 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 3905 * @mtd: MTD device structure 3906 * @from: offset to read from 3907 * @ops: oob operation description structure 3908 * 3909 * NAND read data and/or out-of-band data. 3910 */ 3911 static int nand_read_oob(struct mtd_info *mtd, loff_t from, 3912 struct mtd_oob_ops *ops) 3913 { 3914 struct nand_chip *chip = mtd_to_nand(mtd); 3915 struct mtd_ecc_stats old_stats; 3916 int ret; 3917 3918 ops->retlen = 0; 3919 3920 if (ops->mode != MTD_OPS_PLACE_OOB && 3921 ops->mode != MTD_OPS_AUTO_OOB && 3922 ops->mode != MTD_OPS_RAW) 3923 return -ENOTSUPP; 3924 3925 nand_get_device(chip); 3926 3927 old_stats = mtd->ecc_stats; 3928 3929 if (!ops->datbuf) 3930 ret = nand_do_read_oob(chip, from, ops); 3931 else 3932 ret = nand_do_read_ops(chip, from, ops); 3933 3934 if (ops->stats) { 3935 ops->stats->uncorrectable_errors += 3936 mtd->ecc_stats.failed - old_stats.failed; 3937 ops->stats->corrected_bitflips += 3938 mtd->ecc_stats.corrected - old_stats.corrected; 3939 } 3940 3941 nand_release_device(chip); 3942 return ret; 3943 } 3944 3945 /** 3946 * nand_write_page_raw_notsupp - dummy raw page write function 3947 * @chip: nand chip info structure 3948 * @buf: data buffer 3949 * @oob_required: must write chip->oob_poi to OOB 3950 * @page: page number to write 3951 * 3952 * Returns -ENOTSUPP unconditionally. 3953 */ 3954 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf, 3955 int oob_required, int page) 3956 { 3957 return -ENOTSUPP; 3958 } 3959 3960 /** 3961 * nand_write_page_raw - [INTERN] raw page write function 3962 * @chip: nand chip info structure 3963 * @buf: data buffer 3964 * @oob_required: must write chip->oob_poi to OOB 3965 * @page: page number to write 3966 * 3967 * Not for syndrome calculating ECC controllers, which use a special oob layout. 3968 */ 3969 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 3970 int oob_required, int page) 3971 { 3972 struct mtd_info *mtd = nand_to_mtd(chip); 3973 int ret; 3974 3975 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 3976 if (ret) 3977 return ret; 3978 3979 if (oob_required) { 3980 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, 3981 false); 3982 if (ret) 3983 return ret; 3984 } 3985 3986 return nand_prog_page_end_op(chip); 3987 } 3988 EXPORT_SYMBOL(nand_write_page_raw); 3989 3990 /** 3991 * nand_monolithic_write_page_raw - Monolithic page write in raw mode 3992 * @chip: NAND chip info structure 3993 * @buf: data buffer to write 3994 * @oob_required: must write chip->oob_poi to OOB 3995 * @page: page number to write 3996 * 3997 * This is a raw page write, ie. without any error detection/correction. 3998 * Monolithic means we are requesting all the relevant data (main plus 3999 * eventually OOB) to be sent over the bus and effectively programmed 4000 * into the NAND chip arrays in a single operation. This is an 4001 * alternative to nand_write_page_raw(), which first sends the main 4002 * data, then eventually send the OOB data by latching more data 4003 * cycles on the NAND bus, and finally sends the program command to 4004 * synchronyze the NAND chip cache. 4005 */ 4006 int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf, 4007 int oob_required, int page) 4008 { 4009 struct mtd_info *mtd = nand_to_mtd(chip); 4010 unsigned int size = mtd->writesize; 4011 u8 *write_buf = (u8 *)buf; 4012 4013 if (oob_required) { 4014 size += mtd->oobsize; 4015 4016 if (buf != chip->data_buf) { 4017 write_buf = nand_get_data_buf(chip); 4018 memcpy(write_buf, buf, mtd->writesize); 4019 } 4020 } 4021 4022 return nand_prog_page_op(chip, page, 0, write_buf, size); 4023 } 4024 EXPORT_SYMBOL(nand_monolithic_write_page_raw); 4025 4026 /** 4027 * nand_write_page_raw_syndrome - [INTERN] raw page write function 4028 * @chip: nand chip info structure 4029 * @buf: data buffer 4030 * @oob_required: must write chip->oob_poi to OOB 4031 * @page: page number to write 4032 * 4033 * We need a special oob layout and handling even when ECC isn't checked. 4034 */ 4035 static int nand_write_page_raw_syndrome(struct nand_chip *chip, 4036 const uint8_t *buf, int oob_required, 4037 int page) 4038 { 4039 struct mtd_info *mtd = nand_to_mtd(chip); 4040 int eccsize = chip->ecc.size; 4041 int eccbytes = chip->ecc.bytes; 4042 uint8_t *oob = chip->oob_poi; 4043 int steps, size, ret; 4044 4045 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4046 if (ret) 4047 return ret; 4048 4049 for (steps = chip->ecc.steps; steps > 0; steps--) { 4050 ret = nand_write_data_op(chip, buf, eccsize, false); 4051 if (ret) 4052 return ret; 4053 4054 buf += eccsize; 4055 4056 if (chip->ecc.prepad) { 4057 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 4058 false); 4059 if (ret) 4060 return ret; 4061 4062 oob += chip->ecc.prepad; 4063 } 4064 4065 ret = nand_write_data_op(chip, oob, eccbytes, false); 4066 if (ret) 4067 return ret; 4068 4069 oob += eccbytes; 4070 4071 if (chip->ecc.postpad) { 4072 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 4073 false); 4074 if (ret) 4075 return ret; 4076 4077 oob += chip->ecc.postpad; 4078 } 4079 } 4080 4081 size = mtd->oobsize - (oob - chip->oob_poi); 4082 if (size) { 4083 ret = nand_write_data_op(chip, oob, size, false); 4084 if (ret) 4085 return ret; 4086 } 4087 4088 return nand_prog_page_end_op(chip); 4089 } 4090 /** 4091 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 4092 * @chip: nand chip info structure 4093 * @buf: data buffer 4094 * @oob_required: must write chip->oob_poi to OOB 4095 * @page: page number to write 4096 */ 4097 static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf, 4098 int oob_required, int page) 4099 { 4100 struct mtd_info *mtd = nand_to_mtd(chip); 4101 int i, eccsize = chip->ecc.size, ret; 4102 int eccbytes = chip->ecc.bytes; 4103 int eccsteps = chip->ecc.steps; 4104 uint8_t *ecc_calc = chip->ecc.calc_buf; 4105 const uint8_t *p = buf; 4106 4107 /* Software ECC calculation */ 4108 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 4109 chip->ecc.calculate(chip, p, &ecc_calc[i]); 4110 4111 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4112 chip->ecc.total); 4113 if (ret) 4114 return ret; 4115 4116 return chip->ecc.write_page_raw(chip, buf, 1, page); 4117 } 4118 4119 /** 4120 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 4121 * @chip: nand chip info structure 4122 * @buf: data buffer 4123 * @oob_required: must write chip->oob_poi to OOB 4124 * @page: page number to write 4125 */ 4126 static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf, 4127 int oob_required, int page) 4128 { 4129 struct mtd_info *mtd = nand_to_mtd(chip); 4130 int i, eccsize = chip->ecc.size, ret; 4131 int eccbytes = chip->ecc.bytes; 4132 int eccsteps = chip->ecc.steps; 4133 uint8_t *ecc_calc = chip->ecc.calc_buf; 4134 const uint8_t *p = buf; 4135 4136 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4137 if (ret) 4138 return ret; 4139 4140 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 4141 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4142 4143 ret = nand_write_data_op(chip, p, eccsize, false); 4144 if (ret) 4145 return ret; 4146 4147 chip->ecc.calculate(chip, p, &ecc_calc[i]); 4148 } 4149 4150 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4151 chip->ecc.total); 4152 if (ret) 4153 return ret; 4154 4155 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 4156 if (ret) 4157 return ret; 4158 4159 return nand_prog_page_end_op(chip); 4160 } 4161 4162 4163 /** 4164 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write 4165 * @chip: nand chip info structure 4166 * @offset: column address of subpage within the page 4167 * @data_len: data length 4168 * @buf: data buffer 4169 * @oob_required: must write chip->oob_poi to OOB 4170 * @page: page number to write 4171 */ 4172 static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset, 4173 uint32_t data_len, const uint8_t *buf, 4174 int oob_required, int page) 4175 { 4176 struct mtd_info *mtd = nand_to_mtd(chip); 4177 uint8_t *oob_buf = chip->oob_poi; 4178 uint8_t *ecc_calc = chip->ecc.calc_buf; 4179 int ecc_size = chip->ecc.size; 4180 int ecc_bytes = chip->ecc.bytes; 4181 int ecc_steps = chip->ecc.steps; 4182 uint32_t start_step = offset / ecc_size; 4183 uint32_t end_step = (offset + data_len - 1) / ecc_size; 4184 int oob_bytes = mtd->oobsize / ecc_steps; 4185 int step, ret; 4186 4187 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4188 if (ret) 4189 return ret; 4190 4191 for (step = 0; step < ecc_steps; step++) { 4192 /* configure controller for WRITE access */ 4193 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4194 4195 /* write data (untouched subpages already masked by 0xFF) */ 4196 ret = nand_write_data_op(chip, buf, ecc_size, false); 4197 if (ret) 4198 return ret; 4199 4200 /* mask ECC of un-touched subpages by padding 0xFF */ 4201 if ((step < start_step) || (step > end_step)) 4202 memset(ecc_calc, 0xff, ecc_bytes); 4203 else 4204 chip->ecc.calculate(chip, buf, ecc_calc); 4205 4206 /* mask OOB of un-touched subpages by padding 0xFF */ 4207 /* if oob_required, preserve OOB metadata of written subpage */ 4208 if (!oob_required || (step < start_step) || (step > end_step)) 4209 memset(oob_buf, 0xff, oob_bytes); 4210 4211 buf += ecc_size; 4212 ecc_calc += ecc_bytes; 4213 oob_buf += oob_bytes; 4214 } 4215 4216 /* copy calculated ECC for whole page to chip->buffer->oob */ 4217 /* this include masked-value(0xFF) for unwritten subpages */ 4218 ecc_calc = chip->ecc.calc_buf; 4219 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 4220 chip->ecc.total); 4221 if (ret) 4222 return ret; 4223 4224 /* write OOB buffer to NAND device */ 4225 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 4226 if (ret) 4227 return ret; 4228 4229 return nand_prog_page_end_op(chip); 4230 } 4231 4232 4233 /** 4234 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 4235 * @chip: nand chip info structure 4236 * @buf: data buffer 4237 * @oob_required: must write chip->oob_poi to OOB 4238 * @page: page number to write 4239 * 4240 * The hw generator calculates the error syndrome automatically. Therefore we 4241 * need a special oob layout and handling. 4242 */ 4243 static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf, 4244 int oob_required, int page) 4245 { 4246 struct mtd_info *mtd = nand_to_mtd(chip); 4247 int i, eccsize = chip->ecc.size; 4248 int eccbytes = chip->ecc.bytes; 4249 int eccsteps = chip->ecc.steps; 4250 const uint8_t *p = buf; 4251 uint8_t *oob = chip->oob_poi; 4252 int ret; 4253 4254 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 4255 if (ret) 4256 return ret; 4257 4258 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 4259 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 4260 4261 ret = nand_write_data_op(chip, p, eccsize, false); 4262 if (ret) 4263 return ret; 4264 4265 if (chip->ecc.prepad) { 4266 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 4267 false); 4268 if (ret) 4269 return ret; 4270 4271 oob += chip->ecc.prepad; 4272 } 4273 4274 chip->ecc.calculate(chip, p, oob); 4275 4276 ret = nand_write_data_op(chip, oob, eccbytes, false); 4277 if (ret) 4278 return ret; 4279 4280 oob += eccbytes; 4281 4282 if (chip->ecc.postpad) { 4283 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 4284 false); 4285 if (ret) 4286 return ret; 4287 4288 oob += chip->ecc.postpad; 4289 } 4290 } 4291 4292 /* Calculate remaining oob bytes */ 4293 i = mtd->oobsize - (oob - chip->oob_poi); 4294 if (i) { 4295 ret = nand_write_data_op(chip, oob, i, false); 4296 if (ret) 4297 return ret; 4298 } 4299 4300 return nand_prog_page_end_op(chip); 4301 } 4302 4303 /** 4304 * nand_write_page - write one page 4305 * @chip: NAND chip descriptor 4306 * @offset: address offset within the page 4307 * @data_len: length of actual data to be written 4308 * @buf: the data to write 4309 * @oob_required: must write chip->oob_poi to OOB 4310 * @page: page number to write 4311 * @raw: use _raw version of write_page 4312 */ 4313 static int nand_write_page(struct nand_chip *chip, uint32_t offset, 4314 int data_len, const uint8_t *buf, int oob_required, 4315 int page, int raw) 4316 { 4317 struct mtd_info *mtd = nand_to_mtd(chip); 4318 int status, subpage; 4319 4320 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 4321 chip->ecc.write_subpage) 4322 subpage = offset || (data_len < mtd->writesize); 4323 else 4324 subpage = 0; 4325 4326 if (unlikely(raw)) 4327 status = chip->ecc.write_page_raw(chip, buf, oob_required, 4328 page); 4329 else if (subpage) 4330 status = chip->ecc.write_subpage(chip, offset, data_len, buf, 4331 oob_required, page); 4332 else 4333 status = chip->ecc.write_page(chip, buf, oob_required, page); 4334 4335 if (status < 0) 4336 return status; 4337 4338 return 0; 4339 } 4340 4341 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 4342 4343 /** 4344 * nand_do_write_ops - [INTERN] NAND write with ECC 4345 * @chip: NAND chip object 4346 * @to: offset to write to 4347 * @ops: oob operations description structure 4348 * 4349 * NAND write with ECC. 4350 */ 4351 static int nand_do_write_ops(struct nand_chip *chip, loff_t to, 4352 struct mtd_oob_ops *ops) 4353 { 4354 struct mtd_info *mtd = nand_to_mtd(chip); 4355 int chipnr, realpage, page, column; 4356 uint32_t writelen = ops->len; 4357 4358 uint32_t oobwritelen = ops->ooblen; 4359 uint32_t oobmaxlen = mtd_oobavail(mtd, ops); 4360 4361 uint8_t *oob = ops->oobbuf; 4362 uint8_t *buf = ops->datbuf; 4363 int ret; 4364 int oob_required = oob ? 1 : 0; 4365 4366 ops->retlen = 0; 4367 if (!writelen) 4368 return 0; 4369 4370 /* Reject writes, which are not page aligned */ 4371 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 4372 pr_notice("%s: attempt to write non page aligned data\n", 4373 __func__); 4374 return -EINVAL; 4375 } 4376 4377 /* Check if the region is secured */ 4378 if (nand_region_is_secured(chip, to, writelen)) 4379 return -EIO; 4380 4381 column = to & (mtd->writesize - 1); 4382 4383 chipnr = (int)(to >> chip->chip_shift); 4384 nand_select_target(chip, chipnr); 4385 4386 /* Check, if it is write protected */ 4387 if (nand_check_wp(chip)) { 4388 ret = -EIO; 4389 goto err_out; 4390 } 4391 4392 realpage = (int)(to >> chip->page_shift); 4393 page = realpage & chip->pagemask; 4394 4395 /* Invalidate the page cache, when we write to the cached page */ 4396 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) && 4397 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len)) 4398 chip->pagecache.page = -1; 4399 4400 /* Don't allow multipage oob writes with offset */ 4401 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 4402 ret = -EINVAL; 4403 goto err_out; 4404 } 4405 4406 while (1) { 4407 int bytes = mtd->writesize; 4408 uint8_t *wbuf = buf; 4409 int use_bounce_buf; 4410 int part_pagewr = (column || writelen < mtd->writesize); 4411 4412 if (part_pagewr) 4413 use_bounce_buf = 1; 4414 else if (chip->options & NAND_USES_DMA) 4415 use_bounce_buf = !virt_addr_valid(buf) || 4416 !IS_ALIGNED((unsigned long)buf, 4417 chip->buf_align); 4418 else 4419 use_bounce_buf = 0; 4420 4421 /* 4422 * Copy the data from the initial buffer when doing partial page 4423 * writes or when a bounce buffer is required. 4424 */ 4425 if (use_bounce_buf) { 4426 pr_debug("%s: using write bounce buffer for buf@%p\n", 4427 __func__, buf); 4428 if (part_pagewr) 4429 bytes = min_t(int, bytes - column, writelen); 4430 wbuf = nand_get_data_buf(chip); 4431 memset(wbuf, 0xff, mtd->writesize); 4432 memcpy(&wbuf[column], buf, bytes); 4433 } 4434 4435 if (unlikely(oob)) { 4436 size_t len = min(oobwritelen, oobmaxlen); 4437 oob = nand_fill_oob(chip, oob, len, ops); 4438 oobwritelen -= len; 4439 } else { 4440 /* We still need to erase leftover OOB data */ 4441 memset(chip->oob_poi, 0xff, mtd->oobsize); 4442 } 4443 4444 ret = nand_write_page(chip, column, bytes, wbuf, 4445 oob_required, page, 4446 (ops->mode == MTD_OPS_RAW)); 4447 if (ret) 4448 break; 4449 4450 writelen -= bytes; 4451 if (!writelen) 4452 break; 4453 4454 column = 0; 4455 buf += bytes; 4456 realpage++; 4457 4458 page = realpage & chip->pagemask; 4459 /* Check, if we cross a chip boundary */ 4460 if (!page) { 4461 chipnr++; 4462 nand_deselect_target(chip); 4463 nand_select_target(chip, chipnr); 4464 } 4465 } 4466 4467 ops->retlen = ops->len - writelen; 4468 if (unlikely(oob)) 4469 ops->oobretlen = ops->ooblen; 4470 4471 err_out: 4472 nand_deselect_target(chip); 4473 return ret; 4474 } 4475 4476 /** 4477 * panic_nand_write - [MTD Interface] NAND write with ECC 4478 * @mtd: MTD device structure 4479 * @to: offset to write to 4480 * @len: number of bytes to write 4481 * @retlen: pointer to variable to store the number of written bytes 4482 * @buf: the data to write 4483 * 4484 * NAND write with ECC. Used when performing writes in interrupt context, this 4485 * may for example be called by mtdoops when writing an oops while in panic. 4486 */ 4487 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 4488 size_t *retlen, const uint8_t *buf) 4489 { 4490 struct nand_chip *chip = mtd_to_nand(mtd); 4491 int chipnr = (int)(to >> chip->chip_shift); 4492 struct mtd_oob_ops ops; 4493 int ret; 4494 4495 nand_select_target(chip, chipnr); 4496 4497 /* Wait for the device to get ready */ 4498 panic_nand_wait(chip, 400); 4499 4500 memset(&ops, 0, sizeof(ops)); 4501 ops.len = len; 4502 ops.datbuf = (uint8_t *)buf; 4503 ops.mode = MTD_OPS_PLACE_OOB; 4504 4505 ret = nand_do_write_ops(chip, to, &ops); 4506 4507 *retlen = ops.retlen; 4508 return ret; 4509 } 4510 4511 /** 4512 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 4513 * @mtd: MTD device structure 4514 * @to: offset to write to 4515 * @ops: oob operation description structure 4516 */ 4517 static int nand_write_oob(struct mtd_info *mtd, loff_t to, 4518 struct mtd_oob_ops *ops) 4519 { 4520 struct nand_chip *chip = mtd_to_nand(mtd); 4521 int ret = 0; 4522 4523 ops->retlen = 0; 4524 4525 nand_get_device(chip); 4526 4527 switch (ops->mode) { 4528 case MTD_OPS_PLACE_OOB: 4529 case MTD_OPS_AUTO_OOB: 4530 case MTD_OPS_RAW: 4531 break; 4532 4533 default: 4534 goto out; 4535 } 4536 4537 if (!ops->datbuf) 4538 ret = nand_do_write_oob(chip, to, ops); 4539 else 4540 ret = nand_do_write_ops(chip, to, ops); 4541 4542 out: 4543 nand_release_device(chip); 4544 return ret; 4545 } 4546 4547 /** 4548 * nand_erase - [MTD Interface] erase block(s) 4549 * @mtd: MTD device structure 4550 * @instr: erase instruction 4551 * 4552 * Erase one ore more blocks. 4553 */ 4554 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 4555 { 4556 return nand_erase_nand(mtd_to_nand(mtd), instr, 0); 4557 } 4558 4559 /** 4560 * nand_erase_nand - [INTERN] erase block(s) 4561 * @chip: NAND chip object 4562 * @instr: erase instruction 4563 * @allowbbt: allow erasing the bbt area 4564 * 4565 * Erase one ore more blocks. 4566 */ 4567 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, 4568 int allowbbt) 4569 { 4570 int page, pages_per_block, ret, chipnr; 4571 loff_t len; 4572 4573 pr_debug("%s: start = 0x%012llx, len = %llu\n", 4574 __func__, (unsigned long long)instr->addr, 4575 (unsigned long long)instr->len); 4576 4577 if (check_offs_len(chip, instr->addr, instr->len)) 4578 return -EINVAL; 4579 4580 /* Check if the region is secured */ 4581 if (nand_region_is_secured(chip, instr->addr, instr->len)) 4582 return -EIO; 4583 4584 /* Grab the lock and see if the device is available */ 4585 nand_get_device(chip); 4586 4587 /* Shift to get first page */ 4588 page = (int)(instr->addr >> chip->page_shift); 4589 chipnr = (int)(instr->addr >> chip->chip_shift); 4590 4591 /* Calculate pages in each block */ 4592 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 4593 4594 /* Select the NAND device */ 4595 nand_select_target(chip, chipnr); 4596 4597 /* Check, if it is write protected */ 4598 if (nand_check_wp(chip)) { 4599 pr_debug("%s: device is write protected!\n", 4600 __func__); 4601 ret = -EIO; 4602 goto erase_exit; 4603 } 4604 4605 /* Loop through the pages */ 4606 len = instr->len; 4607 4608 while (len) { 4609 loff_t ofs = (loff_t)page << chip->page_shift; 4610 4611 /* Check if we have a bad block, we do not erase bad blocks! */ 4612 if (nand_block_checkbad(chip, ((loff_t) page) << 4613 chip->page_shift, allowbbt)) { 4614 pr_warn("%s: attempt to erase a bad block at 0x%08llx\n", 4615 __func__, (unsigned long long)ofs); 4616 ret = -EIO; 4617 goto erase_exit; 4618 } 4619 4620 /* 4621 * Invalidate the page cache, if we erase the block which 4622 * contains the current cached page. 4623 */ 4624 if (page <= chip->pagecache.page && chip->pagecache.page < 4625 (page + pages_per_block)) 4626 chip->pagecache.page = -1; 4627 4628 ret = nand_erase_op(chip, (page & chip->pagemask) >> 4629 (chip->phys_erase_shift - chip->page_shift)); 4630 if (ret) { 4631 pr_debug("%s: failed erase, page 0x%08x\n", 4632 __func__, page); 4633 instr->fail_addr = ofs; 4634 goto erase_exit; 4635 } 4636 4637 /* Increment page address and decrement length */ 4638 len -= (1ULL << chip->phys_erase_shift); 4639 page += pages_per_block; 4640 4641 /* Check, if we cross a chip boundary */ 4642 if (len && !(page & chip->pagemask)) { 4643 chipnr++; 4644 nand_deselect_target(chip); 4645 nand_select_target(chip, chipnr); 4646 } 4647 } 4648 4649 ret = 0; 4650 erase_exit: 4651 4652 /* Deselect and wake up anyone waiting on the device */ 4653 nand_deselect_target(chip); 4654 nand_release_device(chip); 4655 4656 /* Return more or less happy */ 4657 return ret; 4658 } 4659 4660 /** 4661 * nand_sync - [MTD Interface] sync 4662 * @mtd: MTD device structure 4663 * 4664 * Sync is actually a wait for chip ready function. 4665 */ 4666 static void nand_sync(struct mtd_info *mtd) 4667 { 4668 struct nand_chip *chip = mtd_to_nand(mtd); 4669 4670 pr_debug("%s: called\n", __func__); 4671 4672 /* Grab the lock and see if the device is available */ 4673 nand_get_device(chip); 4674 /* Release it and go back */ 4675 nand_release_device(chip); 4676 } 4677 4678 /** 4679 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 4680 * @mtd: MTD device structure 4681 * @offs: offset relative to mtd start 4682 */ 4683 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 4684 { 4685 struct nand_chip *chip = mtd_to_nand(mtd); 4686 int chipnr = (int)(offs >> chip->chip_shift); 4687 int ret; 4688 4689 /* Select the NAND device */ 4690 nand_get_device(chip); 4691 4692 nand_select_target(chip, chipnr); 4693 4694 ret = nand_block_checkbad(chip, offs, 0); 4695 4696 nand_deselect_target(chip); 4697 nand_release_device(chip); 4698 4699 return ret; 4700 } 4701 4702 /** 4703 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 4704 * @mtd: MTD device structure 4705 * @ofs: offset relative to mtd start 4706 */ 4707 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 4708 { 4709 int ret; 4710 4711 ret = nand_block_isbad(mtd, ofs); 4712 if (ret) { 4713 /* If it was bad already, return success and do nothing */ 4714 if (ret > 0) 4715 return 0; 4716 return ret; 4717 } 4718 4719 return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs); 4720 } 4721 4722 /** 4723 * nand_suspend - [MTD Interface] Suspend the NAND flash 4724 * @mtd: MTD device structure 4725 * 4726 * Returns 0 for success or negative error code otherwise. 4727 */ 4728 static int nand_suspend(struct mtd_info *mtd) 4729 { 4730 struct nand_chip *chip = mtd_to_nand(mtd); 4731 int ret = 0; 4732 4733 mutex_lock(&chip->lock); 4734 if (chip->ops.suspend) 4735 ret = chip->ops.suspend(chip); 4736 if (!ret) 4737 chip->suspended = 1; 4738 mutex_unlock(&chip->lock); 4739 4740 return ret; 4741 } 4742 4743 /** 4744 * nand_resume - [MTD Interface] Resume the NAND flash 4745 * @mtd: MTD device structure 4746 */ 4747 static void nand_resume(struct mtd_info *mtd) 4748 { 4749 struct nand_chip *chip = mtd_to_nand(mtd); 4750 4751 mutex_lock(&chip->lock); 4752 if (chip->suspended) { 4753 if (chip->ops.resume) 4754 chip->ops.resume(chip); 4755 chip->suspended = 0; 4756 } else { 4757 pr_err("%s called for a chip which is not in suspended state\n", 4758 __func__); 4759 } 4760 mutex_unlock(&chip->lock); 4761 4762 wake_up_all(&chip->resume_wq); 4763 } 4764 4765 /** 4766 * nand_shutdown - [MTD Interface] Finish the current NAND operation and 4767 * prevent further operations 4768 * @mtd: MTD device structure 4769 */ 4770 static void nand_shutdown(struct mtd_info *mtd) 4771 { 4772 nand_suspend(mtd); 4773 } 4774 4775 /** 4776 * nand_lock - [MTD Interface] Lock the NAND flash 4777 * @mtd: MTD device structure 4778 * @ofs: offset byte address 4779 * @len: number of bytes to lock (must be a multiple of block/page size) 4780 */ 4781 static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4782 { 4783 struct nand_chip *chip = mtd_to_nand(mtd); 4784 4785 if (!chip->ops.lock_area) 4786 return -ENOTSUPP; 4787 4788 return chip->ops.lock_area(chip, ofs, len); 4789 } 4790 4791 /** 4792 * nand_unlock - [MTD Interface] Unlock the NAND flash 4793 * @mtd: MTD device structure 4794 * @ofs: offset byte address 4795 * @len: number of bytes to unlock (must be a multiple of block/page size) 4796 */ 4797 static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4798 { 4799 struct nand_chip *chip = mtd_to_nand(mtd); 4800 4801 if (!chip->ops.unlock_area) 4802 return -ENOTSUPP; 4803 4804 return chip->ops.unlock_area(chip, ofs, len); 4805 } 4806 4807 /* Set default functions */ 4808 static void nand_set_defaults(struct nand_chip *chip) 4809 { 4810 /* If no controller is provided, use the dummy, legacy one. */ 4811 if (!chip->controller) { 4812 chip->controller = &chip->legacy.dummy_controller; 4813 nand_controller_init(chip->controller); 4814 } 4815 4816 nand_legacy_set_defaults(chip); 4817 4818 if (!chip->buf_align) 4819 chip->buf_align = 1; 4820 } 4821 4822 /* Sanitize ONFI strings so we can safely print them */ 4823 void sanitize_string(uint8_t *s, size_t len) 4824 { 4825 ssize_t i; 4826 4827 /* Null terminate */ 4828 s[len - 1] = 0; 4829 4830 /* Remove non printable chars */ 4831 for (i = 0; i < len - 1; i++) { 4832 if (s[i] < ' ' || s[i] > 127) 4833 s[i] = '?'; 4834 } 4835 4836 /* Remove trailing spaces */ 4837 strim(s); 4838 } 4839 4840 /* 4841 * nand_id_has_period - Check if an ID string has a given wraparound period 4842 * @id_data: the ID string 4843 * @arrlen: the length of the @id_data array 4844 * @period: the period of repitition 4845 * 4846 * Check if an ID string is repeated within a given sequence of bytes at 4847 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 4848 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 4849 * if the repetition has a period of @period; otherwise, returns zero. 4850 */ 4851 static int nand_id_has_period(u8 *id_data, int arrlen, int period) 4852 { 4853 int i, j; 4854 for (i = 0; i < period; i++) 4855 for (j = i + period; j < arrlen; j += period) 4856 if (id_data[i] != id_data[j]) 4857 return 0; 4858 return 1; 4859 } 4860 4861 /* 4862 * nand_id_len - Get the length of an ID string returned by CMD_READID 4863 * @id_data: the ID string 4864 * @arrlen: the length of the @id_data array 4865 4866 * Returns the length of the ID string, according to known wraparound/trailing 4867 * zero patterns. If no pattern exists, returns the length of the array. 4868 */ 4869 static int nand_id_len(u8 *id_data, int arrlen) 4870 { 4871 int last_nonzero, period; 4872 4873 /* Find last non-zero byte */ 4874 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 4875 if (id_data[last_nonzero]) 4876 break; 4877 4878 /* All zeros */ 4879 if (last_nonzero < 0) 4880 return 0; 4881 4882 /* Calculate wraparound period */ 4883 for (period = 1; period < arrlen; period++) 4884 if (nand_id_has_period(id_data, arrlen, period)) 4885 break; 4886 4887 /* There's a repeated pattern */ 4888 if (period < arrlen) 4889 return period; 4890 4891 /* There are trailing zeros */ 4892 if (last_nonzero < arrlen - 1) 4893 return last_nonzero + 1; 4894 4895 /* No pattern detected */ 4896 return arrlen; 4897 } 4898 4899 /* Extract the bits of per cell from the 3rd byte of the extended ID */ 4900 static int nand_get_bits_per_cell(u8 cellinfo) 4901 { 4902 int bits; 4903 4904 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 4905 bits >>= NAND_CI_CELLTYPE_SHIFT; 4906 return bits + 1; 4907 } 4908 4909 /* 4910 * Many new NAND share similar device ID codes, which represent the size of the 4911 * chip. The rest of the parameters must be decoded according to generic or 4912 * manufacturer-specific "extended ID" decoding patterns. 4913 */ 4914 void nand_decode_ext_id(struct nand_chip *chip) 4915 { 4916 struct nand_memory_organization *memorg; 4917 struct mtd_info *mtd = nand_to_mtd(chip); 4918 int extid; 4919 u8 *id_data = chip->id.data; 4920 4921 memorg = nanddev_get_memorg(&chip->base); 4922 4923 /* The 3rd id byte holds MLC / multichip data */ 4924 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 4925 /* The 4th id byte is the important one */ 4926 extid = id_data[3]; 4927 4928 /* Calc pagesize */ 4929 memorg->pagesize = 1024 << (extid & 0x03); 4930 mtd->writesize = memorg->pagesize; 4931 extid >>= 2; 4932 /* Calc oobsize */ 4933 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); 4934 mtd->oobsize = memorg->oobsize; 4935 extid >>= 2; 4936 /* Calc blocksize. Blocksize is multiples of 64KiB */ 4937 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) / 4938 memorg->pagesize; 4939 mtd->erasesize = (64 * 1024) << (extid & 0x03); 4940 extid >>= 2; 4941 /* Get buswidth information */ 4942 if (extid & 0x1) 4943 chip->options |= NAND_BUSWIDTH_16; 4944 } 4945 EXPORT_SYMBOL_GPL(nand_decode_ext_id); 4946 4947 /* 4948 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 4949 * decodes a matching ID table entry and assigns the MTD size parameters for 4950 * the chip. 4951 */ 4952 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) 4953 { 4954 struct mtd_info *mtd = nand_to_mtd(chip); 4955 struct nand_memory_organization *memorg; 4956 4957 memorg = nanddev_get_memorg(&chip->base); 4958 4959 memorg->pages_per_eraseblock = type->erasesize / type->pagesize; 4960 mtd->erasesize = type->erasesize; 4961 memorg->pagesize = type->pagesize; 4962 mtd->writesize = memorg->pagesize; 4963 memorg->oobsize = memorg->pagesize / 32; 4964 mtd->oobsize = memorg->oobsize; 4965 4966 /* All legacy ID NAND are small-page, SLC */ 4967 memorg->bits_per_cell = 1; 4968 } 4969 4970 /* 4971 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 4972 * heuristic patterns using various detected parameters (e.g., manufacturer, 4973 * page size, cell-type information). 4974 */ 4975 static void nand_decode_bbm_options(struct nand_chip *chip) 4976 { 4977 struct mtd_info *mtd = nand_to_mtd(chip); 4978 4979 /* Set the bad block position */ 4980 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 4981 chip->badblockpos = NAND_BBM_POS_LARGE; 4982 else 4983 chip->badblockpos = NAND_BBM_POS_SMALL; 4984 } 4985 4986 static inline bool is_full_id_nand(struct nand_flash_dev *type) 4987 { 4988 return type->id_len; 4989 } 4990 4991 static bool find_full_id_nand(struct nand_chip *chip, 4992 struct nand_flash_dev *type) 4993 { 4994 struct nand_device *base = &chip->base; 4995 struct nand_ecc_props requirements; 4996 struct mtd_info *mtd = nand_to_mtd(chip); 4997 struct nand_memory_organization *memorg; 4998 u8 *id_data = chip->id.data; 4999 5000 memorg = nanddev_get_memorg(&chip->base); 5001 5002 if (!strncmp(type->id, id_data, type->id_len)) { 5003 memorg->pagesize = type->pagesize; 5004 mtd->writesize = memorg->pagesize; 5005 memorg->pages_per_eraseblock = type->erasesize / 5006 type->pagesize; 5007 mtd->erasesize = type->erasesize; 5008 memorg->oobsize = type->oobsize; 5009 mtd->oobsize = memorg->oobsize; 5010 5011 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 5012 memorg->eraseblocks_per_lun = 5013 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 5014 memorg->pagesize * 5015 memorg->pages_per_eraseblock); 5016 chip->options |= type->options; 5017 requirements.strength = NAND_ECC_STRENGTH(type); 5018 requirements.step_size = NAND_ECC_STEP(type); 5019 nanddev_set_ecc_requirements(base, &requirements); 5020 5021 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 5022 if (!chip->parameters.model) 5023 return false; 5024 5025 return true; 5026 } 5027 return false; 5028 } 5029 5030 /* 5031 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC 5032 * compliant and does not have a full-id or legacy-id entry in the nand_ids 5033 * table. 5034 */ 5035 static void nand_manufacturer_detect(struct nand_chip *chip) 5036 { 5037 /* 5038 * Try manufacturer detection if available and use 5039 * nand_decode_ext_id() otherwise. 5040 */ 5041 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 5042 chip->manufacturer.desc->ops->detect) { 5043 struct nand_memory_organization *memorg; 5044 5045 memorg = nanddev_get_memorg(&chip->base); 5046 5047 /* The 3rd id byte holds MLC / multichip data */ 5048 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 5049 chip->manufacturer.desc->ops->detect(chip); 5050 } else { 5051 nand_decode_ext_id(chip); 5052 } 5053 } 5054 5055 /* 5056 * Manufacturer initialization. This function is called for all NANDs including 5057 * ONFI and JEDEC compliant ones. 5058 * Manufacturer drivers should put all their specific initialization code in 5059 * their ->init() hook. 5060 */ 5061 static int nand_manufacturer_init(struct nand_chip *chip) 5062 { 5063 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || 5064 !chip->manufacturer.desc->ops->init) 5065 return 0; 5066 5067 return chip->manufacturer.desc->ops->init(chip); 5068 } 5069 5070 /* 5071 * Manufacturer cleanup. This function is called for all NANDs including 5072 * ONFI and JEDEC compliant ones. 5073 * Manufacturer drivers should put all their specific cleanup code in their 5074 * ->cleanup() hook. 5075 */ 5076 static void nand_manufacturer_cleanup(struct nand_chip *chip) 5077 { 5078 /* Release manufacturer private data */ 5079 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 5080 chip->manufacturer.desc->ops->cleanup) 5081 chip->manufacturer.desc->ops->cleanup(chip); 5082 } 5083 5084 static const char * 5085 nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc) 5086 { 5087 return manufacturer_desc ? manufacturer_desc->name : "Unknown"; 5088 } 5089 5090 static void rawnand_check_data_only_read_support(struct nand_chip *chip) 5091 { 5092 /* Use an arbitrary size for the check */ 5093 if (!nand_read_data_op(chip, NULL, SZ_512, true, true)) 5094 chip->controller->supported_op.data_only_read = 1; 5095 } 5096 5097 static void rawnand_early_check_supported_ops(struct nand_chip *chip) 5098 { 5099 /* The supported_op fields should not be set by individual drivers */ 5100 WARN_ON_ONCE(chip->controller->supported_op.data_only_read); 5101 5102 if (!nand_has_exec_op(chip)) 5103 return; 5104 5105 rawnand_check_data_only_read_support(chip); 5106 } 5107 5108 static void rawnand_check_cont_read_support(struct nand_chip *chip) 5109 { 5110 struct mtd_info *mtd = nand_to_mtd(chip); 5111 5112 if (!chip->parameters.supports_read_cache) 5113 return; 5114 5115 if (chip->read_retries) 5116 return; 5117 5118 if (!nand_lp_exec_cont_read_page_op(chip, 0, 0, NULL, 5119 mtd->writesize, true)) 5120 chip->controller->supported_op.cont_read = 1; 5121 } 5122 5123 static void rawnand_late_check_supported_ops(struct nand_chip *chip) 5124 { 5125 /* The supported_op fields should not be set by individual drivers */ 5126 WARN_ON_ONCE(chip->controller->supported_op.cont_read); 5127 5128 if (!nand_has_exec_op(chip)) 5129 return; 5130 5131 rawnand_check_cont_read_support(chip); 5132 } 5133 5134 /* 5135 * Get the flash and manufacturer id and lookup if the type is supported. 5136 */ 5137 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) 5138 { 5139 const struct nand_manufacturer_desc *manufacturer_desc; 5140 struct mtd_info *mtd = nand_to_mtd(chip); 5141 struct nand_memory_organization *memorg; 5142 int busw, ret; 5143 u8 *id_data = chip->id.data; 5144 u8 maf_id, dev_id; 5145 u64 targetsize; 5146 5147 /* 5148 * Let's start by initializing memorg fields that might be left 5149 * unassigned by the ID-based detection logic. 5150 */ 5151 memorg = nanddev_get_memorg(&chip->base); 5152 memorg->planes_per_lun = 1; 5153 memorg->luns_per_target = 1; 5154 5155 /* 5156 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 5157 * after power-up. 5158 */ 5159 ret = nand_reset(chip, 0); 5160 if (ret) 5161 return ret; 5162 5163 /* Select the device */ 5164 nand_select_target(chip, 0); 5165 5166 rawnand_early_check_supported_ops(chip); 5167 5168 /* Send the command for reading device ID */ 5169 ret = nand_readid_op(chip, 0, id_data, 2); 5170 if (ret) 5171 return ret; 5172 5173 /* Read manufacturer and device IDs */ 5174 maf_id = id_data[0]; 5175 dev_id = id_data[1]; 5176 5177 /* 5178 * Try again to make sure, as some systems the bus-hold or other 5179 * interface concerns can cause random data which looks like a 5180 * possibly credible NAND flash to appear. If the two results do 5181 * not match, ignore the device completely. 5182 */ 5183 5184 /* Read entire ID string */ 5185 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); 5186 if (ret) 5187 return ret; 5188 5189 if (id_data[0] != maf_id || id_data[1] != dev_id) { 5190 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 5191 maf_id, dev_id, id_data[0], id_data[1]); 5192 return -ENODEV; 5193 } 5194 5195 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); 5196 5197 /* Try to identify manufacturer */ 5198 manufacturer_desc = nand_get_manufacturer_desc(maf_id); 5199 chip->manufacturer.desc = manufacturer_desc; 5200 5201 if (!type) 5202 type = nand_flash_ids; 5203 5204 /* 5205 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic 5206 * override it. 5207 * This is required to make sure initial NAND bus width set by the 5208 * NAND controller driver is coherent with the real NAND bus width 5209 * (extracted by auto-detection code). 5210 */ 5211 busw = chip->options & NAND_BUSWIDTH_16; 5212 5213 /* 5214 * The flag is only set (never cleared), reset it to its default value 5215 * before starting auto-detection. 5216 */ 5217 chip->options &= ~NAND_BUSWIDTH_16; 5218 5219 for (; type->name != NULL; type++) { 5220 if (is_full_id_nand(type)) { 5221 if (find_full_id_nand(chip, type)) 5222 goto ident_done; 5223 } else if (dev_id == type->dev_id) { 5224 break; 5225 } 5226 } 5227 5228 if (!type->name || !type->pagesize) { 5229 /* Check if the chip is ONFI compliant */ 5230 ret = nand_onfi_detect(chip); 5231 if (ret < 0) 5232 return ret; 5233 else if (ret) 5234 goto ident_done; 5235 5236 /* Check if the chip is JEDEC compliant */ 5237 ret = nand_jedec_detect(chip); 5238 if (ret < 0) 5239 return ret; 5240 else if (ret) 5241 goto ident_done; 5242 } 5243 5244 if (!type->name) 5245 return -ENODEV; 5246 5247 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 5248 if (!chip->parameters.model) 5249 return -ENOMEM; 5250 5251 if (!type->pagesize) 5252 nand_manufacturer_detect(chip); 5253 else 5254 nand_decode_id(chip, type); 5255 5256 /* Get chip options */ 5257 chip->options |= type->options; 5258 5259 memorg->eraseblocks_per_lun = 5260 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 5261 memorg->pagesize * 5262 memorg->pages_per_eraseblock); 5263 5264 ident_done: 5265 if (!mtd->name) 5266 mtd->name = chip->parameters.model; 5267 5268 if (chip->options & NAND_BUSWIDTH_AUTO) { 5269 WARN_ON(busw & NAND_BUSWIDTH_16); 5270 nand_set_defaults(chip); 5271 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 5272 /* 5273 * Check, if buswidth is correct. Hardware drivers should set 5274 * chip correct! 5275 */ 5276 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 5277 maf_id, dev_id); 5278 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc), 5279 mtd->name); 5280 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, 5281 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); 5282 ret = -EINVAL; 5283 5284 goto free_detect_allocation; 5285 } 5286 5287 nand_decode_bbm_options(chip); 5288 5289 /* Calculate the address shift from the page size */ 5290 chip->page_shift = ffs(mtd->writesize) - 1; 5291 /* Convert chipsize to number of pages per chip -1 */ 5292 targetsize = nanddev_target_size(&chip->base); 5293 chip->pagemask = (targetsize >> chip->page_shift) - 1; 5294 5295 chip->bbt_erase_shift = chip->phys_erase_shift = 5296 ffs(mtd->erasesize) - 1; 5297 if (targetsize & 0xffffffff) 5298 chip->chip_shift = ffs((unsigned)targetsize) - 1; 5299 else { 5300 chip->chip_shift = ffs((unsigned)(targetsize >> 32)); 5301 chip->chip_shift += 32 - 1; 5302 } 5303 5304 if (chip->chip_shift - chip->page_shift > 16) 5305 chip->options |= NAND_ROW_ADDR_3; 5306 5307 chip->badblockbits = 8; 5308 5309 nand_legacy_adjust_cmdfunc(chip); 5310 5311 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 5312 maf_id, dev_id); 5313 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc), 5314 chip->parameters.model); 5315 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", 5316 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 5317 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); 5318 return 0; 5319 5320 free_detect_allocation: 5321 kfree(chip->parameters.model); 5322 5323 return ret; 5324 } 5325 5326 static enum nand_ecc_engine_type 5327 of_get_rawnand_ecc_engine_type_legacy(struct device_node *np) 5328 { 5329 enum nand_ecc_legacy_mode { 5330 NAND_ECC_INVALID, 5331 NAND_ECC_NONE, 5332 NAND_ECC_SOFT, 5333 NAND_ECC_SOFT_BCH, 5334 NAND_ECC_HW, 5335 NAND_ECC_HW_SYNDROME, 5336 NAND_ECC_ON_DIE, 5337 }; 5338 const char * const nand_ecc_legacy_modes[] = { 5339 [NAND_ECC_NONE] = "none", 5340 [NAND_ECC_SOFT] = "soft", 5341 [NAND_ECC_SOFT_BCH] = "soft_bch", 5342 [NAND_ECC_HW] = "hw", 5343 [NAND_ECC_HW_SYNDROME] = "hw_syndrome", 5344 [NAND_ECC_ON_DIE] = "on-die", 5345 }; 5346 enum nand_ecc_legacy_mode eng_type; 5347 const char *pm; 5348 int err; 5349 5350 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5351 if (err) 5352 return NAND_ECC_ENGINE_TYPE_INVALID; 5353 5354 for (eng_type = NAND_ECC_NONE; 5355 eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) { 5356 if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) { 5357 switch (eng_type) { 5358 case NAND_ECC_NONE: 5359 return NAND_ECC_ENGINE_TYPE_NONE; 5360 case NAND_ECC_SOFT: 5361 case NAND_ECC_SOFT_BCH: 5362 return NAND_ECC_ENGINE_TYPE_SOFT; 5363 case NAND_ECC_HW: 5364 case NAND_ECC_HW_SYNDROME: 5365 return NAND_ECC_ENGINE_TYPE_ON_HOST; 5366 case NAND_ECC_ON_DIE: 5367 return NAND_ECC_ENGINE_TYPE_ON_DIE; 5368 default: 5369 break; 5370 } 5371 } 5372 } 5373 5374 return NAND_ECC_ENGINE_TYPE_INVALID; 5375 } 5376 5377 static enum nand_ecc_placement 5378 of_get_rawnand_ecc_placement_legacy(struct device_node *np) 5379 { 5380 const char *pm; 5381 int err; 5382 5383 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5384 if (!err) { 5385 if (!strcasecmp(pm, "hw_syndrome")) 5386 return NAND_ECC_PLACEMENT_INTERLEAVED; 5387 } 5388 5389 return NAND_ECC_PLACEMENT_UNKNOWN; 5390 } 5391 5392 static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np) 5393 { 5394 const char *pm; 5395 int err; 5396 5397 err = of_property_read_string(np, "nand-ecc-mode", &pm); 5398 if (!err) { 5399 if (!strcasecmp(pm, "soft")) 5400 return NAND_ECC_ALGO_HAMMING; 5401 else if (!strcasecmp(pm, "soft_bch")) 5402 return NAND_ECC_ALGO_BCH; 5403 } 5404 5405 return NAND_ECC_ALGO_UNKNOWN; 5406 } 5407 5408 static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip) 5409 { 5410 struct device_node *dn = nand_get_flash_node(chip); 5411 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; 5412 5413 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5414 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn); 5415 5416 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN) 5417 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn); 5418 5419 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN) 5420 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn); 5421 } 5422 5423 static int of_get_nand_bus_width(struct nand_chip *chip) 5424 { 5425 struct device_node *dn = nand_get_flash_node(chip); 5426 u32 val; 5427 int ret; 5428 5429 ret = of_property_read_u32(dn, "nand-bus-width", &val); 5430 if (ret == -EINVAL) 5431 /* Buswidth defaults to 8 if the property does not exist .*/ 5432 return 0; 5433 else if (ret) 5434 return ret; 5435 5436 if (val == 16) 5437 chip->options |= NAND_BUSWIDTH_16; 5438 else if (val != 8) 5439 return -EINVAL; 5440 return 0; 5441 } 5442 5443 static int of_get_nand_secure_regions(struct nand_chip *chip) 5444 { 5445 struct device_node *dn = nand_get_flash_node(chip); 5446 struct property *prop; 5447 int nr_elem, i, j; 5448 5449 /* Only proceed if the "secure-regions" property is present in DT */ 5450 prop = of_find_property(dn, "secure-regions", NULL); 5451 if (!prop) 5452 return 0; 5453 5454 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64)); 5455 if (nr_elem <= 0) 5456 return nr_elem; 5457 5458 chip->nr_secure_regions = nr_elem / 2; 5459 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions), 5460 GFP_KERNEL); 5461 if (!chip->secure_regions) 5462 return -ENOMEM; 5463 5464 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) { 5465 of_property_read_u64_index(dn, "secure-regions", j, 5466 &chip->secure_regions[i].offset); 5467 of_property_read_u64_index(dn, "secure-regions", j + 1, 5468 &chip->secure_regions[i].size); 5469 } 5470 5471 return 0; 5472 } 5473 5474 /** 5475 * rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller 5476 * @dev: Device that will be parsed. Also used for managed allocations. 5477 * @cs_array: Array of GPIO desc pointers allocated on success 5478 * @ncs_array: Number of entries in @cs_array updated on success. 5479 * @return 0 on success, an error otherwise. 5480 */ 5481 int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array, 5482 unsigned int *ncs_array) 5483 { 5484 struct gpio_desc **descs; 5485 int ndescs, i; 5486 5487 ndescs = gpiod_count(dev, "cs"); 5488 if (ndescs < 0) { 5489 dev_dbg(dev, "No valid cs-gpios property\n"); 5490 return 0; 5491 } 5492 5493 descs = devm_kcalloc(dev, ndescs, sizeof(*descs), GFP_KERNEL); 5494 if (!descs) 5495 return -ENOMEM; 5496 5497 for (i = 0; i < ndescs; i++) { 5498 descs[i] = gpiod_get_index_optional(dev, "cs", i, 5499 GPIOD_OUT_HIGH); 5500 if (IS_ERR(descs[i])) 5501 return PTR_ERR(descs[i]); 5502 } 5503 5504 *ncs_array = ndescs; 5505 *cs_array = descs; 5506 5507 return 0; 5508 } 5509 EXPORT_SYMBOL(rawnand_dt_parse_gpio_cs); 5510 5511 static int rawnand_dt_init(struct nand_chip *chip) 5512 { 5513 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); 5514 struct device_node *dn = nand_get_flash_node(chip); 5515 int ret; 5516 5517 if (!dn) 5518 return 0; 5519 5520 ret = of_get_nand_bus_width(chip); 5521 if (ret) 5522 return ret; 5523 5524 if (of_property_read_bool(dn, "nand-is-boot-medium")) 5525 chip->options |= NAND_IS_BOOT_MEDIUM; 5526 5527 if (of_property_read_bool(dn, "nand-on-flash-bbt")) 5528 chip->bbt_options |= NAND_BBT_USE_FLASH; 5529 5530 of_get_nand_ecc_user_config(nand); 5531 of_get_nand_ecc_legacy_user_config(chip); 5532 5533 /* 5534 * If neither the user nor the NAND controller have requested a specific 5535 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. 5536 */ 5537 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 5538 5539 /* 5540 * Use the user requested engine type, unless there is none, in this 5541 * case default to the NAND controller choice, otherwise fallback to 5542 * the raw NAND default one. 5543 */ 5544 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) 5545 chip->ecc.engine_type = nand->ecc.user_conf.engine_type; 5546 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5547 chip->ecc.engine_type = nand->ecc.defaults.engine_type; 5548 5549 chip->ecc.placement = nand->ecc.user_conf.placement; 5550 chip->ecc.algo = nand->ecc.user_conf.algo; 5551 chip->ecc.strength = nand->ecc.user_conf.strength; 5552 chip->ecc.size = nand->ecc.user_conf.step_size; 5553 5554 return 0; 5555 } 5556 5557 /** 5558 * nand_scan_ident - Scan for the NAND device 5559 * @chip: NAND chip object 5560 * @maxchips: number of chips to scan for 5561 * @table: alternative NAND ID table 5562 * 5563 * This is the first phase of the normal nand_scan() function. It reads the 5564 * flash ID and sets up MTD fields accordingly. 5565 * 5566 * This helper used to be called directly from controller drivers that needed 5567 * to tweak some ECC-related parameters before nand_scan_tail(). This separation 5568 * prevented dynamic allocations during this phase which was unconvenient and 5569 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks. 5570 */ 5571 static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, 5572 struct nand_flash_dev *table) 5573 { 5574 struct mtd_info *mtd = nand_to_mtd(chip); 5575 struct nand_memory_organization *memorg; 5576 int nand_maf_id, nand_dev_id; 5577 unsigned int i; 5578 int ret; 5579 5580 memorg = nanddev_get_memorg(&chip->base); 5581 5582 /* Assume all dies are deselected when we enter nand_scan_ident(). */ 5583 chip->cur_cs = -1; 5584 5585 mutex_init(&chip->lock); 5586 init_waitqueue_head(&chip->resume_wq); 5587 5588 /* Enforce the right timings for reset/detection */ 5589 chip->current_interface_config = nand_get_reset_interface_config(); 5590 5591 ret = rawnand_dt_init(chip); 5592 if (ret) 5593 return ret; 5594 5595 if (!mtd->name && mtd->dev.parent) 5596 mtd->name = dev_name(mtd->dev.parent); 5597 5598 /* Set the default functions */ 5599 nand_set_defaults(chip); 5600 5601 ret = nand_legacy_check_hooks(chip); 5602 if (ret) 5603 return ret; 5604 5605 memorg->ntargets = maxchips; 5606 5607 /* Read the flash type */ 5608 ret = nand_detect(chip, table); 5609 if (ret) { 5610 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 5611 pr_warn("No NAND device found\n"); 5612 nand_deselect_target(chip); 5613 return ret; 5614 } 5615 5616 nand_maf_id = chip->id.data[0]; 5617 nand_dev_id = chip->id.data[1]; 5618 5619 nand_deselect_target(chip); 5620 5621 /* Check for a chip array */ 5622 for (i = 1; i < maxchips; i++) { 5623 u8 id[2]; 5624 5625 /* See comment in nand_get_flash_type for reset */ 5626 ret = nand_reset(chip, i); 5627 if (ret) 5628 break; 5629 5630 nand_select_target(chip, i); 5631 /* Send the command for reading device ID */ 5632 ret = nand_readid_op(chip, 0, id, sizeof(id)); 5633 if (ret) 5634 break; 5635 /* Read manufacturer and device IDs */ 5636 if (nand_maf_id != id[0] || nand_dev_id != id[1]) { 5637 nand_deselect_target(chip); 5638 break; 5639 } 5640 nand_deselect_target(chip); 5641 } 5642 if (i > 1) 5643 pr_info("%d chips detected\n", i); 5644 5645 /* Store the number of chips and calc total size for mtd */ 5646 memorg->ntargets = i; 5647 mtd->size = i * nanddev_target_size(&chip->base); 5648 5649 return 0; 5650 } 5651 5652 static void nand_scan_ident_cleanup(struct nand_chip *chip) 5653 { 5654 kfree(chip->parameters.model); 5655 kfree(chip->parameters.onfi); 5656 } 5657 5658 int rawnand_sw_hamming_init(struct nand_chip *chip) 5659 { 5660 struct nand_ecc_sw_hamming_conf *engine_conf; 5661 struct nand_device *base = &chip->base; 5662 int ret; 5663 5664 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 5665 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING; 5666 base->ecc.user_conf.strength = chip->ecc.strength; 5667 base->ecc.user_conf.step_size = chip->ecc.size; 5668 5669 ret = nand_ecc_sw_hamming_init_ctx(base); 5670 if (ret) 5671 return ret; 5672 5673 engine_conf = base->ecc.ctx.priv; 5674 5675 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER) 5676 engine_conf->sm_order = true; 5677 5678 chip->ecc.size = base->ecc.ctx.conf.step_size; 5679 chip->ecc.strength = base->ecc.ctx.conf.strength; 5680 chip->ecc.total = base->ecc.ctx.total; 5681 chip->ecc.steps = nanddev_get_ecc_nsteps(base); 5682 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); 5683 5684 return 0; 5685 } 5686 EXPORT_SYMBOL(rawnand_sw_hamming_init); 5687 5688 int rawnand_sw_hamming_calculate(struct nand_chip *chip, 5689 const unsigned char *buf, 5690 unsigned char *code) 5691 { 5692 struct nand_device *base = &chip->base; 5693 5694 return nand_ecc_sw_hamming_calculate(base, buf, code); 5695 } 5696 EXPORT_SYMBOL(rawnand_sw_hamming_calculate); 5697 5698 int rawnand_sw_hamming_correct(struct nand_chip *chip, 5699 unsigned char *buf, 5700 unsigned char *read_ecc, 5701 unsigned char *calc_ecc) 5702 { 5703 struct nand_device *base = &chip->base; 5704 5705 return nand_ecc_sw_hamming_correct(base, buf, read_ecc, calc_ecc); 5706 } 5707 EXPORT_SYMBOL(rawnand_sw_hamming_correct); 5708 5709 void rawnand_sw_hamming_cleanup(struct nand_chip *chip) 5710 { 5711 struct nand_device *base = &chip->base; 5712 5713 nand_ecc_sw_hamming_cleanup_ctx(base); 5714 } 5715 EXPORT_SYMBOL(rawnand_sw_hamming_cleanup); 5716 5717 int rawnand_sw_bch_init(struct nand_chip *chip) 5718 { 5719 struct nand_device *base = &chip->base; 5720 const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(base); 5721 int ret; 5722 5723 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 5724 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH; 5725 base->ecc.user_conf.step_size = chip->ecc.size; 5726 base->ecc.user_conf.strength = chip->ecc.strength; 5727 5728 ret = nand_ecc_sw_bch_init_ctx(base); 5729 if (ret) 5730 return ret; 5731 5732 chip->ecc.size = ecc_conf->step_size; 5733 chip->ecc.strength = ecc_conf->strength; 5734 chip->ecc.total = base->ecc.ctx.total; 5735 chip->ecc.steps = nanddev_get_ecc_nsteps(base); 5736 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); 5737 5738 return 0; 5739 } 5740 EXPORT_SYMBOL(rawnand_sw_bch_init); 5741 5742 static int rawnand_sw_bch_calculate(struct nand_chip *chip, 5743 const unsigned char *buf, 5744 unsigned char *code) 5745 { 5746 struct nand_device *base = &chip->base; 5747 5748 return nand_ecc_sw_bch_calculate(base, buf, code); 5749 } 5750 5751 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf, 5752 unsigned char *read_ecc, unsigned char *calc_ecc) 5753 { 5754 struct nand_device *base = &chip->base; 5755 5756 return nand_ecc_sw_bch_correct(base, buf, read_ecc, calc_ecc); 5757 } 5758 EXPORT_SYMBOL(rawnand_sw_bch_correct); 5759 5760 void rawnand_sw_bch_cleanup(struct nand_chip *chip) 5761 { 5762 struct nand_device *base = &chip->base; 5763 5764 nand_ecc_sw_bch_cleanup_ctx(base); 5765 } 5766 EXPORT_SYMBOL(rawnand_sw_bch_cleanup); 5767 5768 static int nand_set_ecc_on_host_ops(struct nand_chip *chip) 5769 { 5770 struct nand_ecc_ctrl *ecc = &chip->ecc; 5771 5772 switch (ecc->placement) { 5773 case NAND_ECC_PLACEMENT_UNKNOWN: 5774 case NAND_ECC_PLACEMENT_OOB: 5775 /* Use standard hwecc read page function? */ 5776 if (!ecc->read_page) 5777 ecc->read_page = nand_read_page_hwecc; 5778 if (!ecc->write_page) 5779 ecc->write_page = nand_write_page_hwecc; 5780 if (!ecc->read_page_raw) 5781 ecc->read_page_raw = nand_read_page_raw; 5782 if (!ecc->write_page_raw) 5783 ecc->write_page_raw = nand_write_page_raw; 5784 if (!ecc->read_oob) 5785 ecc->read_oob = nand_read_oob_std; 5786 if (!ecc->write_oob) 5787 ecc->write_oob = nand_write_oob_std; 5788 if (!ecc->read_subpage) 5789 ecc->read_subpage = nand_read_subpage; 5790 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5791 ecc->write_subpage = nand_write_subpage_hwecc; 5792 fallthrough; 5793 5794 case NAND_ECC_PLACEMENT_INTERLEAVED: 5795 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5796 (!ecc->read_page || 5797 ecc->read_page == nand_read_page_hwecc || 5798 !ecc->write_page || 5799 ecc->write_page == nand_write_page_hwecc)) { 5800 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5801 return -EINVAL; 5802 } 5803 /* Use standard syndrome read/write page function? */ 5804 if (!ecc->read_page) 5805 ecc->read_page = nand_read_page_syndrome; 5806 if (!ecc->write_page) 5807 ecc->write_page = nand_write_page_syndrome; 5808 if (!ecc->read_page_raw) 5809 ecc->read_page_raw = nand_read_page_raw_syndrome; 5810 if (!ecc->write_page_raw) 5811 ecc->write_page_raw = nand_write_page_raw_syndrome; 5812 if (!ecc->read_oob) 5813 ecc->read_oob = nand_read_oob_syndrome; 5814 if (!ecc->write_oob) 5815 ecc->write_oob = nand_write_oob_syndrome; 5816 break; 5817 5818 default: 5819 pr_warn("Invalid NAND_ECC_PLACEMENT %d\n", 5820 ecc->placement); 5821 return -EINVAL; 5822 } 5823 5824 return 0; 5825 } 5826 5827 static int nand_set_ecc_soft_ops(struct nand_chip *chip) 5828 { 5829 struct mtd_info *mtd = nand_to_mtd(chip); 5830 struct nand_device *nanddev = mtd_to_nanddev(mtd); 5831 struct nand_ecc_ctrl *ecc = &chip->ecc; 5832 int ret; 5833 5834 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) 5835 return -EINVAL; 5836 5837 switch (ecc->algo) { 5838 case NAND_ECC_ALGO_HAMMING: 5839 ecc->calculate = rawnand_sw_hamming_calculate; 5840 ecc->correct = rawnand_sw_hamming_correct; 5841 ecc->read_page = nand_read_page_swecc; 5842 ecc->read_subpage = nand_read_subpage; 5843 ecc->write_page = nand_write_page_swecc; 5844 if (!ecc->read_page_raw) 5845 ecc->read_page_raw = nand_read_page_raw; 5846 if (!ecc->write_page_raw) 5847 ecc->write_page_raw = nand_write_page_raw; 5848 ecc->read_oob = nand_read_oob_std; 5849 ecc->write_oob = nand_write_oob_std; 5850 if (!ecc->size) 5851 ecc->size = 256; 5852 ecc->bytes = 3; 5853 ecc->strength = 1; 5854 5855 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)) 5856 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 5857 5858 ret = rawnand_sw_hamming_init(chip); 5859 if (ret) { 5860 WARN(1, "Hamming ECC initialization failed!\n"); 5861 return ret; 5862 } 5863 5864 return 0; 5865 case NAND_ECC_ALGO_BCH: 5866 if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) { 5867 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n"); 5868 return -EINVAL; 5869 } 5870 ecc->calculate = rawnand_sw_bch_calculate; 5871 ecc->correct = rawnand_sw_bch_correct; 5872 ecc->read_page = nand_read_page_swecc; 5873 ecc->read_subpage = nand_read_subpage; 5874 ecc->write_page = nand_write_page_swecc; 5875 if (!ecc->read_page_raw) 5876 ecc->read_page_raw = nand_read_page_raw; 5877 if (!ecc->write_page_raw) 5878 ecc->write_page_raw = nand_write_page_raw; 5879 ecc->read_oob = nand_read_oob_std; 5880 ecc->write_oob = nand_write_oob_std; 5881 5882 /* 5883 * We can only maximize ECC config when the default layout is 5884 * used, otherwise we don't know how many bytes can really be 5885 * used. 5886 */ 5887 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH && 5888 mtd->ooblayout != nand_get_large_page_ooblayout()) 5889 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH; 5890 5891 ret = rawnand_sw_bch_init(chip); 5892 if (ret) { 5893 WARN(1, "BCH ECC initialization failed!\n"); 5894 return ret; 5895 } 5896 5897 return 0; 5898 default: 5899 WARN(1, "Unsupported ECC algorithm!\n"); 5900 return -EINVAL; 5901 } 5902 } 5903 5904 /** 5905 * nand_check_ecc_caps - check the sanity of preset ECC settings 5906 * @chip: nand chip info structure 5907 * @caps: ECC caps info structure 5908 * @oobavail: OOB size that the ECC engine can use 5909 * 5910 * When ECC step size and strength are already set, check if they are supported 5911 * by the controller and the calculated ECC bytes fit within the chip's OOB. 5912 * On success, the calculated ECC bytes is set. 5913 */ 5914 static int 5915 nand_check_ecc_caps(struct nand_chip *chip, 5916 const struct nand_ecc_caps *caps, int oobavail) 5917 { 5918 struct mtd_info *mtd = nand_to_mtd(chip); 5919 const struct nand_ecc_step_info *stepinfo; 5920 int preset_step = chip->ecc.size; 5921 int preset_strength = chip->ecc.strength; 5922 int ecc_bytes, nsteps = mtd->writesize / preset_step; 5923 int i, j; 5924 5925 for (i = 0; i < caps->nstepinfos; i++) { 5926 stepinfo = &caps->stepinfos[i]; 5927 5928 if (stepinfo->stepsize != preset_step) 5929 continue; 5930 5931 for (j = 0; j < stepinfo->nstrengths; j++) { 5932 if (stepinfo->strengths[j] != preset_strength) 5933 continue; 5934 5935 ecc_bytes = caps->calc_ecc_bytes(preset_step, 5936 preset_strength); 5937 if (WARN_ON_ONCE(ecc_bytes < 0)) 5938 return ecc_bytes; 5939 5940 if (ecc_bytes * nsteps > oobavail) { 5941 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", 5942 preset_step, preset_strength); 5943 return -ENOSPC; 5944 } 5945 5946 chip->ecc.bytes = ecc_bytes; 5947 5948 return 0; 5949 } 5950 } 5951 5952 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", 5953 preset_step, preset_strength); 5954 5955 return -ENOTSUPP; 5956 } 5957 5958 /** 5959 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes 5960 * @chip: nand chip info structure 5961 * @caps: ECC engine caps info structure 5962 * @oobavail: OOB size that the ECC engine can use 5963 * 5964 * If a chip's ECC requirement is provided, try to meet it with the least 5965 * number of ECC bytes (i.e. with the largest number of OOB-free bytes). 5966 * On success, the chosen ECC settings are set. 5967 */ 5968 static int 5969 nand_match_ecc_req(struct nand_chip *chip, 5970 const struct nand_ecc_caps *caps, int oobavail) 5971 { 5972 const struct nand_ecc_props *requirements = 5973 nanddev_get_ecc_requirements(&chip->base); 5974 struct mtd_info *mtd = nand_to_mtd(chip); 5975 const struct nand_ecc_step_info *stepinfo; 5976 int req_step = requirements->step_size; 5977 int req_strength = requirements->strength; 5978 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 5979 int best_step = 0, best_strength = 0, best_ecc_bytes = 0; 5980 int best_ecc_bytes_total = INT_MAX; 5981 int i, j; 5982 5983 /* No information provided by the NAND chip */ 5984 if (!req_step || !req_strength) 5985 return -ENOTSUPP; 5986 5987 /* number of correctable bits the chip requires in a page */ 5988 req_corr = mtd->writesize / req_step * req_strength; 5989 5990 for (i = 0; i < caps->nstepinfos; i++) { 5991 stepinfo = &caps->stepinfos[i]; 5992 step_size = stepinfo->stepsize; 5993 5994 for (j = 0; j < stepinfo->nstrengths; j++) { 5995 strength = stepinfo->strengths[j]; 5996 5997 /* 5998 * If both step size and strength are smaller than the 5999 * chip's requirement, it is not easy to compare the 6000 * resulted reliability. 6001 */ 6002 if (step_size < req_step && strength < req_strength) 6003 continue; 6004 6005 if (mtd->writesize % step_size) 6006 continue; 6007 6008 nsteps = mtd->writesize / step_size; 6009 6010 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 6011 if (WARN_ON_ONCE(ecc_bytes < 0)) 6012 continue; 6013 ecc_bytes_total = ecc_bytes * nsteps; 6014 6015 if (ecc_bytes_total > oobavail || 6016 strength * nsteps < req_corr) 6017 continue; 6018 6019 /* 6020 * We assume the best is to meet the chip's requrement 6021 * with the least number of ECC bytes. 6022 */ 6023 if (ecc_bytes_total < best_ecc_bytes_total) { 6024 best_ecc_bytes_total = ecc_bytes_total; 6025 best_step = step_size; 6026 best_strength = strength; 6027 best_ecc_bytes = ecc_bytes; 6028 } 6029 } 6030 } 6031 6032 if (best_ecc_bytes_total == INT_MAX) 6033 return -ENOTSUPP; 6034 6035 chip->ecc.size = best_step; 6036 chip->ecc.strength = best_strength; 6037 chip->ecc.bytes = best_ecc_bytes; 6038 6039 return 0; 6040 } 6041 6042 /** 6043 * nand_maximize_ecc - choose the max ECC strength available 6044 * @chip: nand chip info structure 6045 * @caps: ECC engine caps info structure 6046 * @oobavail: OOB size that the ECC engine can use 6047 * 6048 * Choose the max ECC strength that is supported on the controller, and can fit 6049 * within the chip's OOB. On success, the chosen ECC settings are set. 6050 */ 6051 static int 6052 nand_maximize_ecc(struct nand_chip *chip, 6053 const struct nand_ecc_caps *caps, int oobavail) 6054 { 6055 struct mtd_info *mtd = nand_to_mtd(chip); 6056 const struct nand_ecc_step_info *stepinfo; 6057 int step_size, strength, nsteps, ecc_bytes, corr; 6058 int best_corr = 0; 6059 int best_step = 0; 6060 int best_strength = 0, best_ecc_bytes = 0; 6061 int i, j; 6062 6063 for (i = 0; i < caps->nstepinfos; i++) { 6064 stepinfo = &caps->stepinfos[i]; 6065 step_size = stepinfo->stepsize; 6066 6067 /* If chip->ecc.size is already set, respect it */ 6068 if (chip->ecc.size && step_size != chip->ecc.size) 6069 continue; 6070 6071 for (j = 0; j < stepinfo->nstrengths; j++) { 6072 strength = stepinfo->strengths[j]; 6073 6074 if (mtd->writesize % step_size) 6075 continue; 6076 6077 nsteps = mtd->writesize / step_size; 6078 6079 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 6080 if (WARN_ON_ONCE(ecc_bytes < 0)) 6081 continue; 6082 6083 if (ecc_bytes * nsteps > oobavail) 6084 continue; 6085 6086 corr = strength * nsteps; 6087 6088 /* 6089 * If the number of correctable bits is the same, 6090 * bigger step_size has more reliability. 6091 */ 6092 if (corr > best_corr || 6093 (corr == best_corr && step_size > best_step)) { 6094 best_corr = corr; 6095 best_step = step_size; 6096 best_strength = strength; 6097 best_ecc_bytes = ecc_bytes; 6098 } 6099 } 6100 } 6101 6102 if (!best_corr) 6103 return -ENOTSUPP; 6104 6105 chip->ecc.size = best_step; 6106 chip->ecc.strength = best_strength; 6107 chip->ecc.bytes = best_ecc_bytes; 6108 6109 return 0; 6110 } 6111 6112 /** 6113 * nand_ecc_choose_conf - Set the ECC strength and ECC step size 6114 * @chip: nand chip info structure 6115 * @caps: ECC engine caps info structure 6116 * @oobavail: OOB size that the ECC engine can use 6117 * 6118 * Choose the ECC configuration according to following logic. 6119 * 6120 * 1. If both ECC step size and ECC strength are already set (usually by DT) 6121 * then check if it is supported by this controller. 6122 * 2. If the user provided the nand-ecc-maximize property, then select maximum 6123 * ECC strength. 6124 * 3. Otherwise, try to match the ECC step size and ECC strength closest 6125 * to the chip's requirement. If available OOB size can't fit the chip 6126 * requirement then fallback to the maximum ECC step size and ECC strength. 6127 * 6128 * On success, the chosen ECC settings are set. 6129 */ 6130 int nand_ecc_choose_conf(struct nand_chip *chip, 6131 const struct nand_ecc_caps *caps, int oobavail) 6132 { 6133 struct mtd_info *mtd = nand_to_mtd(chip); 6134 struct nand_device *nanddev = mtd_to_nanddev(mtd); 6135 6136 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) 6137 return -EINVAL; 6138 6139 if (chip->ecc.size && chip->ecc.strength) 6140 return nand_check_ecc_caps(chip, caps, oobavail); 6141 6142 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) 6143 return nand_maximize_ecc(chip, caps, oobavail); 6144 6145 if (!nand_match_ecc_req(chip, caps, oobavail)) 6146 return 0; 6147 6148 return nand_maximize_ecc(chip, caps, oobavail); 6149 } 6150 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf); 6151 6152 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) 6153 { 6154 struct nand_chip *chip = container_of(nand, struct nand_chip, 6155 base); 6156 unsigned int eb = nanddev_pos_to_row(nand, pos); 6157 int ret; 6158 6159 eb >>= nand->rowconv.eraseblock_addr_shift; 6160 6161 nand_select_target(chip, pos->target); 6162 ret = nand_erase_op(chip, eb); 6163 nand_deselect_target(chip); 6164 6165 return ret; 6166 } 6167 6168 static int rawnand_markbad(struct nand_device *nand, 6169 const struct nand_pos *pos) 6170 { 6171 struct nand_chip *chip = container_of(nand, struct nand_chip, 6172 base); 6173 6174 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 6175 } 6176 6177 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos) 6178 { 6179 struct nand_chip *chip = container_of(nand, struct nand_chip, 6180 base); 6181 int ret; 6182 6183 nand_select_target(chip, pos->target); 6184 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 6185 nand_deselect_target(chip); 6186 6187 return ret; 6188 } 6189 6190 static const struct nand_ops rawnand_ops = { 6191 .erase = rawnand_erase, 6192 .markbad = rawnand_markbad, 6193 .isbad = rawnand_isbad, 6194 }; 6195 6196 /** 6197 * nand_scan_tail - Scan for the NAND device 6198 * @chip: NAND chip object 6199 * 6200 * This is the second phase of the normal nand_scan() function. It fills out 6201 * all the uninitialized function pointers with the defaults and scans for a 6202 * bad block table if appropriate. 6203 */ 6204 static int nand_scan_tail(struct nand_chip *chip) 6205 { 6206 struct mtd_info *mtd = nand_to_mtd(chip); 6207 struct nand_ecc_ctrl *ecc = &chip->ecc; 6208 int ret, i; 6209 6210 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 6211 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 6212 !(chip->bbt_options & NAND_BBT_USE_FLASH))) { 6213 return -EINVAL; 6214 } 6215 6216 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 6217 if (!chip->data_buf) 6218 return -ENOMEM; 6219 6220 /* 6221 * FIXME: some NAND manufacturer drivers expect the first die to be 6222 * selected when manufacturer->init() is called. They should be fixed 6223 * to explictly select the relevant die when interacting with the NAND 6224 * chip. 6225 */ 6226 nand_select_target(chip, 0); 6227 ret = nand_manufacturer_init(chip); 6228 nand_deselect_target(chip); 6229 if (ret) 6230 goto err_free_buf; 6231 6232 /* Set the internal oob buffer location, just after the page data */ 6233 chip->oob_poi = chip->data_buf + mtd->writesize; 6234 6235 /* 6236 * If no default placement scheme is given, select an appropriate one. 6237 */ 6238 if (!mtd->ooblayout && 6239 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 6240 ecc->algo == NAND_ECC_ALGO_BCH) && 6241 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 6242 ecc->algo == NAND_ECC_ALGO_HAMMING)) { 6243 switch (mtd->oobsize) { 6244 case 8: 6245 case 16: 6246 mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout()); 6247 break; 6248 case 64: 6249 case 128: 6250 mtd_set_ooblayout(mtd, 6251 nand_get_large_page_hamming_ooblayout()); 6252 break; 6253 default: 6254 /* 6255 * Expose the whole OOB area to users if ECC_NONE 6256 * is passed. We could do that for all kind of 6257 * ->oobsize, but we must keep the old large/small 6258 * page with ECC layout when ->oobsize <= 128 for 6259 * compatibility reasons. 6260 */ 6261 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { 6262 mtd_set_ooblayout(mtd, 6263 nand_get_large_page_ooblayout()); 6264 break; 6265 } 6266 6267 WARN(1, "No oob scheme defined for oobsize %d\n", 6268 mtd->oobsize); 6269 ret = -EINVAL; 6270 goto err_nand_manuf_cleanup; 6271 } 6272 } 6273 6274 /* 6275 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 6276 * selected and we have 256 byte pagesize fallback to software ECC 6277 */ 6278 6279 switch (ecc->engine_type) { 6280 case NAND_ECC_ENGINE_TYPE_ON_HOST: 6281 ret = nand_set_ecc_on_host_ops(chip); 6282 if (ret) 6283 goto err_nand_manuf_cleanup; 6284 6285 if (mtd->writesize >= ecc->size) { 6286 if (!ecc->strength) { 6287 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); 6288 ret = -EINVAL; 6289 goto err_nand_manuf_cleanup; 6290 } 6291 break; 6292 } 6293 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 6294 ecc->size, mtd->writesize); 6295 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 6296 ecc->algo = NAND_ECC_ALGO_HAMMING; 6297 fallthrough; 6298 6299 case NAND_ECC_ENGINE_TYPE_SOFT: 6300 ret = nand_set_ecc_soft_ops(chip); 6301 if (ret) 6302 goto err_nand_manuf_cleanup; 6303 break; 6304 6305 case NAND_ECC_ENGINE_TYPE_ON_DIE: 6306 if (!ecc->read_page || !ecc->write_page) { 6307 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); 6308 ret = -EINVAL; 6309 goto err_nand_manuf_cleanup; 6310 } 6311 if (!ecc->read_oob) 6312 ecc->read_oob = nand_read_oob_std; 6313 if (!ecc->write_oob) 6314 ecc->write_oob = nand_write_oob_std; 6315 break; 6316 6317 case NAND_ECC_ENGINE_TYPE_NONE: 6318 pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n"); 6319 ecc->read_page = nand_read_page_raw; 6320 ecc->write_page = nand_write_page_raw; 6321 ecc->read_oob = nand_read_oob_std; 6322 ecc->read_page_raw = nand_read_page_raw; 6323 ecc->write_page_raw = nand_write_page_raw; 6324 ecc->write_oob = nand_write_oob_std; 6325 ecc->size = mtd->writesize; 6326 ecc->bytes = 0; 6327 ecc->strength = 0; 6328 break; 6329 6330 default: 6331 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); 6332 ret = -EINVAL; 6333 goto err_nand_manuf_cleanup; 6334 } 6335 6336 if (ecc->correct || ecc->calculate) { 6337 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 6338 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 6339 if (!ecc->calc_buf || !ecc->code_buf) { 6340 ret = -ENOMEM; 6341 goto err_nand_manuf_cleanup; 6342 } 6343 } 6344 6345 /* For many systems, the standard OOB write also works for raw */ 6346 if (!ecc->read_oob_raw) 6347 ecc->read_oob_raw = ecc->read_oob; 6348 if (!ecc->write_oob_raw) 6349 ecc->write_oob_raw = ecc->write_oob; 6350 6351 /* propagate ecc info to mtd_info */ 6352 mtd->ecc_strength = ecc->strength; 6353 mtd->ecc_step_size = ecc->size; 6354 6355 /* 6356 * Set the number of read / write steps for one page depending on ECC 6357 * mode. 6358 */ 6359 if (!ecc->steps) 6360 ecc->steps = mtd->writesize / ecc->size; 6361 if (ecc->steps * ecc->size != mtd->writesize) { 6362 WARN(1, "Invalid ECC parameters\n"); 6363 ret = -EINVAL; 6364 goto err_nand_manuf_cleanup; 6365 } 6366 6367 if (!ecc->total) { 6368 ecc->total = ecc->steps * ecc->bytes; 6369 chip->base.ecc.ctx.total = ecc->total; 6370 } 6371 6372 if (ecc->total > mtd->oobsize) { 6373 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); 6374 ret = -EINVAL; 6375 goto err_nand_manuf_cleanup; 6376 } 6377 6378 /* 6379 * The number of bytes available for a client to place data into 6380 * the out of band area. 6381 */ 6382 ret = mtd_ooblayout_count_freebytes(mtd); 6383 if (ret < 0) 6384 ret = 0; 6385 6386 mtd->oobavail = ret; 6387 6388 /* ECC sanity check: warn if it's too weak */ 6389 if (!nand_ecc_is_strong_enough(&chip->base)) 6390 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n", 6391 mtd->name, chip->ecc.strength, chip->ecc.size, 6392 nanddev_get_ecc_requirements(&chip->base)->strength, 6393 nanddev_get_ecc_requirements(&chip->base)->step_size); 6394 6395 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 6396 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 6397 switch (ecc->steps) { 6398 case 2: 6399 mtd->subpage_sft = 1; 6400 break; 6401 case 4: 6402 case 8: 6403 case 16: 6404 mtd->subpage_sft = 2; 6405 break; 6406 } 6407 } 6408 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 6409 6410 /* Invalidate the pagebuffer reference */ 6411 chip->pagecache.page = -1; 6412 6413 /* Large page NAND with SOFT_ECC should support subpage reads */ 6414 switch (ecc->engine_type) { 6415 case NAND_ECC_ENGINE_TYPE_SOFT: 6416 if (chip->page_shift > 9) 6417 chip->options |= NAND_SUBPAGE_READ; 6418 break; 6419 6420 default: 6421 break; 6422 } 6423 6424 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); 6425 if (ret) 6426 goto err_nand_manuf_cleanup; 6427 6428 /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */ 6429 if (chip->options & NAND_ROM) 6430 mtd->flags = MTD_CAP_ROM; 6431 6432 /* Fill in remaining MTD driver data */ 6433 mtd->_erase = nand_erase; 6434 mtd->_point = NULL; 6435 mtd->_unpoint = NULL; 6436 mtd->_panic_write = panic_nand_write; 6437 mtd->_read_oob = nand_read_oob; 6438 mtd->_write_oob = nand_write_oob; 6439 mtd->_sync = nand_sync; 6440 mtd->_lock = nand_lock; 6441 mtd->_unlock = nand_unlock; 6442 mtd->_suspend = nand_suspend; 6443 mtd->_resume = nand_resume; 6444 mtd->_reboot = nand_shutdown; 6445 mtd->_block_isreserved = nand_block_isreserved; 6446 mtd->_block_isbad = nand_block_isbad; 6447 mtd->_block_markbad = nand_block_markbad; 6448 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; 6449 6450 /* 6451 * Initialize bitflip_threshold to its default prior scan_bbt() call. 6452 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 6453 * properly set. 6454 */ 6455 if (!mtd->bitflip_threshold) 6456 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); 6457 6458 /* Find the fastest data interface for this chip */ 6459 ret = nand_choose_interface_config(chip); 6460 if (ret) 6461 goto err_nanddev_cleanup; 6462 6463 /* Enter fastest possible mode on all dies. */ 6464 for (i = 0; i < nanddev_ntargets(&chip->base); i++) { 6465 ret = nand_setup_interface(chip, i); 6466 if (ret) 6467 goto err_free_interface_config; 6468 } 6469 6470 rawnand_late_check_supported_ops(chip); 6471 6472 /* 6473 * Look for secure regions in the NAND chip. These regions are supposed 6474 * to be protected by a secure element like Trustzone. So the read/write 6475 * accesses to these regions will be blocked in the runtime by this 6476 * driver. 6477 */ 6478 ret = of_get_nand_secure_regions(chip); 6479 if (ret) 6480 goto err_free_interface_config; 6481 6482 /* Check, if we should skip the bad block table scan */ 6483 if (chip->options & NAND_SKIP_BBTSCAN) 6484 return 0; 6485 6486 /* Build bad block table */ 6487 ret = nand_create_bbt(chip); 6488 if (ret) 6489 goto err_free_secure_regions; 6490 6491 return 0; 6492 6493 err_free_secure_regions: 6494 kfree(chip->secure_regions); 6495 6496 err_free_interface_config: 6497 kfree(chip->best_interface_config); 6498 6499 err_nanddev_cleanup: 6500 nanddev_cleanup(&chip->base); 6501 6502 err_nand_manuf_cleanup: 6503 nand_manufacturer_cleanup(chip); 6504 6505 err_free_buf: 6506 kfree(chip->data_buf); 6507 kfree(ecc->code_buf); 6508 kfree(ecc->calc_buf); 6509 6510 return ret; 6511 } 6512 6513 static int nand_attach(struct nand_chip *chip) 6514 { 6515 if (chip->controller->ops && chip->controller->ops->attach_chip) 6516 return chip->controller->ops->attach_chip(chip); 6517 6518 return 0; 6519 } 6520 6521 static void nand_detach(struct nand_chip *chip) 6522 { 6523 if (chip->controller->ops && chip->controller->ops->detach_chip) 6524 chip->controller->ops->detach_chip(chip); 6525 } 6526 6527 /** 6528 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device 6529 * @chip: NAND chip object 6530 * @maxchips: number of chips to scan for. 6531 * @ids: optional flash IDs table 6532 * 6533 * This fills out all the uninitialized function pointers with the defaults. 6534 * The flash ID is read and the mtd/chip structures are filled with the 6535 * appropriate values. 6536 */ 6537 int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips, 6538 struct nand_flash_dev *ids) 6539 { 6540 int ret; 6541 6542 if (!maxchips) 6543 return -EINVAL; 6544 6545 ret = nand_scan_ident(chip, maxchips, ids); 6546 if (ret) 6547 return ret; 6548 6549 ret = nand_attach(chip); 6550 if (ret) 6551 goto cleanup_ident; 6552 6553 ret = nand_scan_tail(chip); 6554 if (ret) 6555 goto detach_chip; 6556 6557 return 0; 6558 6559 detach_chip: 6560 nand_detach(chip); 6561 cleanup_ident: 6562 nand_scan_ident_cleanup(chip); 6563 6564 return ret; 6565 } 6566 EXPORT_SYMBOL(nand_scan_with_ids); 6567 6568 /** 6569 * nand_cleanup - [NAND Interface] Free resources held by the NAND device 6570 * @chip: NAND chip object 6571 */ 6572 void nand_cleanup(struct nand_chip *chip) 6573 { 6574 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) { 6575 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 6576 rawnand_sw_hamming_cleanup(chip); 6577 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 6578 rawnand_sw_bch_cleanup(chip); 6579 } 6580 6581 nanddev_cleanup(&chip->base); 6582 6583 /* Free secure regions data */ 6584 kfree(chip->secure_regions); 6585 6586 /* Free bad block table memory */ 6587 kfree(chip->bbt); 6588 kfree(chip->data_buf); 6589 kfree(chip->ecc.code_buf); 6590 kfree(chip->ecc.calc_buf); 6591 6592 /* Free bad block descriptor memory */ 6593 if (chip->badblock_pattern && chip->badblock_pattern->options 6594 & NAND_BBT_DYNAMICSTRUCT) 6595 kfree(chip->badblock_pattern); 6596 6597 /* Free the data interface */ 6598 kfree(chip->best_interface_config); 6599 6600 /* Free manufacturer priv data. */ 6601 nand_manufacturer_cleanup(chip); 6602 6603 /* Free controller specific allocations after chip identification */ 6604 nand_detach(chip); 6605 6606 /* Free identification phase allocations */ 6607 nand_scan_ident_cleanup(chip); 6608 } 6609 6610 EXPORT_SYMBOL_GPL(nand_cleanup); 6611 6612 MODULE_LICENSE("GPL"); 6613 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 6614 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 6615 MODULE_DESCRIPTION("Generic NAND flash driver code"); 6616