1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Overview: 4 * This is the generic MTD driver for NAND flash devices. It should be 5 * capable of working with almost all NAND chips currently available. 6 * 7 * Additional technical information is available on 8 * http://www.linux-mtd.infradead.org/doc/nand.html 9 * 10 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 12 * 13 * Credits: 14 * David Woodhouse for adding multichip support 15 * 16 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 17 * rework for 2K page size chips 18 * 19 * TODO: 20 * Enable cached programming for 2k page size chips 21 * Check, if mtd->ecctype should be set to MTD_ECC_HW 22 * if we have HW ECC support. 23 * BBT table is not serialized, has to be fixed 24 */ 25 26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 27 28 #include <linux/module.h> 29 #include <linux/delay.h> 30 #include <linux/errno.h> 31 #include <linux/err.h> 32 #include <linux/sched.h> 33 #include <linux/slab.h> 34 #include <linux/mm.h> 35 #include <linux/types.h> 36 #include <linux/mtd/mtd.h> 37 #include <linux/mtd/nand_ecc.h> 38 #include <linux/mtd/nand_bch.h> 39 #include <linux/interrupt.h> 40 #include <linux/bitops.h> 41 #include <linux/io.h> 42 #include <linux/mtd/partitions.h> 43 #include <linux/of.h> 44 #include <linux/gpio/consumer.h> 45 46 #include "internals.h" 47 48 /* Define default oob placement schemes for large and small page devices */ 49 static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, 50 struct mtd_oob_region *oobregion) 51 { 52 struct nand_chip *chip = mtd_to_nand(mtd); 53 struct nand_ecc_ctrl *ecc = &chip->ecc; 54 55 if (section > 1) 56 return -ERANGE; 57 58 if (!section) { 59 oobregion->offset = 0; 60 if (mtd->oobsize == 16) 61 oobregion->length = 4; 62 else 63 oobregion->length = 3; 64 } else { 65 if (mtd->oobsize == 8) 66 return -ERANGE; 67 68 oobregion->offset = 6; 69 oobregion->length = ecc->total - 4; 70 } 71 72 return 0; 73 } 74 75 static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, 76 struct mtd_oob_region *oobregion) 77 { 78 if (section > 1) 79 return -ERANGE; 80 81 if (mtd->oobsize == 16) { 82 if (section) 83 return -ERANGE; 84 85 oobregion->length = 8; 86 oobregion->offset = 8; 87 } else { 88 oobregion->length = 2; 89 if (!section) 90 oobregion->offset = 3; 91 else 92 oobregion->offset = 6; 93 } 94 95 return 0; 96 } 97 98 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { 99 .ecc = nand_ooblayout_ecc_sp, 100 .free = nand_ooblayout_free_sp, 101 }; 102 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); 103 104 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, 105 struct mtd_oob_region *oobregion) 106 { 107 struct nand_chip *chip = mtd_to_nand(mtd); 108 struct nand_ecc_ctrl *ecc = &chip->ecc; 109 110 if (section || !ecc->total) 111 return -ERANGE; 112 113 oobregion->length = ecc->total; 114 oobregion->offset = mtd->oobsize - oobregion->length; 115 116 return 0; 117 } 118 119 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, 120 struct mtd_oob_region *oobregion) 121 { 122 struct nand_chip *chip = mtd_to_nand(mtd); 123 struct nand_ecc_ctrl *ecc = &chip->ecc; 124 125 if (section) 126 return -ERANGE; 127 128 oobregion->length = mtd->oobsize - ecc->total - 2; 129 oobregion->offset = 2; 130 131 return 0; 132 } 133 134 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { 135 .ecc = nand_ooblayout_ecc_lp, 136 .free = nand_ooblayout_free_lp, 137 }; 138 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); 139 140 /* 141 * Support the old "large page" layout used for 1-bit Hamming ECC where ECC 142 * are placed at a fixed offset. 143 */ 144 static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, 145 struct mtd_oob_region *oobregion) 146 { 147 struct nand_chip *chip = mtd_to_nand(mtd); 148 struct nand_ecc_ctrl *ecc = &chip->ecc; 149 150 if (section) 151 return -ERANGE; 152 153 switch (mtd->oobsize) { 154 case 64: 155 oobregion->offset = 40; 156 break; 157 case 128: 158 oobregion->offset = 80; 159 break; 160 default: 161 return -EINVAL; 162 } 163 164 oobregion->length = ecc->total; 165 if (oobregion->offset + oobregion->length > mtd->oobsize) 166 return -ERANGE; 167 168 return 0; 169 } 170 171 static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, 172 struct mtd_oob_region *oobregion) 173 { 174 struct nand_chip *chip = mtd_to_nand(mtd); 175 struct nand_ecc_ctrl *ecc = &chip->ecc; 176 int ecc_offset = 0; 177 178 if (section < 0 || section > 1) 179 return -ERANGE; 180 181 switch (mtd->oobsize) { 182 case 64: 183 ecc_offset = 40; 184 break; 185 case 128: 186 ecc_offset = 80; 187 break; 188 default: 189 return -EINVAL; 190 } 191 192 if (section == 0) { 193 oobregion->offset = 2; 194 oobregion->length = ecc_offset - 2; 195 } else { 196 oobregion->offset = ecc_offset + ecc->total; 197 oobregion->length = mtd->oobsize - oobregion->offset; 198 } 199 200 return 0; 201 } 202 203 static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { 204 .ecc = nand_ooblayout_ecc_lp_hamming, 205 .free = nand_ooblayout_free_lp_hamming, 206 }; 207 208 static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page, 209 struct mtd_pairing_info *info) 210 { 211 int lastpage = (mtd->erasesize / mtd->writesize) - 1; 212 int dist = 3; 213 214 if (page == lastpage) 215 dist = 2; 216 217 if (!page || (page & 1)) { 218 info->group = 0; 219 info->pair = (page + 1) / 2; 220 } else { 221 info->group = 1; 222 info->pair = (page + 1 - dist) / 2; 223 } 224 225 return 0; 226 } 227 228 static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd, 229 const struct mtd_pairing_info *info) 230 { 231 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2; 232 int page = info->pair * 2; 233 int dist = 3; 234 235 if (!info->group && !info->pair) 236 return 0; 237 238 if (info->pair == lastpair && info->group) 239 dist = 2; 240 241 if (!info->group) 242 page--; 243 else if (info->pair) 244 page += dist - 1; 245 246 if (page >= mtd->erasesize / mtd->writesize) 247 return -EINVAL; 248 249 return page; 250 } 251 252 const struct mtd_pairing_scheme dist3_pairing_scheme = { 253 .ngroups = 2, 254 .get_info = nand_pairing_dist3_get_info, 255 .get_wunit = nand_pairing_dist3_get_wunit, 256 }; 257 258 static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len) 259 { 260 int ret = 0; 261 262 /* Start address must align on block boundary */ 263 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 264 pr_debug("%s: unaligned address\n", __func__); 265 ret = -EINVAL; 266 } 267 268 /* Length must align on block boundary */ 269 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 270 pr_debug("%s: length not block aligned\n", __func__); 271 ret = -EINVAL; 272 } 273 274 return ret; 275 } 276 277 /** 278 * nand_select_target() - Select a NAND target (A.K.A. die) 279 * @chip: NAND chip object 280 * @cs: the CS line to select. Note that this CS id is always from the chip 281 * PoV, not the controller one 282 * 283 * Select a NAND target so that further operations executed on @chip go to the 284 * selected NAND target. 285 */ 286 void nand_select_target(struct nand_chip *chip, unsigned int cs) 287 { 288 /* 289 * cs should always lie between 0 and nanddev_ntargets(), when that's 290 * not the case it's a bug and the caller should be fixed. 291 */ 292 if (WARN_ON(cs > nanddev_ntargets(&chip->base))) 293 return; 294 295 chip->cur_cs = cs; 296 297 if (chip->legacy.select_chip) 298 chip->legacy.select_chip(chip, cs); 299 } 300 EXPORT_SYMBOL_GPL(nand_select_target); 301 302 /** 303 * nand_deselect_target() - Deselect the currently selected target 304 * @chip: NAND chip object 305 * 306 * Deselect the currently selected NAND target. The result of operations 307 * executed on @chip after the target has been deselected is undefined. 308 */ 309 void nand_deselect_target(struct nand_chip *chip) 310 { 311 if (chip->legacy.select_chip) 312 chip->legacy.select_chip(chip, -1); 313 314 chip->cur_cs = -1; 315 } 316 EXPORT_SYMBOL_GPL(nand_deselect_target); 317 318 /** 319 * nand_release_device - [GENERIC] release chip 320 * @chip: NAND chip object 321 * 322 * Release chip lock and wake up anyone waiting on the device. 323 */ 324 static void nand_release_device(struct nand_chip *chip) 325 { 326 /* Release the controller and the chip */ 327 mutex_unlock(&chip->controller->lock); 328 mutex_unlock(&chip->lock); 329 } 330 331 /** 332 * nand_bbm_get_next_page - Get the next page for bad block markers 333 * @chip: NAND chip object 334 * @page: First page to start checking for bad block marker usage 335 * 336 * Returns an integer that corresponds to the page offset within a block, for 337 * a page that is used to store bad block markers. If no more pages are 338 * available, -EINVAL is returned. 339 */ 340 int nand_bbm_get_next_page(struct nand_chip *chip, int page) 341 { 342 struct mtd_info *mtd = nand_to_mtd(chip); 343 int last_page = ((mtd->erasesize - mtd->writesize) >> 344 chip->page_shift) & chip->pagemask; 345 unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE 346 | NAND_BBM_LASTPAGE; 347 348 if (page == 0 && !(chip->options & bbm_flags)) 349 return 0; 350 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE) 351 return 0; 352 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE) 353 return 1; 354 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE) 355 return last_page; 356 357 return -EINVAL; 358 } 359 360 /** 361 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 362 * @chip: NAND chip object 363 * @ofs: offset from device start 364 * 365 * Check, if the block is bad. 366 */ 367 static int nand_block_bad(struct nand_chip *chip, loff_t ofs) 368 { 369 int first_page, page_offset; 370 int res; 371 u8 bad; 372 373 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask; 374 page_offset = nand_bbm_get_next_page(chip, 0); 375 376 while (page_offset >= 0) { 377 res = chip->ecc.read_oob(chip, first_page + page_offset); 378 if (res < 0) 379 return res; 380 381 bad = chip->oob_poi[chip->badblockpos]; 382 383 if (likely(chip->badblockbits == 8)) 384 res = bad != 0xFF; 385 else 386 res = hweight8(bad) < chip->badblockbits; 387 if (res) 388 return res; 389 390 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 391 } 392 393 return 0; 394 } 395 396 static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) 397 { 398 if (chip->legacy.block_bad) 399 return chip->legacy.block_bad(chip, ofs); 400 401 return nand_block_bad(chip, ofs); 402 } 403 404 /** 405 * nand_get_device - [GENERIC] Get chip for selected access 406 * @chip: NAND chip structure 407 * 408 * Lock the device and its controller for exclusive access 409 * 410 * Return: -EBUSY if the chip has been suspended, 0 otherwise 411 */ 412 static int nand_get_device(struct nand_chip *chip) 413 { 414 mutex_lock(&chip->lock); 415 if (chip->suspended) { 416 mutex_unlock(&chip->lock); 417 return -EBUSY; 418 } 419 mutex_lock(&chip->controller->lock); 420 421 return 0; 422 } 423 424 /** 425 * nand_check_wp - [GENERIC] check if the chip is write protected 426 * @chip: NAND chip object 427 * 428 * Check, if the device is write protected. The function expects, that the 429 * device is already selected. 430 */ 431 static int nand_check_wp(struct nand_chip *chip) 432 { 433 u8 status; 434 int ret; 435 436 /* Broken xD cards report WP despite being writable */ 437 if (chip->options & NAND_BROKEN_XD) 438 return 0; 439 440 /* Check the WP bit */ 441 ret = nand_status_op(chip, &status); 442 if (ret) 443 return ret; 444 445 return status & NAND_STATUS_WP ? 0 : 1; 446 } 447 448 /** 449 * nand_fill_oob - [INTERN] Transfer client buffer to oob 450 * @chip: NAND chip object 451 * @oob: oob data buffer 452 * @len: oob data write length 453 * @ops: oob ops structure 454 */ 455 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len, 456 struct mtd_oob_ops *ops) 457 { 458 struct mtd_info *mtd = nand_to_mtd(chip); 459 int ret; 460 461 /* 462 * Initialise to all 0xFF, to avoid the possibility of left over OOB 463 * data from a previous OOB read. 464 */ 465 memset(chip->oob_poi, 0xff, mtd->oobsize); 466 467 switch (ops->mode) { 468 469 case MTD_OPS_PLACE_OOB: 470 case MTD_OPS_RAW: 471 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 472 return oob + len; 473 474 case MTD_OPS_AUTO_OOB: 475 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, 476 ops->ooboffs, len); 477 BUG_ON(ret); 478 return oob + len; 479 480 default: 481 BUG(); 482 } 483 return NULL; 484 } 485 486 /** 487 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 488 * @chip: NAND chip object 489 * @to: offset to write to 490 * @ops: oob operation description structure 491 * 492 * NAND write out-of-band. 493 */ 494 static int nand_do_write_oob(struct nand_chip *chip, loff_t to, 495 struct mtd_oob_ops *ops) 496 { 497 struct mtd_info *mtd = nand_to_mtd(chip); 498 int chipnr, page, status, len, ret; 499 500 pr_debug("%s: to = 0x%08x, len = %i\n", 501 __func__, (unsigned int)to, (int)ops->ooblen); 502 503 len = mtd_oobavail(mtd, ops); 504 505 /* Do not allow write past end of page */ 506 if ((ops->ooboffs + ops->ooblen) > len) { 507 pr_debug("%s: attempt to write past end of page\n", 508 __func__); 509 return -EINVAL; 510 } 511 512 chipnr = (int)(to >> chip->chip_shift); 513 514 /* 515 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 516 * of my DiskOnChip 2000 test units) will clear the whole data page too 517 * if we don't do this. I have no clue why, but I seem to have 'fixed' 518 * it in the doc2000 driver in August 1999. dwmw2. 519 */ 520 ret = nand_reset(chip, chipnr); 521 if (ret) 522 return ret; 523 524 nand_select_target(chip, chipnr); 525 526 /* Shift to get page */ 527 page = (int)(to >> chip->page_shift); 528 529 /* Check, if it is write protected */ 530 if (nand_check_wp(chip)) { 531 nand_deselect_target(chip); 532 return -EROFS; 533 } 534 535 /* Invalidate the page cache, if we write to the cached page */ 536 if (page == chip->pagecache.page) 537 chip->pagecache.page = -1; 538 539 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops); 540 541 if (ops->mode == MTD_OPS_RAW) 542 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); 543 else 544 status = chip->ecc.write_oob(chip, page & chip->pagemask); 545 546 nand_deselect_target(chip); 547 548 if (status) 549 return status; 550 551 ops->oobretlen = ops->ooblen; 552 553 return 0; 554 } 555 556 /** 557 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 558 * @chip: NAND chip object 559 * @ofs: offset from device start 560 * 561 * This is the default implementation, which can be overridden by a hardware 562 * specific driver. It provides the details for writing a bad block marker to a 563 * block. 564 */ 565 static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs) 566 { 567 struct mtd_info *mtd = nand_to_mtd(chip); 568 struct mtd_oob_ops ops; 569 uint8_t buf[2] = { 0, 0 }; 570 int ret = 0, res, page_offset; 571 572 memset(&ops, 0, sizeof(ops)); 573 ops.oobbuf = buf; 574 ops.ooboffs = chip->badblockpos; 575 if (chip->options & NAND_BUSWIDTH_16) { 576 ops.ooboffs &= ~0x01; 577 ops.len = ops.ooblen = 2; 578 } else { 579 ops.len = ops.ooblen = 1; 580 } 581 ops.mode = MTD_OPS_PLACE_OOB; 582 583 page_offset = nand_bbm_get_next_page(chip, 0); 584 585 while (page_offset >= 0) { 586 res = nand_do_write_oob(chip, 587 ofs + (page_offset * mtd->writesize), 588 &ops); 589 590 if (!ret) 591 ret = res; 592 593 page_offset = nand_bbm_get_next_page(chip, page_offset + 1); 594 } 595 596 return ret; 597 } 598 599 /** 600 * nand_markbad_bbm - mark a block by updating the BBM 601 * @chip: NAND chip object 602 * @ofs: offset of the block to mark bad 603 */ 604 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs) 605 { 606 if (chip->legacy.block_markbad) 607 return chip->legacy.block_markbad(chip, ofs); 608 609 return nand_default_block_markbad(chip, ofs); 610 } 611 612 /** 613 * nand_block_markbad_lowlevel - mark a block bad 614 * @chip: NAND chip object 615 * @ofs: offset from device start 616 * 617 * This function performs the generic NAND bad block marking steps (i.e., bad 618 * block table(s) and/or marker(s)). We only allow the hardware driver to 619 * specify how to write bad block markers to OOB (chip->legacy.block_markbad). 620 * 621 * We try operations in the following order: 622 * 623 * (1) erase the affected block, to allow OOB marker to be written cleanly 624 * (2) write bad block marker to OOB area of affected block (unless flag 625 * NAND_BBT_NO_OOB_BBM is present) 626 * (3) update the BBT 627 * 628 * Note that we retain the first error encountered in (2) or (3), finish the 629 * procedures, and dump the error in the end. 630 */ 631 static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs) 632 { 633 struct mtd_info *mtd = nand_to_mtd(chip); 634 int res, ret = 0; 635 636 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 637 struct erase_info einfo; 638 639 /* Attempt erase before marking OOB */ 640 memset(&einfo, 0, sizeof(einfo)); 641 einfo.addr = ofs; 642 einfo.len = 1ULL << chip->phys_erase_shift; 643 nand_erase_nand(chip, &einfo, 0); 644 645 /* Write bad block marker to OOB */ 646 ret = nand_get_device(chip); 647 if (ret) 648 return ret; 649 650 ret = nand_markbad_bbm(chip, ofs); 651 nand_release_device(chip); 652 } 653 654 /* Mark block bad in BBT */ 655 if (chip->bbt) { 656 res = nand_markbad_bbt(chip, ofs); 657 if (!ret) 658 ret = res; 659 } 660 661 if (!ret) 662 mtd->ecc_stats.badblocks++; 663 664 return ret; 665 } 666 667 /** 668 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. 669 * @mtd: MTD device structure 670 * @ofs: offset from device start 671 * 672 * Check if the block is marked as reserved. 673 */ 674 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 675 { 676 struct nand_chip *chip = mtd_to_nand(mtd); 677 678 if (!chip->bbt) 679 return 0; 680 /* Return info from the table */ 681 return nand_isreserved_bbt(chip, ofs); 682 } 683 684 /** 685 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 686 * @chip: NAND chip object 687 * @ofs: offset from device start 688 * @allowbbt: 1, if its allowed to access the bbt area 689 * 690 * Check, if the block is bad. Either by reading the bad block table or 691 * calling of the scan function. 692 */ 693 static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt) 694 { 695 /* Return info from the table */ 696 if (chip->bbt) 697 return nand_isbad_bbt(chip, ofs, allowbbt); 698 699 return nand_isbad_bbm(chip, ofs); 700 } 701 702 /** 703 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1 704 * @chip: NAND chip structure 705 * @timeout_ms: Timeout in ms 706 * 707 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1. 708 * If that does not happen whitin the specified timeout, -ETIMEDOUT is 709 * returned. 710 * 711 * This helper is intended to be used when the controller does not have access 712 * to the NAND R/B pin. 713 * 714 * Be aware that calling this helper from an ->exec_op() implementation means 715 * ->exec_op() must be re-entrant. 716 * 717 * Return 0 if the NAND chip is ready, a negative error otherwise. 718 */ 719 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms) 720 { 721 const struct nand_sdr_timings *timings; 722 u8 status = 0; 723 int ret; 724 725 if (!nand_has_exec_op(chip)) 726 return -ENOTSUPP; 727 728 /* Wait tWB before polling the STATUS reg. */ 729 timings = nand_get_sdr_timings(&chip->data_interface); 730 ndelay(PSEC_TO_NSEC(timings->tWB_max)); 731 732 ret = nand_status_op(chip, NULL); 733 if (ret) 734 return ret; 735 736 /* 737 * +1 below is necessary because if we are now in the last fraction 738 * of jiffy and msecs_to_jiffies is 1 then we will wait only that 739 * small jiffy fraction - possibly leading to false timeout 740 */ 741 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1; 742 do { 743 ret = nand_read_data_op(chip, &status, sizeof(status), true); 744 if (ret) 745 break; 746 747 if (status & NAND_STATUS_READY) 748 break; 749 750 /* 751 * Typical lowest execution time for a tR on most NANDs is 10us, 752 * use this as polling delay before doing something smarter (ie. 753 * deriving a delay from the timeout value, timeout_ms/ratio). 754 */ 755 udelay(10); 756 } while (time_before(jiffies, timeout_ms)); 757 758 /* 759 * We have to exit READ_STATUS mode in order to read real data on the 760 * bus in case the WAITRDY instruction is preceding a DATA_IN 761 * instruction. 762 */ 763 nand_exit_status_op(chip); 764 765 if (ret) 766 return ret; 767 768 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT; 769 }; 770 EXPORT_SYMBOL_GPL(nand_soft_waitrdy); 771 772 /** 773 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready 774 * @chip: NAND chip structure 775 * @gpiod: GPIO descriptor of R/B pin 776 * @timeout_ms: Timeout in ms 777 * 778 * Poll the R/B GPIO pin until it becomes ready. If that does not happen 779 * whitin the specified timeout, -ETIMEDOUT is returned. 780 * 781 * This helper is intended to be used when the controller has access to the 782 * NAND R/B pin over GPIO. 783 * 784 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise. 785 */ 786 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 787 unsigned long timeout_ms) 788 { 789 /* Wait until R/B pin indicates chip is ready or timeout occurs */ 790 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms); 791 do { 792 if (gpiod_get_value_cansleep(gpiod)) 793 return 0; 794 795 cond_resched(); 796 } while (time_before(jiffies, timeout_ms)); 797 798 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT; 799 }; 800 EXPORT_SYMBOL_GPL(nand_gpio_waitrdy); 801 802 /** 803 * panic_nand_wait - [GENERIC] wait until the command is done 804 * @chip: NAND chip structure 805 * @timeo: timeout 806 * 807 * Wait for command done. This is a helper function for nand_wait used when 808 * we are in interrupt context. May happen when in panic and trying to write 809 * an oops through mtdoops. 810 */ 811 void panic_nand_wait(struct nand_chip *chip, unsigned long timeo) 812 { 813 int i; 814 for (i = 0; i < timeo; i++) { 815 if (chip->legacy.dev_ready) { 816 if (chip->legacy.dev_ready(chip)) 817 break; 818 } else { 819 int ret; 820 u8 status; 821 822 ret = nand_read_data_op(chip, &status, sizeof(status), 823 true); 824 if (ret) 825 return; 826 827 if (status & NAND_STATUS_READY) 828 break; 829 } 830 mdelay(1); 831 } 832 } 833 834 static bool nand_supports_get_features(struct nand_chip *chip, int addr) 835 { 836 return (chip->parameters.supports_set_get_features && 837 test_bit(addr, chip->parameters.get_feature_list)); 838 } 839 840 static bool nand_supports_set_features(struct nand_chip *chip, int addr) 841 { 842 return (chip->parameters.supports_set_get_features && 843 test_bit(addr, chip->parameters.set_feature_list)); 844 } 845 846 /** 847 * nand_reset_data_interface - Reset data interface and timings 848 * @chip: The NAND chip 849 * @chipnr: Internal die id 850 * 851 * Reset the Data interface and timings to ONFI mode 0. 852 * 853 * Returns 0 for success or negative error code otherwise. 854 */ 855 static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) 856 { 857 int ret; 858 859 if (!nand_has_setup_data_iface(chip)) 860 return 0; 861 862 /* 863 * The ONFI specification says: 864 * " 865 * To transition from NV-DDR or NV-DDR2 to the SDR data 866 * interface, the host shall use the Reset (FFh) command 867 * using SDR timing mode 0. A device in any timing mode is 868 * required to recognize Reset (FFh) command issued in SDR 869 * timing mode 0. 870 * " 871 * 872 * Configure the data interface in SDR mode and set the 873 * timings to timing mode 0. 874 */ 875 876 onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0); 877 ret = chip->controller->ops->setup_data_interface(chip, chipnr, 878 &chip->data_interface); 879 if (ret) 880 pr_err("Failed to configure data interface to SDR timing mode 0\n"); 881 882 return ret; 883 } 884 885 /** 886 * nand_setup_data_interface - Setup the best data interface and timings 887 * @chip: The NAND chip 888 * @chipnr: Internal die id 889 * 890 * Find and configure the best data interface and NAND timings supported by 891 * the chip and the driver. 892 * First tries to retrieve supported timing modes from ONFI information, 893 * and if the NAND chip does not support ONFI, relies on the 894 * ->onfi_timing_mode_default specified in the nand_ids table. 895 * 896 * Returns 0 for success or negative error code otherwise. 897 */ 898 static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) 899 { 900 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { 901 chip->onfi_timing_mode_default, 902 }; 903 int ret; 904 905 if (!nand_has_setup_data_iface(chip)) 906 return 0; 907 908 /* Change the mode on the chip side (if supported by the NAND chip) */ 909 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) { 910 nand_select_target(chip, chipnr); 911 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 912 tmode_param); 913 nand_deselect_target(chip); 914 if (ret) 915 return ret; 916 } 917 918 /* Change the mode on the controller side */ 919 ret = chip->controller->ops->setup_data_interface(chip, chipnr, 920 &chip->data_interface); 921 if (ret) 922 return ret; 923 924 /* Check the mode has been accepted by the chip, if supported */ 925 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) 926 return 0; 927 928 memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN); 929 nand_select_target(chip, chipnr); 930 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE, 931 tmode_param); 932 nand_deselect_target(chip); 933 if (ret) 934 goto err_reset_chip; 935 936 if (tmode_param[0] != chip->onfi_timing_mode_default) { 937 pr_warn("timing mode %d not acknowledged by the NAND chip\n", 938 chip->onfi_timing_mode_default); 939 goto err_reset_chip; 940 } 941 942 return 0; 943 944 err_reset_chip: 945 /* 946 * Fallback to mode 0 if the chip explicitly did not ack the chosen 947 * timing mode. 948 */ 949 nand_reset_data_interface(chip, chipnr); 950 nand_select_target(chip, chipnr); 951 nand_reset_op(chip); 952 nand_deselect_target(chip); 953 954 return ret; 955 } 956 957 /** 958 * nand_init_data_interface - find the best data interface and timings 959 * @chip: The NAND chip 960 * 961 * Find the best data interface and NAND timings supported by the chip 962 * and the driver. 963 * First tries to retrieve supported timing modes from ONFI information, 964 * and if the NAND chip does not support ONFI, relies on the 965 * ->onfi_timing_mode_default specified in the nand_ids table. After this 966 * function nand_chip->data_interface is initialized with the best timing mode 967 * available. 968 * 969 * Returns 0 for success or negative error code otherwise. 970 */ 971 static int nand_init_data_interface(struct nand_chip *chip) 972 { 973 int modes, mode, ret; 974 975 if (!nand_has_setup_data_iface(chip)) 976 return 0; 977 978 /* 979 * First try to identify the best timings from ONFI parameters and 980 * if the NAND does not support ONFI, fallback to the default ONFI 981 * timing mode. 982 */ 983 if (chip->parameters.onfi) { 984 modes = chip->parameters.onfi->async_timing_mode; 985 } else { 986 if (!chip->onfi_timing_mode_default) 987 return 0; 988 989 modes = GENMASK(chip->onfi_timing_mode_default, 0); 990 } 991 992 for (mode = fls(modes) - 1; mode >= 0; mode--) { 993 ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode); 994 if (ret) 995 continue; 996 997 /* 998 * Pass NAND_DATA_IFACE_CHECK_ONLY to only check if the 999 * controller supports the requested timings. 1000 */ 1001 ret = chip->controller->ops->setup_data_interface(chip, 1002 NAND_DATA_IFACE_CHECK_ONLY, 1003 &chip->data_interface); 1004 if (!ret) { 1005 chip->onfi_timing_mode_default = mode; 1006 break; 1007 } 1008 } 1009 1010 return 0; 1011 } 1012 1013 /** 1014 * nand_fill_column_cycles - fill the column cycles of an address 1015 * @chip: The NAND chip 1016 * @addrs: Array of address cycles to fill 1017 * @offset_in_page: The offset in the page 1018 * 1019 * Fills the first or the first two bytes of the @addrs field depending 1020 * on the NAND bus width and the page size. 1021 * 1022 * Returns the number of cycles needed to encode the column, or a negative 1023 * error code in case one of the arguments is invalid. 1024 */ 1025 static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs, 1026 unsigned int offset_in_page) 1027 { 1028 struct mtd_info *mtd = nand_to_mtd(chip); 1029 1030 /* Make sure the offset is less than the actual page size. */ 1031 if (offset_in_page > mtd->writesize + mtd->oobsize) 1032 return -EINVAL; 1033 1034 /* 1035 * On small page NANDs, there's a dedicated command to access the OOB 1036 * area, and the column address is relative to the start of the OOB 1037 * area, not the start of the page. Asjust the address accordingly. 1038 */ 1039 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize) 1040 offset_in_page -= mtd->writesize; 1041 1042 /* 1043 * The offset in page is expressed in bytes, if the NAND bus is 16-bit 1044 * wide, then it must be divided by 2. 1045 */ 1046 if (chip->options & NAND_BUSWIDTH_16) { 1047 if (WARN_ON(offset_in_page % 2)) 1048 return -EINVAL; 1049 1050 offset_in_page /= 2; 1051 } 1052 1053 addrs[0] = offset_in_page; 1054 1055 /* 1056 * Small page NANDs use 1 cycle for the columns, while large page NANDs 1057 * need 2 1058 */ 1059 if (mtd->writesize <= 512) 1060 return 1; 1061 1062 addrs[1] = offset_in_page >> 8; 1063 1064 return 2; 1065 } 1066 1067 static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1068 unsigned int offset_in_page, void *buf, 1069 unsigned int len) 1070 { 1071 struct mtd_info *mtd = nand_to_mtd(chip); 1072 const struct nand_sdr_timings *sdr = 1073 nand_get_sdr_timings(&chip->data_interface); 1074 u8 addrs[4]; 1075 struct nand_op_instr instrs[] = { 1076 NAND_OP_CMD(NAND_CMD_READ0, 0), 1077 NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)), 1078 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), 1079 PSEC_TO_NSEC(sdr->tRR_min)), 1080 NAND_OP_DATA_IN(len, buf, 0), 1081 }; 1082 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1083 int ret; 1084 1085 /* Drop the DATA_IN instruction if len is set to 0. */ 1086 if (!len) 1087 op.ninstrs--; 1088 1089 if (offset_in_page >= mtd->writesize) 1090 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1091 else if (offset_in_page >= 256 && 1092 !(chip->options & NAND_BUSWIDTH_16)) 1093 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1094 1095 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1096 if (ret < 0) 1097 return ret; 1098 1099 addrs[1] = page; 1100 addrs[2] = page >> 8; 1101 1102 if (chip->options & NAND_ROW_ADDR_3) { 1103 addrs[3] = page >> 16; 1104 instrs[1].ctx.addr.naddrs++; 1105 } 1106 1107 return nand_exec_op(chip, &op); 1108 } 1109 1110 static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page, 1111 unsigned int offset_in_page, void *buf, 1112 unsigned int len) 1113 { 1114 const struct nand_sdr_timings *sdr = 1115 nand_get_sdr_timings(&chip->data_interface); 1116 u8 addrs[5]; 1117 struct nand_op_instr instrs[] = { 1118 NAND_OP_CMD(NAND_CMD_READ0, 0), 1119 NAND_OP_ADDR(4, addrs, 0), 1120 NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)), 1121 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), 1122 PSEC_TO_NSEC(sdr->tRR_min)), 1123 NAND_OP_DATA_IN(len, buf, 0), 1124 }; 1125 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1126 int ret; 1127 1128 /* Drop the DATA_IN instruction if len is set to 0. */ 1129 if (!len) 1130 op.ninstrs--; 1131 1132 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1133 if (ret < 0) 1134 return ret; 1135 1136 addrs[2] = page; 1137 addrs[3] = page >> 8; 1138 1139 if (chip->options & NAND_ROW_ADDR_3) { 1140 addrs[4] = page >> 16; 1141 instrs[1].ctx.addr.naddrs++; 1142 } 1143 1144 return nand_exec_op(chip, &op); 1145 } 1146 1147 /** 1148 * nand_read_page_op - Do a READ PAGE operation 1149 * @chip: The NAND chip 1150 * @page: page to read 1151 * @offset_in_page: offset within the page 1152 * @buf: buffer used to store the data 1153 * @len: length of the buffer 1154 * 1155 * This function issues a READ PAGE operation. 1156 * This function does not select/unselect the CS line. 1157 * 1158 * Returns 0 on success, a negative error code otherwise. 1159 */ 1160 int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1161 unsigned int offset_in_page, void *buf, unsigned int len) 1162 { 1163 struct mtd_info *mtd = nand_to_mtd(chip); 1164 1165 if (len && !buf) 1166 return -EINVAL; 1167 1168 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1169 return -EINVAL; 1170 1171 if (nand_has_exec_op(chip)) { 1172 if (mtd->writesize > 512) 1173 return nand_lp_exec_read_page_op(chip, page, 1174 offset_in_page, buf, 1175 len); 1176 1177 return nand_sp_exec_read_page_op(chip, page, offset_in_page, 1178 buf, len); 1179 } 1180 1181 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page); 1182 if (len) 1183 chip->legacy.read_buf(chip, buf, len); 1184 1185 return 0; 1186 } 1187 EXPORT_SYMBOL_GPL(nand_read_page_op); 1188 1189 /** 1190 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation 1191 * @chip: The NAND chip 1192 * @page: parameter page to read 1193 * @buf: buffer used to store the data 1194 * @len: length of the buffer 1195 * 1196 * This function issues a READ PARAMETER PAGE operation. 1197 * This function does not select/unselect the CS line. 1198 * 1199 * Returns 0 on success, a negative error code otherwise. 1200 */ 1201 int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf, 1202 unsigned int len) 1203 { 1204 unsigned int i; 1205 u8 *p = buf; 1206 1207 if (len && !buf) 1208 return -EINVAL; 1209 1210 if (nand_has_exec_op(chip)) { 1211 const struct nand_sdr_timings *sdr = 1212 nand_get_sdr_timings(&chip->data_interface); 1213 struct nand_op_instr instrs[] = { 1214 NAND_OP_CMD(NAND_CMD_PARAM, 0), 1215 NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)), 1216 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max), 1217 PSEC_TO_NSEC(sdr->tRR_min)), 1218 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1219 }; 1220 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1221 1222 /* Drop the DATA_IN instruction if len is set to 0. */ 1223 if (!len) 1224 op.ninstrs--; 1225 1226 return nand_exec_op(chip, &op); 1227 } 1228 1229 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1); 1230 for (i = 0; i < len; i++) 1231 p[i] = chip->legacy.read_byte(chip); 1232 1233 return 0; 1234 } 1235 1236 /** 1237 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation 1238 * @chip: The NAND chip 1239 * @offset_in_page: offset within the page 1240 * @buf: buffer used to store the data 1241 * @len: length of the buffer 1242 * @force_8bit: force 8-bit bus access 1243 * 1244 * This function issues a CHANGE READ COLUMN operation. 1245 * This function does not select/unselect the CS line. 1246 * 1247 * Returns 0 on success, a negative error code otherwise. 1248 */ 1249 int nand_change_read_column_op(struct nand_chip *chip, 1250 unsigned int offset_in_page, void *buf, 1251 unsigned int len, bool force_8bit) 1252 { 1253 struct mtd_info *mtd = nand_to_mtd(chip); 1254 1255 if (len && !buf) 1256 return -EINVAL; 1257 1258 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1259 return -EINVAL; 1260 1261 /* Small page NANDs do not support column change. */ 1262 if (mtd->writesize <= 512) 1263 return -ENOTSUPP; 1264 1265 if (nand_has_exec_op(chip)) { 1266 const struct nand_sdr_timings *sdr = 1267 nand_get_sdr_timings(&chip->data_interface); 1268 u8 addrs[2] = {}; 1269 struct nand_op_instr instrs[] = { 1270 NAND_OP_CMD(NAND_CMD_RNDOUT, 0), 1271 NAND_OP_ADDR(2, addrs, 0), 1272 NAND_OP_CMD(NAND_CMD_RNDOUTSTART, 1273 PSEC_TO_NSEC(sdr->tCCS_min)), 1274 NAND_OP_DATA_IN(len, buf, 0), 1275 }; 1276 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1277 int ret; 1278 1279 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1280 if (ret < 0) 1281 return ret; 1282 1283 /* Drop the DATA_IN instruction if len is set to 0. */ 1284 if (!len) 1285 op.ninstrs--; 1286 1287 instrs[3].ctx.data.force_8bit = force_8bit; 1288 1289 return nand_exec_op(chip, &op); 1290 } 1291 1292 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1); 1293 if (len) 1294 chip->legacy.read_buf(chip, buf, len); 1295 1296 return 0; 1297 } 1298 EXPORT_SYMBOL_GPL(nand_change_read_column_op); 1299 1300 /** 1301 * nand_read_oob_op - Do a READ OOB operation 1302 * @chip: The NAND chip 1303 * @page: page to read 1304 * @offset_in_oob: offset within the OOB area 1305 * @buf: buffer used to store the data 1306 * @len: length of the buffer 1307 * 1308 * This function issues a READ OOB operation. 1309 * This function does not select/unselect the CS line. 1310 * 1311 * Returns 0 on success, a negative error code otherwise. 1312 */ 1313 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1314 unsigned int offset_in_oob, void *buf, unsigned int len) 1315 { 1316 struct mtd_info *mtd = nand_to_mtd(chip); 1317 1318 if (len && !buf) 1319 return -EINVAL; 1320 1321 if (offset_in_oob + len > mtd->oobsize) 1322 return -EINVAL; 1323 1324 if (nand_has_exec_op(chip)) 1325 return nand_read_page_op(chip, page, 1326 mtd->writesize + offset_in_oob, 1327 buf, len); 1328 1329 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page); 1330 if (len) 1331 chip->legacy.read_buf(chip, buf, len); 1332 1333 return 0; 1334 } 1335 EXPORT_SYMBOL_GPL(nand_read_oob_op); 1336 1337 static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page, 1338 unsigned int offset_in_page, const void *buf, 1339 unsigned int len, bool prog) 1340 { 1341 struct mtd_info *mtd = nand_to_mtd(chip); 1342 const struct nand_sdr_timings *sdr = 1343 nand_get_sdr_timings(&chip->data_interface); 1344 u8 addrs[5] = {}; 1345 struct nand_op_instr instrs[] = { 1346 /* 1347 * The first instruction will be dropped if we're dealing 1348 * with a large page NAND and adjusted if we're dealing 1349 * with a small page NAND and the page offset is > 255. 1350 */ 1351 NAND_OP_CMD(NAND_CMD_READ0, 0), 1352 NAND_OP_CMD(NAND_CMD_SEQIN, 0), 1353 NAND_OP_ADDR(0, addrs, PSEC_TO_NSEC(sdr->tADL_min)), 1354 NAND_OP_DATA_OUT(len, buf, 0), 1355 NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)), 1356 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0), 1357 }; 1358 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1359 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page); 1360 int ret; 1361 u8 status; 1362 1363 if (naddrs < 0) 1364 return naddrs; 1365 1366 addrs[naddrs++] = page; 1367 addrs[naddrs++] = page >> 8; 1368 if (chip->options & NAND_ROW_ADDR_3) 1369 addrs[naddrs++] = page >> 16; 1370 1371 instrs[2].ctx.addr.naddrs = naddrs; 1372 1373 /* Drop the last two instructions if we're not programming the page. */ 1374 if (!prog) { 1375 op.ninstrs -= 2; 1376 /* Also drop the DATA_OUT instruction if empty. */ 1377 if (!len) 1378 op.ninstrs--; 1379 } 1380 1381 if (mtd->writesize <= 512) { 1382 /* 1383 * Small pages need some more tweaking: we have to adjust the 1384 * first instruction depending on the page offset we're trying 1385 * to access. 1386 */ 1387 if (offset_in_page >= mtd->writesize) 1388 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB; 1389 else if (offset_in_page >= 256 && 1390 !(chip->options & NAND_BUSWIDTH_16)) 1391 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1; 1392 } else { 1393 /* 1394 * Drop the first command if we're dealing with a large page 1395 * NAND. 1396 */ 1397 op.instrs++; 1398 op.ninstrs--; 1399 } 1400 1401 ret = nand_exec_op(chip, &op); 1402 if (!prog || ret) 1403 return ret; 1404 1405 ret = nand_status_op(chip, &status); 1406 if (ret) 1407 return ret; 1408 1409 return status; 1410 } 1411 1412 /** 1413 * nand_prog_page_begin_op - starts a PROG PAGE operation 1414 * @chip: The NAND chip 1415 * @page: page to write 1416 * @offset_in_page: offset within the page 1417 * @buf: buffer containing the data to write to the page 1418 * @len: length of the buffer 1419 * 1420 * This function issues the first half of a PROG PAGE operation. 1421 * This function does not select/unselect the CS line. 1422 * 1423 * Returns 0 on success, a negative error code otherwise. 1424 */ 1425 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1426 unsigned int offset_in_page, const void *buf, 1427 unsigned int len) 1428 { 1429 struct mtd_info *mtd = nand_to_mtd(chip); 1430 1431 if (len && !buf) 1432 return -EINVAL; 1433 1434 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1435 return -EINVAL; 1436 1437 if (nand_has_exec_op(chip)) 1438 return nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1439 len, false); 1440 1441 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page); 1442 1443 if (buf) 1444 chip->legacy.write_buf(chip, buf, len); 1445 1446 return 0; 1447 } 1448 EXPORT_SYMBOL_GPL(nand_prog_page_begin_op); 1449 1450 /** 1451 * nand_prog_page_end_op - ends a PROG PAGE operation 1452 * @chip: The NAND chip 1453 * 1454 * This function issues the second half of a PROG PAGE operation. 1455 * This function does not select/unselect the CS line. 1456 * 1457 * Returns 0 on success, a negative error code otherwise. 1458 */ 1459 int nand_prog_page_end_op(struct nand_chip *chip) 1460 { 1461 int ret; 1462 u8 status; 1463 1464 if (nand_has_exec_op(chip)) { 1465 const struct nand_sdr_timings *sdr = 1466 nand_get_sdr_timings(&chip->data_interface); 1467 struct nand_op_instr instrs[] = { 1468 NAND_OP_CMD(NAND_CMD_PAGEPROG, 1469 PSEC_TO_NSEC(sdr->tWB_max)), 1470 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0), 1471 }; 1472 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1473 1474 ret = nand_exec_op(chip, &op); 1475 if (ret) 1476 return ret; 1477 1478 ret = nand_status_op(chip, &status); 1479 if (ret) 1480 return ret; 1481 } else { 1482 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1483 ret = chip->legacy.waitfunc(chip); 1484 if (ret < 0) 1485 return ret; 1486 1487 status = ret; 1488 } 1489 1490 if (status & NAND_STATUS_FAIL) 1491 return -EIO; 1492 1493 return 0; 1494 } 1495 EXPORT_SYMBOL_GPL(nand_prog_page_end_op); 1496 1497 /** 1498 * nand_prog_page_op - Do a full PROG PAGE operation 1499 * @chip: The NAND chip 1500 * @page: page to write 1501 * @offset_in_page: offset within the page 1502 * @buf: buffer containing the data to write to the page 1503 * @len: length of the buffer 1504 * 1505 * This function issues a full PROG PAGE operation. 1506 * This function does not select/unselect the CS line. 1507 * 1508 * Returns 0 on success, a negative error code otherwise. 1509 */ 1510 int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1511 unsigned int offset_in_page, const void *buf, 1512 unsigned int len) 1513 { 1514 struct mtd_info *mtd = nand_to_mtd(chip); 1515 int status; 1516 1517 if (!len || !buf) 1518 return -EINVAL; 1519 1520 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1521 return -EINVAL; 1522 1523 if (nand_has_exec_op(chip)) { 1524 status = nand_exec_prog_page_op(chip, page, offset_in_page, buf, 1525 len, true); 1526 } else { 1527 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, 1528 page); 1529 chip->legacy.write_buf(chip, buf, len); 1530 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1); 1531 status = chip->legacy.waitfunc(chip); 1532 } 1533 1534 if (status & NAND_STATUS_FAIL) 1535 return -EIO; 1536 1537 return 0; 1538 } 1539 EXPORT_SYMBOL_GPL(nand_prog_page_op); 1540 1541 /** 1542 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation 1543 * @chip: The NAND chip 1544 * @offset_in_page: offset within the page 1545 * @buf: buffer containing the data to send to the NAND 1546 * @len: length of the buffer 1547 * @force_8bit: force 8-bit bus access 1548 * 1549 * This function issues a CHANGE WRITE COLUMN operation. 1550 * This function does not select/unselect the CS line. 1551 * 1552 * Returns 0 on success, a negative error code otherwise. 1553 */ 1554 int nand_change_write_column_op(struct nand_chip *chip, 1555 unsigned int offset_in_page, 1556 const void *buf, unsigned int len, 1557 bool force_8bit) 1558 { 1559 struct mtd_info *mtd = nand_to_mtd(chip); 1560 1561 if (len && !buf) 1562 return -EINVAL; 1563 1564 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1565 return -EINVAL; 1566 1567 /* Small page NANDs do not support column change. */ 1568 if (mtd->writesize <= 512) 1569 return -ENOTSUPP; 1570 1571 if (nand_has_exec_op(chip)) { 1572 const struct nand_sdr_timings *sdr = 1573 nand_get_sdr_timings(&chip->data_interface); 1574 u8 addrs[2]; 1575 struct nand_op_instr instrs[] = { 1576 NAND_OP_CMD(NAND_CMD_RNDIN, 0), 1577 NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)), 1578 NAND_OP_DATA_OUT(len, buf, 0), 1579 }; 1580 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1581 int ret; 1582 1583 ret = nand_fill_column_cycles(chip, addrs, offset_in_page); 1584 if (ret < 0) 1585 return ret; 1586 1587 instrs[2].ctx.data.force_8bit = force_8bit; 1588 1589 /* Drop the DATA_OUT instruction if len is set to 0. */ 1590 if (!len) 1591 op.ninstrs--; 1592 1593 return nand_exec_op(chip, &op); 1594 } 1595 1596 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1); 1597 if (len) 1598 chip->legacy.write_buf(chip, buf, len); 1599 1600 return 0; 1601 } 1602 EXPORT_SYMBOL_GPL(nand_change_write_column_op); 1603 1604 /** 1605 * nand_readid_op - Do a READID operation 1606 * @chip: The NAND chip 1607 * @addr: address cycle to pass after the READID command 1608 * @buf: buffer used to store the ID 1609 * @len: length of the buffer 1610 * 1611 * This function sends a READID command and reads back the ID returned by the 1612 * NAND. 1613 * This function does not select/unselect the CS line. 1614 * 1615 * Returns 0 on success, a negative error code otherwise. 1616 */ 1617 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1618 unsigned int len) 1619 { 1620 unsigned int i; 1621 u8 *id = buf; 1622 1623 if (len && !buf) 1624 return -EINVAL; 1625 1626 if (nand_has_exec_op(chip)) { 1627 const struct nand_sdr_timings *sdr = 1628 nand_get_sdr_timings(&chip->data_interface); 1629 struct nand_op_instr instrs[] = { 1630 NAND_OP_CMD(NAND_CMD_READID, 0), 1631 NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)), 1632 NAND_OP_8BIT_DATA_IN(len, buf, 0), 1633 }; 1634 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1635 1636 /* Drop the DATA_IN instruction if len is set to 0. */ 1637 if (!len) 1638 op.ninstrs--; 1639 1640 return nand_exec_op(chip, &op); 1641 } 1642 1643 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1); 1644 1645 for (i = 0; i < len; i++) 1646 id[i] = chip->legacy.read_byte(chip); 1647 1648 return 0; 1649 } 1650 EXPORT_SYMBOL_GPL(nand_readid_op); 1651 1652 /** 1653 * nand_status_op - Do a STATUS operation 1654 * @chip: The NAND chip 1655 * @status: out variable to store the NAND status 1656 * 1657 * This function sends a STATUS command and reads back the status returned by 1658 * the NAND. 1659 * This function does not select/unselect the CS line. 1660 * 1661 * Returns 0 on success, a negative error code otherwise. 1662 */ 1663 int nand_status_op(struct nand_chip *chip, u8 *status) 1664 { 1665 if (nand_has_exec_op(chip)) { 1666 const struct nand_sdr_timings *sdr = 1667 nand_get_sdr_timings(&chip->data_interface); 1668 struct nand_op_instr instrs[] = { 1669 NAND_OP_CMD(NAND_CMD_STATUS, 1670 PSEC_TO_NSEC(sdr->tADL_min)), 1671 NAND_OP_8BIT_DATA_IN(1, status, 0), 1672 }; 1673 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1674 1675 if (!status) 1676 op.ninstrs--; 1677 1678 return nand_exec_op(chip, &op); 1679 } 1680 1681 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1); 1682 if (status) 1683 *status = chip->legacy.read_byte(chip); 1684 1685 return 0; 1686 } 1687 EXPORT_SYMBOL_GPL(nand_status_op); 1688 1689 /** 1690 * nand_exit_status_op - Exit a STATUS operation 1691 * @chip: The NAND chip 1692 * 1693 * This function sends a READ0 command to cancel the effect of the STATUS 1694 * command to avoid reading only the status until a new read command is sent. 1695 * 1696 * This function does not select/unselect the CS line. 1697 * 1698 * Returns 0 on success, a negative error code otherwise. 1699 */ 1700 int nand_exit_status_op(struct nand_chip *chip) 1701 { 1702 if (nand_has_exec_op(chip)) { 1703 struct nand_op_instr instrs[] = { 1704 NAND_OP_CMD(NAND_CMD_READ0, 0), 1705 }; 1706 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1707 1708 return nand_exec_op(chip, &op); 1709 } 1710 1711 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1); 1712 1713 return 0; 1714 } 1715 1716 /** 1717 * nand_erase_op - Do an erase operation 1718 * @chip: The NAND chip 1719 * @eraseblock: block to erase 1720 * 1721 * This function sends an ERASE command and waits for the NAND to be ready 1722 * before returning. 1723 * This function does not select/unselect the CS line. 1724 * 1725 * Returns 0 on success, a negative error code otherwise. 1726 */ 1727 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock) 1728 { 1729 unsigned int page = eraseblock << 1730 (chip->phys_erase_shift - chip->page_shift); 1731 int ret; 1732 u8 status; 1733 1734 if (nand_has_exec_op(chip)) { 1735 const struct nand_sdr_timings *sdr = 1736 nand_get_sdr_timings(&chip->data_interface); 1737 u8 addrs[3] = { page, page >> 8, page >> 16 }; 1738 struct nand_op_instr instrs[] = { 1739 NAND_OP_CMD(NAND_CMD_ERASE1, 0), 1740 NAND_OP_ADDR(2, addrs, 0), 1741 NAND_OP_CMD(NAND_CMD_ERASE2, 1742 PSEC_TO_MSEC(sdr->tWB_max)), 1743 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0), 1744 }; 1745 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1746 1747 if (chip->options & NAND_ROW_ADDR_3) 1748 instrs[1].ctx.addr.naddrs++; 1749 1750 ret = nand_exec_op(chip, &op); 1751 if (ret) 1752 return ret; 1753 1754 ret = nand_status_op(chip, &status); 1755 if (ret) 1756 return ret; 1757 } else { 1758 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page); 1759 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1); 1760 1761 ret = chip->legacy.waitfunc(chip); 1762 if (ret < 0) 1763 return ret; 1764 1765 status = ret; 1766 } 1767 1768 if (status & NAND_STATUS_FAIL) 1769 return -EIO; 1770 1771 return 0; 1772 } 1773 EXPORT_SYMBOL_GPL(nand_erase_op); 1774 1775 /** 1776 * nand_set_features_op - Do a SET FEATURES operation 1777 * @chip: The NAND chip 1778 * @feature: feature id 1779 * @data: 4 bytes of data 1780 * 1781 * This function sends a SET FEATURES command and waits for the NAND to be 1782 * ready before returning. 1783 * This function does not select/unselect the CS line. 1784 * 1785 * Returns 0 on success, a negative error code otherwise. 1786 */ 1787 static int nand_set_features_op(struct nand_chip *chip, u8 feature, 1788 const void *data) 1789 { 1790 const u8 *params = data; 1791 int i, ret; 1792 1793 if (nand_has_exec_op(chip)) { 1794 const struct nand_sdr_timings *sdr = 1795 nand_get_sdr_timings(&chip->data_interface); 1796 struct nand_op_instr instrs[] = { 1797 NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0), 1798 NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)), 1799 NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data, 1800 PSEC_TO_NSEC(sdr->tWB_max)), 1801 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0), 1802 }; 1803 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1804 1805 return nand_exec_op(chip, &op); 1806 } 1807 1808 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1); 1809 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1810 chip->legacy.write_byte(chip, params[i]); 1811 1812 ret = chip->legacy.waitfunc(chip); 1813 if (ret < 0) 1814 return ret; 1815 1816 if (ret & NAND_STATUS_FAIL) 1817 return -EIO; 1818 1819 return 0; 1820 } 1821 1822 /** 1823 * nand_get_features_op - Do a GET FEATURES operation 1824 * @chip: The NAND chip 1825 * @feature: feature id 1826 * @data: 4 bytes of data 1827 * 1828 * This function sends a GET FEATURES command and waits for the NAND to be 1829 * ready before returning. 1830 * This function does not select/unselect the CS line. 1831 * 1832 * Returns 0 on success, a negative error code otherwise. 1833 */ 1834 static int nand_get_features_op(struct nand_chip *chip, u8 feature, 1835 void *data) 1836 { 1837 u8 *params = data; 1838 int i; 1839 1840 if (nand_has_exec_op(chip)) { 1841 const struct nand_sdr_timings *sdr = 1842 nand_get_sdr_timings(&chip->data_interface); 1843 struct nand_op_instr instrs[] = { 1844 NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0), 1845 NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)), 1846 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 1847 PSEC_TO_NSEC(sdr->tRR_min)), 1848 NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN, 1849 data, 0), 1850 }; 1851 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1852 1853 return nand_exec_op(chip, &op); 1854 } 1855 1856 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1); 1857 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1858 params[i] = chip->legacy.read_byte(chip); 1859 1860 return 0; 1861 } 1862 1863 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms, 1864 unsigned int delay_ns) 1865 { 1866 if (nand_has_exec_op(chip)) { 1867 struct nand_op_instr instrs[] = { 1868 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms), 1869 PSEC_TO_NSEC(delay_ns)), 1870 }; 1871 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1872 1873 return nand_exec_op(chip, &op); 1874 } 1875 1876 /* Apply delay or wait for ready/busy pin */ 1877 if (!chip->legacy.dev_ready) 1878 udelay(chip->legacy.chip_delay); 1879 else 1880 nand_wait_ready(chip); 1881 1882 return 0; 1883 } 1884 1885 /** 1886 * nand_reset_op - Do a reset operation 1887 * @chip: The NAND chip 1888 * 1889 * This function sends a RESET command and waits for the NAND to be ready 1890 * before returning. 1891 * This function does not select/unselect the CS line. 1892 * 1893 * Returns 0 on success, a negative error code otherwise. 1894 */ 1895 int nand_reset_op(struct nand_chip *chip) 1896 { 1897 if (nand_has_exec_op(chip)) { 1898 const struct nand_sdr_timings *sdr = 1899 nand_get_sdr_timings(&chip->data_interface); 1900 struct nand_op_instr instrs[] = { 1901 NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)), 1902 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0), 1903 }; 1904 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1905 1906 return nand_exec_op(chip, &op); 1907 } 1908 1909 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1); 1910 1911 return 0; 1912 } 1913 EXPORT_SYMBOL_GPL(nand_reset_op); 1914 1915 /** 1916 * nand_read_data_op - Read data from the NAND 1917 * @chip: The NAND chip 1918 * @buf: buffer used to store the data 1919 * @len: length of the buffer 1920 * @force_8bit: force 8-bit bus access 1921 * 1922 * This function does a raw data read on the bus. Usually used after launching 1923 * another NAND operation like nand_read_page_op(). 1924 * This function does not select/unselect the CS line. 1925 * 1926 * Returns 0 on success, a negative error code otherwise. 1927 */ 1928 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1929 bool force_8bit) 1930 { 1931 if (!len || !buf) 1932 return -EINVAL; 1933 1934 if (nand_has_exec_op(chip)) { 1935 struct nand_op_instr instrs[] = { 1936 NAND_OP_DATA_IN(len, buf, 0), 1937 }; 1938 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1939 1940 instrs[0].ctx.data.force_8bit = force_8bit; 1941 1942 return nand_exec_op(chip, &op); 1943 } 1944 1945 if (force_8bit) { 1946 u8 *p = buf; 1947 unsigned int i; 1948 1949 for (i = 0; i < len; i++) 1950 p[i] = chip->legacy.read_byte(chip); 1951 } else { 1952 chip->legacy.read_buf(chip, buf, len); 1953 } 1954 1955 return 0; 1956 } 1957 EXPORT_SYMBOL_GPL(nand_read_data_op); 1958 1959 /** 1960 * nand_write_data_op - Write data from the NAND 1961 * @chip: The NAND chip 1962 * @buf: buffer containing the data to send on the bus 1963 * @len: length of the buffer 1964 * @force_8bit: force 8-bit bus access 1965 * 1966 * This function does a raw data write on the bus. Usually used after launching 1967 * another NAND operation like nand_write_page_begin_op(). 1968 * This function does not select/unselect the CS line. 1969 * 1970 * Returns 0 on success, a negative error code otherwise. 1971 */ 1972 int nand_write_data_op(struct nand_chip *chip, const void *buf, 1973 unsigned int len, bool force_8bit) 1974 { 1975 if (!len || !buf) 1976 return -EINVAL; 1977 1978 if (nand_has_exec_op(chip)) { 1979 struct nand_op_instr instrs[] = { 1980 NAND_OP_DATA_OUT(len, buf, 0), 1981 }; 1982 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 1983 1984 instrs[0].ctx.data.force_8bit = force_8bit; 1985 1986 return nand_exec_op(chip, &op); 1987 } 1988 1989 if (force_8bit) { 1990 const u8 *p = buf; 1991 unsigned int i; 1992 1993 for (i = 0; i < len; i++) 1994 chip->legacy.write_byte(chip, p[i]); 1995 } else { 1996 chip->legacy.write_buf(chip, buf, len); 1997 } 1998 1999 return 0; 2000 } 2001 EXPORT_SYMBOL_GPL(nand_write_data_op); 2002 2003 /** 2004 * struct nand_op_parser_ctx - Context used by the parser 2005 * @instrs: array of all the instructions that must be addressed 2006 * @ninstrs: length of the @instrs array 2007 * @subop: Sub-operation to be passed to the NAND controller 2008 * 2009 * This structure is used by the core to split NAND operations into 2010 * sub-operations that can be handled by the NAND controller. 2011 */ 2012 struct nand_op_parser_ctx { 2013 const struct nand_op_instr *instrs; 2014 unsigned int ninstrs; 2015 struct nand_subop subop; 2016 }; 2017 2018 /** 2019 * nand_op_parser_must_split_instr - Checks if an instruction must be split 2020 * @pat: the parser pattern element that matches @instr 2021 * @instr: pointer to the instruction to check 2022 * @start_offset: this is an in/out parameter. If @instr has already been 2023 * split, then @start_offset is the offset from which to start 2024 * (either an address cycle or an offset in the data buffer). 2025 * Conversely, if the function returns true (ie. instr must be 2026 * split), this parameter is updated to point to the first 2027 * data/address cycle that has not been taken care of. 2028 * 2029 * Some NAND controllers are limited and cannot send X address cycles with a 2030 * unique operation, or cannot read/write more than Y bytes at the same time. 2031 * In this case, split the instruction that does not fit in a single 2032 * controller-operation into two or more chunks. 2033 * 2034 * Returns true if the instruction must be split, false otherwise. 2035 * The @start_offset parameter is also updated to the offset at which the next 2036 * bundle of instruction must start (if an address or a data instruction). 2037 */ 2038 static bool 2039 nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat, 2040 const struct nand_op_instr *instr, 2041 unsigned int *start_offset) 2042 { 2043 switch (pat->type) { 2044 case NAND_OP_ADDR_INSTR: 2045 if (!pat->ctx.addr.maxcycles) 2046 break; 2047 2048 if (instr->ctx.addr.naddrs - *start_offset > 2049 pat->ctx.addr.maxcycles) { 2050 *start_offset += pat->ctx.addr.maxcycles; 2051 return true; 2052 } 2053 break; 2054 2055 case NAND_OP_DATA_IN_INSTR: 2056 case NAND_OP_DATA_OUT_INSTR: 2057 if (!pat->ctx.data.maxlen) 2058 break; 2059 2060 if (instr->ctx.data.len - *start_offset > 2061 pat->ctx.data.maxlen) { 2062 *start_offset += pat->ctx.data.maxlen; 2063 return true; 2064 } 2065 break; 2066 2067 default: 2068 break; 2069 } 2070 2071 return false; 2072 } 2073 2074 /** 2075 * nand_op_parser_match_pat - Checks if a pattern matches the instructions 2076 * remaining in the parser context 2077 * @pat: the pattern to test 2078 * @ctx: the parser context structure to match with the pattern @pat 2079 * 2080 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx. 2081 * Returns true if this is the case, false ortherwise. When true is returned, 2082 * @ctx->subop is updated with the set of instructions to be passed to the 2083 * controller driver. 2084 */ 2085 static bool 2086 nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat, 2087 struct nand_op_parser_ctx *ctx) 2088 { 2089 unsigned int instr_offset = ctx->subop.first_instr_start_off; 2090 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs; 2091 const struct nand_op_instr *instr = ctx->subop.instrs; 2092 unsigned int i, ninstrs; 2093 2094 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) { 2095 /* 2096 * The pattern instruction does not match the operation 2097 * instruction. If the instruction is marked optional in the 2098 * pattern definition, we skip the pattern element and continue 2099 * to the next one. If the element is mandatory, there's no 2100 * match and we can return false directly. 2101 */ 2102 if (instr->type != pat->elems[i].type) { 2103 if (!pat->elems[i].optional) 2104 return false; 2105 2106 continue; 2107 } 2108 2109 /* 2110 * Now check the pattern element constraints. If the pattern is 2111 * not able to handle the whole instruction in a single step, 2112 * we have to split it. 2113 * The last_instr_end_off value comes back updated to point to 2114 * the position where we have to split the instruction (the 2115 * start of the next subop chunk). 2116 */ 2117 if (nand_op_parser_must_split_instr(&pat->elems[i], instr, 2118 &instr_offset)) { 2119 ninstrs++; 2120 i++; 2121 break; 2122 } 2123 2124 instr++; 2125 ninstrs++; 2126 instr_offset = 0; 2127 } 2128 2129 /* 2130 * This can happen if all instructions of a pattern are optional. 2131 * Still, if there's not at least one instruction handled by this 2132 * pattern, this is not a match, and we should try the next one (if 2133 * any). 2134 */ 2135 if (!ninstrs) 2136 return false; 2137 2138 /* 2139 * We had a match on the pattern head, but the pattern may be longer 2140 * than the instructions we're asked to execute. We need to make sure 2141 * there's no mandatory elements in the pattern tail. 2142 */ 2143 for (; i < pat->nelems; i++) { 2144 if (!pat->elems[i].optional) 2145 return false; 2146 } 2147 2148 /* 2149 * We have a match: update the subop structure accordingly and return 2150 * true. 2151 */ 2152 ctx->subop.ninstrs = ninstrs; 2153 ctx->subop.last_instr_end_off = instr_offset; 2154 2155 return true; 2156 } 2157 2158 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG) 2159 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2160 { 2161 const struct nand_op_instr *instr; 2162 char *prefix = " "; 2163 unsigned int i; 2164 2165 pr_debug("executing subop:\n"); 2166 2167 for (i = 0; i < ctx->ninstrs; i++) { 2168 instr = &ctx->instrs[i]; 2169 2170 if (instr == &ctx->subop.instrs[0]) 2171 prefix = " ->"; 2172 2173 nand_op_trace(prefix, instr); 2174 2175 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1]) 2176 prefix = " "; 2177 } 2178 } 2179 #else 2180 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx) 2181 { 2182 /* NOP */ 2183 } 2184 #endif 2185 2186 static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a, 2187 const struct nand_op_parser_ctx *b) 2188 { 2189 if (a->subop.ninstrs < b->subop.ninstrs) 2190 return -1; 2191 else if (a->subop.ninstrs > b->subop.ninstrs) 2192 return 1; 2193 2194 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off) 2195 return -1; 2196 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off) 2197 return 1; 2198 2199 return 0; 2200 } 2201 2202 /** 2203 * nand_op_parser_exec_op - exec_op parser 2204 * @chip: the NAND chip 2205 * @parser: patterns description provided by the controller driver 2206 * @op: the NAND operation to address 2207 * @check_only: when true, the function only checks if @op can be handled but 2208 * does not execute the operation 2209 * 2210 * Helper function designed to ease integration of NAND controller drivers that 2211 * only support a limited set of instruction sequences. The supported sequences 2212 * are described in @parser, and the framework takes care of splitting @op into 2213 * multiple sub-operations (if required) and pass them back to the ->exec() 2214 * callback of the matching pattern if @check_only is set to false. 2215 * 2216 * NAND controller drivers should call this function from their own ->exec_op() 2217 * implementation. 2218 * 2219 * Returns 0 on success, a negative error code otherwise. A failure can be 2220 * caused by an unsupported operation (none of the supported patterns is able 2221 * to handle the requested operation), or an error returned by one of the 2222 * matching pattern->exec() hook. 2223 */ 2224 int nand_op_parser_exec_op(struct nand_chip *chip, 2225 const struct nand_op_parser *parser, 2226 const struct nand_operation *op, bool check_only) 2227 { 2228 struct nand_op_parser_ctx ctx = { 2229 .subop.instrs = op->instrs, 2230 .instrs = op->instrs, 2231 .ninstrs = op->ninstrs, 2232 }; 2233 unsigned int i; 2234 2235 while (ctx.subop.instrs < op->instrs + op->ninstrs) { 2236 const struct nand_op_parser_pattern *pattern; 2237 struct nand_op_parser_ctx best_ctx; 2238 int ret, best_pattern = -1; 2239 2240 for (i = 0; i < parser->npatterns; i++) { 2241 struct nand_op_parser_ctx test_ctx = ctx; 2242 2243 pattern = &parser->patterns[i]; 2244 if (!nand_op_parser_match_pat(pattern, &test_ctx)) 2245 continue; 2246 2247 if (best_pattern >= 0 && 2248 nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0) 2249 continue; 2250 2251 best_pattern = i; 2252 best_ctx = test_ctx; 2253 } 2254 2255 if (best_pattern < 0) { 2256 pr_debug("->exec_op() parser: pattern not found!\n"); 2257 return -ENOTSUPP; 2258 } 2259 2260 ctx = best_ctx; 2261 nand_op_parser_trace(&ctx); 2262 2263 if (!check_only) { 2264 pattern = &parser->patterns[best_pattern]; 2265 ret = pattern->exec(chip, &ctx.subop); 2266 if (ret) 2267 return ret; 2268 } 2269 2270 /* 2271 * Update the context structure by pointing to the start of the 2272 * next subop. 2273 */ 2274 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs; 2275 if (ctx.subop.last_instr_end_off) 2276 ctx.subop.instrs -= 1; 2277 2278 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off; 2279 } 2280 2281 return 0; 2282 } 2283 EXPORT_SYMBOL_GPL(nand_op_parser_exec_op); 2284 2285 static bool nand_instr_is_data(const struct nand_op_instr *instr) 2286 { 2287 return instr && (instr->type == NAND_OP_DATA_IN_INSTR || 2288 instr->type == NAND_OP_DATA_OUT_INSTR); 2289 } 2290 2291 static bool nand_subop_instr_is_valid(const struct nand_subop *subop, 2292 unsigned int instr_idx) 2293 { 2294 return subop && instr_idx < subop->ninstrs; 2295 } 2296 2297 static unsigned int nand_subop_get_start_off(const struct nand_subop *subop, 2298 unsigned int instr_idx) 2299 { 2300 if (instr_idx) 2301 return 0; 2302 2303 return subop->first_instr_start_off; 2304 } 2305 2306 /** 2307 * nand_subop_get_addr_start_off - Get the start offset in an address array 2308 * @subop: The entire sub-operation 2309 * @instr_idx: Index of the instruction inside the sub-operation 2310 * 2311 * During driver development, one could be tempted to directly use the 2312 * ->addr.addrs field of address instructions. This is wrong as address 2313 * instructions might be split. 2314 * 2315 * Given an address instruction, returns the offset of the first cycle to issue. 2316 */ 2317 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 2318 unsigned int instr_idx) 2319 { 2320 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2321 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2322 return 0; 2323 2324 return nand_subop_get_start_off(subop, instr_idx); 2325 } 2326 EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off); 2327 2328 /** 2329 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert 2330 * @subop: The entire sub-operation 2331 * @instr_idx: Index of the instruction inside the sub-operation 2332 * 2333 * During driver development, one could be tempted to directly use the 2334 * ->addr->naddrs field of a data instruction. This is wrong as instructions 2335 * might be split. 2336 * 2337 * Given an address instruction, returns the number of address cycle to issue. 2338 */ 2339 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 2340 unsigned int instr_idx) 2341 { 2342 int start_off, end_off; 2343 2344 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2345 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR)) 2346 return 0; 2347 2348 start_off = nand_subop_get_addr_start_off(subop, instr_idx); 2349 2350 if (instr_idx == subop->ninstrs - 1 && 2351 subop->last_instr_end_off) 2352 end_off = subop->last_instr_end_off; 2353 else 2354 end_off = subop->instrs[instr_idx].ctx.addr.naddrs; 2355 2356 return end_off - start_off; 2357 } 2358 EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc); 2359 2360 /** 2361 * nand_subop_get_data_start_off - Get the start offset in a data array 2362 * @subop: The entire sub-operation 2363 * @instr_idx: Index of the instruction inside the sub-operation 2364 * 2365 * During driver development, one could be tempted to directly use the 2366 * ->data->buf.{in,out} field of data instructions. This is wrong as data 2367 * instructions might be split. 2368 * 2369 * Given a data instruction, returns the offset to start from. 2370 */ 2371 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 2372 unsigned int instr_idx) 2373 { 2374 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2375 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2376 return 0; 2377 2378 return nand_subop_get_start_off(subop, instr_idx); 2379 } 2380 EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off); 2381 2382 /** 2383 * nand_subop_get_data_len - Get the number of bytes to retrieve 2384 * @subop: The entire sub-operation 2385 * @instr_idx: Index of the instruction inside the sub-operation 2386 * 2387 * During driver development, one could be tempted to directly use the 2388 * ->data->len field of a data instruction. This is wrong as data instructions 2389 * might be split. 2390 * 2391 * Returns the length of the chunk of data to send/receive. 2392 */ 2393 unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 2394 unsigned int instr_idx) 2395 { 2396 int start_off = 0, end_off; 2397 2398 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) || 2399 !nand_instr_is_data(&subop->instrs[instr_idx]))) 2400 return 0; 2401 2402 start_off = nand_subop_get_data_start_off(subop, instr_idx); 2403 2404 if (instr_idx == subop->ninstrs - 1 && 2405 subop->last_instr_end_off) 2406 end_off = subop->last_instr_end_off; 2407 else 2408 end_off = subop->instrs[instr_idx].ctx.data.len; 2409 2410 return end_off - start_off; 2411 } 2412 EXPORT_SYMBOL_GPL(nand_subop_get_data_len); 2413 2414 /** 2415 * nand_reset - Reset and initialize a NAND device 2416 * @chip: The NAND chip 2417 * @chipnr: Internal die id 2418 * 2419 * Save the timings data structure, then apply SDR timings mode 0 (see 2420 * nand_reset_data_interface for details), do the reset operation, and 2421 * apply back the previous timings. 2422 * 2423 * Returns 0 on success, a negative error code otherwise. 2424 */ 2425 int nand_reset(struct nand_chip *chip, int chipnr) 2426 { 2427 struct nand_data_interface saved_data_intf = chip->data_interface; 2428 int ret; 2429 2430 ret = nand_reset_data_interface(chip, chipnr); 2431 if (ret) 2432 return ret; 2433 2434 /* 2435 * The CS line has to be released before we can apply the new NAND 2436 * interface settings, hence this weird nand_select_target() 2437 * nand_deselect_target() dance. 2438 */ 2439 nand_select_target(chip, chipnr); 2440 ret = nand_reset_op(chip); 2441 nand_deselect_target(chip); 2442 if (ret) 2443 return ret; 2444 2445 /* 2446 * A nand_reset_data_interface() put both the NAND chip and the NAND 2447 * controller in timings mode 0. If the default mode for this chip is 2448 * also 0, no need to proceed to the change again. Plus, at probe time, 2449 * nand_setup_data_interface() uses ->set/get_features() which would 2450 * fail anyway as the parameter page is not available yet. 2451 */ 2452 if (!chip->onfi_timing_mode_default) 2453 return 0; 2454 2455 chip->data_interface = saved_data_intf; 2456 ret = nand_setup_data_interface(chip, chipnr); 2457 if (ret) 2458 return ret; 2459 2460 return 0; 2461 } 2462 EXPORT_SYMBOL_GPL(nand_reset); 2463 2464 /** 2465 * nand_get_features - wrapper to perform a GET_FEATURE 2466 * @chip: NAND chip info structure 2467 * @addr: feature address 2468 * @subfeature_param: the subfeature parameters, a four bytes array 2469 * 2470 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2471 * operation cannot be handled. 2472 */ 2473 int nand_get_features(struct nand_chip *chip, int addr, 2474 u8 *subfeature_param) 2475 { 2476 if (!nand_supports_get_features(chip, addr)) 2477 return -ENOTSUPP; 2478 2479 if (chip->legacy.get_features) 2480 return chip->legacy.get_features(chip, addr, subfeature_param); 2481 2482 return nand_get_features_op(chip, addr, subfeature_param); 2483 } 2484 2485 /** 2486 * nand_set_features - wrapper to perform a SET_FEATURE 2487 * @chip: NAND chip info structure 2488 * @addr: feature address 2489 * @subfeature_param: the subfeature parameters, a four bytes array 2490 * 2491 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the 2492 * operation cannot be handled. 2493 */ 2494 int nand_set_features(struct nand_chip *chip, int addr, 2495 u8 *subfeature_param) 2496 { 2497 if (!nand_supports_set_features(chip, addr)) 2498 return -ENOTSUPP; 2499 2500 if (chip->legacy.set_features) 2501 return chip->legacy.set_features(chip, addr, subfeature_param); 2502 2503 return nand_set_features_op(chip, addr, subfeature_param); 2504 } 2505 2506 /** 2507 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data 2508 * @buf: buffer to test 2509 * @len: buffer length 2510 * @bitflips_threshold: maximum number of bitflips 2511 * 2512 * Check if a buffer contains only 0xff, which means the underlying region 2513 * has been erased and is ready to be programmed. 2514 * The bitflips_threshold specify the maximum number of bitflips before 2515 * considering the region is not erased. 2516 * Note: The logic of this function has been extracted from the memweight 2517 * implementation, except that nand_check_erased_buf function exit before 2518 * testing the whole buffer if the number of bitflips exceed the 2519 * bitflips_threshold value. 2520 * 2521 * Returns a positive number of bitflips less than or equal to 2522 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 2523 * threshold. 2524 */ 2525 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) 2526 { 2527 const unsigned char *bitmap = buf; 2528 int bitflips = 0; 2529 int weight; 2530 2531 for (; len && ((uintptr_t)bitmap) % sizeof(long); 2532 len--, bitmap++) { 2533 weight = hweight8(*bitmap); 2534 bitflips += BITS_PER_BYTE - weight; 2535 if (unlikely(bitflips > bitflips_threshold)) 2536 return -EBADMSG; 2537 } 2538 2539 for (; len >= sizeof(long); 2540 len -= sizeof(long), bitmap += sizeof(long)) { 2541 unsigned long d = *((unsigned long *)bitmap); 2542 if (d == ~0UL) 2543 continue; 2544 weight = hweight_long(d); 2545 bitflips += BITS_PER_LONG - weight; 2546 if (unlikely(bitflips > bitflips_threshold)) 2547 return -EBADMSG; 2548 } 2549 2550 for (; len > 0; len--, bitmap++) { 2551 weight = hweight8(*bitmap); 2552 bitflips += BITS_PER_BYTE - weight; 2553 if (unlikely(bitflips > bitflips_threshold)) 2554 return -EBADMSG; 2555 } 2556 2557 return bitflips; 2558 } 2559 2560 /** 2561 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only 2562 * 0xff data 2563 * @data: data buffer to test 2564 * @datalen: data length 2565 * @ecc: ECC buffer 2566 * @ecclen: ECC length 2567 * @extraoob: extra OOB buffer 2568 * @extraooblen: extra OOB length 2569 * @bitflips_threshold: maximum number of bitflips 2570 * 2571 * Check if a data buffer and its associated ECC and OOB data contains only 2572 * 0xff pattern, which means the underlying region has been erased and is 2573 * ready to be programmed. 2574 * The bitflips_threshold specify the maximum number of bitflips before 2575 * considering the region as not erased. 2576 * 2577 * Note: 2578 * 1/ ECC algorithms are working on pre-defined block sizes which are usually 2579 * different from the NAND page size. When fixing bitflips, ECC engines will 2580 * report the number of errors per chunk, and the NAND core infrastructure 2581 * expect you to return the maximum number of bitflips for the whole page. 2582 * This is why you should always use this function on a single chunk and 2583 * not on the whole page. After checking each chunk you should update your 2584 * max_bitflips value accordingly. 2585 * 2/ When checking for bitflips in erased pages you should not only check 2586 * the payload data but also their associated ECC data, because a user might 2587 * have programmed almost all bits to 1 but a few. In this case, we 2588 * shouldn't consider the chunk as erased, and checking ECC bytes prevent 2589 * this case. 2590 * 3/ The extraoob argument is optional, and should be used if some of your OOB 2591 * data are protected by the ECC engine. 2592 * It could also be used if you support subpages and want to attach some 2593 * extra OOB data to an ECC chunk. 2594 * 2595 * Returns a positive number of bitflips less than or equal to 2596 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 2597 * threshold. In case of success, the passed buffers are filled with 0xff. 2598 */ 2599 int nand_check_erased_ecc_chunk(void *data, int datalen, 2600 void *ecc, int ecclen, 2601 void *extraoob, int extraooblen, 2602 int bitflips_threshold) 2603 { 2604 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; 2605 2606 data_bitflips = nand_check_erased_buf(data, datalen, 2607 bitflips_threshold); 2608 if (data_bitflips < 0) 2609 return data_bitflips; 2610 2611 bitflips_threshold -= data_bitflips; 2612 2613 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); 2614 if (ecc_bitflips < 0) 2615 return ecc_bitflips; 2616 2617 bitflips_threshold -= ecc_bitflips; 2618 2619 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, 2620 bitflips_threshold); 2621 if (extraoob_bitflips < 0) 2622 return extraoob_bitflips; 2623 2624 if (data_bitflips) 2625 memset(data, 0xff, datalen); 2626 2627 if (ecc_bitflips) 2628 memset(ecc, 0xff, ecclen); 2629 2630 if (extraoob_bitflips) 2631 memset(extraoob, 0xff, extraooblen); 2632 2633 return data_bitflips + ecc_bitflips + extraoob_bitflips; 2634 } 2635 EXPORT_SYMBOL(nand_check_erased_ecc_chunk); 2636 2637 /** 2638 * nand_read_page_raw_notsupp - dummy read raw page function 2639 * @chip: nand chip info structure 2640 * @buf: buffer to store read data 2641 * @oob_required: caller requires OOB data read to chip->oob_poi 2642 * @page: page number to read 2643 * 2644 * Returns -ENOTSUPP unconditionally. 2645 */ 2646 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf, 2647 int oob_required, int page) 2648 { 2649 return -ENOTSUPP; 2650 } 2651 2652 /** 2653 * nand_read_page_raw - [INTERN] read raw page data without ecc 2654 * @chip: nand chip info structure 2655 * @buf: buffer to store read data 2656 * @oob_required: caller requires OOB data read to chip->oob_poi 2657 * @page: page number to read 2658 * 2659 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2660 */ 2661 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 2662 int page) 2663 { 2664 struct mtd_info *mtd = nand_to_mtd(chip); 2665 int ret; 2666 2667 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize); 2668 if (ret) 2669 return ret; 2670 2671 if (oob_required) { 2672 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, 2673 false); 2674 if (ret) 2675 return ret; 2676 } 2677 2678 return 0; 2679 } 2680 EXPORT_SYMBOL(nand_read_page_raw); 2681 2682 /** 2683 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 2684 * @chip: nand chip info structure 2685 * @buf: buffer to store read data 2686 * @oob_required: caller requires OOB data read to chip->oob_poi 2687 * @page: page number to read 2688 * 2689 * We need a special oob layout and handling even when OOB isn't used. 2690 */ 2691 static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf, 2692 int oob_required, int page) 2693 { 2694 struct mtd_info *mtd = nand_to_mtd(chip); 2695 int eccsize = chip->ecc.size; 2696 int eccbytes = chip->ecc.bytes; 2697 uint8_t *oob = chip->oob_poi; 2698 int steps, size, ret; 2699 2700 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2701 if (ret) 2702 return ret; 2703 2704 for (steps = chip->ecc.steps; steps > 0; steps--) { 2705 ret = nand_read_data_op(chip, buf, eccsize, false); 2706 if (ret) 2707 return ret; 2708 2709 buf += eccsize; 2710 2711 if (chip->ecc.prepad) { 2712 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 2713 false); 2714 if (ret) 2715 return ret; 2716 2717 oob += chip->ecc.prepad; 2718 } 2719 2720 ret = nand_read_data_op(chip, oob, eccbytes, false); 2721 if (ret) 2722 return ret; 2723 2724 oob += eccbytes; 2725 2726 if (chip->ecc.postpad) { 2727 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 2728 false); 2729 if (ret) 2730 return ret; 2731 2732 oob += chip->ecc.postpad; 2733 } 2734 } 2735 2736 size = mtd->oobsize - (oob - chip->oob_poi); 2737 if (size) { 2738 ret = nand_read_data_op(chip, oob, size, false); 2739 if (ret) 2740 return ret; 2741 } 2742 2743 return 0; 2744 } 2745 2746 /** 2747 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 2748 * @chip: nand chip info structure 2749 * @buf: buffer to store read data 2750 * @oob_required: caller requires OOB data read to chip->oob_poi 2751 * @page: page number to read 2752 */ 2753 static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf, 2754 int oob_required, int page) 2755 { 2756 struct mtd_info *mtd = nand_to_mtd(chip); 2757 int i, eccsize = chip->ecc.size, ret; 2758 int eccbytes = chip->ecc.bytes; 2759 int eccsteps = chip->ecc.steps; 2760 uint8_t *p = buf; 2761 uint8_t *ecc_calc = chip->ecc.calc_buf; 2762 uint8_t *ecc_code = chip->ecc.code_buf; 2763 unsigned int max_bitflips = 0; 2764 2765 chip->ecc.read_page_raw(chip, buf, 1, page); 2766 2767 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 2768 chip->ecc.calculate(chip, p, &ecc_calc[i]); 2769 2770 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 2771 chip->ecc.total); 2772 if (ret) 2773 return ret; 2774 2775 eccsteps = chip->ecc.steps; 2776 p = buf; 2777 2778 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2779 int stat; 2780 2781 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 2782 if (stat < 0) { 2783 mtd->ecc_stats.failed++; 2784 } else { 2785 mtd->ecc_stats.corrected += stat; 2786 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2787 } 2788 } 2789 return max_bitflips; 2790 } 2791 2792 /** 2793 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 2794 * @chip: nand chip info structure 2795 * @data_offs: offset of requested data within the page 2796 * @readlen: data length 2797 * @bufpoi: buffer to store read data 2798 * @page: page number to read 2799 */ 2800 static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs, 2801 uint32_t readlen, uint8_t *bufpoi, int page) 2802 { 2803 struct mtd_info *mtd = nand_to_mtd(chip); 2804 int start_step, end_step, num_steps, ret; 2805 uint8_t *p; 2806 int data_col_addr, i, gaps = 0; 2807 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 2808 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 2809 int index, section = 0; 2810 unsigned int max_bitflips = 0; 2811 struct mtd_oob_region oobregion = { }; 2812 2813 /* Column address within the page aligned to ECC size (256bytes) */ 2814 start_step = data_offs / chip->ecc.size; 2815 end_step = (data_offs + readlen - 1) / chip->ecc.size; 2816 num_steps = end_step - start_step + 1; 2817 index = start_step * chip->ecc.bytes; 2818 2819 /* Data size aligned to ECC ecc.size */ 2820 datafrag_len = num_steps * chip->ecc.size; 2821 eccfrag_len = num_steps * chip->ecc.bytes; 2822 2823 data_col_addr = start_step * chip->ecc.size; 2824 /* If we read not a page aligned data */ 2825 p = bufpoi + data_col_addr; 2826 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len); 2827 if (ret) 2828 return ret; 2829 2830 /* Calculate ECC */ 2831 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 2832 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); 2833 2834 /* 2835 * The performance is faster if we position offsets according to 2836 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 2837 */ 2838 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); 2839 if (ret) 2840 return ret; 2841 2842 if (oobregion.length < eccfrag_len) 2843 gaps = 1; 2844 2845 if (gaps) { 2846 ret = nand_change_read_column_op(chip, mtd->writesize, 2847 chip->oob_poi, mtd->oobsize, 2848 false); 2849 if (ret) 2850 return ret; 2851 } else { 2852 /* 2853 * Send the command to read the particular ECC bytes take care 2854 * about buswidth alignment in read_buf. 2855 */ 2856 aligned_pos = oobregion.offset & ~(busw - 1); 2857 aligned_len = eccfrag_len; 2858 if (oobregion.offset & (busw - 1)) 2859 aligned_len++; 2860 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & 2861 (busw - 1)) 2862 aligned_len++; 2863 2864 ret = nand_change_read_column_op(chip, 2865 mtd->writesize + aligned_pos, 2866 &chip->oob_poi[aligned_pos], 2867 aligned_len, false); 2868 if (ret) 2869 return ret; 2870 } 2871 2872 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, 2873 chip->oob_poi, index, eccfrag_len); 2874 if (ret) 2875 return ret; 2876 2877 p = bufpoi + data_col_addr; 2878 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 2879 int stat; 2880 2881 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], 2882 &chip->ecc.calc_buf[i]); 2883 if (stat == -EBADMSG && 2884 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 2885 /* check for empty pages with bitflips */ 2886 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 2887 &chip->ecc.code_buf[i], 2888 chip->ecc.bytes, 2889 NULL, 0, 2890 chip->ecc.strength); 2891 } 2892 2893 if (stat < 0) { 2894 mtd->ecc_stats.failed++; 2895 } else { 2896 mtd->ecc_stats.corrected += stat; 2897 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2898 } 2899 } 2900 return max_bitflips; 2901 } 2902 2903 /** 2904 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 2905 * @chip: nand chip info structure 2906 * @buf: buffer to store read data 2907 * @oob_required: caller requires OOB data read to chip->oob_poi 2908 * @page: page number to read 2909 * 2910 * Not for syndrome calculating ECC controllers which need a special oob layout. 2911 */ 2912 static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf, 2913 int oob_required, int page) 2914 { 2915 struct mtd_info *mtd = nand_to_mtd(chip); 2916 int i, eccsize = chip->ecc.size, ret; 2917 int eccbytes = chip->ecc.bytes; 2918 int eccsteps = chip->ecc.steps; 2919 uint8_t *p = buf; 2920 uint8_t *ecc_calc = chip->ecc.calc_buf; 2921 uint8_t *ecc_code = chip->ecc.code_buf; 2922 unsigned int max_bitflips = 0; 2923 2924 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2925 if (ret) 2926 return ret; 2927 2928 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2929 chip->ecc.hwctl(chip, NAND_ECC_READ); 2930 2931 ret = nand_read_data_op(chip, p, eccsize, false); 2932 if (ret) 2933 return ret; 2934 2935 chip->ecc.calculate(chip, p, &ecc_calc[i]); 2936 } 2937 2938 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false); 2939 if (ret) 2940 return ret; 2941 2942 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 2943 chip->ecc.total); 2944 if (ret) 2945 return ret; 2946 2947 eccsteps = chip->ecc.steps; 2948 p = buf; 2949 2950 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2951 int stat; 2952 2953 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); 2954 if (stat == -EBADMSG && 2955 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 2956 /* check for empty pages with bitflips */ 2957 stat = nand_check_erased_ecc_chunk(p, eccsize, 2958 &ecc_code[i], eccbytes, 2959 NULL, 0, 2960 chip->ecc.strength); 2961 } 2962 2963 if (stat < 0) { 2964 mtd->ecc_stats.failed++; 2965 } else { 2966 mtd->ecc_stats.corrected += stat; 2967 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2968 } 2969 } 2970 return max_bitflips; 2971 } 2972 2973 /** 2974 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first 2975 * @chip: nand chip info structure 2976 * @buf: buffer to store read data 2977 * @oob_required: caller requires OOB data read to chip->oob_poi 2978 * @page: page number to read 2979 * 2980 * Hardware ECC for large page chips, require OOB to be read first. For this 2981 * ECC mode, the write_page method is re-used from ECC_HW. These methods 2982 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with 2983 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from 2984 * the data area, by overwriting the NAND manufacturer bad block markings. 2985 */ 2986 static int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf, 2987 int oob_required, int page) 2988 { 2989 struct mtd_info *mtd = nand_to_mtd(chip); 2990 int i, eccsize = chip->ecc.size, ret; 2991 int eccbytes = chip->ecc.bytes; 2992 int eccsteps = chip->ecc.steps; 2993 uint8_t *p = buf; 2994 uint8_t *ecc_code = chip->ecc.code_buf; 2995 uint8_t *ecc_calc = chip->ecc.calc_buf; 2996 unsigned int max_bitflips = 0; 2997 2998 /* Read the OOB area first */ 2999 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3000 if (ret) 3001 return ret; 3002 3003 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3004 if (ret) 3005 return ret; 3006 3007 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 3008 chip->ecc.total); 3009 if (ret) 3010 return ret; 3011 3012 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3013 int stat; 3014 3015 chip->ecc.hwctl(chip, NAND_ECC_READ); 3016 3017 ret = nand_read_data_op(chip, p, eccsize, false); 3018 if (ret) 3019 return ret; 3020 3021 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3022 3023 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL); 3024 if (stat == -EBADMSG && 3025 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3026 /* check for empty pages with bitflips */ 3027 stat = nand_check_erased_ecc_chunk(p, eccsize, 3028 &ecc_code[i], eccbytes, 3029 NULL, 0, 3030 chip->ecc.strength); 3031 } 3032 3033 if (stat < 0) { 3034 mtd->ecc_stats.failed++; 3035 } else { 3036 mtd->ecc_stats.corrected += stat; 3037 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3038 } 3039 } 3040 return max_bitflips; 3041 } 3042 3043 /** 3044 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 3045 * @chip: nand chip info structure 3046 * @buf: buffer to store read data 3047 * @oob_required: caller requires OOB data read to chip->oob_poi 3048 * @page: page number to read 3049 * 3050 * The hw generator calculates the error syndrome automatically. Therefore we 3051 * need a special oob layout and handling. 3052 */ 3053 static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf, 3054 int oob_required, int page) 3055 { 3056 struct mtd_info *mtd = nand_to_mtd(chip); 3057 int ret, i, eccsize = chip->ecc.size; 3058 int eccbytes = chip->ecc.bytes; 3059 int eccsteps = chip->ecc.steps; 3060 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 3061 uint8_t *p = buf; 3062 uint8_t *oob = chip->oob_poi; 3063 unsigned int max_bitflips = 0; 3064 3065 ret = nand_read_page_op(chip, page, 0, NULL, 0); 3066 if (ret) 3067 return ret; 3068 3069 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3070 int stat; 3071 3072 chip->ecc.hwctl(chip, NAND_ECC_READ); 3073 3074 ret = nand_read_data_op(chip, p, eccsize, false); 3075 if (ret) 3076 return ret; 3077 3078 if (chip->ecc.prepad) { 3079 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 3080 false); 3081 if (ret) 3082 return ret; 3083 3084 oob += chip->ecc.prepad; 3085 } 3086 3087 chip->ecc.hwctl(chip, NAND_ECC_READSYN); 3088 3089 ret = nand_read_data_op(chip, oob, eccbytes, false); 3090 if (ret) 3091 return ret; 3092 3093 stat = chip->ecc.correct(chip, p, oob, NULL); 3094 3095 oob += eccbytes; 3096 3097 if (chip->ecc.postpad) { 3098 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 3099 false); 3100 if (ret) 3101 return ret; 3102 3103 oob += chip->ecc.postpad; 3104 } 3105 3106 if (stat == -EBADMSG && 3107 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 3108 /* check for empty pages with bitflips */ 3109 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 3110 oob - eccpadbytes, 3111 eccpadbytes, 3112 NULL, 0, 3113 chip->ecc.strength); 3114 } 3115 3116 if (stat < 0) { 3117 mtd->ecc_stats.failed++; 3118 } else { 3119 mtd->ecc_stats.corrected += stat; 3120 max_bitflips = max_t(unsigned int, max_bitflips, stat); 3121 } 3122 } 3123 3124 /* Calculate remaining oob bytes */ 3125 i = mtd->oobsize - (oob - chip->oob_poi); 3126 if (i) { 3127 ret = nand_read_data_op(chip, oob, i, false); 3128 if (ret) 3129 return ret; 3130 } 3131 3132 return max_bitflips; 3133 } 3134 3135 /** 3136 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 3137 * @chip: NAND chip object 3138 * @oob: oob destination address 3139 * @ops: oob ops structure 3140 * @len: size of oob to transfer 3141 */ 3142 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 3143 struct mtd_oob_ops *ops, size_t len) 3144 { 3145 struct mtd_info *mtd = nand_to_mtd(chip); 3146 int ret; 3147 3148 switch (ops->mode) { 3149 3150 case MTD_OPS_PLACE_OOB: 3151 case MTD_OPS_RAW: 3152 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 3153 return oob + len; 3154 3155 case MTD_OPS_AUTO_OOB: 3156 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, 3157 ops->ooboffs, len); 3158 BUG_ON(ret); 3159 return oob + len; 3160 3161 default: 3162 BUG(); 3163 } 3164 return NULL; 3165 } 3166 3167 /** 3168 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 3169 * @chip: NAND chip object 3170 * @retry_mode: the retry mode to use 3171 * 3172 * Some vendors supply a special command to shift the Vt threshold, to be used 3173 * when there are too many bitflips in a page (i.e., ECC error). After setting 3174 * a new threshold, the host should retry reading the page. 3175 */ 3176 static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode) 3177 { 3178 pr_debug("setting READ RETRY mode %d\n", retry_mode); 3179 3180 if (retry_mode >= chip->read_retries) 3181 return -EINVAL; 3182 3183 if (!chip->setup_read_retry) 3184 return -EOPNOTSUPP; 3185 3186 return chip->setup_read_retry(chip, retry_mode); 3187 } 3188 3189 static void nand_wait_readrdy(struct nand_chip *chip) 3190 { 3191 const struct nand_sdr_timings *sdr; 3192 3193 if (!(chip->options & NAND_NEED_READRDY)) 3194 return; 3195 3196 sdr = nand_get_sdr_timings(&chip->data_interface); 3197 WARN_ON(nand_wait_rdy_op(chip, PSEC_TO_MSEC(sdr->tR_max), 0)); 3198 } 3199 3200 /** 3201 * nand_do_read_ops - [INTERN] Read data with ECC 3202 * @chip: NAND chip object 3203 * @from: offset to read from 3204 * @ops: oob ops structure 3205 * 3206 * Internal function. Called with chip held. 3207 */ 3208 static int nand_do_read_ops(struct nand_chip *chip, loff_t from, 3209 struct mtd_oob_ops *ops) 3210 { 3211 int chipnr, page, realpage, col, bytes, aligned, oob_required; 3212 struct mtd_info *mtd = nand_to_mtd(chip); 3213 int ret = 0; 3214 uint32_t readlen = ops->len; 3215 uint32_t oobreadlen = ops->ooblen; 3216 uint32_t max_oobsize = mtd_oobavail(mtd, ops); 3217 3218 uint8_t *bufpoi, *oob, *buf; 3219 int use_bounce_buf; 3220 unsigned int max_bitflips = 0; 3221 int retry_mode = 0; 3222 bool ecc_fail = false; 3223 3224 chipnr = (int)(from >> chip->chip_shift); 3225 nand_select_target(chip, chipnr); 3226 3227 realpage = (int)(from >> chip->page_shift); 3228 page = realpage & chip->pagemask; 3229 3230 col = (int)(from & (mtd->writesize - 1)); 3231 3232 buf = ops->datbuf; 3233 oob = ops->oobbuf; 3234 oob_required = oob ? 1 : 0; 3235 3236 while (1) { 3237 unsigned int ecc_failures = mtd->ecc_stats.failed; 3238 3239 bytes = min(mtd->writesize - col, readlen); 3240 aligned = (bytes == mtd->writesize); 3241 3242 if (!aligned) 3243 use_bounce_buf = 1; 3244 else if (chip->options & NAND_USES_DMA) 3245 use_bounce_buf = !virt_addr_valid(buf) || 3246 !IS_ALIGNED((unsigned long)buf, 3247 chip->buf_align); 3248 else 3249 use_bounce_buf = 0; 3250 3251 /* Is the current page in the buffer? */ 3252 if (realpage != chip->pagecache.page || oob) { 3253 bufpoi = use_bounce_buf ? chip->data_buf : buf; 3254 3255 if (use_bounce_buf && aligned) 3256 pr_debug("%s: using read bounce buffer for buf@%p\n", 3257 __func__, buf); 3258 3259 read_retry: 3260 /* 3261 * Now read the page into the buffer. Absent an error, 3262 * the read methods return max bitflips per ecc step. 3263 */ 3264 if (unlikely(ops->mode == MTD_OPS_RAW)) 3265 ret = chip->ecc.read_page_raw(chip, bufpoi, 3266 oob_required, 3267 page); 3268 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 3269 !oob) 3270 ret = chip->ecc.read_subpage(chip, col, bytes, 3271 bufpoi, page); 3272 else 3273 ret = chip->ecc.read_page(chip, bufpoi, 3274 oob_required, page); 3275 if (ret < 0) { 3276 if (use_bounce_buf) 3277 /* Invalidate page cache */ 3278 chip->pagecache.page = -1; 3279 break; 3280 } 3281 3282 /* 3283 * Copy back the data in the initial buffer when reading 3284 * partial pages or when a bounce buffer is required. 3285 */ 3286 if (use_bounce_buf) { 3287 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 3288 !(mtd->ecc_stats.failed - ecc_failures) && 3289 (ops->mode != MTD_OPS_RAW)) { 3290 chip->pagecache.page = realpage; 3291 chip->pagecache.bitflips = ret; 3292 } else { 3293 /* Invalidate page cache */ 3294 chip->pagecache.page = -1; 3295 } 3296 memcpy(buf, bufpoi + col, bytes); 3297 } 3298 3299 if (unlikely(oob)) { 3300 int toread = min(oobreadlen, max_oobsize); 3301 3302 if (toread) { 3303 oob = nand_transfer_oob(chip, oob, ops, 3304 toread); 3305 oobreadlen -= toread; 3306 } 3307 } 3308 3309 nand_wait_readrdy(chip); 3310 3311 if (mtd->ecc_stats.failed - ecc_failures) { 3312 if (retry_mode + 1 < chip->read_retries) { 3313 retry_mode++; 3314 ret = nand_setup_read_retry(chip, 3315 retry_mode); 3316 if (ret < 0) 3317 break; 3318 3319 /* Reset failures; retry */ 3320 mtd->ecc_stats.failed = ecc_failures; 3321 goto read_retry; 3322 } else { 3323 /* No more retry modes; real failure */ 3324 ecc_fail = true; 3325 } 3326 } 3327 3328 buf += bytes; 3329 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3330 } else { 3331 memcpy(buf, chip->data_buf + col, bytes); 3332 buf += bytes; 3333 max_bitflips = max_t(unsigned int, max_bitflips, 3334 chip->pagecache.bitflips); 3335 } 3336 3337 readlen -= bytes; 3338 3339 /* Reset to retry mode 0 */ 3340 if (retry_mode) { 3341 ret = nand_setup_read_retry(chip, 0); 3342 if (ret < 0) 3343 break; 3344 retry_mode = 0; 3345 } 3346 3347 if (!readlen) 3348 break; 3349 3350 /* For subsequent reads align to page boundary */ 3351 col = 0; 3352 /* Increment page address */ 3353 realpage++; 3354 3355 page = realpage & chip->pagemask; 3356 /* Check, if we cross a chip boundary */ 3357 if (!page) { 3358 chipnr++; 3359 nand_deselect_target(chip); 3360 nand_select_target(chip, chipnr); 3361 } 3362 } 3363 nand_deselect_target(chip); 3364 3365 ops->retlen = ops->len - (size_t) readlen; 3366 if (oob) 3367 ops->oobretlen = ops->ooblen - oobreadlen; 3368 3369 if (ret < 0) 3370 return ret; 3371 3372 if (ecc_fail) 3373 return -EBADMSG; 3374 3375 return max_bitflips; 3376 } 3377 3378 /** 3379 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 3380 * @chip: nand chip info structure 3381 * @page: page number to read 3382 */ 3383 int nand_read_oob_std(struct nand_chip *chip, int page) 3384 { 3385 struct mtd_info *mtd = nand_to_mtd(chip); 3386 3387 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 3388 } 3389 EXPORT_SYMBOL(nand_read_oob_std); 3390 3391 /** 3392 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 3393 * with syndromes 3394 * @chip: nand chip info structure 3395 * @page: page number to read 3396 */ 3397 static int nand_read_oob_syndrome(struct nand_chip *chip, int page) 3398 { 3399 struct mtd_info *mtd = nand_to_mtd(chip); 3400 int length = mtd->oobsize; 3401 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3402 int eccsize = chip->ecc.size; 3403 uint8_t *bufpoi = chip->oob_poi; 3404 int i, toread, sndrnd = 0, pos, ret; 3405 3406 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); 3407 if (ret) 3408 return ret; 3409 3410 for (i = 0; i < chip->ecc.steps; i++) { 3411 if (sndrnd) { 3412 int ret; 3413 3414 pos = eccsize + i * (eccsize + chunk); 3415 if (mtd->writesize > 512) 3416 ret = nand_change_read_column_op(chip, pos, 3417 NULL, 0, 3418 false); 3419 else 3420 ret = nand_read_page_op(chip, page, pos, NULL, 3421 0); 3422 3423 if (ret) 3424 return ret; 3425 } else 3426 sndrnd = 1; 3427 toread = min_t(int, length, chunk); 3428 3429 ret = nand_read_data_op(chip, bufpoi, toread, false); 3430 if (ret) 3431 return ret; 3432 3433 bufpoi += toread; 3434 length -= toread; 3435 } 3436 if (length > 0) { 3437 ret = nand_read_data_op(chip, bufpoi, length, false); 3438 if (ret) 3439 return ret; 3440 } 3441 3442 return 0; 3443 } 3444 3445 /** 3446 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 3447 * @chip: nand chip info structure 3448 * @page: page number to write 3449 */ 3450 int nand_write_oob_std(struct nand_chip *chip, int page) 3451 { 3452 struct mtd_info *mtd = nand_to_mtd(chip); 3453 3454 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 3455 mtd->oobsize); 3456 } 3457 EXPORT_SYMBOL(nand_write_oob_std); 3458 3459 /** 3460 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 3461 * with syndrome - only for large page flash 3462 * @chip: nand chip info structure 3463 * @page: page number to write 3464 */ 3465 static int nand_write_oob_syndrome(struct nand_chip *chip, int page) 3466 { 3467 struct mtd_info *mtd = nand_to_mtd(chip); 3468 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 3469 int eccsize = chip->ecc.size, length = mtd->oobsize; 3470 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; 3471 const uint8_t *bufpoi = chip->oob_poi; 3472 3473 /* 3474 * data-ecc-data-ecc ... ecc-oob 3475 * or 3476 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 3477 */ 3478 if (!chip->ecc.prepad && !chip->ecc.postpad) { 3479 pos = steps * (eccsize + chunk); 3480 steps = 0; 3481 } else 3482 pos = eccsize; 3483 3484 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0); 3485 if (ret) 3486 return ret; 3487 3488 for (i = 0; i < steps; i++) { 3489 if (sndcmd) { 3490 if (mtd->writesize <= 512) { 3491 uint32_t fill = 0xFFFFFFFF; 3492 3493 len = eccsize; 3494 while (len > 0) { 3495 int num = min_t(int, len, 4); 3496 3497 ret = nand_write_data_op(chip, &fill, 3498 num, false); 3499 if (ret) 3500 return ret; 3501 3502 len -= num; 3503 } 3504 } else { 3505 pos = eccsize + i * (eccsize + chunk); 3506 ret = nand_change_write_column_op(chip, pos, 3507 NULL, 0, 3508 false); 3509 if (ret) 3510 return ret; 3511 } 3512 } else 3513 sndcmd = 1; 3514 len = min_t(int, length, chunk); 3515 3516 ret = nand_write_data_op(chip, bufpoi, len, false); 3517 if (ret) 3518 return ret; 3519 3520 bufpoi += len; 3521 length -= len; 3522 } 3523 if (length > 0) { 3524 ret = nand_write_data_op(chip, bufpoi, length, false); 3525 if (ret) 3526 return ret; 3527 } 3528 3529 return nand_prog_page_end_op(chip); 3530 } 3531 3532 /** 3533 * nand_do_read_oob - [INTERN] NAND read out-of-band 3534 * @chip: NAND chip object 3535 * @from: offset to read from 3536 * @ops: oob operations description structure 3537 * 3538 * NAND read out-of-band data from the spare area. 3539 */ 3540 static int nand_do_read_oob(struct nand_chip *chip, loff_t from, 3541 struct mtd_oob_ops *ops) 3542 { 3543 struct mtd_info *mtd = nand_to_mtd(chip); 3544 unsigned int max_bitflips = 0; 3545 int page, realpage, chipnr; 3546 struct mtd_ecc_stats stats; 3547 int readlen = ops->ooblen; 3548 int len; 3549 uint8_t *buf = ops->oobbuf; 3550 int ret = 0; 3551 3552 pr_debug("%s: from = 0x%08Lx, len = %i\n", 3553 __func__, (unsigned long long)from, readlen); 3554 3555 stats = mtd->ecc_stats; 3556 3557 len = mtd_oobavail(mtd, ops); 3558 3559 chipnr = (int)(from >> chip->chip_shift); 3560 nand_select_target(chip, chipnr); 3561 3562 /* Shift to get page */ 3563 realpage = (int)(from >> chip->page_shift); 3564 page = realpage & chip->pagemask; 3565 3566 while (1) { 3567 if (ops->mode == MTD_OPS_RAW) 3568 ret = chip->ecc.read_oob_raw(chip, page); 3569 else 3570 ret = chip->ecc.read_oob(chip, page); 3571 3572 if (ret < 0) 3573 break; 3574 3575 len = min(len, readlen); 3576 buf = nand_transfer_oob(chip, buf, ops, len); 3577 3578 nand_wait_readrdy(chip); 3579 3580 max_bitflips = max_t(unsigned int, max_bitflips, ret); 3581 3582 readlen -= len; 3583 if (!readlen) 3584 break; 3585 3586 /* Increment page address */ 3587 realpage++; 3588 3589 page = realpage & chip->pagemask; 3590 /* Check, if we cross a chip boundary */ 3591 if (!page) { 3592 chipnr++; 3593 nand_deselect_target(chip); 3594 nand_select_target(chip, chipnr); 3595 } 3596 } 3597 nand_deselect_target(chip); 3598 3599 ops->oobretlen = ops->ooblen - readlen; 3600 3601 if (ret < 0) 3602 return ret; 3603 3604 if (mtd->ecc_stats.failed - stats.failed) 3605 return -EBADMSG; 3606 3607 return max_bitflips; 3608 } 3609 3610 /** 3611 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 3612 * @mtd: MTD device structure 3613 * @from: offset to read from 3614 * @ops: oob operation description structure 3615 * 3616 * NAND read data and/or out-of-band data. 3617 */ 3618 static int nand_read_oob(struct mtd_info *mtd, loff_t from, 3619 struct mtd_oob_ops *ops) 3620 { 3621 struct nand_chip *chip = mtd_to_nand(mtd); 3622 int ret; 3623 3624 ops->retlen = 0; 3625 3626 if (ops->mode != MTD_OPS_PLACE_OOB && 3627 ops->mode != MTD_OPS_AUTO_OOB && 3628 ops->mode != MTD_OPS_RAW) 3629 return -ENOTSUPP; 3630 3631 ret = nand_get_device(chip); 3632 if (ret) 3633 return ret; 3634 3635 if (!ops->datbuf) 3636 ret = nand_do_read_oob(chip, from, ops); 3637 else 3638 ret = nand_do_read_ops(chip, from, ops); 3639 3640 nand_release_device(chip); 3641 return ret; 3642 } 3643 3644 /** 3645 * nand_write_page_raw_notsupp - dummy raw page write function 3646 * @chip: nand chip info structure 3647 * @buf: data buffer 3648 * @oob_required: must write chip->oob_poi to OOB 3649 * @page: page number to write 3650 * 3651 * Returns -ENOTSUPP unconditionally. 3652 */ 3653 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf, 3654 int oob_required, int page) 3655 { 3656 return -ENOTSUPP; 3657 } 3658 3659 /** 3660 * nand_write_page_raw - [INTERN] raw page write function 3661 * @chip: nand chip info structure 3662 * @buf: data buffer 3663 * @oob_required: must write chip->oob_poi to OOB 3664 * @page: page number to write 3665 * 3666 * Not for syndrome calculating ECC controllers, which use a special oob layout. 3667 */ 3668 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 3669 int oob_required, int page) 3670 { 3671 struct mtd_info *mtd = nand_to_mtd(chip); 3672 int ret; 3673 3674 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); 3675 if (ret) 3676 return ret; 3677 3678 if (oob_required) { 3679 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, 3680 false); 3681 if (ret) 3682 return ret; 3683 } 3684 3685 return nand_prog_page_end_op(chip); 3686 } 3687 EXPORT_SYMBOL(nand_write_page_raw); 3688 3689 /** 3690 * nand_write_page_raw_syndrome - [INTERN] raw page write function 3691 * @chip: nand chip info structure 3692 * @buf: data buffer 3693 * @oob_required: must write chip->oob_poi to OOB 3694 * @page: page number to write 3695 * 3696 * We need a special oob layout and handling even when ECC isn't checked. 3697 */ 3698 static int nand_write_page_raw_syndrome(struct nand_chip *chip, 3699 const uint8_t *buf, int oob_required, 3700 int page) 3701 { 3702 struct mtd_info *mtd = nand_to_mtd(chip); 3703 int eccsize = chip->ecc.size; 3704 int eccbytes = chip->ecc.bytes; 3705 uint8_t *oob = chip->oob_poi; 3706 int steps, size, ret; 3707 3708 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 3709 if (ret) 3710 return ret; 3711 3712 for (steps = chip->ecc.steps; steps > 0; steps--) { 3713 ret = nand_write_data_op(chip, buf, eccsize, false); 3714 if (ret) 3715 return ret; 3716 3717 buf += eccsize; 3718 3719 if (chip->ecc.prepad) { 3720 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 3721 false); 3722 if (ret) 3723 return ret; 3724 3725 oob += chip->ecc.prepad; 3726 } 3727 3728 ret = nand_write_data_op(chip, oob, eccbytes, false); 3729 if (ret) 3730 return ret; 3731 3732 oob += eccbytes; 3733 3734 if (chip->ecc.postpad) { 3735 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 3736 false); 3737 if (ret) 3738 return ret; 3739 3740 oob += chip->ecc.postpad; 3741 } 3742 } 3743 3744 size = mtd->oobsize - (oob - chip->oob_poi); 3745 if (size) { 3746 ret = nand_write_data_op(chip, oob, size, false); 3747 if (ret) 3748 return ret; 3749 } 3750 3751 return nand_prog_page_end_op(chip); 3752 } 3753 /** 3754 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 3755 * @chip: nand chip info structure 3756 * @buf: data buffer 3757 * @oob_required: must write chip->oob_poi to OOB 3758 * @page: page number to write 3759 */ 3760 static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf, 3761 int oob_required, int page) 3762 { 3763 struct mtd_info *mtd = nand_to_mtd(chip); 3764 int i, eccsize = chip->ecc.size, ret; 3765 int eccbytes = chip->ecc.bytes; 3766 int eccsteps = chip->ecc.steps; 3767 uint8_t *ecc_calc = chip->ecc.calc_buf; 3768 const uint8_t *p = buf; 3769 3770 /* Software ECC calculation */ 3771 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 3772 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3773 3774 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 3775 chip->ecc.total); 3776 if (ret) 3777 return ret; 3778 3779 return chip->ecc.write_page_raw(chip, buf, 1, page); 3780 } 3781 3782 /** 3783 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 3784 * @chip: nand chip info structure 3785 * @buf: data buffer 3786 * @oob_required: must write chip->oob_poi to OOB 3787 * @page: page number to write 3788 */ 3789 static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf, 3790 int oob_required, int page) 3791 { 3792 struct mtd_info *mtd = nand_to_mtd(chip); 3793 int i, eccsize = chip->ecc.size, ret; 3794 int eccbytes = chip->ecc.bytes; 3795 int eccsteps = chip->ecc.steps; 3796 uint8_t *ecc_calc = chip->ecc.calc_buf; 3797 const uint8_t *p = buf; 3798 3799 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 3800 if (ret) 3801 return ret; 3802 3803 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3804 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 3805 3806 ret = nand_write_data_op(chip, p, eccsize, false); 3807 if (ret) 3808 return ret; 3809 3810 chip->ecc.calculate(chip, p, &ecc_calc[i]); 3811 } 3812 3813 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 3814 chip->ecc.total); 3815 if (ret) 3816 return ret; 3817 3818 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 3819 if (ret) 3820 return ret; 3821 3822 return nand_prog_page_end_op(chip); 3823 } 3824 3825 3826 /** 3827 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write 3828 * @chip: nand chip info structure 3829 * @offset: column address of subpage within the page 3830 * @data_len: data length 3831 * @buf: data buffer 3832 * @oob_required: must write chip->oob_poi to OOB 3833 * @page: page number to write 3834 */ 3835 static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset, 3836 uint32_t data_len, const uint8_t *buf, 3837 int oob_required, int page) 3838 { 3839 struct mtd_info *mtd = nand_to_mtd(chip); 3840 uint8_t *oob_buf = chip->oob_poi; 3841 uint8_t *ecc_calc = chip->ecc.calc_buf; 3842 int ecc_size = chip->ecc.size; 3843 int ecc_bytes = chip->ecc.bytes; 3844 int ecc_steps = chip->ecc.steps; 3845 uint32_t start_step = offset / ecc_size; 3846 uint32_t end_step = (offset + data_len - 1) / ecc_size; 3847 int oob_bytes = mtd->oobsize / ecc_steps; 3848 int step, ret; 3849 3850 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 3851 if (ret) 3852 return ret; 3853 3854 for (step = 0; step < ecc_steps; step++) { 3855 /* configure controller for WRITE access */ 3856 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 3857 3858 /* write data (untouched subpages already masked by 0xFF) */ 3859 ret = nand_write_data_op(chip, buf, ecc_size, false); 3860 if (ret) 3861 return ret; 3862 3863 /* mask ECC of un-touched subpages by padding 0xFF */ 3864 if ((step < start_step) || (step > end_step)) 3865 memset(ecc_calc, 0xff, ecc_bytes); 3866 else 3867 chip->ecc.calculate(chip, buf, ecc_calc); 3868 3869 /* mask OOB of un-touched subpages by padding 0xFF */ 3870 /* if oob_required, preserve OOB metadata of written subpage */ 3871 if (!oob_required || (step < start_step) || (step > end_step)) 3872 memset(oob_buf, 0xff, oob_bytes); 3873 3874 buf += ecc_size; 3875 ecc_calc += ecc_bytes; 3876 oob_buf += oob_bytes; 3877 } 3878 3879 /* copy calculated ECC for whole page to chip->buffer->oob */ 3880 /* this include masked-value(0xFF) for unwritten subpages */ 3881 ecc_calc = chip->ecc.calc_buf; 3882 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, 3883 chip->ecc.total); 3884 if (ret) 3885 return ret; 3886 3887 /* write OOB buffer to NAND device */ 3888 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 3889 if (ret) 3890 return ret; 3891 3892 return nand_prog_page_end_op(chip); 3893 } 3894 3895 3896 /** 3897 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 3898 * @chip: nand chip info structure 3899 * @buf: data buffer 3900 * @oob_required: must write chip->oob_poi to OOB 3901 * @page: page number to write 3902 * 3903 * The hw generator calculates the error syndrome automatically. Therefore we 3904 * need a special oob layout and handling. 3905 */ 3906 static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf, 3907 int oob_required, int page) 3908 { 3909 struct mtd_info *mtd = nand_to_mtd(chip); 3910 int i, eccsize = chip->ecc.size; 3911 int eccbytes = chip->ecc.bytes; 3912 int eccsteps = chip->ecc.steps; 3913 const uint8_t *p = buf; 3914 uint8_t *oob = chip->oob_poi; 3915 int ret; 3916 3917 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 3918 if (ret) 3919 return ret; 3920 3921 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3922 chip->ecc.hwctl(chip, NAND_ECC_WRITE); 3923 3924 ret = nand_write_data_op(chip, p, eccsize, false); 3925 if (ret) 3926 return ret; 3927 3928 if (chip->ecc.prepad) { 3929 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 3930 false); 3931 if (ret) 3932 return ret; 3933 3934 oob += chip->ecc.prepad; 3935 } 3936 3937 chip->ecc.calculate(chip, p, oob); 3938 3939 ret = nand_write_data_op(chip, oob, eccbytes, false); 3940 if (ret) 3941 return ret; 3942 3943 oob += eccbytes; 3944 3945 if (chip->ecc.postpad) { 3946 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 3947 false); 3948 if (ret) 3949 return ret; 3950 3951 oob += chip->ecc.postpad; 3952 } 3953 } 3954 3955 /* Calculate remaining oob bytes */ 3956 i = mtd->oobsize - (oob - chip->oob_poi); 3957 if (i) { 3958 ret = nand_write_data_op(chip, oob, i, false); 3959 if (ret) 3960 return ret; 3961 } 3962 3963 return nand_prog_page_end_op(chip); 3964 } 3965 3966 /** 3967 * nand_write_page - write one page 3968 * @chip: NAND chip descriptor 3969 * @offset: address offset within the page 3970 * @data_len: length of actual data to be written 3971 * @buf: the data to write 3972 * @oob_required: must write chip->oob_poi to OOB 3973 * @page: page number to write 3974 * @raw: use _raw version of write_page 3975 */ 3976 static int nand_write_page(struct nand_chip *chip, uint32_t offset, 3977 int data_len, const uint8_t *buf, int oob_required, 3978 int page, int raw) 3979 { 3980 struct mtd_info *mtd = nand_to_mtd(chip); 3981 int status, subpage; 3982 3983 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 3984 chip->ecc.write_subpage) 3985 subpage = offset || (data_len < mtd->writesize); 3986 else 3987 subpage = 0; 3988 3989 if (unlikely(raw)) 3990 status = chip->ecc.write_page_raw(chip, buf, oob_required, 3991 page); 3992 else if (subpage) 3993 status = chip->ecc.write_subpage(chip, offset, data_len, buf, 3994 oob_required, page); 3995 else 3996 status = chip->ecc.write_page(chip, buf, oob_required, page); 3997 3998 if (status < 0) 3999 return status; 4000 4001 return 0; 4002 } 4003 4004 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 4005 4006 /** 4007 * nand_do_write_ops - [INTERN] NAND write with ECC 4008 * @chip: NAND chip object 4009 * @to: offset to write to 4010 * @ops: oob operations description structure 4011 * 4012 * NAND write with ECC. 4013 */ 4014 static int nand_do_write_ops(struct nand_chip *chip, loff_t to, 4015 struct mtd_oob_ops *ops) 4016 { 4017 struct mtd_info *mtd = nand_to_mtd(chip); 4018 int chipnr, realpage, page, column; 4019 uint32_t writelen = ops->len; 4020 4021 uint32_t oobwritelen = ops->ooblen; 4022 uint32_t oobmaxlen = mtd_oobavail(mtd, ops); 4023 4024 uint8_t *oob = ops->oobbuf; 4025 uint8_t *buf = ops->datbuf; 4026 int ret; 4027 int oob_required = oob ? 1 : 0; 4028 4029 ops->retlen = 0; 4030 if (!writelen) 4031 return 0; 4032 4033 /* Reject writes, which are not page aligned */ 4034 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { 4035 pr_notice("%s: attempt to write non page aligned data\n", 4036 __func__); 4037 return -EINVAL; 4038 } 4039 4040 column = to & (mtd->writesize - 1); 4041 4042 chipnr = (int)(to >> chip->chip_shift); 4043 nand_select_target(chip, chipnr); 4044 4045 /* Check, if it is write protected */ 4046 if (nand_check_wp(chip)) { 4047 ret = -EIO; 4048 goto err_out; 4049 } 4050 4051 realpage = (int)(to >> chip->page_shift); 4052 page = realpage & chip->pagemask; 4053 4054 /* Invalidate the page cache, when we write to the cached page */ 4055 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) && 4056 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len)) 4057 chip->pagecache.page = -1; 4058 4059 /* Don't allow multipage oob writes with offset */ 4060 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 4061 ret = -EINVAL; 4062 goto err_out; 4063 } 4064 4065 while (1) { 4066 int bytes = mtd->writesize; 4067 uint8_t *wbuf = buf; 4068 int use_bounce_buf; 4069 int part_pagewr = (column || writelen < mtd->writesize); 4070 4071 if (part_pagewr) 4072 use_bounce_buf = 1; 4073 else if (chip->options & NAND_USES_DMA) 4074 use_bounce_buf = !virt_addr_valid(buf) || 4075 !IS_ALIGNED((unsigned long)buf, 4076 chip->buf_align); 4077 else 4078 use_bounce_buf = 0; 4079 4080 /* 4081 * Copy the data from the initial buffer when doing partial page 4082 * writes or when a bounce buffer is required. 4083 */ 4084 if (use_bounce_buf) { 4085 pr_debug("%s: using write bounce buffer for buf@%p\n", 4086 __func__, buf); 4087 if (part_pagewr) 4088 bytes = min_t(int, bytes - column, writelen); 4089 wbuf = nand_get_data_buf(chip); 4090 memset(wbuf, 0xff, mtd->writesize); 4091 memcpy(&wbuf[column], buf, bytes); 4092 } 4093 4094 if (unlikely(oob)) { 4095 size_t len = min(oobwritelen, oobmaxlen); 4096 oob = nand_fill_oob(chip, oob, len, ops); 4097 oobwritelen -= len; 4098 } else { 4099 /* We still need to erase leftover OOB data */ 4100 memset(chip->oob_poi, 0xff, mtd->oobsize); 4101 } 4102 4103 ret = nand_write_page(chip, column, bytes, wbuf, 4104 oob_required, page, 4105 (ops->mode == MTD_OPS_RAW)); 4106 if (ret) 4107 break; 4108 4109 writelen -= bytes; 4110 if (!writelen) 4111 break; 4112 4113 column = 0; 4114 buf += bytes; 4115 realpage++; 4116 4117 page = realpage & chip->pagemask; 4118 /* Check, if we cross a chip boundary */ 4119 if (!page) { 4120 chipnr++; 4121 nand_deselect_target(chip); 4122 nand_select_target(chip, chipnr); 4123 } 4124 } 4125 4126 ops->retlen = ops->len - writelen; 4127 if (unlikely(oob)) 4128 ops->oobretlen = ops->ooblen; 4129 4130 err_out: 4131 nand_deselect_target(chip); 4132 return ret; 4133 } 4134 4135 /** 4136 * panic_nand_write - [MTD Interface] NAND write with ECC 4137 * @mtd: MTD device structure 4138 * @to: offset to write to 4139 * @len: number of bytes to write 4140 * @retlen: pointer to variable to store the number of written bytes 4141 * @buf: the data to write 4142 * 4143 * NAND write with ECC. Used when performing writes in interrupt context, this 4144 * may for example be called by mtdoops when writing an oops while in panic. 4145 */ 4146 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 4147 size_t *retlen, const uint8_t *buf) 4148 { 4149 struct nand_chip *chip = mtd_to_nand(mtd); 4150 int chipnr = (int)(to >> chip->chip_shift); 4151 struct mtd_oob_ops ops; 4152 int ret; 4153 4154 nand_select_target(chip, chipnr); 4155 4156 /* Wait for the device to get ready */ 4157 panic_nand_wait(chip, 400); 4158 4159 memset(&ops, 0, sizeof(ops)); 4160 ops.len = len; 4161 ops.datbuf = (uint8_t *)buf; 4162 ops.mode = MTD_OPS_PLACE_OOB; 4163 4164 ret = nand_do_write_ops(chip, to, &ops); 4165 4166 *retlen = ops.retlen; 4167 return ret; 4168 } 4169 4170 /** 4171 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 4172 * @mtd: MTD device structure 4173 * @to: offset to write to 4174 * @ops: oob operation description structure 4175 */ 4176 static int nand_write_oob(struct mtd_info *mtd, loff_t to, 4177 struct mtd_oob_ops *ops) 4178 { 4179 struct nand_chip *chip = mtd_to_nand(mtd); 4180 int ret; 4181 4182 ops->retlen = 0; 4183 4184 ret = nand_get_device(chip); 4185 if (ret) 4186 return ret; 4187 4188 switch (ops->mode) { 4189 case MTD_OPS_PLACE_OOB: 4190 case MTD_OPS_AUTO_OOB: 4191 case MTD_OPS_RAW: 4192 break; 4193 4194 default: 4195 goto out; 4196 } 4197 4198 if (!ops->datbuf) 4199 ret = nand_do_write_oob(chip, to, ops); 4200 else 4201 ret = nand_do_write_ops(chip, to, ops); 4202 4203 out: 4204 nand_release_device(chip); 4205 return ret; 4206 } 4207 4208 /** 4209 * nand_erase - [MTD Interface] erase block(s) 4210 * @mtd: MTD device structure 4211 * @instr: erase instruction 4212 * 4213 * Erase one ore more blocks. 4214 */ 4215 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 4216 { 4217 return nand_erase_nand(mtd_to_nand(mtd), instr, 0); 4218 } 4219 4220 /** 4221 * nand_erase_nand - [INTERN] erase block(s) 4222 * @chip: NAND chip object 4223 * @instr: erase instruction 4224 * @allowbbt: allow erasing the bbt area 4225 * 4226 * Erase one ore more blocks. 4227 */ 4228 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr, 4229 int allowbbt) 4230 { 4231 int page, pages_per_block, ret, chipnr; 4232 loff_t len; 4233 4234 pr_debug("%s: start = 0x%012llx, len = %llu\n", 4235 __func__, (unsigned long long)instr->addr, 4236 (unsigned long long)instr->len); 4237 4238 if (check_offs_len(chip, instr->addr, instr->len)) 4239 return -EINVAL; 4240 4241 /* Grab the lock and see if the device is available */ 4242 ret = nand_get_device(chip); 4243 if (ret) 4244 return ret; 4245 4246 /* Shift to get first page */ 4247 page = (int)(instr->addr >> chip->page_shift); 4248 chipnr = (int)(instr->addr >> chip->chip_shift); 4249 4250 /* Calculate pages in each block */ 4251 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 4252 4253 /* Select the NAND device */ 4254 nand_select_target(chip, chipnr); 4255 4256 /* Check, if it is write protected */ 4257 if (nand_check_wp(chip)) { 4258 pr_debug("%s: device is write protected!\n", 4259 __func__); 4260 ret = -EIO; 4261 goto erase_exit; 4262 } 4263 4264 /* Loop through the pages */ 4265 len = instr->len; 4266 4267 while (len) { 4268 /* Check if we have a bad block, we do not erase bad blocks! */ 4269 if (nand_block_checkbad(chip, ((loff_t) page) << 4270 chip->page_shift, allowbbt)) { 4271 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", 4272 __func__, page); 4273 ret = -EIO; 4274 goto erase_exit; 4275 } 4276 4277 /* 4278 * Invalidate the page cache, if we erase the block which 4279 * contains the current cached page. 4280 */ 4281 if (page <= chip->pagecache.page && chip->pagecache.page < 4282 (page + pages_per_block)) 4283 chip->pagecache.page = -1; 4284 4285 ret = nand_erase_op(chip, (page & chip->pagemask) >> 4286 (chip->phys_erase_shift - chip->page_shift)); 4287 if (ret) { 4288 pr_debug("%s: failed erase, page 0x%08x\n", 4289 __func__, page); 4290 instr->fail_addr = 4291 ((loff_t)page << chip->page_shift); 4292 goto erase_exit; 4293 } 4294 4295 /* Increment page address and decrement length */ 4296 len -= (1ULL << chip->phys_erase_shift); 4297 page += pages_per_block; 4298 4299 /* Check, if we cross a chip boundary */ 4300 if (len && !(page & chip->pagemask)) { 4301 chipnr++; 4302 nand_deselect_target(chip); 4303 nand_select_target(chip, chipnr); 4304 } 4305 } 4306 4307 ret = 0; 4308 erase_exit: 4309 4310 /* Deselect and wake up anyone waiting on the device */ 4311 nand_deselect_target(chip); 4312 nand_release_device(chip); 4313 4314 /* Return more or less happy */ 4315 return ret; 4316 } 4317 4318 /** 4319 * nand_sync - [MTD Interface] sync 4320 * @mtd: MTD device structure 4321 * 4322 * Sync is actually a wait for chip ready function. 4323 */ 4324 static void nand_sync(struct mtd_info *mtd) 4325 { 4326 struct nand_chip *chip = mtd_to_nand(mtd); 4327 4328 pr_debug("%s: called\n", __func__); 4329 4330 /* Grab the lock and see if the device is available */ 4331 WARN_ON(nand_get_device(chip)); 4332 /* Release it and go back */ 4333 nand_release_device(chip); 4334 } 4335 4336 /** 4337 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 4338 * @mtd: MTD device structure 4339 * @offs: offset relative to mtd start 4340 */ 4341 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 4342 { 4343 struct nand_chip *chip = mtd_to_nand(mtd); 4344 int chipnr = (int)(offs >> chip->chip_shift); 4345 int ret; 4346 4347 /* Select the NAND device */ 4348 ret = nand_get_device(chip); 4349 if (ret) 4350 return ret; 4351 4352 nand_select_target(chip, chipnr); 4353 4354 ret = nand_block_checkbad(chip, offs, 0); 4355 4356 nand_deselect_target(chip); 4357 nand_release_device(chip); 4358 4359 return ret; 4360 } 4361 4362 /** 4363 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 4364 * @mtd: MTD device structure 4365 * @ofs: offset relative to mtd start 4366 */ 4367 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 4368 { 4369 int ret; 4370 4371 ret = nand_block_isbad(mtd, ofs); 4372 if (ret) { 4373 /* If it was bad already, return success and do nothing */ 4374 if (ret > 0) 4375 return 0; 4376 return ret; 4377 } 4378 4379 return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs); 4380 } 4381 4382 /** 4383 * nand_suspend - [MTD Interface] Suspend the NAND flash 4384 * @mtd: MTD device structure 4385 * 4386 * Returns 0 for success or negative error code otherwise. 4387 */ 4388 static int nand_suspend(struct mtd_info *mtd) 4389 { 4390 struct nand_chip *chip = mtd_to_nand(mtd); 4391 int ret = 0; 4392 4393 mutex_lock(&chip->lock); 4394 if (chip->suspend) 4395 ret = chip->suspend(chip); 4396 if (!ret) 4397 chip->suspended = 1; 4398 mutex_unlock(&chip->lock); 4399 4400 return ret; 4401 } 4402 4403 /** 4404 * nand_resume - [MTD Interface] Resume the NAND flash 4405 * @mtd: MTD device structure 4406 */ 4407 static void nand_resume(struct mtd_info *mtd) 4408 { 4409 struct nand_chip *chip = mtd_to_nand(mtd); 4410 4411 mutex_lock(&chip->lock); 4412 if (chip->suspended) { 4413 if (chip->resume) 4414 chip->resume(chip); 4415 chip->suspended = 0; 4416 } else { 4417 pr_err("%s called for a chip which is not in suspended state\n", 4418 __func__); 4419 } 4420 mutex_unlock(&chip->lock); 4421 } 4422 4423 /** 4424 * nand_shutdown - [MTD Interface] Finish the current NAND operation and 4425 * prevent further operations 4426 * @mtd: MTD device structure 4427 */ 4428 static void nand_shutdown(struct mtd_info *mtd) 4429 { 4430 nand_suspend(mtd); 4431 } 4432 4433 /** 4434 * nand_lock - [MTD Interface] Lock the NAND flash 4435 * @mtd: MTD device structure 4436 * @ofs: offset byte address 4437 * @len: number of bytes to lock (must be a multiple of block/page size) 4438 */ 4439 static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4440 { 4441 struct nand_chip *chip = mtd_to_nand(mtd); 4442 4443 if (!chip->lock_area) 4444 return -ENOTSUPP; 4445 4446 return chip->lock_area(chip, ofs, len); 4447 } 4448 4449 /** 4450 * nand_unlock - [MTD Interface] Unlock the NAND flash 4451 * @mtd: MTD device structure 4452 * @ofs: offset byte address 4453 * @len: number of bytes to unlock (must be a multiple of block/page size) 4454 */ 4455 static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 4456 { 4457 struct nand_chip *chip = mtd_to_nand(mtd); 4458 4459 if (!chip->unlock_area) 4460 return -ENOTSUPP; 4461 4462 return chip->unlock_area(chip, ofs, len); 4463 } 4464 4465 /* Set default functions */ 4466 static void nand_set_defaults(struct nand_chip *chip) 4467 { 4468 /* If no controller is provided, use the dummy, legacy one. */ 4469 if (!chip->controller) { 4470 chip->controller = &chip->legacy.dummy_controller; 4471 nand_controller_init(chip->controller); 4472 } 4473 4474 nand_legacy_set_defaults(chip); 4475 4476 if (!chip->buf_align) 4477 chip->buf_align = 1; 4478 } 4479 4480 /* Sanitize ONFI strings so we can safely print them */ 4481 void sanitize_string(uint8_t *s, size_t len) 4482 { 4483 ssize_t i; 4484 4485 /* Null terminate */ 4486 s[len - 1] = 0; 4487 4488 /* Remove non printable chars */ 4489 for (i = 0; i < len - 1; i++) { 4490 if (s[i] < ' ' || s[i] > 127) 4491 s[i] = '?'; 4492 } 4493 4494 /* Remove trailing spaces */ 4495 strim(s); 4496 } 4497 4498 /* 4499 * nand_id_has_period - Check if an ID string has a given wraparound period 4500 * @id_data: the ID string 4501 * @arrlen: the length of the @id_data array 4502 * @period: the period of repitition 4503 * 4504 * Check if an ID string is repeated within a given sequence of bytes at 4505 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 4506 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 4507 * if the repetition has a period of @period; otherwise, returns zero. 4508 */ 4509 static int nand_id_has_period(u8 *id_data, int arrlen, int period) 4510 { 4511 int i, j; 4512 for (i = 0; i < period; i++) 4513 for (j = i + period; j < arrlen; j += period) 4514 if (id_data[i] != id_data[j]) 4515 return 0; 4516 return 1; 4517 } 4518 4519 /* 4520 * nand_id_len - Get the length of an ID string returned by CMD_READID 4521 * @id_data: the ID string 4522 * @arrlen: the length of the @id_data array 4523 4524 * Returns the length of the ID string, according to known wraparound/trailing 4525 * zero patterns. If no pattern exists, returns the length of the array. 4526 */ 4527 static int nand_id_len(u8 *id_data, int arrlen) 4528 { 4529 int last_nonzero, period; 4530 4531 /* Find last non-zero byte */ 4532 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 4533 if (id_data[last_nonzero]) 4534 break; 4535 4536 /* All zeros */ 4537 if (last_nonzero < 0) 4538 return 0; 4539 4540 /* Calculate wraparound period */ 4541 for (period = 1; period < arrlen; period++) 4542 if (nand_id_has_period(id_data, arrlen, period)) 4543 break; 4544 4545 /* There's a repeated pattern */ 4546 if (period < arrlen) 4547 return period; 4548 4549 /* There are trailing zeros */ 4550 if (last_nonzero < arrlen - 1) 4551 return last_nonzero + 1; 4552 4553 /* No pattern detected */ 4554 return arrlen; 4555 } 4556 4557 /* Extract the bits of per cell from the 3rd byte of the extended ID */ 4558 static int nand_get_bits_per_cell(u8 cellinfo) 4559 { 4560 int bits; 4561 4562 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 4563 bits >>= NAND_CI_CELLTYPE_SHIFT; 4564 return bits + 1; 4565 } 4566 4567 /* 4568 * Many new NAND share similar device ID codes, which represent the size of the 4569 * chip. The rest of the parameters must be decoded according to generic or 4570 * manufacturer-specific "extended ID" decoding patterns. 4571 */ 4572 void nand_decode_ext_id(struct nand_chip *chip) 4573 { 4574 struct nand_memory_organization *memorg; 4575 struct mtd_info *mtd = nand_to_mtd(chip); 4576 int extid; 4577 u8 *id_data = chip->id.data; 4578 4579 memorg = nanddev_get_memorg(&chip->base); 4580 4581 /* The 3rd id byte holds MLC / multichip data */ 4582 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 4583 /* The 4th id byte is the important one */ 4584 extid = id_data[3]; 4585 4586 /* Calc pagesize */ 4587 memorg->pagesize = 1024 << (extid & 0x03); 4588 mtd->writesize = memorg->pagesize; 4589 extid >>= 2; 4590 /* Calc oobsize */ 4591 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); 4592 mtd->oobsize = memorg->oobsize; 4593 extid >>= 2; 4594 /* Calc blocksize. Blocksize is multiples of 64KiB */ 4595 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) / 4596 memorg->pagesize; 4597 mtd->erasesize = (64 * 1024) << (extid & 0x03); 4598 extid >>= 2; 4599 /* Get buswidth information */ 4600 if (extid & 0x1) 4601 chip->options |= NAND_BUSWIDTH_16; 4602 } 4603 EXPORT_SYMBOL_GPL(nand_decode_ext_id); 4604 4605 /* 4606 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 4607 * decodes a matching ID table entry and assigns the MTD size parameters for 4608 * the chip. 4609 */ 4610 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) 4611 { 4612 struct mtd_info *mtd = nand_to_mtd(chip); 4613 struct nand_memory_organization *memorg; 4614 4615 memorg = nanddev_get_memorg(&chip->base); 4616 4617 memorg->pages_per_eraseblock = type->erasesize / type->pagesize; 4618 mtd->erasesize = type->erasesize; 4619 memorg->pagesize = type->pagesize; 4620 mtd->writesize = memorg->pagesize; 4621 memorg->oobsize = memorg->pagesize / 32; 4622 mtd->oobsize = memorg->oobsize; 4623 4624 /* All legacy ID NAND are small-page, SLC */ 4625 memorg->bits_per_cell = 1; 4626 } 4627 4628 /* 4629 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 4630 * heuristic patterns using various detected parameters (e.g., manufacturer, 4631 * page size, cell-type information). 4632 */ 4633 static void nand_decode_bbm_options(struct nand_chip *chip) 4634 { 4635 struct mtd_info *mtd = nand_to_mtd(chip); 4636 4637 /* Set the bad block position */ 4638 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 4639 chip->badblockpos = NAND_BBM_POS_LARGE; 4640 else 4641 chip->badblockpos = NAND_BBM_POS_SMALL; 4642 } 4643 4644 static inline bool is_full_id_nand(struct nand_flash_dev *type) 4645 { 4646 return type->id_len; 4647 } 4648 4649 static bool find_full_id_nand(struct nand_chip *chip, 4650 struct nand_flash_dev *type) 4651 { 4652 struct mtd_info *mtd = nand_to_mtd(chip); 4653 struct nand_memory_organization *memorg; 4654 u8 *id_data = chip->id.data; 4655 4656 memorg = nanddev_get_memorg(&chip->base); 4657 4658 if (!strncmp(type->id, id_data, type->id_len)) { 4659 memorg->pagesize = type->pagesize; 4660 mtd->writesize = memorg->pagesize; 4661 memorg->pages_per_eraseblock = type->erasesize / 4662 type->pagesize; 4663 mtd->erasesize = type->erasesize; 4664 memorg->oobsize = type->oobsize; 4665 mtd->oobsize = memorg->oobsize; 4666 4667 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]); 4668 memorg->eraseblocks_per_lun = 4669 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 4670 memorg->pagesize * 4671 memorg->pages_per_eraseblock); 4672 chip->options |= type->options; 4673 chip->base.eccreq.strength = NAND_ECC_STRENGTH(type); 4674 chip->base.eccreq.step_size = NAND_ECC_STEP(type); 4675 chip->onfi_timing_mode_default = 4676 type->onfi_timing_mode_default; 4677 4678 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 4679 if (!chip->parameters.model) 4680 return false; 4681 4682 return true; 4683 } 4684 return false; 4685 } 4686 4687 /* 4688 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC 4689 * compliant and does not have a full-id or legacy-id entry in the nand_ids 4690 * table. 4691 */ 4692 static void nand_manufacturer_detect(struct nand_chip *chip) 4693 { 4694 /* 4695 * Try manufacturer detection if available and use 4696 * nand_decode_ext_id() otherwise. 4697 */ 4698 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 4699 chip->manufacturer.desc->ops->detect) { 4700 struct nand_memory_organization *memorg; 4701 4702 memorg = nanddev_get_memorg(&chip->base); 4703 4704 /* The 3rd id byte holds MLC / multichip data */ 4705 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 4706 chip->manufacturer.desc->ops->detect(chip); 4707 } else { 4708 nand_decode_ext_id(chip); 4709 } 4710 } 4711 4712 /* 4713 * Manufacturer initialization. This function is called for all NANDs including 4714 * ONFI and JEDEC compliant ones. 4715 * Manufacturer drivers should put all their specific initialization code in 4716 * their ->init() hook. 4717 */ 4718 static int nand_manufacturer_init(struct nand_chip *chip) 4719 { 4720 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || 4721 !chip->manufacturer.desc->ops->init) 4722 return 0; 4723 4724 return chip->manufacturer.desc->ops->init(chip); 4725 } 4726 4727 /* 4728 * Manufacturer cleanup. This function is called for all NANDs including 4729 * ONFI and JEDEC compliant ones. 4730 * Manufacturer drivers should put all their specific cleanup code in their 4731 * ->cleanup() hook. 4732 */ 4733 static void nand_manufacturer_cleanup(struct nand_chip *chip) 4734 { 4735 /* Release manufacturer private data */ 4736 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 4737 chip->manufacturer.desc->ops->cleanup) 4738 chip->manufacturer.desc->ops->cleanup(chip); 4739 } 4740 4741 static const char * 4742 nand_manufacturer_name(const struct nand_manufacturer *manufacturer) 4743 { 4744 return manufacturer ? manufacturer->name : "Unknown"; 4745 } 4746 4747 /* 4748 * Get the flash and manufacturer id and lookup if the type is supported. 4749 */ 4750 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) 4751 { 4752 const struct nand_manufacturer *manufacturer; 4753 struct mtd_info *mtd = nand_to_mtd(chip); 4754 struct nand_memory_organization *memorg; 4755 int busw, ret; 4756 u8 *id_data = chip->id.data; 4757 u8 maf_id, dev_id; 4758 u64 targetsize; 4759 4760 /* 4761 * Let's start by initializing memorg fields that might be left 4762 * unassigned by the ID-based detection logic. 4763 */ 4764 memorg = nanddev_get_memorg(&chip->base); 4765 memorg->planes_per_lun = 1; 4766 memorg->luns_per_target = 1; 4767 4768 /* 4769 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 4770 * after power-up. 4771 */ 4772 ret = nand_reset(chip, 0); 4773 if (ret) 4774 return ret; 4775 4776 /* Select the device */ 4777 nand_select_target(chip, 0); 4778 4779 /* Send the command for reading device ID */ 4780 ret = nand_readid_op(chip, 0, id_data, 2); 4781 if (ret) 4782 return ret; 4783 4784 /* Read manufacturer and device IDs */ 4785 maf_id = id_data[0]; 4786 dev_id = id_data[1]; 4787 4788 /* 4789 * Try again to make sure, as some systems the bus-hold or other 4790 * interface concerns can cause random data which looks like a 4791 * possibly credible NAND flash to appear. If the two results do 4792 * not match, ignore the device completely. 4793 */ 4794 4795 /* Read entire ID string */ 4796 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data)); 4797 if (ret) 4798 return ret; 4799 4800 if (id_data[0] != maf_id || id_data[1] != dev_id) { 4801 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 4802 maf_id, dev_id, id_data[0], id_data[1]); 4803 return -ENODEV; 4804 } 4805 4806 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); 4807 4808 /* Try to identify manufacturer */ 4809 manufacturer = nand_get_manufacturer(maf_id); 4810 chip->manufacturer.desc = manufacturer; 4811 4812 if (!type) 4813 type = nand_flash_ids; 4814 4815 /* 4816 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic 4817 * override it. 4818 * This is required to make sure initial NAND bus width set by the 4819 * NAND controller driver is coherent with the real NAND bus width 4820 * (extracted by auto-detection code). 4821 */ 4822 busw = chip->options & NAND_BUSWIDTH_16; 4823 4824 /* 4825 * The flag is only set (never cleared), reset it to its default value 4826 * before starting auto-detection. 4827 */ 4828 chip->options &= ~NAND_BUSWIDTH_16; 4829 4830 for (; type->name != NULL; type++) { 4831 if (is_full_id_nand(type)) { 4832 if (find_full_id_nand(chip, type)) 4833 goto ident_done; 4834 } else if (dev_id == type->dev_id) { 4835 break; 4836 } 4837 } 4838 4839 if (!type->name || !type->pagesize) { 4840 /* Check if the chip is ONFI compliant */ 4841 ret = nand_onfi_detect(chip); 4842 if (ret < 0) 4843 return ret; 4844 else if (ret) 4845 goto ident_done; 4846 4847 /* Check if the chip is JEDEC compliant */ 4848 ret = nand_jedec_detect(chip); 4849 if (ret < 0) 4850 return ret; 4851 else if (ret) 4852 goto ident_done; 4853 } 4854 4855 if (!type->name) 4856 return -ENODEV; 4857 4858 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 4859 if (!chip->parameters.model) 4860 return -ENOMEM; 4861 4862 if (!type->pagesize) 4863 nand_manufacturer_detect(chip); 4864 else 4865 nand_decode_id(chip, type); 4866 4867 /* Get chip options */ 4868 chip->options |= type->options; 4869 4870 memorg->eraseblocks_per_lun = 4871 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20, 4872 memorg->pagesize * 4873 memorg->pages_per_eraseblock); 4874 4875 ident_done: 4876 if (!mtd->name) 4877 mtd->name = chip->parameters.model; 4878 4879 if (chip->options & NAND_BUSWIDTH_AUTO) { 4880 WARN_ON(busw & NAND_BUSWIDTH_16); 4881 nand_set_defaults(chip); 4882 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 4883 /* 4884 * Check, if buswidth is correct. Hardware drivers should set 4885 * chip correct! 4886 */ 4887 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 4888 maf_id, dev_id); 4889 pr_info("%s %s\n", nand_manufacturer_name(manufacturer), 4890 mtd->name); 4891 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, 4892 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); 4893 ret = -EINVAL; 4894 4895 goto free_detect_allocation; 4896 } 4897 4898 nand_decode_bbm_options(chip); 4899 4900 /* Calculate the address shift from the page size */ 4901 chip->page_shift = ffs(mtd->writesize) - 1; 4902 /* Convert chipsize to number of pages per chip -1 */ 4903 targetsize = nanddev_target_size(&chip->base); 4904 chip->pagemask = (targetsize >> chip->page_shift) - 1; 4905 4906 chip->bbt_erase_shift = chip->phys_erase_shift = 4907 ffs(mtd->erasesize) - 1; 4908 if (targetsize & 0xffffffff) 4909 chip->chip_shift = ffs((unsigned)targetsize) - 1; 4910 else { 4911 chip->chip_shift = ffs((unsigned)(targetsize >> 32)); 4912 chip->chip_shift += 32 - 1; 4913 } 4914 4915 if (chip->chip_shift - chip->page_shift > 16) 4916 chip->options |= NAND_ROW_ADDR_3; 4917 4918 chip->badblockbits = 8; 4919 4920 nand_legacy_adjust_cmdfunc(chip); 4921 4922 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 4923 maf_id, dev_id); 4924 pr_info("%s %s\n", nand_manufacturer_name(manufacturer), 4925 chip->parameters.model); 4926 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", 4927 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 4928 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); 4929 return 0; 4930 4931 free_detect_allocation: 4932 kfree(chip->parameters.model); 4933 4934 return ret; 4935 } 4936 4937 static const char * const nand_ecc_modes[] = { 4938 [NAND_ECC_NONE] = "none", 4939 [NAND_ECC_SOFT] = "soft", 4940 [NAND_ECC_HW] = "hw", 4941 [NAND_ECC_HW_SYNDROME] = "hw_syndrome", 4942 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first", 4943 [NAND_ECC_ON_DIE] = "on-die", 4944 }; 4945 4946 static int of_get_nand_ecc_mode(struct device_node *np) 4947 { 4948 const char *pm; 4949 int err, i; 4950 4951 err = of_property_read_string(np, "nand-ecc-mode", &pm); 4952 if (err < 0) 4953 return err; 4954 4955 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++) 4956 if (!strcasecmp(pm, nand_ecc_modes[i])) 4957 return i; 4958 4959 /* 4960 * For backward compatibility we support few obsoleted values that don't 4961 * have their mappings into nand_ecc_modes_t anymore (they were merged 4962 * with other enums). 4963 */ 4964 if (!strcasecmp(pm, "soft_bch")) 4965 return NAND_ECC_SOFT; 4966 4967 return -ENODEV; 4968 } 4969 4970 static const char * const nand_ecc_algos[] = { 4971 [NAND_ECC_HAMMING] = "hamming", 4972 [NAND_ECC_BCH] = "bch", 4973 [NAND_ECC_RS] = "rs", 4974 }; 4975 4976 static int of_get_nand_ecc_algo(struct device_node *np) 4977 { 4978 const char *pm; 4979 int err, i; 4980 4981 err = of_property_read_string(np, "nand-ecc-algo", &pm); 4982 if (!err) { 4983 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++) 4984 if (!strcasecmp(pm, nand_ecc_algos[i])) 4985 return i; 4986 return -ENODEV; 4987 } 4988 4989 /* 4990 * For backward compatibility we also read "nand-ecc-mode" checking 4991 * for some obsoleted values that were specifying ECC algorithm. 4992 */ 4993 err = of_property_read_string(np, "nand-ecc-mode", &pm); 4994 if (err < 0) 4995 return err; 4996 4997 if (!strcasecmp(pm, "soft")) 4998 return NAND_ECC_HAMMING; 4999 else if (!strcasecmp(pm, "soft_bch")) 5000 return NAND_ECC_BCH; 5001 5002 return -ENODEV; 5003 } 5004 5005 static int of_get_nand_ecc_step_size(struct device_node *np) 5006 { 5007 int ret; 5008 u32 val; 5009 5010 ret = of_property_read_u32(np, "nand-ecc-step-size", &val); 5011 return ret ? ret : val; 5012 } 5013 5014 static int of_get_nand_ecc_strength(struct device_node *np) 5015 { 5016 int ret; 5017 u32 val; 5018 5019 ret = of_property_read_u32(np, "nand-ecc-strength", &val); 5020 return ret ? ret : val; 5021 } 5022 5023 static int of_get_nand_bus_width(struct device_node *np) 5024 { 5025 u32 val; 5026 5027 if (of_property_read_u32(np, "nand-bus-width", &val)) 5028 return 8; 5029 5030 switch (val) { 5031 case 8: 5032 case 16: 5033 return val; 5034 default: 5035 return -EIO; 5036 } 5037 } 5038 5039 static bool of_get_nand_on_flash_bbt(struct device_node *np) 5040 { 5041 return of_property_read_bool(np, "nand-on-flash-bbt"); 5042 } 5043 5044 static int nand_dt_init(struct nand_chip *chip) 5045 { 5046 struct device_node *dn = nand_get_flash_node(chip); 5047 int ecc_mode, ecc_algo, ecc_strength, ecc_step; 5048 5049 if (!dn) 5050 return 0; 5051 5052 if (of_get_nand_bus_width(dn) == 16) 5053 chip->options |= NAND_BUSWIDTH_16; 5054 5055 if (of_property_read_bool(dn, "nand-is-boot-medium")) 5056 chip->options |= NAND_IS_BOOT_MEDIUM; 5057 5058 if (of_get_nand_on_flash_bbt(dn)) 5059 chip->bbt_options |= NAND_BBT_USE_FLASH; 5060 5061 ecc_mode = of_get_nand_ecc_mode(dn); 5062 ecc_algo = of_get_nand_ecc_algo(dn); 5063 ecc_strength = of_get_nand_ecc_strength(dn); 5064 ecc_step = of_get_nand_ecc_step_size(dn); 5065 5066 if (ecc_mode >= 0) 5067 chip->ecc.mode = ecc_mode; 5068 5069 if (ecc_algo >= 0) 5070 chip->ecc.algo = ecc_algo; 5071 5072 if (ecc_strength >= 0) 5073 chip->ecc.strength = ecc_strength; 5074 5075 if (ecc_step > 0) 5076 chip->ecc.size = ecc_step; 5077 5078 if (of_property_read_bool(dn, "nand-ecc-maximize")) 5079 chip->ecc.options |= NAND_ECC_MAXIMIZE; 5080 5081 return 0; 5082 } 5083 5084 /** 5085 * nand_scan_ident - Scan for the NAND device 5086 * @chip: NAND chip object 5087 * @maxchips: number of chips to scan for 5088 * @table: alternative NAND ID table 5089 * 5090 * This is the first phase of the normal nand_scan() function. It reads the 5091 * flash ID and sets up MTD fields accordingly. 5092 * 5093 * This helper used to be called directly from controller drivers that needed 5094 * to tweak some ECC-related parameters before nand_scan_tail(). This separation 5095 * prevented dynamic allocations during this phase which was unconvenient and 5096 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks. 5097 */ 5098 static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips, 5099 struct nand_flash_dev *table) 5100 { 5101 struct mtd_info *mtd = nand_to_mtd(chip); 5102 struct nand_memory_organization *memorg; 5103 int nand_maf_id, nand_dev_id; 5104 unsigned int i; 5105 int ret; 5106 5107 memorg = nanddev_get_memorg(&chip->base); 5108 5109 /* Assume all dies are deselected when we enter nand_scan_ident(). */ 5110 chip->cur_cs = -1; 5111 5112 mutex_init(&chip->lock); 5113 5114 /* Enforce the right timings for reset/detection */ 5115 onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0); 5116 5117 ret = nand_dt_init(chip); 5118 if (ret) 5119 return ret; 5120 5121 if (!mtd->name && mtd->dev.parent) 5122 mtd->name = dev_name(mtd->dev.parent); 5123 5124 /* Set the default functions */ 5125 nand_set_defaults(chip); 5126 5127 ret = nand_legacy_check_hooks(chip); 5128 if (ret) 5129 return ret; 5130 5131 memorg->ntargets = maxchips; 5132 5133 /* Read the flash type */ 5134 ret = nand_detect(chip, table); 5135 if (ret) { 5136 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 5137 pr_warn("No NAND device found\n"); 5138 nand_deselect_target(chip); 5139 return ret; 5140 } 5141 5142 nand_maf_id = chip->id.data[0]; 5143 nand_dev_id = chip->id.data[1]; 5144 5145 nand_deselect_target(chip); 5146 5147 /* Check for a chip array */ 5148 for (i = 1; i < maxchips; i++) { 5149 u8 id[2]; 5150 5151 /* See comment in nand_get_flash_type for reset */ 5152 ret = nand_reset(chip, i); 5153 if (ret) 5154 break; 5155 5156 nand_select_target(chip, i); 5157 /* Send the command for reading device ID */ 5158 ret = nand_readid_op(chip, 0, id, sizeof(id)); 5159 if (ret) 5160 break; 5161 /* Read manufacturer and device IDs */ 5162 if (nand_maf_id != id[0] || nand_dev_id != id[1]) { 5163 nand_deselect_target(chip); 5164 break; 5165 } 5166 nand_deselect_target(chip); 5167 } 5168 if (i > 1) 5169 pr_info("%d chips detected\n", i); 5170 5171 /* Store the number of chips and calc total size for mtd */ 5172 memorg->ntargets = i; 5173 mtd->size = i * nanddev_target_size(&chip->base); 5174 5175 return 0; 5176 } 5177 5178 static void nand_scan_ident_cleanup(struct nand_chip *chip) 5179 { 5180 kfree(chip->parameters.model); 5181 kfree(chip->parameters.onfi); 5182 } 5183 5184 static int nand_set_ecc_soft_ops(struct nand_chip *chip) 5185 { 5186 struct mtd_info *mtd = nand_to_mtd(chip); 5187 struct nand_ecc_ctrl *ecc = &chip->ecc; 5188 5189 if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) 5190 return -EINVAL; 5191 5192 switch (ecc->algo) { 5193 case NAND_ECC_HAMMING: 5194 ecc->calculate = nand_calculate_ecc; 5195 ecc->correct = nand_correct_data; 5196 ecc->read_page = nand_read_page_swecc; 5197 ecc->read_subpage = nand_read_subpage; 5198 ecc->write_page = nand_write_page_swecc; 5199 ecc->read_page_raw = nand_read_page_raw; 5200 ecc->write_page_raw = nand_write_page_raw; 5201 ecc->read_oob = nand_read_oob_std; 5202 ecc->write_oob = nand_write_oob_std; 5203 if (!ecc->size) 5204 ecc->size = 256; 5205 ecc->bytes = 3; 5206 ecc->strength = 1; 5207 5208 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC)) 5209 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 5210 5211 return 0; 5212 case NAND_ECC_BCH: 5213 if (!mtd_nand_has_bch()) { 5214 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n"); 5215 return -EINVAL; 5216 } 5217 ecc->calculate = nand_bch_calculate_ecc; 5218 ecc->correct = nand_bch_correct_data; 5219 ecc->read_page = nand_read_page_swecc; 5220 ecc->read_subpage = nand_read_subpage; 5221 ecc->write_page = nand_write_page_swecc; 5222 ecc->read_page_raw = nand_read_page_raw; 5223 ecc->write_page_raw = nand_write_page_raw; 5224 ecc->read_oob = nand_read_oob_std; 5225 ecc->write_oob = nand_write_oob_std; 5226 5227 /* 5228 * Board driver should supply ecc.size and ecc.strength 5229 * values to select how many bits are correctable. 5230 * Otherwise, default to 4 bits for large page devices. 5231 */ 5232 if (!ecc->size && (mtd->oobsize >= 64)) { 5233 ecc->size = 512; 5234 ecc->strength = 4; 5235 } 5236 5237 /* 5238 * if no ecc placement scheme was provided pickup the default 5239 * large page one. 5240 */ 5241 if (!mtd->ooblayout) { 5242 /* handle large page devices only */ 5243 if (mtd->oobsize < 64) { 5244 WARN(1, "OOB layout is required when using software BCH on small pages\n"); 5245 return -EINVAL; 5246 } 5247 5248 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 5249 5250 } 5251 5252 /* 5253 * We can only maximize ECC config when the default layout is 5254 * used, otherwise we don't know how many bytes can really be 5255 * used. 5256 */ 5257 if (mtd->ooblayout == &nand_ooblayout_lp_ops && 5258 ecc->options & NAND_ECC_MAXIMIZE) { 5259 int steps, bytes; 5260 5261 /* Always prefer 1k blocks over 512bytes ones */ 5262 ecc->size = 1024; 5263 steps = mtd->writesize / ecc->size; 5264 5265 /* Reserve 2 bytes for the BBM */ 5266 bytes = (mtd->oobsize - 2) / steps; 5267 ecc->strength = bytes * 8 / fls(8 * ecc->size); 5268 } 5269 5270 /* See nand_bch_init() for details. */ 5271 ecc->bytes = 0; 5272 ecc->priv = nand_bch_init(mtd); 5273 if (!ecc->priv) { 5274 WARN(1, "BCH ECC initialization failed!\n"); 5275 return -EINVAL; 5276 } 5277 return 0; 5278 default: 5279 WARN(1, "Unsupported ECC algorithm!\n"); 5280 return -EINVAL; 5281 } 5282 } 5283 5284 /** 5285 * nand_check_ecc_caps - check the sanity of preset ECC settings 5286 * @chip: nand chip info structure 5287 * @caps: ECC caps info structure 5288 * @oobavail: OOB size that the ECC engine can use 5289 * 5290 * When ECC step size and strength are already set, check if they are supported 5291 * by the controller and the calculated ECC bytes fit within the chip's OOB. 5292 * On success, the calculated ECC bytes is set. 5293 */ 5294 static int 5295 nand_check_ecc_caps(struct nand_chip *chip, 5296 const struct nand_ecc_caps *caps, int oobavail) 5297 { 5298 struct mtd_info *mtd = nand_to_mtd(chip); 5299 const struct nand_ecc_step_info *stepinfo; 5300 int preset_step = chip->ecc.size; 5301 int preset_strength = chip->ecc.strength; 5302 int ecc_bytes, nsteps = mtd->writesize / preset_step; 5303 int i, j; 5304 5305 for (i = 0; i < caps->nstepinfos; i++) { 5306 stepinfo = &caps->stepinfos[i]; 5307 5308 if (stepinfo->stepsize != preset_step) 5309 continue; 5310 5311 for (j = 0; j < stepinfo->nstrengths; j++) { 5312 if (stepinfo->strengths[j] != preset_strength) 5313 continue; 5314 5315 ecc_bytes = caps->calc_ecc_bytes(preset_step, 5316 preset_strength); 5317 if (WARN_ON_ONCE(ecc_bytes < 0)) 5318 return ecc_bytes; 5319 5320 if (ecc_bytes * nsteps > oobavail) { 5321 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", 5322 preset_step, preset_strength); 5323 return -ENOSPC; 5324 } 5325 5326 chip->ecc.bytes = ecc_bytes; 5327 5328 return 0; 5329 } 5330 } 5331 5332 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", 5333 preset_step, preset_strength); 5334 5335 return -ENOTSUPP; 5336 } 5337 5338 /** 5339 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes 5340 * @chip: nand chip info structure 5341 * @caps: ECC engine caps info structure 5342 * @oobavail: OOB size that the ECC engine can use 5343 * 5344 * If a chip's ECC requirement is provided, try to meet it with the least 5345 * number of ECC bytes (i.e. with the largest number of OOB-free bytes). 5346 * On success, the chosen ECC settings are set. 5347 */ 5348 static int 5349 nand_match_ecc_req(struct nand_chip *chip, 5350 const struct nand_ecc_caps *caps, int oobavail) 5351 { 5352 struct mtd_info *mtd = nand_to_mtd(chip); 5353 const struct nand_ecc_step_info *stepinfo; 5354 int req_step = chip->base.eccreq.step_size; 5355 int req_strength = chip->base.eccreq.strength; 5356 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 5357 int best_step, best_strength, best_ecc_bytes; 5358 int best_ecc_bytes_total = INT_MAX; 5359 int i, j; 5360 5361 /* No information provided by the NAND chip */ 5362 if (!req_step || !req_strength) 5363 return -ENOTSUPP; 5364 5365 /* number of correctable bits the chip requires in a page */ 5366 req_corr = mtd->writesize / req_step * req_strength; 5367 5368 for (i = 0; i < caps->nstepinfos; i++) { 5369 stepinfo = &caps->stepinfos[i]; 5370 step_size = stepinfo->stepsize; 5371 5372 for (j = 0; j < stepinfo->nstrengths; j++) { 5373 strength = stepinfo->strengths[j]; 5374 5375 /* 5376 * If both step size and strength are smaller than the 5377 * chip's requirement, it is not easy to compare the 5378 * resulted reliability. 5379 */ 5380 if (step_size < req_step && strength < req_strength) 5381 continue; 5382 5383 if (mtd->writesize % step_size) 5384 continue; 5385 5386 nsteps = mtd->writesize / step_size; 5387 5388 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 5389 if (WARN_ON_ONCE(ecc_bytes < 0)) 5390 continue; 5391 ecc_bytes_total = ecc_bytes * nsteps; 5392 5393 if (ecc_bytes_total > oobavail || 5394 strength * nsteps < req_corr) 5395 continue; 5396 5397 /* 5398 * We assume the best is to meet the chip's requrement 5399 * with the least number of ECC bytes. 5400 */ 5401 if (ecc_bytes_total < best_ecc_bytes_total) { 5402 best_ecc_bytes_total = ecc_bytes_total; 5403 best_step = step_size; 5404 best_strength = strength; 5405 best_ecc_bytes = ecc_bytes; 5406 } 5407 } 5408 } 5409 5410 if (best_ecc_bytes_total == INT_MAX) 5411 return -ENOTSUPP; 5412 5413 chip->ecc.size = best_step; 5414 chip->ecc.strength = best_strength; 5415 chip->ecc.bytes = best_ecc_bytes; 5416 5417 return 0; 5418 } 5419 5420 /** 5421 * nand_maximize_ecc - choose the max ECC strength available 5422 * @chip: nand chip info structure 5423 * @caps: ECC engine caps info structure 5424 * @oobavail: OOB size that the ECC engine can use 5425 * 5426 * Choose the max ECC strength that is supported on the controller, and can fit 5427 * within the chip's OOB. On success, the chosen ECC settings are set. 5428 */ 5429 static int 5430 nand_maximize_ecc(struct nand_chip *chip, 5431 const struct nand_ecc_caps *caps, int oobavail) 5432 { 5433 struct mtd_info *mtd = nand_to_mtd(chip); 5434 const struct nand_ecc_step_info *stepinfo; 5435 int step_size, strength, nsteps, ecc_bytes, corr; 5436 int best_corr = 0; 5437 int best_step = 0; 5438 int best_strength, best_ecc_bytes; 5439 int i, j; 5440 5441 for (i = 0; i < caps->nstepinfos; i++) { 5442 stepinfo = &caps->stepinfos[i]; 5443 step_size = stepinfo->stepsize; 5444 5445 /* If chip->ecc.size is already set, respect it */ 5446 if (chip->ecc.size && step_size != chip->ecc.size) 5447 continue; 5448 5449 for (j = 0; j < stepinfo->nstrengths; j++) { 5450 strength = stepinfo->strengths[j]; 5451 5452 if (mtd->writesize % step_size) 5453 continue; 5454 5455 nsteps = mtd->writesize / step_size; 5456 5457 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 5458 if (WARN_ON_ONCE(ecc_bytes < 0)) 5459 continue; 5460 5461 if (ecc_bytes * nsteps > oobavail) 5462 continue; 5463 5464 corr = strength * nsteps; 5465 5466 /* 5467 * If the number of correctable bits is the same, 5468 * bigger step_size has more reliability. 5469 */ 5470 if (corr > best_corr || 5471 (corr == best_corr && step_size > best_step)) { 5472 best_corr = corr; 5473 best_step = step_size; 5474 best_strength = strength; 5475 best_ecc_bytes = ecc_bytes; 5476 } 5477 } 5478 } 5479 5480 if (!best_corr) 5481 return -ENOTSUPP; 5482 5483 chip->ecc.size = best_step; 5484 chip->ecc.strength = best_strength; 5485 chip->ecc.bytes = best_ecc_bytes; 5486 5487 return 0; 5488 } 5489 5490 /** 5491 * nand_ecc_choose_conf - Set the ECC strength and ECC step size 5492 * @chip: nand chip info structure 5493 * @caps: ECC engine caps info structure 5494 * @oobavail: OOB size that the ECC engine can use 5495 * 5496 * Choose the ECC configuration according to following logic 5497 * 5498 * 1. If both ECC step size and ECC strength are already set (usually by DT) 5499 * then check if it is supported by this controller. 5500 * 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength. 5501 * 3. Otherwise, try to match the ECC step size and ECC strength closest 5502 * to the chip's requirement. If available OOB size can't fit the chip 5503 * requirement then fallback to the maximum ECC step size and ECC strength. 5504 * 5505 * On success, the chosen ECC settings are set. 5506 */ 5507 int nand_ecc_choose_conf(struct nand_chip *chip, 5508 const struct nand_ecc_caps *caps, int oobavail) 5509 { 5510 struct mtd_info *mtd = nand_to_mtd(chip); 5511 5512 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) 5513 return -EINVAL; 5514 5515 if (chip->ecc.size && chip->ecc.strength) 5516 return nand_check_ecc_caps(chip, caps, oobavail); 5517 5518 if (chip->ecc.options & NAND_ECC_MAXIMIZE) 5519 return nand_maximize_ecc(chip, caps, oobavail); 5520 5521 if (!nand_match_ecc_req(chip, caps, oobavail)) 5522 return 0; 5523 5524 return nand_maximize_ecc(chip, caps, oobavail); 5525 } 5526 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf); 5527 5528 /* 5529 * Check if the chip configuration meet the datasheet requirements. 5530 5531 * If our configuration corrects A bits per B bytes and the minimum 5532 * required correction level is X bits per Y bytes, then we must ensure 5533 * both of the following are true: 5534 * 5535 * (1) A / B >= X / Y 5536 * (2) A >= X 5537 * 5538 * Requirement (1) ensures we can correct for the required bitflip density. 5539 * Requirement (2) ensures we can correct even when all bitflips are clumped 5540 * in the same sector. 5541 */ 5542 static bool nand_ecc_strength_good(struct nand_chip *chip) 5543 { 5544 struct mtd_info *mtd = nand_to_mtd(chip); 5545 struct nand_ecc_ctrl *ecc = &chip->ecc; 5546 int corr, ds_corr; 5547 5548 if (ecc->size == 0 || chip->base.eccreq.step_size == 0) 5549 /* Not enough information */ 5550 return true; 5551 5552 /* 5553 * We get the number of corrected bits per page to compare 5554 * the correction density. 5555 */ 5556 corr = (mtd->writesize * ecc->strength) / ecc->size; 5557 ds_corr = (mtd->writesize * chip->base.eccreq.strength) / 5558 chip->base.eccreq.step_size; 5559 5560 return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength; 5561 } 5562 5563 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) 5564 { 5565 struct nand_chip *chip = container_of(nand, struct nand_chip, 5566 base); 5567 unsigned int eb = nanddev_pos_to_row(nand, pos); 5568 int ret; 5569 5570 eb >>= nand->rowconv.eraseblock_addr_shift; 5571 5572 nand_select_target(chip, pos->target); 5573 ret = nand_erase_op(chip, eb); 5574 nand_deselect_target(chip); 5575 5576 return ret; 5577 } 5578 5579 static int rawnand_markbad(struct nand_device *nand, 5580 const struct nand_pos *pos) 5581 { 5582 struct nand_chip *chip = container_of(nand, struct nand_chip, 5583 base); 5584 5585 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 5586 } 5587 5588 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos) 5589 { 5590 struct nand_chip *chip = container_of(nand, struct nand_chip, 5591 base); 5592 int ret; 5593 5594 nand_select_target(chip, pos->target); 5595 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos)); 5596 nand_deselect_target(chip); 5597 5598 return ret; 5599 } 5600 5601 static const struct nand_ops rawnand_ops = { 5602 .erase = rawnand_erase, 5603 .markbad = rawnand_markbad, 5604 .isbad = rawnand_isbad, 5605 }; 5606 5607 /** 5608 * nand_scan_tail - Scan for the NAND device 5609 * @chip: NAND chip object 5610 * 5611 * This is the second phase of the normal nand_scan() function. It fills out 5612 * all the uninitialized function pointers with the defaults and scans for a 5613 * bad block table if appropriate. 5614 */ 5615 static int nand_scan_tail(struct nand_chip *chip) 5616 { 5617 struct mtd_info *mtd = nand_to_mtd(chip); 5618 struct nand_ecc_ctrl *ecc = &chip->ecc; 5619 int ret, i; 5620 5621 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 5622 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 5623 !(chip->bbt_options & NAND_BBT_USE_FLASH))) { 5624 return -EINVAL; 5625 } 5626 5627 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 5628 if (!chip->data_buf) 5629 return -ENOMEM; 5630 5631 /* 5632 * FIXME: some NAND manufacturer drivers expect the first die to be 5633 * selected when manufacturer->init() is called. They should be fixed 5634 * to explictly select the relevant die when interacting with the NAND 5635 * chip. 5636 */ 5637 nand_select_target(chip, 0); 5638 ret = nand_manufacturer_init(chip); 5639 nand_deselect_target(chip); 5640 if (ret) 5641 goto err_free_buf; 5642 5643 /* Set the internal oob buffer location, just after the page data */ 5644 chip->oob_poi = chip->data_buf + mtd->writesize; 5645 5646 /* 5647 * If no default placement scheme is given, select an appropriate one. 5648 */ 5649 if (!mtd->ooblayout && 5650 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { 5651 switch (mtd->oobsize) { 5652 case 8: 5653 case 16: 5654 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); 5655 break; 5656 case 64: 5657 case 128: 5658 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); 5659 break; 5660 default: 5661 /* 5662 * Expose the whole OOB area to users if ECC_NONE 5663 * is passed. We could do that for all kind of 5664 * ->oobsize, but we must keep the old large/small 5665 * page with ECC layout when ->oobsize <= 128 for 5666 * compatibility reasons. 5667 */ 5668 if (ecc->mode == NAND_ECC_NONE) { 5669 mtd_set_ooblayout(mtd, 5670 &nand_ooblayout_lp_ops); 5671 break; 5672 } 5673 5674 WARN(1, "No oob scheme defined for oobsize %d\n", 5675 mtd->oobsize); 5676 ret = -EINVAL; 5677 goto err_nand_manuf_cleanup; 5678 } 5679 } 5680 5681 /* 5682 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 5683 * selected and we have 256 byte pagesize fallback to software ECC 5684 */ 5685 5686 switch (ecc->mode) { 5687 case NAND_ECC_HW_OOB_FIRST: 5688 /* Similar to NAND_ECC_HW, but a separate read_page handle */ 5689 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { 5690 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5691 ret = -EINVAL; 5692 goto err_nand_manuf_cleanup; 5693 } 5694 if (!ecc->read_page) 5695 ecc->read_page = nand_read_page_hwecc_oob_first; 5696 fallthrough; 5697 case NAND_ECC_HW: 5698 /* Use standard hwecc read page function? */ 5699 if (!ecc->read_page) 5700 ecc->read_page = nand_read_page_hwecc; 5701 if (!ecc->write_page) 5702 ecc->write_page = nand_write_page_hwecc; 5703 if (!ecc->read_page_raw) 5704 ecc->read_page_raw = nand_read_page_raw; 5705 if (!ecc->write_page_raw) 5706 ecc->write_page_raw = nand_write_page_raw; 5707 if (!ecc->read_oob) 5708 ecc->read_oob = nand_read_oob_std; 5709 if (!ecc->write_oob) 5710 ecc->write_oob = nand_write_oob_std; 5711 if (!ecc->read_subpage) 5712 ecc->read_subpage = nand_read_subpage; 5713 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5714 ecc->write_subpage = nand_write_subpage_hwecc; 5715 fallthrough; 5716 case NAND_ECC_HW_SYNDROME: 5717 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5718 (!ecc->read_page || 5719 ecc->read_page == nand_read_page_hwecc || 5720 !ecc->write_page || 5721 ecc->write_page == nand_write_page_hwecc)) { 5722 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5723 ret = -EINVAL; 5724 goto err_nand_manuf_cleanup; 5725 } 5726 /* Use standard syndrome read/write page function? */ 5727 if (!ecc->read_page) 5728 ecc->read_page = nand_read_page_syndrome; 5729 if (!ecc->write_page) 5730 ecc->write_page = nand_write_page_syndrome; 5731 if (!ecc->read_page_raw) 5732 ecc->read_page_raw = nand_read_page_raw_syndrome; 5733 if (!ecc->write_page_raw) 5734 ecc->write_page_raw = nand_write_page_raw_syndrome; 5735 if (!ecc->read_oob) 5736 ecc->read_oob = nand_read_oob_syndrome; 5737 if (!ecc->write_oob) 5738 ecc->write_oob = nand_write_oob_syndrome; 5739 5740 if (mtd->writesize >= ecc->size) { 5741 if (!ecc->strength) { 5742 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); 5743 ret = -EINVAL; 5744 goto err_nand_manuf_cleanup; 5745 } 5746 break; 5747 } 5748 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 5749 ecc->size, mtd->writesize); 5750 ecc->mode = NAND_ECC_SOFT; 5751 ecc->algo = NAND_ECC_HAMMING; 5752 fallthrough; 5753 case NAND_ECC_SOFT: 5754 ret = nand_set_ecc_soft_ops(chip); 5755 if (ret) { 5756 ret = -EINVAL; 5757 goto err_nand_manuf_cleanup; 5758 } 5759 break; 5760 5761 case NAND_ECC_ON_DIE: 5762 if (!ecc->read_page || !ecc->write_page) { 5763 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); 5764 ret = -EINVAL; 5765 goto err_nand_manuf_cleanup; 5766 } 5767 if (!ecc->read_oob) 5768 ecc->read_oob = nand_read_oob_std; 5769 if (!ecc->write_oob) 5770 ecc->write_oob = nand_write_oob_std; 5771 break; 5772 5773 case NAND_ECC_NONE: 5774 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); 5775 ecc->read_page = nand_read_page_raw; 5776 ecc->write_page = nand_write_page_raw; 5777 ecc->read_oob = nand_read_oob_std; 5778 ecc->read_page_raw = nand_read_page_raw; 5779 ecc->write_page_raw = nand_write_page_raw; 5780 ecc->write_oob = nand_write_oob_std; 5781 ecc->size = mtd->writesize; 5782 ecc->bytes = 0; 5783 ecc->strength = 0; 5784 break; 5785 5786 default: 5787 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); 5788 ret = -EINVAL; 5789 goto err_nand_manuf_cleanup; 5790 } 5791 5792 if (ecc->correct || ecc->calculate) { 5793 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 5794 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); 5795 if (!ecc->calc_buf || !ecc->code_buf) { 5796 ret = -ENOMEM; 5797 goto err_nand_manuf_cleanup; 5798 } 5799 } 5800 5801 /* For many systems, the standard OOB write also works for raw */ 5802 if (!ecc->read_oob_raw) 5803 ecc->read_oob_raw = ecc->read_oob; 5804 if (!ecc->write_oob_raw) 5805 ecc->write_oob_raw = ecc->write_oob; 5806 5807 /* propagate ecc info to mtd_info */ 5808 mtd->ecc_strength = ecc->strength; 5809 mtd->ecc_step_size = ecc->size; 5810 5811 /* 5812 * Set the number of read / write steps for one page depending on ECC 5813 * mode. 5814 */ 5815 ecc->steps = mtd->writesize / ecc->size; 5816 if (ecc->steps * ecc->size != mtd->writesize) { 5817 WARN(1, "Invalid ECC parameters\n"); 5818 ret = -EINVAL; 5819 goto err_nand_manuf_cleanup; 5820 } 5821 ecc->total = ecc->steps * ecc->bytes; 5822 if (ecc->total > mtd->oobsize) { 5823 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); 5824 ret = -EINVAL; 5825 goto err_nand_manuf_cleanup; 5826 } 5827 5828 /* 5829 * The number of bytes available for a client to place data into 5830 * the out of band area. 5831 */ 5832 ret = mtd_ooblayout_count_freebytes(mtd); 5833 if (ret < 0) 5834 ret = 0; 5835 5836 mtd->oobavail = ret; 5837 5838 /* ECC sanity check: warn if it's too weak */ 5839 if (!nand_ecc_strength_good(chip)) 5840 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n", 5841 mtd->name, chip->ecc.strength, chip->ecc.size, 5842 chip->base.eccreq.strength, 5843 chip->base.eccreq.step_size); 5844 5845 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 5846 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 5847 switch (ecc->steps) { 5848 case 2: 5849 mtd->subpage_sft = 1; 5850 break; 5851 case 4: 5852 case 8: 5853 case 16: 5854 mtd->subpage_sft = 2; 5855 break; 5856 } 5857 } 5858 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 5859 5860 /* Invalidate the pagebuffer reference */ 5861 chip->pagecache.page = -1; 5862 5863 /* Large page NAND with SOFT_ECC should support subpage reads */ 5864 switch (ecc->mode) { 5865 case NAND_ECC_SOFT: 5866 if (chip->page_shift > 9) 5867 chip->options |= NAND_SUBPAGE_READ; 5868 break; 5869 5870 default: 5871 break; 5872 } 5873 5874 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner); 5875 if (ret) 5876 goto err_nand_manuf_cleanup; 5877 5878 /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */ 5879 if (chip->options & NAND_ROM) 5880 mtd->flags = MTD_CAP_ROM; 5881 5882 /* Fill in remaining MTD driver data */ 5883 mtd->_erase = nand_erase; 5884 mtd->_point = NULL; 5885 mtd->_unpoint = NULL; 5886 mtd->_panic_write = panic_nand_write; 5887 mtd->_read_oob = nand_read_oob; 5888 mtd->_write_oob = nand_write_oob; 5889 mtd->_sync = nand_sync; 5890 mtd->_lock = nand_lock; 5891 mtd->_unlock = nand_unlock; 5892 mtd->_suspend = nand_suspend; 5893 mtd->_resume = nand_resume; 5894 mtd->_reboot = nand_shutdown; 5895 mtd->_block_isreserved = nand_block_isreserved; 5896 mtd->_block_isbad = nand_block_isbad; 5897 mtd->_block_markbad = nand_block_markbad; 5898 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; 5899 5900 /* 5901 * Initialize bitflip_threshold to its default prior scan_bbt() call. 5902 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 5903 * properly set. 5904 */ 5905 if (!mtd->bitflip_threshold) 5906 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); 5907 5908 /* Initialize the ->data_interface field. */ 5909 ret = nand_init_data_interface(chip); 5910 if (ret) 5911 goto err_nanddev_cleanup; 5912 5913 /* Enter fastest possible mode on all dies. */ 5914 for (i = 0; i < nanddev_ntargets(&chip->base); i++) { 5915 ret = nand_setup_data_interface(chip, i); 5916 if (ret) 5917 goto err_nanddev_cleanup; 5918 } 5919 5920 /* Check, if we should skip the bad block table scan */ 5921 if (chip->options & NAND_SKIP_BBTSCAN) 5922 return 0; 5923 5924 /* Build bad block table */ 5925 ret = nand_create_bbt(chip); 5926 if (ret) 5927 goto err_nanddev_cleanup; 5928 5929 return 0; 5930 5931 5932 err_nanddev_cleanup: 5933 nanddev_cleanup(&chip->base); 5934 5935 err_nand_manuf_cleanup: 5936 nand_manufacturer_cleanup(chip); 5937 5938 err_free_buf: 5939 kfree(chip->data_buf); 5940 kfree(ecc->code_buf); 5941 kfree(ecc->calc_buf); 5942 5943 return ret; 5944 } 5945 5946 static int nand_attach(struct nand_chip *chip) 5947 { 5948 if (chip->controller->ops && chip->controller->ops->attach_chip) 5949 return chip->controller->ops->attach_chip(chip); 5950 5951 return 0; 5952 } 5953 5954 static void nand_detach(struct nand_chip *chip) 5955 { 5956 if (chip->controller->ops && chip->controller->ops->detach_chip) 5957 chip->controller->ops->detach_chip(chip); 5958 } 5959 5960 /** 5961 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device 5962 * @chip: NAND chip object 5963 * @maxchips: number of chips to scan for. 5964 * @ids: optional flash IDs table 5965 * 5966 * This fills out all the uninitialized function pointers with the defaults. 5967 * The flash ID is read and the mtd/chip structures are filled with the 5968 * appropriate values. 5969 */ 5970 int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips, 5971 struct nand_flash_dev *ids) 5972 { 5973 int ret; 5974 5975 if (!maxchips) 5976 return -EINVAL; 5977 5978 ret = nand_scan_ident(chip, maxchips, ids); 5979 if (ret) 5980 return ret; 5981 5982 ret = nand_attach(chip); 5983 if (ret) 5984 goto cleanup_ident; 5985 5986 ret = nand_scan_tail(chip); 5987 if (ret) 5988 goto detach_chip; 5989 5990 return 0; 5991 5992 detach_chip: 5993 nand_detach(chip); 5994 cleanup_ident: 5995 nand_scan_ident_cleanup(chip); 5996 5997 return ret; 5998 } 5999 EXPORT_SYMBOL(nand_scan_with_ids); 6000 6001 /** 6002 * nand_cleanup - [NAND Interface] Free resources held by the NAND device 6003 * @chip: NAND chip object 6004 */ 6005 void nand_cleanup(struct nand_chip *chip) 6006 { 6007 if (chip->ecc.mode == NAND_ECC_SOFT && 6008 chip->ecc.algo == NAND_ECC_BCH) 6009 nand_bch_free((struct nand_bch_control *)chip->ecc.priv); 6010 6011 nanddev_cleanup(&chip->base); 6012 6013 /* Free bad block table memory */ 6014 kfree(chip->bbt); 6015 kfree(chip->data_buf); 6016 kfree(chip->ecc.code_buf); 6017 kfree(chip->ecc.calc_buf); 6018 6019 /* Free bad block descriptor memory */ 6020 if (chip->badblock_pattern && chip->badblock_pattern->options 6021 & NAND_BBT_DYNAMICSTRUCT) 6022 kfree(chip->badblock_pattern); 6023 6024 /* Free manufacturer priv data. */ 6025 nand_manufacturer_cleanup(chip); 6026 6027 /* Free controller specific allocations after chip identification */ 6028 nand_detach(chip); 6029 6030 /* Free identification phase allocations */ 6031 nand_scan_ident_cleanup(chip); 6032 } 6033 6034 EXPORT_SYMBOL_GPL(nand_cleanup); 6035 6036 /** 6037 * nand_release - [NAND Interface] Unregister the MTD device and free resources 6038 * held by the NAND device 6039 * @chip: NAND chip object 6040 */ 6041 void nand_release(struct nand_chip *chip) 6042 { 6043 mtd_device_unregister(nand_to_mtd(chip)); 6044 nand_cleanup(chip); 6045 } 6046 EXPORT_SYMBOL_GPL(nand_release); 6047 6048 MODULE_LICENSE("GPL"); 6049 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 6050 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 6051 MODULE_DESCRIPTION("Generic NAND flash driver code"); 6052