1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * Copyright 2009 Semihalf. 5 * 6 * Approved as OSADL project by a majority of OSADL members and funded 7 * by OSADL membership fees in 2009; for details see www.osadl.org. 8 * 9 * Based on original driver from Freescale Semiconductor 10 * written by John Rigby <jrigby@freescale.com> on basis of mxc_nand.c. 11 * Reworked and extended by Piotr Ziecik <kosmo@semihalf.com>. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/gfp.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/rawnand.h> 23 #include <linux/mtd/partitions.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/platform_device.h> 27 28 #include <asm/mpc5121.h> 29 30 /* Addresses for NFC MAIN RAM BUFFER areas */ 31 #define NFC_MAIN_AREA(n) ((n) * 0x200) 32 33 /* Addresses for NFC SPARE BUFFER areas */ 34 #define NFC_SPARE_BUFFERS 8 35 #define NFC_SPARE_LEN 0x40 36 #define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN)) 37 38 /* MPC5121 NFC registers */ 39 #define NFC_BUF_ADDR 0x1E04 40 #define NFC_FLASH_ADDR 0x1E06 41 #define NFC_FLASH_CMD 0x1E08 42 #define NFC_CONFIG 0x1E0A 43 #define NFC_ECC_STATUS1 0x1E0C 44 #define NFC_ECC_STATUS2 0x1E0E 45 #define NFC_SPAS 0x1E10 46 #define NFC_WRPROT 0x1E12 47 #define NFC_NF_WRPRST 0x1E18 48 #define NFC_CONFIG1 0x1E1A 49 #define NFC_CONFIG2 0x1E1C 50 #define NFC_UNLOCKSTART_BLK0 0x1E20 51 #define NFC_UNLOCKEND_BLK0 0x1E22 52 #define NFC_UNLOCKSTART_BLK1 0x1E24 53 #define NFC_UNLOCKEND_BLK1 0x1E26 54 #define NFC_UNLOCKSTART_BLK2 0x1E28 55 #define NFC_UNLOCKEND_BLK2 0x1E2A 56 #define NFC_UNLOCKSTART_BLK3 0x1E2C 57 #define NFC_UNLOCKEND_BLK3 0x1E2E 58 59 /* Bit Definitions: NFC_BUF_ADDR */ 60 #define NFC_RBA_MASK (7 << 0) 61 #define NFC_ACTIVE_CS_SHIFT 5 62 #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT) 63 64 /* Bit Definitions: NFC_CONFIG */ 65 #define NFC_BLS_UNLOCKED (1 << 1) 66 67 /* Bit Definitions: NFC_CONFIG1 */ 68 #define NFC_ECC_4BIT (1 << 0) 69 #define NFC_FULL_PAGE_DMA (1 << 1) 70 #define NFC_SPARE_ONLY (1 << 2) 71 #define NFC_ECC_ENABLE (1 << 3) 72 #define NFC_INT_MASK (1 << 4) 73 #define NFC_BIG_ENDIAN (1 << 5) 74 #define NFC_RESET (1 << 6) 75 #define NFC_CE (1 << 7) 76 #define NFC_ONE_CYCLE (1 << 8) 77 #define NFC_PPB_32 (0 << 9) 78 #define NFC_PPB_64 (1 << 9) 79 #define NFC_PPB_128 (2 << 9) 80 #define NFC_PPB_256 (3 << 9) 81 #define NFC_PPB_MASK (3 << 9) 82 #define NFC_FULL_PAGE_INT (1 << 11) 83 84 /* Bit Definitions: NFC_CONFIG2 */ 85 #define NFC_COMMAND (1 << 0) 86 #define NFC_ADDRESS (1 << 1) 87 #define NFC_INPUT (1 << 2) 88 #define NFC_OUTPUT (1 << 3) 89 #define NFC_ID (1 << 4) 90 #define NFC_STATUS (1 << 5) 91 #define NFC_CMD_FAIL (1 << 15) 92 #define NFC_INT (1 << 15) 93 94 /* Bit Definitions: NFC_WRPROT */ 95 #define NFC_WPC_LOCK_TIGHT (1 << 0) 96 #define NFC_WPC_LOCK (1 << 1) 97 #define NFC_WPC_UNLOCK (1 << 2) 98 99 #define DRV_NAME "mpc5121_nfc" 100 101 /* Timeouts */ 102 #define NFC_RESET_TIMEOUT 1000 /* 1 ms */ 103 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */ 104 105 struct mpc5121_nfc_prv { 106 struct nand_controller controller; 107 struct nand_chip chip; 108 int irq; 109 void __iomem *regs; 110 struct clk *clk; 111 wait_queue_head_t irq_waitq; 112 uint column; 113 int spareonly; 114 void __iomem *csreg; 115 struct device *dev; 116 }; 117 118 static void mpc5121_nfc_done(struct mtd_info *mtd); 119 120 /* Read NFC register */ 121 static inline u16 nfc_read(struct mtd_info *mtd, uint reg) 122 { 123 struct nand_chip *chip = mtd_to_nand(mtd); 124 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 125 126 return in_be16(prv->regs + reg); 127 } 128 129 /* Write NFC register */ 130 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) 131 { 132 struct nand_chip *chip = mtd_to_nand(mtd); 133 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 134 135 out_be16(prv->regs + reg, val); 136 } 137 138 /* Set bits in NFC register */ 139 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits) 140 { 141 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits); 142 } 143 144 /* Clear bits in NFC register */ 145 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits) 146 { 147 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits); 148 } 149 150 /* Invoke address cycle */ 151 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr) 152 { 153 nfc_write(mtd, NFC_FLASH_ADDR, addr); 154 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS); 155 mpc5121_nfc_done(mtd); 156 } 157 158 /* Invoke command cycle */ 159 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd) 160 { 161 nfc_write(mtd, NFC_FLASH_CMD, cmd); 162 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND); 163 mpc5121_nfc_done(mtd); 164 } 165 166 /* Send data from NFC buffers to NAND flash */ 167 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd) 168 { 169 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 170 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT); 171 mpc5121_nfc_done(mtd); 172 } 173 174 /* Receive data from NAND flash */ 175 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd) 176 { 177 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 178 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT); 179 mpc5121_nfc_done(mtd); 180 } 181 182 /* Receive ID from NAND flash */ 183 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd) 184 { 185 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 186 nfc_write(mtd, NFC_CONFIG2, NFC_ID); 187 mpc5121_nfc_done(mtd); 188 } 189 190 /* Receive status from NAND flash */ 191 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd) 192 { 193 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK); 194 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS); 195 mpc5121_nfc_done(mtd); 196 } 197 198 /* NFC interrupt handler */ 199 static irqreturn_t mpc5121_nfc_irq(int irq, void *data) 200 { 201 struct mtd_info *mtd = data; 202 struct nand_chip *chip = mtd_to_nand(mtd); 203 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 204 205 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK); 206 wake_up(&prv->irq_waitq); 207 208 return IRQ_HANDLED; 209 } 210 211 /* Wait for operation complete */ 212 static void mpc5121_nfc_done(struct mtd_info *mtd) 213 { 214 struct nand_chip *chip = mtd_to_nand(mtd); 215 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 216 int rv; 217 218 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) { 219 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK); 220 rv = wait_event_timeout(prv->irq_waitq, 221 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT); 222 223 if (!rv) 224 dev_warn(prv->dev, 225 "Timeout while waiting for interrupt.\n"); 226 } 227 228 nfc_clear(mtd, NFC_CONFIG2, NFC_INT); 229 } 230 231 /* Do address cycle(s) */ 232 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) 233 { 234 struct nand_chip *chip = mtd_to_nand(mtd); 235 u32 pagemask = chip->pagemask; 236 237 if (column != -1) { 238 mpc5121_nfc_send_addr(mtd, column); 239 if (mtd->writesize > 512) 240 mpc5121_nfc_send_addr(mtd, column >> 8); 241 } 242 243 if (page != -1) { 244 do { 245 mpc5121_nfc_send_addr(mtd, page & 0xFF); 246 page >>= 8; 247 pagemask >>= 8; 248 } while (pagemask); 249 } 250 } 251 252 /* Control chip select signals */ 253 static void mpc5121_nfc_select_chip(struct nand_chip *nand, int chip) 254 { 255 struct mtd_info *mtd = nand_to_mtd(nand); 256 257 if (chip < 0) { 258 nfc_clear(mtd, NFC_CONFIG1, NFC_CE); 259 return; 260 } 261 262 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK); 263 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) & 264 NFC_ACTIVE_CS_MASK); 265 nfc_set(mtd, NFC_CONFIG1, NFC_CE); 266 } 267 268 /* Init external chip select logic on ADS5121 board */ 269 static int ads5121_chipselect_init(struct mtd_info *mtd) 270 { 271 struct nand_chip *chip = mtd_to_nand(mtd); 272 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 273 struct device_node *dn; 274 275 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld"); 276 if (dn) { 277 prv->csreg = of_iomap(dn, 0); 278 of_node_put(dn); 279 if (!prv->csreg) 280 return -ENOMEM; 281 282 /* CPLD Register 9 controls NAND /CE Lines */ 283 prv->csreg += 9; 284 return 0; 285 } 286 287 return -EINVAL; 288 } 289 290 /* Control chips select signal on ADS5121 board */ 291 static void ads5121_select_chip(struct nand_chip *nand, int chip) 292 { 293 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); 294 u8 v; 295 296 v = in_8(prv->csreg); 297 v |= 0x0F; 298 299 if (chip >= 0) { 300 mpc5121_nfc_select_chip(nand, 0); 301 v &= ~(1 << chip); 302 } else 303 mpc5121_nfc_select_chip(nand, -1); 304 305 out_8(prv->csreg, v); 306 } 307 308 /* Read NAND Ready/Busy signal */ 309 static int mpc5121_nfc_dev_ready(struct nand_chip *nand) 310 { 311 /* 312 * NFC handles ready/busy signal internally. Therefore, this function 313 * always returns status as ready. 314 */ 315 return 1; 316 } 317 318 /* Write command to NAND flash */ 319 static void mpc5121_nfc_command(struct nand_chip *chip, unsigned command, 320 int column, int page) 321 { 322 struct mtd_info *mtd = nand_to_mtd(chip); 323 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 324 325 prv->column = (column >= 0) ? column : 0; 326 prv->spareonly = 0; 327 328 switch (command) { 329 case NAND_CMD_PAGEPROG: 330 mpc5121_nfc_send_prog_page(mtd); 331 break; 332 /* 333 * NFC does not support sub-page reads and writes, 334 * so emulate them using full page transfers. 335 */ 336 case NAND_CMD_READ0: 337 column = 0; 338 break; 339 340 case NAND_CMD_READ1: 341 prv->column += 256; 342 command = NAND_CMD_READ0; 343 column = 0; 344 break; 345 346 case NAND_CMD_READOOB: 347 prv->spareonly = 1; 348 command = NAND_CMD_READ0; 349 column = 0; 350 break; 351 352 case NAND_CMD_SEQIN: 353 mpc5121_nfc_command(chip, NAND_CMD_READ0, column, page); 354 column = 0; 355 break; 356 357 case NAND_CMD_ERASE1: 358 case NAND_CMD_ERASE2: 359 case NAND_CMD_READID: 360 case NAND_CMD_STATUS: 361 break; 362 363 default: 364 return; 365 } 366 367 mpc5121_nfc_send_cmd(mtd, command); 368 mpc5121_nfc_addr_cycle(mtd, column, page); 369 370 switch (command) { 371 case NAND_CMD_READ0: 372 if (mtd->writesize > 512) 373 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART); 374 mpc5121_nfc_send_read_page(mtd); 375 break; 376 377 case NAND_CMD_READID: 378 mpc5121_nfc_send_read_id(mtd); 379 break; 380 381 case NAND_CMD_STATUS: 382 mpc5121_nfc_send_read_status(mtd); 383 if (chip->options & NAND_BUSWIDTH_16) 384 prv->column = 1; 385 else 386 prv->column = 0; 387 break; 388 } 389 } 390 391 /* Copy data from/to NFC spare buffers. */ 392 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset, 393 u8 *buffer, uint size, int wr) 394 { 395 struct nand_chip *nand = mtd_to_nand(mtd); 396 struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand); 397 uint o, s, sbsize, blksize; 398 399 /* 400 * NAND spare area is available through NFC spare buffers. 401 * The NFC divides spare area into (page_size / 512) chunks. 402 * Each chunk is placed into separate spare memory area, using 403 * first (spare_size / num_of_chunks) bytes of the buffer. 404 * 405 * For NAND device in which the spare area is not divided fully 406 * by the number of chunks, number of used bytes in each spare 407 * buffer is rounded down to the nearest even number of bytes, 408 * and all remaining bytes are added to the last used spare area. 409 * 410 * For more information read section 26.6.10 of MPC5121e 411 * Microcontroller Reference Manual, Rev. 3. 412 */ 413 414 /* Calculate number of valid bytes in each spare buffer */ 415 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1; 416 417 while (size) { 418 /* Calculate spare buffer number */ 419 s = offset / sbsize; 420 if (s > NFC_SPARE_BUFFERS - 1) 421 s = NFC_SPARE_BUFFERS - 1; 422 423 /* 424 * Calculate offset to requested data block in selected spare 425 * buffer and its size. 426 */ 427 o = offset - (s * sbsize); 428 blksize = min(sbsize - o, size); 429 430 if (wr) 431 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o, 432 buffer, blksize); 433 else 434 memcpy_fromio(buffer, 435 prv->regs + NFC_SPARE_AREA(s) + o, blksize); 436 437 buffer += blksize; 438 offset += blksize; 439 size -= blksize; 440 } 441 } 442 443 /* Copy data from/to NFC main and spare buffers */ 444 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len, 445 int wr) 446 { 447 struct nand_chip *chip = mtd_to_nand(mtd); 448 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 449 uint c = prv->column; 450 uint l; 451 452 /* Handle spare area access */ 453 if (prv->spareonly || c >= mtd->writesize) { 454 /* Calculate offset from beginning of spare area */ 455 if (c >= mtd->writesize) 456 c -= mtd->writesize; 457 458 prv->column += len; 459 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr); 460 return; 461 } 462 463 /* 464 * Handle main area access - limit copy length to prevent 465 * crossing main/spare boundary. 466 */ 467 l = min((uint)len, mtd->writesize - c); 468 prv->column += l; 469 470 if (wr) 471 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l); 472 else 473 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l); 474 475 /* Handle crossing main/spare boundary */ 476 if (l != len) { 477 buf += l; 478 len -= l; 479 mpc5121_nfc_buf_copy(mtd, buf, len, wr); 480 } 481 } 482 483 /* Read data from NFC buffers */ 484 static void mpc5121_nfc_read_buf(struct nand_chip *chip, u_char *buf, int len) 485 { 486 mpc5121_nfc_buf_copy(nand_to_mtd(chip), buf, len, 0); 487 } 488 489 /* Write data to NFC buffers */ 490 static void mpc5121_nfc_write_buf(struct nand_chip *chip, const u_char *buf, 491 int len) 492 { 493 mpc5121_nfc_buf_copy(nand_to_mtd(chip), (u_char *)buf, len, 1); 494 } 495 496 /* Read byte from NFC buffers */ 497 static u8 mpc5121_nfc_read_byte(struct nand_chip *chip) 498 { 499 u8 tmp; 500 501 mpc5121_nfc_read_buf(chip, &tmp, sizeof(tmp)); 502 503 return tmp; 504 } 505 506 /* 507 * Read NFC configuration from Reset Config Word 508 * 509 * NFC is configured during reset in basis of information stored 510 * in Reset Config Word. There is no other way to set NAND block 511 * size, spare size and bus width. 512 */ 513 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd) 514 { 515 struct nand_chip *chip = mtd_to_nand(mtd); 516 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 517 struct mpc512x_reset_module *rm; 518 struct device_node *rmnode; 519 uint rcw_pagesize = 0; 520 uint rcw_sparesize = 0; 521 uint rcw_width; 522 uint rcwh; 523 uint romloc, ps; 524 int ret = 0; 525 526 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset"); 527 if (!rmnode) { 528 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' " 529 "node in device tree!\n"); 530 return -ENODEV; 531 } 532 533 rm = of_iomap(rmnode, 0); 534 if (!rm) { 535 dev_err(prv->dev, "Error mapping reset module node!\n"); 536 ret = -EBUSY; 537 goto out; 538 } 539 540 rcwh = in_be32(&rm->rcwhr); 541 542 /* Bit 6: NFC bus width */ 543 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1; 544 545 /* Bit 7: NFC Page/Spare size */ 546 ps = (rcwh >> 7) & 0x1; 547 548 /* Bits [22:21]: ROM Location */ 549 romloc = (rcwh >> 21) & 0x3; 550 551 /* Decode RCW bits */ 552 switch ((ps << 2) | romloc) { 553 case 0x00: 554 case 0x01: 555 rcw_pagesize = 512; 556 rcw_sparesize = 16; 557 break; 558 case 0x02: 559 case 0x03: 560 rcw_pagesize = 4096; 561 rcw_sparesize = 128; 562 break; 563 case 0x04: 564 case 0x05: 565 rcw_pagesize = 2048; 566 rcw_sparesize = 64; 567 break; 568 case 0x06: 569 case 0x07: 570 rcw_pagesize = 4096; 571 rcw_sparesize = 218; 572 break; 573 } 574 575 mtd->writesize = rcw_pagesize; 576 mtd->oobsize = rcw_sparesize; 577 if (rcw_width == 2) 578 chip->options |= NAND_BUSWIDTH_16; 579 580 dev_notice(prv->dev, "Configured for " 581 "%u-bit NAND, page size %u " 582 "with %u spare.\n", 583 rcw_width * 8, rcw_pagesize, 584 rcw_sparesize); 585 iounmap(rm); 586 out: 587 of_node_put(rmnode); 588 return ret; 589 } 590 591 /* Free driver resources */ 592 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd) 593 { 594 struct nand_chip *chip = mtd_to_nand(mtd); 595 struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); 596 597 if (prv->csreg) 598 iounmap(prv->csreg); 599 } 600 601 static int mpc5121_nfc_attach_chip(struct nand_chip *chip) 602 { 603 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 604 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) 605 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 606 607 return 0; 608 } 609 610 static const struct nand_controller_ops mpc5121_nfc_ops = { 611 .attach_chip = mpc5121_nfc_attach_chip, 612 }; 613 614 static int mpc5121_nfc_probe(struct platform_device *op) 615 { 616 struct device_node *dn = op->dev.of_node; 617 struct clk *clk; 618 struct device *dev = &op->dev; 619 struct mpc5121_nfc_prv *prv; 620 struct mtd_info *mtd; 621 struct nand_chip *chip; 622 const __be32 *chips_no; 623 void __iomem *regs; 624 int resettime = 0; 625 int retval = 0; 626 int rev, len; 627 int irq; 628 629 /* 630 * Check SoC revision. This driver supports only NFC 631 * in MPC5121 revision 2 and MPC5123 revision 3. 632 */ 633 rev = (mfspr(SPRN_SVR) >> 4) & 0xF; 634 if ((rev != 2) && (rev != 3)) { 635 dev_err(dev, "SoC revision %u is not supported!\n", rev); 636 return -ENXIO; 637 } 638 639 regs = devm_platform_ioremap_resource(op, 0); 640 if (IS_ERR(regs)) 641 return PTR_ERR(regs); 642 643 irq = platform_get_irq(op, 0); 644 if (irq < 0) 645 return irq; 646 647 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL); 648 if (!prv) 649 return -ENOMEM; 650 651 chip = &prv->chip; 652 mtd = nand_to_mtd(chip); 653 654 nand_controller_init(&prv->controller); 655 prv->controller.ops = &mpc5121_nfc_ops; 656 chip->controller = &prv->controller; 657 658 mtd->dev.parent = dev; 659 nand_set_controller_data(chip, prv); 660 nand_set_flash_node(chip, dn); 661 prv->dev = dev; 662 663 /* Read NFC configuration from Reset Config Word */ 664 retval = mpc5121_nfc_read_hw_config(mtd); 665 if (retval) { 666 dev_err(dev, "Unable to read NFC config!\n"); 667 return retval; 668 } 669 670 prv->irq = irq; 671 672 chips_no = of_get_property(dn, "chips", &len); 673 if (!chips_no || len != sizeof(*chips_no)) { 674 dev_err(dev, "Invalid/missing 'chips' property!\n"); 675 return -EINVAL; 676 } 677 678 prv->regs = regs; 679 680 mtd->name = "MPC5121 NAND"; 681 chip->legacy.dev_ready = mpc5121_nfc_dev_ready; 682 chip->legacy.cmdfunc = mpc5121_nfc_command; 683 chip->legacy.read_byte = mpc5121_nfc_read_byte; 684 chip->legacy.read_buf = mpc5121_nfc_read_buf; 685 chip->legacy.write_buf = mpc5121_nfc_write_buf; 686 chip->legacy.select_chip = mpc5121_nfc_select_chip; 687 chip->legacy.set_features = nand_get_set_features_notsupp; 688 chip->legacy.get_features = nand_get_set_features_notsupp; 689 chip->bbt_options = NAND_BBT_USE_FLASH; 690 691 /* Support external chip-select logic on ADS5121 board */ 692 if (of_machine_is_compatible("fsl,mpc5121ads")) { 693 retval = ads5121_chipselect_init(mtd); 694 if (retval) { 695 dev_err(dev, "Chipselect init error!\n"); 696 return retval; 697 } 698 699 chip->legacy.select_chip = ads5121_select_chip; 700 } 701 702 /* Enable NFC clock */ 703 clk = devm_clk_get_enabled(dev, "ipg"); 704 if (IS_ERR(clk)) { 705 dev_err(dev, "Unable to acquire and enable NFC clock!\n"); 706 retval = PTR_ERR(clk); 707 goto error; 708 } 709 prv->clk = clk; 710 711 /* Reset NAND Flash controller */ 712 nfc_set(mtd, NFC_CONFIG1, NFC_RESET); 713 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) { 714 if (resettime++ >= NFC_RESET_TIMEOUT) { 715 dev_err(dev, "Timeout while resetting NFC!\n"); 716 retval = -EINVAL; 717 goto error; 718 } 719 720 udelay(1); 721 } 722 723 /* Enable write to NFC memory */ 724 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED); 725 726 /* Enable write to all NAND pages */ 727 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000); 728 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF); 729 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK); 730 731 /* 732 * Setup NFC: 733 * - Big Endian transfers, 734 * - Interrupt after full page read/write. 735 */ 736 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK | 737 NFC_FULL_PAGE_INT); 738 739 /* Set spare area size */ 740 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1); 741 742 init_waitqueue_head(&prv->irq_waitq); 743 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME, 744 mtd); 745 if (retval) { 746 dev_err(dev, "Error requesting IRQ!\n"); 747 goto error; 748 } 749 750 /* 751 * This driver assumes that the default ECC engine should be TYPE_SOFT. 752 * Set ->engine_type before registering the NAND devices in order to 753 * provide a driver specific default value. 754 */ 755 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 756 757 /* Detect NAND chips */ 758 retval = nand_scan(chip, be32_to_cpup(chips_no)); 759 if (retval) { 760 dev_err(dev, "NAND Flash not found !\n"); 761 goto error; 762 } 763 764 /* Set erase block size */ 765 switch (mtd->erasesize / mtd->writesize) { 766 case 32: 767 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32); 768 break; 769 770 case 64: 771 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64); 772 break; 773 774 case 128: 775 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128); 776 break; 777 778 case 256: 779 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256); 780 break; 781 782 default: 783 dev_err(dev, "Unsupported NAND flash!\n"); 784 retval = -ENXIO; 785 goto error; 786 } 787 788 dev_set_drvdata(dev, mtd); 789 790 /* Register device in MTD */ 791 retval = mtd_device_register(mtd, NULL, 0); 792 if (retval) { 793 dev_err(dev, "Error adding MTD device!\n"); 794 goto error; 795 } 796 797 return 0; 798 error: 799 mpc5121_nfc_free(dev, mtd); 800 return retval; 801 } 802 803 static void mpc5121_nfc_remove(struct platform_device *op) 804 { 805 struct device *dev = &op->dev; 806 struct mtd_info *mtd = dev_get_drvdata(dev); 807 int ret; 808 809 ret = mtd_device_unregister(mtd); 810 WARN_ON(ret); 811 nand_cleanup(mtd_to_nand(mtd)); 812 mpc5121_nfc_free(dev, mtd); 813 } 814 815 static const struct of_device_id mpc5121_nfc_match[] = { 816 { .compatible = "fsl,mpc5121-nfc", }, 817 {}, 818 }; 819 MODULE_DEVICE_TABLE(of, mpc5121_nfc_match); 820 821 static struct platform_driver mpc5121_nfc_driver = { 822 .probe = mpc5121_nfc_probe, 823 .remove = mpc5121_nfc_remove, 824 .driver = { 825 .name = DRV_NAME, 826 .of_match_table = mpc5121_nfc_match, 827 }, 828 }; 829 830 module_platform_driver(mpc5121_nfc_driver); 831 832 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 833 MODULE_DESCRIPTION("MPC5121 NAND MTD driver"); 834 MODULE_LICENSE("GPL"); 835