1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2010-2015 Broadcom Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/init.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/platform_device.h> 12 #include <linux/platform_data/brcmnand.h> 13 #include <linux/err.h> 14 #include <linux/completion.h> 15 #include <linux/interrupt.h> 16 #include <linux/spinlock.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/ioport.h> 19 #include <linux/bug.h> 20 #include <linux/kernel.h> 21 #include <linux/bitops.h> 22 #include <linux/mm.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/rawnand.h> 25 #include <linux/mtd/partitions.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/slab.h> 29 #include <linux/static_key.h> 30 #include <linux/list.h> 31 #include <linux/log2.h> 32 33 #include "brcmnand.h" 34 35 /* 36 * This flag controls if WP stays on between erase/write commands to mitigate 37 * flash corruption due to power glitches. Values: 38 * 0: NAND_WP is not used or not available 39 * 1: NAND_WP is set by default, cleared for erase/write operations 40 * 2: NAND_WP is always cleared 41 */ 42 static int wp_on = 1; 43 module_param(wp_on, int, 0444); 44 45 /*********************************************************************** 46 * Definitions 47 ***********************************************************************/ 48 49 #define DRV_NAME "brcmnand" 50 51 #define CMD_NULL 0x00 52 #define CMD_PAGE_READ 0x01 53 #define CMD_SPARE_AREA_READ 0x02 54 #define CMD_STATUS_READ 0x03 55 #define CMD_PROGRAM_PAGE 0x04 56 #define CMD_PROGRAM_SPARE_AREA 0x05 57 #define CMD_COPY_BACK 0x06 58 #define CMD_DEVICE_ID_READ 0x07 59 #define CMD_BLOCK_ERASE 0x08 60 #define CMD_FLASH_RESET 0x09 61 #define CMD_BLOCKS_LOCK 0x0a 62 #define CMD_BLOCKS_LOCK_DOWN 0x0b 63 #define CMD_BLOCKS_UNLOCK 0x0c 64 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d 65 #define CMD_PARAMETER_READ 0x0e 66 #define CMD_PARAMETER_CHANGE_COL 0x0f 67 #define CMD_LOW_LEVEL_OP 0x10 68 #define CMD_NOT_SUPPORTED 0xff 69 70 struct brcm_nand_dma_desc { 71 u32 next_desc; 72 u32 next_desc_ext; 73 u32 cmd_irq; 74 u32 dram_addr; 75 u32 dram_addr_ext; 76 u32 tfr_len; 77 u32 total_len; 78 u32 flash_addr; 79 u32 flash_addr_ext; 80 u32 cs; 81 u32 pad2[5]; 82 u32 status_valid; 83 } __packed; 84 85 /* Bitfields for brcm_nand_dma_desc::status_valid */ 86 #define FLASH_DMA_ECC_ERROR (1 << 8) 87 #define FLASH_DMA_CORR_ERROR (1 << 9) 88 89 /* Bitfields for DMA_MODE */ 90 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ 91 #define FLASH_DMA_MODE_MODE BIT(0) /* link list */ 92 #define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \ 93 FLASH_DMA_MODE_MODE) 94 95 /* 512B flash cache in the NAND controller HW */ 96 #define FC_SHIFT 9U 97 #define FC_BYTES 512U 98 #define FC_WORDS (FC_BYTES >> 2) 99 100 #define BRCMNAND_MIN_PAGESIZE 512 101 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) 102 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) 103 104 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 105 #define NAND_POLL_STATUS_TIMEOUT_MS 500 106 107 #define EDU_CMD_WRITE 0x00 108 #define EDU_CMD_READ 0x01 109 #define EDU_STATUS_ACTIVE BIT(0) 110 #define EDU_ERR_STATUS_ERRACK BIT(0) 111 #define EDU_DONE_MASK GENMASK(1, 0) 112 113 #define EDU_CONFIG_MODE_NAND BIT(0) 114 #define EDU_CONFIG_SWAP_BYTE BIT(1) 115 #ifdef CONFIG_CPU_BIG_ENDIAN 116 #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE 117 #else 118 #define EDU_CONFIG_SWAP_CFG 0 119 #endif 120 121 /* edu registers */ 122 enum edu_reg { 123 EDU_CONFIG = 0, 124 EDU_DRAM_ADDR, 125 EDU_EXT_ADDR, 126 EDU_LENGTH, 127 EDU_CMD, 128 EDU_STOP, 129 EDU_STATUS, 130 EDU_DONE, 131 EDU_ERR_STATUS, 132 }; 133 134 static const u16 edu_regs[] = { 135 [EDU_CONFIG] = 0x00, 136 [EDU_DRAM_ADDR] = 0x04, 137 [EDU_EXT_ADDR] = 0x08, 138 [EDU_LENGTH] = 0x0c, 139 [EDU_CMD] = 0x10, 140 [EDU_STOP] = 0x14, 141 [EDU_STATUS] = 0x18, 142 [EDU_DONE] = 0x1c, 143 [EDU_ERR_STATUS] = 0x20, 144 }; 145 146 /* flash_dma registers */ 147 enum flash_dma_reg { 148 FLASH_DMA_REVISION = 0, 149 FLASH_DMA_FIRST_DESC, 150 FLASH_DMA_FIRST_DESC_EXT, 151 FLASH_DMA_CTRL, 152 FLASH_DMA_MODE, 153 FLASH_DMA_STATUS, 154 FLASH_DMA_INTERRUPT_DESC, 155 FLASH_DMA_INTERRUPT_DESC_EXT, 156 FLASH_DMA_ERROR_STATUS, 157 FLASH_DMA_CURRENT_DESC, 158 FLASH_DMA_CURRENT_DESC_EXT, 159 }; 160 161 /* flash_dma registers v0*/ 162 static const u16 flash_dma_regs_v0[] = { 163 [FLASH_DMA_REVISION] = 0x00, 164 [FLASH_DMA_FIRST_DESC] = 0x04, 165 [FLASH_DMA_CTRL] = 0x08, 166 [FLASH_DMA_MODE] = 0x0c, 167 [FLASH_DMA_STATUS] = 0x10, 168 [FLASH_DMA_INTERRUPT_DESC] = 0x14, 169 [FLASH_DMA_ERROR_STATUS] = 0x18, 170 [FLASH_DMA_CURRENT_DESC] = 0x1c, 171 }; 172 173 /* flash_dma registers v1*/ 174 static const u16 flash_dma_regs_v1[] = { 175 [FLASH_DMA_REVISION] = 0x00, 176 [FLASH_DMA_FIRST_DESC] = 0x04, 177 [FLASH_DMA_FIRST_DESC_EXT] = 0x08, 178 [FLASH_DMA_CTRL] = 0x0c, 179 [FLASH_DMA_MODE] = 0x10, 180 [FLASH_DMA_STATUS] = 0x14, 181 [FLASH_DMA_INTERRUPT_DESC] = 0x18, 182 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c, 183 [FLASH_DMA_ERROR_STATUS] = 0x20, 184 [FLASH_DMA_CURRENT_DESC] = 0x24, 185 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28, 186 }; 187 188 /* flash_dma registers v4 */ 189 static const u16 flash_dma_regs_v4[] = { 190 [FLASH_DMA_REVISION] = 0x00, 191 [FLASH_DMA_FIRST_DESC] = 0x08, 192 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c, 193 [FLASH_DMA_CTRL] = 0x10, 194 [FLASH_DMA_MODE] = 0x14, 195 [FLASH_DMA_STATUS] = 0x18, 196 [FLASH_DMA_INTERRUPT_DESC] = 0x20, 197 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24, 198 [FLASH_DMA_ERROR_STATUS] = 0x28, 199 [FLASH_DMA_CURRENT_DESC] = 0x30, 200 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, 201 }; 202 203 /* Native command conversion for legacy controllers (< v5.0) */ 204 static const u8 native_cmd_conv[] = { 205 [NAND_CMD_READ0] = CMD_NOT_SUPPORTED, 206 [NAND_CMD_READ1] = CMD_NOT_SUPPORTED, 207 [NAND_CMD_RNDOUT] = CMD_PARAMETER_CHANGE_COL, 208 [NAND_CMD_PAGEPROG] = CMD_NOT_SUPPORTED, 209 [NAND_CMD_READOOB] = CMD_NOT_SUPPORTED, 210 [NAND_CMD_ERASE1] = CMD_BLOCK_ERASE, 211 [NAND_CMD_STATUS] = CMD_NOT_SUPPORTED, 212 [NAND_CMD_SEQIN] = CMD_NOT_SUPPORTED, 213 [NAND_CMD_RNDIN] = CMD_NOT_SUPPORTED, 214 [NAND_CMD_READID] = CMD_DEVICE_ID_READ, 215 [NAND_CMD_ERASE2] = CMD_NULL, 216 [NAND_CMD_PARAM] = CMD_PARAMETER_READ, 217 [NAND_CMD_GET_FEATURES] = CMD_NOT_SUPPORTED, 218 [NAND_CMD_SET_FEATURES] = CMD_NOT_SUPPORTED, 219 [NAND_CMD_RESET] = CMD_NOT_SUPPORTED, 220 [NAND_CMD_READSTART] = CMD_NOT_SUPPORTED, 221 [NAND_CMD_READCACHESEQ] = CMD_NOT_SUPPORTED, 222 [NAND_CMD_READCACHEEND] = CMD_NOT_SUPPORTED, 223 [NAND_CMD_RNDOUTSTART] = CMD_NULL, 224 [NAND_CMD_CACHEDPROG] = CMD_NOT_SUPPORTED, 225 }; 226 227 /* Controller feature flags */ 228 enum { 229 BRCMNAND_HAS_1K_SECTORS = BIT(0), 230 BRCMNAND_HAS_PREFETCH = BIT(1), 231 BRCMNAND_HAS_CACHE_MODE = BIT(2), 232 BRCMNAND_HAS_WP = BIT(3), 233 }; 234 235 struct brcmnand_host; 236 237 static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key); 238 239 struct brcmnand_controller { 240 struct device *dev; 241 struct nand_controller controller; 242 void __iomem *nand_base; 243 void __iomem *nand_fc; /* flash cache */ 244 void __iomem *flash_dma_base; 245 int irq; 246 unsigned int dma_irq; 247 int nand_version; 248 249 /* Some SoCs provide custom interrupt status register(s) */ 250 struct brcmnand_soc *soc; 251 252 /* Some SoCs have a gateable clock for the controller */ 253 struct clk *clk; 254 255 int cmd_pending; 256 bool dma_pending; 257 bool edu_pending; 258 struct completion done; 259 struct completion dma_done; 260 struct completion edu_done; 261 262 /* List of NAND hosts (one for each chip-select) */ 263 struct list_head host_list; 264 265 /* Functions to be called from exec_op */ 266 int (*check_instr)(struct nand_chip *chip, 267 const struct nand_operation *op); 268 int (*exec_instr)(struct nand_chip *chip, 269 const struct nand_operation *op); 270 271 /* EDU info, per-transaction */ 272 const u16 *edu_offsets; 273 void __iomem *edu_base; 274 int edu_irq; 275 int edu_count; 276 u64 edu_dram_addr; 277 u32 edu_ext_addr; 278 u32 edu_cmd; 279 u32 edu_config; 280 int sas; /* spare area size, per flash cache */ 281 int sector_size_1k; 282 u8 *oob; 283 284 /* flash_dma reg */ 285 const u16 *flash_dma_offsets; 286 struct brcm_nand_dma_desc *dma_desc; 287 dma_addr_t dma_pa; 288 289 int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf, 290 u8 *oob, u32 len, u8 dma_cmd); 291 292 /* in-memory cache of the FLASH_CACHE, used only for some commands */ 293 u8 flash_cache[FC_BYTES]; 294 295 /* Controller revision details */ 296 const u16 *reg_offsets; 297 unsigned int reg_spacing; /* between CS1, CS2, ... regs */ 298 const u8 *cs_offsets; /* within each chip-select */ 299 const u8 *cs0_offsets; /* within CS0, if different */ 300 unsigned int max_block_size; 301 const unsigned int *block_sizes; 302 unsigned int max_page_size; 303 const unsigned int *page_sizes; 304 unsigned int page_size_shift; 305 unsigned int max_oob; 306 u32 ecc_level_shift; 307 u32 features; 308 309 /* for low-power standby/resume only */ 310 u32 nand_cs_nand_select; 311 u32 nand_cs_nand_xor; 312 u32 corr_stat_threshold; 313 u32 flash_dma_mode; 314 u32 flash_edu_mode; 315 bool pio_poll_mode; 316 }; 317 318 struct brcmnand_cfg { 319 u64 device_size; 320 unsigned int block_size; 321 unsigned int page_size; 322 unsigned int spare_area_size; 323 unsigned int device_width; 324 unsigned int col_adr_bytes; 325 unsigned int blk_adr_bytes; 326 unsigned int ful_adr_bytes; 327 unsigned int sector_size_1k; 328 unsigned int ecc_level; 329 /* use for low-power standby/resume only */ 330 u32 acc_control; 331 u32 config; 332 u32 config_ext; 333 u32 timing_1; 334 u32 timing_2; 335 }; 336 337 struct brcmnand_host { 338 struct list_head node; 339 340 struct nand_chip chip; 341 struct platform_device *pdev; 342 int cs; 343 344 struct brcmnand_cfg hwcfg; 345 struct brcmnand_controller *ctrl; 346 }; 347 348 enum brcmnand_reg { 349 BRCMNAND_CMD_START = 0, 350 BRCMNAND_CMD_EXT_ADDRESS, 351 BRCMNAND_CMD_ADDRESS, 352 BRCMNAND_INTFC_STATUS, 353 BRCMNAND_CS_SELECT, 354 BRCMNAND_CS_XOR, 355 BRCMNAND_LL_OP, 356 BRCMNAND_CS0_BASE, 357 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ 358 BRCMNAND_CORR_THRESHOLD, 359 BRCMNAND_CORR_THRESHOLD_EXT, 360 BRCMNAND_UNCORR_COUNT, 361 BRCMNAND_CORR_COUNT, 362 BRCMNAND_CORR_EXT_ADDR, 363 BRCMNAND_CORR_ADDR, 364 BRCMNAND_UNCORR_EXT_ADDR, 365 BRCMNAND_UNCORR_ADDR, 366 BRCMNAND_SEMAPHORE, 367 BRCMNAND_ID, 368 BRCMNAND_ID_EXT, 369 BRCMNAND_LL_RDATA, 370 BRCMNAND_OOB_READ_BASE, 371 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ 372 BRCMNAND_OOB_WRITE_BASE, 373 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ 374 BRCMNAND_FC_BASE, 375 }; 376 377 /* BRCMNAND v2.1-v2.2 */ 378 static const u16 brcmnand_regs_v21[] = { 379 [BRCMNAND_CMD_START] = 0x04, 380 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 381 [BRCMNAND_CMD_ADDRESS] = 0x0c, 382 [BRCMNAND_INTFC_STATUS] = 0x5c, 383 [BRCMNAND_CS_SELECT] = 0x14, 384 [BRCMNAND_CS_XOR] = 0x18, 385 [BRCMNAND_LL_OP] = 0, 386 [BRCMNAND_CS0_BASE] = 0x40, 387 [BRCMNAND_CS1_BASE] = 0, 388 [BRCMNAND_CORR_THRESHOLD] = 0, 389 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 390 [BRCMNAND_UNCORR_COUNT] = 0, 391 [BRCMNAND_CORR_COUNT] = 0, 392 [BRCMNAND_CORR_EXT_ADDR] = 0x60, 393 [BRCMNAND_CORR_ADDR] = 0x64, 394 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68, 395 [BRCMNAND_UNCORR_ADDR] = 0x6c, 396 [BRCMNAND_SEMAPHORE] = 0x50, 397 [BRCMNAND_ID] = 0x54, 398 [BRCMNAND_ID_EXT] = 0, 399 [BRCMNAND_LL_RDATA] = 0, 400 [BRCMNAND_OOB_READ_BASE] = 0x20, 401 [BRCMNAND_OOB_READ_10_BASE] = 0, 402 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 403 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 404 [BRCMNAND_FC_BASE] = 0x200, 405 }; 406 407 /* BRCMNAND v3.3-v4.0 */ 408 static const u16 brcmnand_regs_v33[] = { 409 [BRCMNAND_CMD_START] = 0x04, 410 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 411 [BRCMNAND_CMD_ADDRESS] = 0x0c, 412 [BRCMNAND_INTFC_STATUS] = 0x6c, 413 [BRCMNAND_CS_SELECT] = 0x14, 414 [BRCMNAND_CS_XOR] = 0x18, 415 [BRCMNAND_LL_OP] = 0x178, 416 [BRCMNAND_CS0_BASE] = 0x40, 417 [BRCMNAND_CS1_BASE] = 0xd0, 418 [BRCMNAND_CORR_THRESHOLD] = 0x84, 419 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 420 [BRCMNAND_UNCORR_COUNT] = 0, 421 [BRCMNAND_CORR_COUNT] = 0, 422 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 423 [BRCMNAND_CORR_ADDR] = 0x74, 424 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 425 [BRCMNAND_UNCORR_ADDR] = 0x7c, 426 [BRCMNAND_SEMAPHORE] = 0x58, 427 [BRCMNAND_ID] = 0x60, 428 [BRCMNAND_ID_EXT] = 0x64, 429 [BRCMNAND_LL_RDATA] = 0x17c, 430 [BRCMNAND_OOB_READ_BASE] = 0x20, 431 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 432 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 433 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 434 [BRCMNAND_FC_BASE] = 0x200, 435 }; 436 437 /* BRCMNAND v5.0 */ 438 static const u16 brcmnand_regs_v50[] = { 439 [BRCMNAND_CMD_START] = 0x04, 440 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 441 [BRCMNAND_CMD_ADDRESS] = 0x0c, 442 [BRCMNAND_INTFC_STATUS] = 0x6c, 443 [BRCMNAND_CS_SELECT] = 0x14, 444 [BRCMNAND_CS_XOR] = 0x18, 445 [BRCMNAND_LL_OP] = 0x178, 446 [BRCMNAND_CS0_BASE] = 0x40, 447 [BRCMNAND_CS1_BASE] = 0xd0, 448 [BRCMNAND_CORR_THRESHOLD] = 0x84, 449 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 450 [BRCMNAND_UNCORR_COUNT] = 0, 451 [BRCMNAND_CORR_COUNT] = 0, 452 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 453 [BRCMNAND_CORR_ADDR] = 0x74, 454 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 455 [BRCMNAND_UNCORR_ADDR] = 0x7c, 456 [BRCMNAND_SEMAPHORE] = 0x58, 457 [BRCMNAND_ID] = 0x60, 458 [BRCMNAND_ID_EXT] = 0x64, 459 [BRCMNAND_LL_RDATA] = 0x17c, 460 [BRCMNAND_OOB_READ_BASE] = 0x20, 461 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 462 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 463 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, 464 [BRCMNAND_FC_BASE] = 0x200, 465 }; 466 467 /* BRCMNAND v6.0 - v7.1 */ 468 static const u16 brcmnand_regs_v60[] = { 469 [BRCMNAND_CMD_START] = 0x04, 470 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 471 [BRCMNAND_CMD_ADDRESS] = 0x0c, 472 [BRCMNAND_INTFC_STATUS] = 0x14, 473 [BRCMNAND_CS_SELECT] = 0x18, 474 [BRCMNAND_CS_XOR] = 0x1c, 475 [BRCMNAND_LL_OP] = 0x20, 476 [BRCMNAND_CS0_BASE] = 0x50, 477 [BRCMNAND_CS1_BASE] = 0, 478 [BRCMNAND_CORR_THRESHOLD] = 0xc0, 479 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, 480 [BRCMNAND_UNCORR_COUNT] = 0xfc, 481 [BRCMNAND_CORR_COUNT] = 0x100, 482 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 483 [BRCMNAND_CORR_ADDR] = 0x110, 484 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 485 [BRCMNAND_UNCORR_ADDR] = 0x118, 486 [BRCMNAND_SEMAPHORE] = 0x150, 487 [BRCMNAND_ID] = 0x194, 488 [BRCMNAND_ID_EXT] = 0x198, 489 [BRCMNAND_LL_RDATA] = 0x19c, 490 [BRCMNAND_OOB_READ_BASE] = 0x200, 491 [BRCMNAND_OOB_READ_10_BASE] = 0, 492 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 493 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 494 [BRCMNAND_FC_BASE] = 0x400, 495 }; 496 497 /* BRCMNAND v7.1 */ 498 static const u16 brcmnand_regs_v71[] = { 499 [BRCMNAND_CMD_START] = 0x04, 500 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 501 [BRCMNAND_CMD_ADDRESS] = 0x0c, 502 [BRCMNAND_INTFC_STATUS] = 0x14, 503 [BRCMNAND_CS_SELECT] = 0x18, 504 [BRCMNAND_CS_XOR] = 0x1c, 505 [BRCMNAND_LL_OP] = 0x20, 506 [BRCMNAND_CS0_BASE] = 0x50, 507 [BRCMNAND_CS1_BASE] = 0, 508 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 509 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 510 [BRCMNAND_UNCORR_COUNT] = 0xfc, 511 [BRCMNAND_CORR_COUNT] = 0x100, 512 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 513 [BRCMNAND_CORR_ADDR] = 0x110, 514 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 515 [BRCMNAND_UNCORR_ADDR] = 0x118, 516 [BRCMNAND_SEMAPHORE] = 0x150, 517 [BRCMNAND_ID] = 0x194, 518 [BRCMNAND_ID_EXT] = 0x198, 519 [BRCMNAND_LL_RDATA] = 0x19c, 520 [BRCMNAND_OOB_READ_BASE] = 0x200, 521 [BRCMNAND_OOB_READ_10_BASE] = 0, 522 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 523 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 524 [BRCMNAND_FC_BASE] = 0x400, 525 }; 526 527 /* BRCMNAND v7.2 */ 528 static const u16 brcmnand_regs_v72[] = { 529 [BRCMNAND_CMD_START] = 0x04, 530 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 531 [BRCMNAND_CMD_ADDRESS] = 0x0c, 532 [BRCMNAND_INTFC_STATUS] = 0x14, 533 [BRCMNAND_CS_SELECT] = 0x18, 534 [BRCMNAND_CS_XOR] = 0x1c, 535 [BRCMNAND_LL_OP] = 0x20, 536 [BRCMNAND_CS0_BASE] = 0x50, 537 [BRCMNAND_CS1_BASE] = 0, 538 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 539 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 540 [BRCMNAND_UNCORR_COUNT] = 0xfc, 541 [BRCMNAND_CORR_COUNT] = 0x100, 542 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 543 [BRCMNAND_CORR_ADDR] = 0x110, 544 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 545 [BRCMNAND_UNCORR_ADDR] = 0x118, 546 [BRCMNAND_SEMAPHORE] = 0x150, 547 [BRCMNAND_ID] = 0x194, 548 [BRCMNAND_ID_EXT] = 0x198, 549 [BRCMNAND_LL_RDATA] = 0x19c, 550 [BRCMNAND_OOB_READ_BASE] = 0x200, 551 [BRCMNAND_OOB_READ_10_BASE] = 0, 552 [BRCMNAND_OOB_WRITE_BASE] = 0x400, 553 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 554 [BRCMNAND_FC_BASE] = 0x600, 555 }; 556 557 enum brcmnand_cs_reg { 558 BRCMNAND_CS_CFG_EXT = 0, 559 BRCMNAND_CS_CFG, 560 BRCMNAND_CS_ACC_CONTROL, 561 BRCMNAND_CS_TIMING1, 562 BRCMNAND_CS_TIMING2, 563 }; 564 565 /* Per chip-select offsets for v7.1 */ 566 static const u8 brcmnand_cs_offsets_v71[] = { 567 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 568 [BRCMNAND_CS_CFG_EXT] = 0x04, 569 [BRCMNAND_CS_CFG] = 0x08, 570 [BRCMNAND_CS_TIMING1] = 0x0c, 571 [BRCMNAND_CS_TIMING2] = 0x10, 572 }; 573 574 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ 575 static const u8 brcmnand_cs_offsets[] = { 576 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 577 [BRCMNAND_CS_CFG_EXT] = 0x04, 578 [BRCMNAND_CS_CFG] = 0x04, 579 [BRCMNAND_CS_TIMING1] = 0x08, 580 [BRCMNAND_CS_TIMING2] = 0x0c, 581 }; 582 583 /* Per chip-select offset for <= v5.0 on CS0 only */ 584 static const u8 brcmnand_cs_offsets_cs0[] = { 585 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 586 [BRCMNAND_CS_CFG_EXT] = 0x08, 587 [BRCMNAND_CS_CFG] = 0x08, 588 [BRCMNAND_CS_TIMING1] = 0x10, 589 [BRCMNAND_CS_TIMING2] = 0x14, 590 }; 591 592 /* 593 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had 594 * one config register, but once the bitfields overflowed, newer controllers 595 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. 596 */ 597 enum { 598 CFG_BLK_ADR_BYTES_SHIFT = 8, 599 CFG_COL_ADR_BYTES_SHIFT = 12, 600 CFG_FUL_ADR_BYTES_SHIFT = 16, 601 CFG_BUS_WIDTH_SHIFT = 23, 602 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), 603 CFG_DEVICE_SIZE_SHIFT = 24, 604 605 /* Only for v2.1 */ 606 CFG_PAGE_SIZE_SHIFT_v2_1 = 30, 607 608 /* Only for pre-v7.1 (with no CFG_EXT register) */ 609 CFG_PAGE_SIZE_SHIFT = 20, 610 CFG_BLK_SIZE_SHIFT = 28, 611 612 /* Only for v7.1+ (with CFG_EXT register) */ 613 CFG_EXT_PAGE_SIZE_SHIFT = 0, 614 CFG_EXT_BLK_SIZE_SHIFT = 4, 615 }; 616 617 /* BRCMNAND_INTFC_STATUS */ 618 enum { 619 INTFC_FLASH_STATUS = GENMASK(7, 0), 620 621 INTFC_ERASED = BIT(27), 622 INTFC_OOB_VALID = BIT(28), 623 INTFC_CACHE_VALID = BIT(29), 624 INTFC_FLASH_READY = BIT(30), 625 INTFC_CTLR_READY = BIT(31), 626 }; 627 628 /*********************************************************************** 629 * NAND ACC CONTROL bitfield 630 * 631 * Some bits have remained constant throughout hardware revision, while 632 * others have shifted around. 633 ***********************************************************************/ 634 635 /* Constant for all versions (where supported) */ 636 enum { 637 /* See BRCMNAND_HAS_CACHE_MODE */ 638 ACC_CONTROL_CACHE_MODE = BIT(22), 639 640 /* See BRCMNAND_HAS_PREFETCH */ 641 ACC_CONTROL_PREFETCH = BIT(23), 642 643 ACC_CONTROL_PAGE_HIT = BIT(24), 644 ACC_CONTROL_WR_PREEMPT = BIT(25), 645 ACC_CONTROL_PARTIAL_PAGE = BIT(26), 646 ACC_CONTROL_RD_ERASED = BIT(27), 647 ACC_CONTROL_FAST_PGM_RDIN = BIT(28), 648 ACC_CONTROL_WR_ECC = BIT(30), 649 ACC_CONTROL_RD_ECC = BIT(31), 650 }; 651 652 #define ACC_CONTROL_ECC_SHIFT 16 653 /* Only for v7.2 */ 654 #define ACC_CONTROL_ECC_EXT_SHIFT 13 655 656 static int brcmnand_status(struct brcmnand_host *host); 657 658 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) 659 { 660 #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) 661 return static_branch_unlikely(&brcmnand_soc_has_ops_key); 662 #else 663 return false; 664 #endif 665 } 666 667 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) 668 { 669 if (brcmnand_non_mmio_ops(ctrl)) 670 return brcmnand_soc_read(ctrl->soc, offs); 671 return brcmnand_readl(ctrl->nand_base + offs); 672 } 673 674 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, 675 u32 val) 676 { 677 if (brcmnand_non_mmio_ops(ctrl)) 678 brcmnand_soc_write(ctrl->soc, val, offs); 679 else 680 brcmnand_writel(val, ctrl->nand_base + offs); 681 } 682 683 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) 684 { 685 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; 686 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; 687 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 }; 688 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 }; 689 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 }; 690 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 }; 691 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 }; 692 693 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; 694 695 /* Only support v2.1+ */ 696 if (ctrl->nand_version < 0x0201) { 697 dev_err(ctrl->dev, "version %#x not supported\n", 698 ctrl->nand_version); 699 return -ENODEV; 700 } 701 702 /* Register offsets */ 703 if (ctrl->nand_version >= 0x0702) 704 ctrl->reg_offsets = brcmnand_regs_v72; 705 else if (ctrl->nand_version == 0x0701) 706 ctrl->reg_offsets = brcmnand_regs_v71; 707 else if (ctrl->nand_version >= 0x0600) 708 ctrl->reg_offsets = brcmnand_regs_v60; 709 else if (ctrl->nand_version >= 0x0500) 710 ctrl->reg_offsets = brcmnand_regs_v50; 711 else if (ctrl->nand_version >= 0x0303) 712 ctrl->reg_offsets = brcmnand_regs_v33; 713 else if (ctrl->nand_version >= 0x0201) 714 ctrl->reg_offsets = brcmnand_regs_v21; 715 716 /* Chip-select stride */ 717 if (ctrl->nand_version >= 0x0701) 718 ctrl->reg_spacing = 0x14; 719 else 720 ctrl->reg_spacing = 0x10; 721 722 /* Per chip-select registers */ 723 if (ctrl->nand_version >= 0x0701) { 724 ctrl->cs_offsets = brcmnand_cs_offsets_v71; 725 } else { 726 ctrl->cs_offsets = brcmnand_cs_offsets; 727 728 /* v3.3-5.0 have a different CS0 offset layout */ 729 if (ctrl->nand_version >= 0x0303 && 730 ctrl->nand_version <= 0x0500) 731 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; 732 } 733 734 /* Page / block sizes */ 735 if (ctrl->nand_version >= 0x0701) { 736 /* >= v7.1 use nice power-of-2 values! */ 737 ctrl->max_page_size = 16 * 1024; 738 ctrl->max_block_size = 2 * 1024 * 1024; 739 } else { 740 if (ctrl->nand_version >= 0x0304) 741 ctrl->page_sizes = page_sizes_v3_4; 742 else if (ctrl->nand_version >= 0x0202) 743 ctrl->page_sizes = page_sizes_v2_2; 744 else 745 ctrl->page_sizes = page_sizes_v2_1; 746 747 if (ctrl->nand_version >= 0x0202) 748 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; 749 else 750 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; 751 752 if (ctrl->nand_version >= 0x0600) 753 ctrl->block_sizes = block_sizes_v6; 754 else if (ctrl->nand_version >= 0x0400) 755 ctrl->block_sizes = block_sizes_v4; 756 else if (ctrl->nand_version >= 0x0202) 757 ctrl->block_sizes = block_sizes_v2_2; 758 else 759 ctrl->block_sizes = block_sizes_v2_1; 760 761 if (ctrl->nand_version < 0x0400) { 762 if (ctrl->nand_version < 0x0202) 763 ctrl->max_page_size = 2048; 764 else 765 ctrl->max_page_size = 4096; 766 ctrl->max_block_size = 512 * 1024; 767 } 768 } 769 770 /* Maximum spare area sector size (per 512B) */ 771 if (ctrl->nand_version == 0x0702) 772 ctrl->max_oob = 128; 773 else if (ctrl->nand_version >= 0x0600) 774 ctrl->max_oob = 64; 775 else if (ctrl->nand_version >= 0x0500) 776 ctrl->max_oob = 32; 777 else 778 ctrl->max_oob = 16; 779 780 /* v6.0 and newer (except v6.1) have prefetch support */ 781 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) 782 ctrl->features |= BRCMNAND_HAS_PREFETCH; 783 784 /* 785 * v6.x has cache mode, but it's implemented differently. Ignore it for 786 * now. 787 */ 788 if (ctrl->nand_version >= 0x0700) 789 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; 790 791 if (ctrl->nand_version >= 0x0500) 792 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; 793 794 if (ctrl->nand_version >= 0x0700) 795 ctrl->features |= BRCMNAND_HAS_WP; 796 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) 797 ctrl->features |= BRCMNAND_HAS_WP; 798 799 /* v7.2 has different ecc level shift in the acc register */ 800 if (ctrl->nand_version == 0x0702) 801 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; 802 else 803 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; 804 805 return 0; 806 } 807 808 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) 809 { 810 /* flash_dma register offsets */ 811 if (ctrl->nand_version >= 0x0703) 812 ctrl->flash_dma_offsets = flash_dma_regs_v4; 813 else if (ctrl->nand_version == 0x0602) 814 ctrl->flash_dma_offsets = flash_dma_regs_v0; 815 else 816 ctrl->flash_dma_offsets = flash_dma_regs_v1; 817 } 818 819 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, 820 enum brcmnand_reg reg) 821 { 822 u16 offs = ctrl->reg_offsets[reg]; 823 824 if (offs) 825 return nand_readreg(ctrl, offs); 826 else 827 return 0; 828 } 829 830 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, 831 enum brcmnand_reg reg, u32 val) 832 { 833 u16 offs = ctrl->reg_offsets[reg]; 834 835 if (offs) 836 nand_writereg(ctrl, offs, val); 837 } 838 839 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, 840 enum brcmnand_reg reg, u32 mask, unsigned 841 int shift, u32 val) 842 { 843 u32 tmp = brcmnand_read_reg(ctrl, reg); 844 845 tmp &= ~mask; 846 tmp |= val << shift; 847 brcmnand_write_reg(ctrl, reg, tmp); 848 } 849 850 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) 851 { 852 if (brcmnand_non_mmio_ops(ctrl)) 853 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); 854 return __raw_readl(ctrl->nand_fc + word * 4); 855 } 856 857 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, 858 int word, u32 val) 859 { 860 if (brcmnand_non_mmio_ops(ctrl)) 861 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); 862 else 863 __raw_writel(val, ctrl->nand_fc + word * 4); 864 } 865 866 static inline void edu_writel(struct brcmnand_controller *ctrl, 867 enum edu_reg reg, u32 val) 868 { 869 u16 offs = ctrl->edu_offsets[reg]; 870 871 brcmnand_writel(val, ctrl->edu_base + offs); 872 } 873 874 static inline u32 edu_readl(struct brcmnand_controller *ctrl, 875 enum edu_reg reg) 876 { 877 u16 offs = ctrl->edu_offsets[reg]; 878 879 return brcmnand_readl(ctrl->edu_base + offs); 880 } 881 882 static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl, 883 void __iomem *flash_cache, u32 *buffer, int fc_words) 884 { 885 struct brcmnand_soc *soc = ctrl->soc; 886 int i; 887 888 if (soc && soc->read_data_bus) { 889 soc->read_data_bus(soc, flash_cache, buffer, fc_words); 890 } else { 891 for (i = 0; i < fc_words; i++) 892 buffer[i] = brcmnand_read_fc(ctrl, i); 893 } 894 } 895 896 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) 897 { 898 899 /* Clear error addresses */ 900 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); 901 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); 902 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); 903 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); 904 } 905 906 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) 907 { 908 u64 err_addr; 909 910 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); 911 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 912 BRCMNAND_UNCORR_EXT_ADDR) 913 & 0xffff) << 32); 914 915 return err_addr; 916 } 917 918 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) 919 { 920 u64 err_addr; 921 922 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); 923 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 924 BRCMNAND_CORR_EXT_ADDR) 925 & 0xffff) << 32); 926 927 return err_addr; 928 } 929 930 static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr) 931 { 932 struct nand_chip *chip = mtd_to_nand(mtd); 933 struct brcmnand_host *host = nand_get_controller_data(chip); 934 struct brcmnand_controller *ctrl = host->ctrl; 935 936 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 937 (host->cs << 16) | ((addr >> 32) & 0xffff)); 938 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 939 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 940 lower_32_bits(addr)); 941 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 942 } 943 944 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, 945 enum brcmnand_cs_reg reg) 946 { 947 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; 948 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; 949 u8 cs_offs; 950 951 if (cs == 0 && ctrl->cs0_offsets) 952 cs_offs = ctrl->cs0_offsets[reg]; 953 else 954 cs_offs = ctrl->cs_offsets[reg]; 955 956 if (cs && offs_cs1) 957 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; 958 959 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; 960 } 961 962 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) 963 { 964 if (ctrl->nand_version < 0x0600) 965 return 1; 966 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); 967 } 968 969 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) 970 { 971 struct brcmnand_controller *ctrl = host->ctrl; 972 unsigned int shift = 0, bits; 973 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; 974 int cs = host->cs; 975 976 if (!ctrl->reg_offsets[reg]) 977 return; 978 979 if (ctrl->nand_version == 0x0702) 980 bits = 7; 981 else if (ctrl->nand_version >= 0x0600) 982 bits = 6; 983 else if (ctrl->nand_version >= 0x0500) 984 bits = 5; 985 else 986 bits = 4; 987 988 if (ctrl->nand_version >= 0x0702) { 989 if (cs >= 4) 990 reg = BRCMNAND_CORR_THRESHOLD_EXT; 991 shift = (cs % 4) * bits; 992 } else if (ctrl->nand_version >= 0x0600) { 993 if (cs >= 5) 994 reg = BRCMNAND_CORR_THRESHOLD_EXT; 995 shift = (cs % 5) * bits; 996 } 997 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); 998 } 999 1000 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) 1001 { 1002 /* Kludge for the BCMA-based NAND controller which does not actually 1003 * shift the command 1004 */ 1005 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) 1006 return 0; 1007 1008 if (ctrl->nand_version < 0x0602) 1009 return 24; 1010 return 0; 1011 } 1012 1013 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) 1014 { 1015 if (ctrl->nand_version == 0x0702) 1016 return GENMASK(7, 0); 1017 else if (ctrl->nand_version >= 0x0600) 1018 return GENMASK(6, 0); 1019 else if (ctrl->nand_version >= 0x0303) 1020 return GENMASK(5, 0); 1021 else 1022 return GENMASK(4, 0); 1023 } 1024 1025 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) 1026 { 1027 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; 1028 1029 mask <<= ACC_CONTROL_ECC_SHIFT; 1030 1031 /* v7.2 includes additional ECC levels */ 1032 if (ctrl->nand_version == 0x0702) 1033 mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; 1034 1035 return mask; 1036 } 1037 1038 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) 1039 { 1040 struct brcmnand_controller *ctrl = host->ctrl; 1041 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 1042 u32 acc_control = nand_readreg(ctrl, offs); 1043 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; 1044 1045 if (en) { 1046 acc_control |= ecc_flags; /* enable RD/WR ECC */ 1047 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 1048 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; 1049 } else { 1050 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ 1051 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 1052 } 1053 1054 nand_writereg(ctrl, offs, acc_control); 1055 } 1056 1057 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) 1058 { 1059 if (ctrl->nand_version >= 0x0702) 1060 return 9; 1061 else if (ctrl->nand_version >= 0x0600) 1062 return 7; 1063 else if (ctrl->nand_version >= 0x0500) 1064 return 6; 1065 else 1066 return -1; 1067 } 1068 1069 static bool brcmnand_get_sector_size_1k(struct brcmnand_host *host) 1070 { 1071 struct brcmnand_controller *ctrl = host->ctrl; 1072 int sector_size_bit = brcmnand_sector_1k_shift(ctrl); 1073 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1074 BRCMNAND_CS_ACC_CONTROL); 1075 u32 acc_control; 1076 1077 if (sector_size_bit < 0) 1078 return false; 1079 1080 acc_control = nand_readreg(ctrl, acc_control_offs); 1081 1082 return ((acc_control & BIT(sector_size_bit)) != 0); 1083 } 1084 1085 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) 1086 { 1087 struct brcmnand_controller *ctrl = host->ctrl; 1088 int shift = brcmnand_sector_1k_shift(ctrl); 1089 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1090 BRCMNAND_CS_ACC_CONTROL); 1091 u32 tmp; 1092 1093 if (shift < 0) 1094 return; 1095 1096 tmp = nand_readreg(ctrl, acc_control_offs); 1097 tmp &= ~(1 << shift); 1098 tmp |= (!!val) << shift; 1099 nand_writereg(ctrl, acc_control_offs, tmp); 1100 } 1101 1102 static int brcmnand_get_spare_size(struct brcmnand_host *host) 1103 { 1104 struct brcmnand_controller *ctrl = host->ctrl; 1105 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1106 BRCMNAND_CS_ACC_CONTROL); 1107 u32 acc = nand_readreg(ctrl, acc_control_offs); 1108 1109 return (acc & brcmnand_spare_area_mask(ctrl)); 1110 } 1111 1112 static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct nand_chip *chip) 1113 { 1114 struct brcmnand_controller *ctrl = host->ctrl; 1115 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1116 BRCMNAND_CS_ACC_CONTROL); 1117 bool sector_size_1k = brcmnand_get_sector_size_1k(host); 1118 int spare_area_size, ecc_level; 1119 u32 acc; 1120 1121 spare_area_size = brcmnand_get_spare_size(host); 1122 acc = nand_readreg(ctrl, acc_control_offs); 1123 ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift; 1124 if (sector_size_1k) 1125 chip->ecc.strength = ecc_level * 2; 1126 else if (spare_area_size == 16 && ecc_level == 15) 1127 chip->ecc.strength = 1; /* hamming */ 1128 else 1129 chip->ecc.strength = ecc_level; 1130 1131 if (chip->ecc.size == 0) { 1132 if (sector_size_1k) 1133 chip->ecc.size = 1024; 1134 else 1135 chip->ecc.size = 512; 1136 } 1137 } 1138 1139 /*********************************************************************** 1140 * CS_NAND_SELECT 1141 ***********************************************************************/ 1142 1143 enum { 1144 CS_SELECT_NAND_WP = BIT(29), 1145 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), 1146 }; 1147 1148 static int bcmnand_ctrl_poll_status(struct brcmnand_host *host, 1149 u32 mask, u32 expected_val, 1150 unsigned long timeout_ms) 1151 { 1152 struct brcmnand_controller *ctrl = host->ctrl; 1153 unsigned long limit; 1154 u32 val; 1155 1156 if (!timeout_ms) 1157 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 1158 1159 limit = jiffies + msecs_to_jiffies(timeout_ms); 1160 do { 1161 if (mask & INTFC_FLASH_STATUS) 1162 brcmnand_status(host); 1163 1164 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1165 if ((val & mask) == expected_val) 1166 return 0; 1167 1168 cpu_relax(); 1169 } while (time_after(limit, jiffies)); 1170 1171 /* 1172 * do a final check after time out in case the CPU was busy and the driver 1173 * did not get enough time to perform the polling to avoid false alarms 1174 */ 1175 if (mask & INTFC_FLASH_STATUS) 1176 brcmnand_status(host); 1177 1178 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1179 if ((val & mask) == expected_val) 1180 return 0; 1181 1182 dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n", 1183 expected_val, val & mask); 1184 1185 return -ETIMEDOUT; 1186 } 1187 1188 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) 1189 { 1190 u32 val = en ? CS_SELECT_NAND_WP : 0; 1191 1192 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); 1193 } 1194 1195 /*********************************************************************** 1196 * Flash DMA 1197 ***********************************************************************/ 1198 1199 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 1200 { 1201 return ctrl->flash_dma_base; 1202 } 1203 1204 static inline bool has_edu(struct brcmnand_controller *ctrl) 1205 { 1206 return ctrl->edu_base; 1207 } 1208 1209 static inline bool use_dma(struct brcmnand_controller *ctrl) 1210 { 1211 return has_flash_dma(ctrl) || has_edu(ctrl); 1212 } 1213 1214 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) 1215 { 1216 if (ctrl->pio_poll_mode) 1217 return; 1218 1219 if (has_flash_dma(ctrl)) { 1220 ctrl->flash_dma_base = NULL; 1221 disable_irq(ctrl->dma_irq); 1222 } 1223 1224 disable_irq(ctrl->irq); 1225 ctrl->pio_poll_mode = true; 1226 } 1227 1228 static inline bool flash_dma_buf_ok(const void *buf) 1229 { 1230 return buf && !is_vmalloc_addr(buf) && 1231 likely(IS_ALIGNED((uintptr_t)buf, 4)); 1232 } 1233 1234 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, 1235 enum flash_dma_reg dma_reg, u32 val) 1236 { 1237 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1238 1239 brcmnand_writel(val, ctrl->flash_dma_base + offs); 1240 } 1241 1242 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, 1243 enum flash_dma_reg dma_reg) 1244 { 1245 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1246 1247 return brcmnand_readl(ctrl->flash_dma_base + offs); 1248 } 1249 1250 /* Low-level operation types: command, address, write, or read */ 1251 enum brcmnand_llop_type { 1252 LL_OP_CMD, 1253 LL_OP_ADDR, 1254 LL_OP_WR, 1255 LL_OP_RD, 1256 }; 1257 1258 /*********************************************************************** 1259 * Internal support functions 1260 ***********************************************************************/ 1261 1262 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, 1263 struct brcmnand_cfg *cfg) 1264 { 1265 if (ctrl->nand_version <= 0x0701) 1266 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && 1267 cfg->ecc_level == 15; 1268 else 1269 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && 1270 cfg->ecc_level == 15) || 1271 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); 1272 } 1273 1274 /* 1275 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given 1276 * the layout/configuration. 1277 * Returns -ERRCODE on failure. 1278 */ 1279 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section, 1280 struct mtd_oob_region *oobregion) 1281 { 1282 struct nand_chip *chip = mtd_to_nand(mtd); 1283 struct brcmnand_host *host = nand_get_controller_data(chip); 1284 struct brcmnand_cfg *cfg = &host->hwcfg; 1285 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1286 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1287 1288 if (section >= sectors) 1289 return -ERANGE; 1290 1291 oobregion->offset = (section * sas) + 6; 1292 oobregion->length = 3; 1293 1294 return 0; 1295 } 1296 1297 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section, 1298 struct mtd_oob_region *oobregion) 1299 { 1300 struct nand_chip *chip = mtd_to_nand(mtd); 1301 struct brcmnand_host *host = nand_get_controller_data(chip); 1302 struct brcmnand_cfg *cfg = &host->hwcfg; 1303 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1304 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1305 u32 next; 1306 1307 if (section > sectors) 1308 return -ERANGE; 1309 1310 next = (section * sas); 1311 if (section < sectors) 1312 next += 6; 1313 1314 if (section) { 1315 oobregion->offset = ((section - 1) * sas) + 9; 1316 } else { 1317 if (cfg->page_size > 512) { 1318 /* Large page NAND uses first 2 bytes for BBI */ 1319 oobregion->offset = 2; 1320 } else { 1321 /* Small page NAND uses last byte before ECC for BBI */ 1322 oobregion->offset = 0; 1323 next--; 1324 } 1325 } 1326 1327 oobregion->length = next - oobregion->offset; 1328 1329 return 0; 1330 } 1331 1332 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = { 1333 .ecc = brcmnand_hamming_ooblayout_ecc, 1334 .free = brcmnand_hamming_ooblayout_free, 1335 }; 1336 1337 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section, 1338 struct mtd_oob_region *oobregion) 1339 { 1340 struct nand_chip *chip = mtd_to_nand(mtd); 1341 struct brcmnand_host *host = nand_get_controller_data(chip); 1342 struct brcmnand_cfg *cfg = &host->hwcfg; 1343 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1344 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1345 1346 if (section >= sectors) 1347 return -ERANGE; 1348 1349 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; 1350 oobregion->length = chip->ecc.bytes; 1351 1352 return 0; 1353 } 1354 1355 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section, 1356 struct mtd_oob_region *oobregion) 1357 { 1358 struct nand_chip *chip = mtd_to_nand(mtd); 1359 struct brcmnand_host *host = nand_get_controller_data(chip); 1360 struct brcmnand_cfg *cfg = &host->hwcfg; 1361 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1362 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1363 1364 if (section >= sectors) 1365 return -ERANGE; 1366 1367 if (sas <= chip->ecc.bytes) 1368 return 0; 1369 1370 oobregion->offset = section * sas; 1371 oobregion->length = sas - chip->ecc.bytes; 1372 1373 if (!section) { 1374 oobregion->offset++; 1375 oobregion->length--; 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section, 1382 struct mtd_oob_region *oobregion) 1383 { 1384 struct nand_chip *chip = mtd_to_nand(mtd); 1385 struct brcmnand_host *host = nand_get_controller_data(chip); 1386 struct brcmnand_cfg *cfg = &host->hwcfg; 1387 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1388 1389 if (section > 1 || sas - chip->ecc.bytes < 6 || 1390 (section && sas - chip->ecc.bytes == 6)) 1391 return -ERANGE; 1392 1393 if (!section) { 1394 oobregion->offset = 0; 1395 oobregion->length = 5; 1396 } else { 1397 oobregion->offset = 6; 1398 oobregion->length = sas - chip->ecc.bytes - 6; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = { 1405 .ecc = brcmnand_bch_ooblayout_ecc, 1406 .free = brcmnand_bch_ooblayout_free_lp, 1407 }; 1408 1409 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = { 1410 .ecc = brcmnand_bch_ooblayout_ecc, 1411 .free = brcmnand_bch_ooblayout_free_sp, 1412 }; 1413 1414 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host) 1415 { 1416 struct brcmnand_cfg *p = &host->hwcfg; 1417 struct mtd_info *mtd = nand_to_mtd(&host->chip); 1418 struct nand_ecc_ctrl *ecc = &host->chip.ecc; 1419 unsigned int ecc_level = p->ecc_level; 1420 int sas = p->spare_area_size << p->sector_size_1k; 1421 int sectors = p->page_size / (512 << p->sector_size_1k); 1422 1423 if (p->sector_size_1k) 1424 ecc_level <<= 1; 1425 1426 if (is_hamming_ecc(host->ctrl, p)) { 1427 ecc->bytes = 3 * sectors; 1428 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops); 1429 return 0; 1430 } 1431 1432 /* 1433 * CONTROLLER_VERSION: 1434 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) 1435 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) 1436 * But we will just be conservative. 1437 */ 1438 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); 1439 if (p->page_size == 512) 1440 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops); 1441 else 1442 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops); 1443 1444 if (ecc->bytes >= sas) { 1445 dev_err(&host->pdev->dev, 1446 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", 1447 ecc->bytes, sas); 1448 return -EINVAL; 1449 } 1450 1451 return 0; 1452 } 1453 1454 static void brcmnand_wp(struct mtd_info *mtd, int wp) 1455 { 1456 struct nand_chip *chip = mtd_to_nand(mtd); 1457 struct brcmnand_host *host = nand_get_controller_data(chip); 1458 struct brcmnand_controller *ctrl = host->ctrl; 1459 1460 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { 1461 static int old_wp = -1; 1462 int ret; 1463 1464 if (old_wp != wp) { 1465 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); 1466 old_wp = wp; 1467 } 1468 1469 /* 1470 * make sure ctrl/flash ready before and after 1471 * changing state of #WP pin 1472 */ 1473 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY | 1474 NAND_STATUS_READY, 1475 NAND_CTRL_RDY | 1476 NAND_STATUS_READY, 0); 1477 if (ret) 1478 return; 1479 1480 brcmnand_set_wp(ctrl, wp); 1481 /* force controller operation to update internal copy of NAND chip status */ 1482 brcmnand_status(host); 1483 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ 1484 ret = bcmnand_ctrl_poll_status(host, 1485 NAND_CTRL_RDY | 1486 NAND_STATUS_READY | 1487 NAND_STATUS_WP, 1488 NAND_CTRL_RDY | 1489 NAND_STATUS_READY | 1490 (wp ? 0 : NAND_STATUS_WP), 0); 1491 1492 if (ret) 1493 dev_err_ratelimited(&host->pdev->dev, 1494 "nand #WP expected %s\n", 1495 wp ? "on" : "off"); 1496 } 1497 } 1498 1499 /* Helper functions for reading and writing OOB registers */ 1500 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) 1501 { 1502 u16 offset0, offset10, reg_offs; 1503 1504 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; 1505 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; 1506 1507 if (offs >= ctrl->max_oob) 1508 return 0x77; 1509 1510 if (offs >= 16 && offset10) 1511 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1512 else 1513 reg_offs = offset0 + (offs & ~0x03); 1514 1515 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); 1516 } 1517 1518 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, 1519 u32 data) 1520 { 1521 u16 offset0, offset10, reg_offs; 1522 1523 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; 1524 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; 1525 1526 if (offs >= ctrl->max_oob) 1527 return; 1528 1529 if (offs >= 16 && offset10) 1530 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1531 else 1532 reg_offs = offset0 + (offs & ~0x03); 1533 1534 nand_writereg(ctrl, reg_offs, data); 1535 } 1536 1537 /* 1538 * read_oob_from_regs - read data from OOB registers 1539 * @ctrl: NAND controller 1540 * @i: sub-page sector index 1541 * @oob: buffer to read to 1542 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1543 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1544 */ 1545 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, 1546 int sas, int sector_1k) 1547 { 1548 int tbytes = sas << sector_1k; 1549 int j; 1550 1551 /* Adjust OOB values for 1K sector size */ 1552 if (sector_1k && (i & 0x01)) 1553 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1554 tbytes = min_t(int, tbytes, ctrl->max_oob); 1555 1556 for (j = 0; j < tbytes; j++) 1557 oob[j] = oob_reg_read(ctrl, j); 1558 return tbytes; 1559 } 1560 1561 /* 1562 * write_oob_to_regs - write data to OOB registers 1563 * @i: sub-page sector index 1564 * @oob: buffer to write from 1565 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1566 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1567 */ 1568 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, 1569 const u8 *oob, int sas, int sector_1k) 1570 { 1571 int tbytes = sas << sector_1k; 1572 int j, k = 0; 1573 u32 last = 0xffffffff; 1574 u8 *plast = (u8 *)&last; 1575 1576 /* Adjust OOB values for 1K sector size */ 1577 if (sector_1k && (i & 0x01)) 1578 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1579 tbytes = min_t(int, tbytes, ctrl->max_oob); 1580 1581 /* 1582 * tbytes may not be multiple of words. Make sure we don't read out of 1583 * the boundary and stop at last word. 1584 */ 1585 for (j = 0; (j + 3) < tbytes; j += 4) 1586 oob_reg_write(ctrl, j, 1587 (oob[j + 0] << 24) | 1588 (oob[j + 1] << 16) | 1589 (oob[j + 2] << 8) | 1590 (oob[j + 3] << 0)); 1591 1592 /* handle the remaining bytes */ 1593 while (j < tbytes) 1594 plast[k++] = oob[j++]; 1595 1596 if (tbytes & 0x3) 1597 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); 1598 1599 return tbytes; 1600 } 1601 1602 static void brcmnand_edu_init(struct brcmnand_controller *ctrl) 1603 { 1604 /* initialize edu */ 1605 edu_writel(ctrl, EDU_ERR_STATUS, 0); 1606 edu_readl(ctrl, EDU_ERR_STATUS); 1607 edu_writel(ctrl, EDU_DONE, 0); 1608 edu_writel(ctrl, EDU_DONE, 0); 1609 edu_writel(ctrl, EDU_DONE, 0); 1610 edu_writel(ctrl, EDU_DONE, 0); 1611 edu_readl(ctrl, EDU_DONE); 1612 } 1613 1614 /* edu irq */ 1615 static irqreturn_t brcmnand_edu_irq(int irq, void *data) 1616 { 1617 struct brcmnand_controller *ctrl = data; 1618 1619 if (ctrl->edu_count) { 1620 ctrl->edu_count--; 1621 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) 1622 udelay(1); 1623 edu_writel(ctrl, EDU_DONE, 0); 1624 edu_readl(ctrl, EDU_DONE); 1625 } 1626 1627 if (ctrl->edu_count) { 1628 ctrl->edu_dram_addr += FC_BYTES; 1629 ctrl->edu_ext_addr += FC_BYTES; 1630 1631 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1632 edu_readl(ctrl, EDU_DRAM_ADDR); 1633 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1634 edu_readl(ctrl, EDU_EXT_ADDR); 1635 1636 if (ctrl->oob) { 1637 if (ctrl->edu_cmd == EDU_CMD_READ) { 1638 ctrl->oob += read_oob_from_regs(ctrl, 1639 ctrl->edu_count + 1, 1640 ctrl->oob, ctrl->sas, 1641 ctrl->sector_size_1k); 1642 } else { 1643 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 1644 ctrl->edu_ext_addr); 1645 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1646 ctrl->oob += write_oob_to_regs(ctrl, 1647 ctrl->edu_count, 1648 ctrl->oob, ctrl->sas, 1649 ctrl->sector_size_1k); 1650 } 1651 } 1652 1653 mb(); /* flush previous writes */ 1654 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1655 edu_readl(ctrl, EDU_CMD); 1656 1657 return IRQ_HANDLED; 1658 } 1659 1660 complete(&ctrl->edu_done); 1661 1662 return IRQ_HANDLED; 1663 } 1664 1665 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 1666 { 1667 struct brcmnand_controller *ctrl = data; 1668 1669 /* Discard all NAND_CTLRDY interrupts during DMA */ 1670 if (ctrl->dma_pending) 1671 return IRQ_HANDLED; 1672 1673 /* check if you need to piggy back on the ctrlrdy irq */ 1674 if (ctrl->edu_pending) { 1675 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) 1676 /* Discard interrupts while using dedicated edu irq */ 1677 return IRQ_HANDLED; 1678 1679 /* no registered edu irq, call handler */ 1680 return brcmnand_edu_irq(irq, data); 1681 } 1682 1683 complete(&ctrl->done); 1684 return IRQ_HANDLED; 1685 } 1686 1687 /* Handle SoC-specific interrupt hardware */ 1688 static irqreturn_t brcmnand_irq(int irq, void *data) 1689 { 1690 struct brcmnand_controller *ctrl = data; 1691 1692 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) 1693 return brcmnand_ctlrdy_irq(irq, data); 1694 1695 return IRQ_NONE; 1696 } 1697 1698 static irqreturn_t brcmnand_dma_irq(int irq, void *data) 1699 { 1700 struct brcmnand_controller *ctrl = data; 1701 1702 complete(&ctrl->dma_done); 1703 1704 return IRQ_HANDLED; 1705 } 1706 1707 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) 1708 { 1709 struct brcmnand_controller *ctrl = host->ctrl; 1710 int ret; 1711 u64 cmd_addr; 1712 1713 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1714 1715 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); 1716 1717 /* 1718 * If we came here through _panic_write and there is a pending 1719 * command, try to wait for it. If it times out, rather than 1720 * hitting BUG_ON, just return so we don't crash while crashing. 1721 */ 1722 if (oops_in_progress) { 1723 if (ctrl->cmd_pending && 1724 bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) 1725 return; 1726 } else 1727 BUG_ON(ctrl->cmd_pending != 0); 1728 ctrl->cmd_pending = cmd; 1729 1730 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 1731 WARN_ON(ret); 1732 1733 mb(); /* flush previous writes */ 1734 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, 1735 cmd << brcmnand_cmd_shift(ctrl)); 1736 } 1737 1738 static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip) 1739 { 1740 struct brcmnand_host *host = nand_get_controller_data(chip); 1741 struct brcmnand_controller *ctrl = host->ctrl; 1742 struct mtd_info *mtd = nand_to_mtd(chip); 1743 bool err = false; 1744 int sts; 1745 1746 if (mtd->oops_panic_write || ctrl->irq < 0) { 1747 /* switch to interrupt polling and PIO mode */ 1748 disable_ctrl_irqs(ctrl); 1749 sts = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, 1750 NAND_CTRL_RDY, 0); 1751 err = sts < 0; 1752 } else { 1753 unsigned long timeo = msecs_to_jiffies( 1754 NAND_POLL_STATUS_TIMEOUT_MS); 1755 /* wait for completion interrupt */ 1756 sts = wait_for_completion_timeout(&ctrl->done, timeo); 1757 err = !sts; 1758 } 1759 1760 return err; 1761 } 1762 1763 static int brcmnand_waitfunc(struct nand_chip *chip) 1764 { 1765 struct brcmnand_host *host = nand_get_controller_data(chip); 1766 struct brcmnand_controller *ctrl = host->ctrl; 1767 bool err = false; 1768 1769 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 1770 if (ctrl->cmd_pending) 1771 err = brcmstb_nand_wait_for_completion(chip); 1772 1773 ctrl->cmd_pending = 0; 1774 if (err) { 1775 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) 1776 >> brcmnand_cmd_shift(ctrl); 1777 1778 dev_err_ratelimited(ctrl->dev, 1779 "timeout waiting for command %#02x\n", cmd); 1780 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", 1781 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); 1782 return -ETIMEDOUT; 1783 } 1784 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1785 INTFC_FLASH_STATUS; 1786 } 1787 1788 static int brcmnand_status(struct brcmnand_host *host) 1789 { 1790 struct nand_chip *chip = &host->chip; 1791 struct mtd_info *mtd = nand_to_mtd(chip); 1792 1793 brcmnand_set_cmd_addr(mtd, 0); 1794 brcmnand_send_cmd(host, CMD_STATUS_READ); 1795 1796 return brcmnand_waitfunc(chip); 1797 } 1798 1799 static int brcmnand_reset(struct brcmnand_host *host) 1800 { 1801 struct nand_chip *chip = &host->chip; 1802 1803 brcmnand_send_cmd(host, CMD_FLASH_RESET); 1804 1805 return brcmnand_waitfunc(chip); 1806 } 1807 1808 enum { 1809 LLOP_RE = BIT(16), 1810 LLOP_WE = BIT(17), 1811 LLOP_ALE = BIT(18), 1812 LLOP_CLE = BIT(19), 1813 LLOP_RETURN_IDLE = BIT(31), 1814 1815 LLOP_DATA_MASK = GENMASK(15, 0), 1816 }; 1817 1818 static int brcmnand_low_level_op(struct brcmnand_host *host, 1819 enum brcmnand_llop_type type, u32 data, 1820 bool last_op) 1821 { 1822 struct nand_chip *chip = &host->chip; 1823 struct brcmnand_controller *ctrl = host->ctrl; 1824 u32 tmp; 1825 1826 tmp = data & LLOP_DATA_MASK; 1827 switch (type) { 1828 case LL_OP_CMD: 1829 tmp |= LLOP_WE | LLOP_CLE; 1830 break; 1831 case LL_OP_ADDR: 1832 /* WE | ALE */ 1833 tmp |= LLOP_WE | LLOP_ALE; 1834 break; 1835 case LL_OP_WR: 1836 /* WE */ 1837 tmp |= LLOP_WE; 1838 break; 1839 case LL_OP_RD: 1840 /* RE */ 1841 tmp |= LLOP_RE; 1842 break; 1843 } 1844 if (last_op) 1845 /* RETURN_IDLE */ 1846 tmp |= LLOP_RETURN_IDLE; 1847 1848 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); 1849 1850 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); 1851 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); 1852 1853 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); 1854 return brcmnand_waitfunc(chip); 1855 } 1856 1857 /* 1858 * Kick EDU engine 1859 */ 1860 static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 1861 u8 *oob, u32 len, u8 cmd) 1862 { 1863 struct brcmnand_controller *ctrl = host->ctrl; 1864 struct brcmnand_cfg *cfg = &host->hwcfg; 1865 unsigned long timeo = msecs_to_jiffies(200); 1866 int ret = 0; 1867 int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 1868 u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE); 1869 unsigned int trans = len >> FC_SHIFT; 1870 dma_addr_t pa; 1871 1872 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? 1873 "read" : "write"), buf, oob); 1874 1875 pa = dma_map_single(ctrl->dev, buf, len, dir); 1876 if (dma_mapping_error(ctrl->dev, pa)) { 1877 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); 1878 return -ENOMEM; 1879 } 1880 1881 ctrl->edu_pending = true; 1882 ctrl->edu_dram_addr = pa; 1883 ctrl->edu_ext_addr = addr; 1884 ctrl->edu_cmd = edu_cmd; 1885 ctrl->edu_count = trans; 1886 ctrl->sas = cfg->spare_area_size; 1887 ctrl->oob = oob; 1888 1889 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1890 edu_readl(ctrl, EDU_DRAM_ADDR); 1891 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1892 edu_readl(ctrl, EDU_EXT_ADDR); 1893 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); 1894 edu_readl(ctrl, EDU_LENGTH); 1895 1896 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { 1897 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 1898 ctrl->edu_ext_addr); 1899 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1900 ctrl->oob += write_oob_to_regs(ctrl, 1901 1, 1902 ctrl->oob, ctrl->sas, 1903 ctrl->sector_size_1k); 1904 } 1905 1906 /* Start edu engine */ 1907 mb(); /* flush previous writes */ 1908 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1909 edu_readl(ctrl, EDU_CMD); 1910 1911 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { 1912 dev_err(ctrl->dev, 1913 "timeout waiting for EDU; status %#x, error status %#x\n", 1914 edu_readl(ctrl, EDU_STATUS), 1915 edu_readl(ctrl, EDU_ERR_STATUS)); 1916 } 1917 1918 dma_unmap_single(ctrl->dev, pa, len, dir); 1919 1920 /* read last subpage oob */ 1921 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { 1922 ctrl->oob += read_oob_from_regs(ctrl, 1923 1, 1924 ctrl->oob, ctrl->sas, 1925 ctrl->sector_size_1k); 1926 } 1927 1928 /* for program page check NAND status */ 1929 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1930 INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) && 1931 edu_cmd == EDU_CMD_WRITE) { 1932 dev_info(ctrl->dev, "program failed at %llx\n", 1933 (unsigned long long)addr); 1934 ret = -EIO; 1935 } 1936 1937 /* Make sure the EDU status is clean */ 1938 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) 1939 dev_warn(ctrl->dev, "EDU still active: %#x\n", 1940 edu_readl(ctrl, EDU_STATUS)); 1941 1942 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { 1943 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", 1944 (unsigned long long)addr); 1945 ret = -EIO; 1946 } 1947 1948 ctrl->edu_pending = false; 1949 brcmnand_edu_init(ctrl); 1950 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ 1951 edu_readl(ctrl, EDU_STOP); 1952 1953 if (!ret && edu_cmd == EDU_CMD_READ) { 1954 u64 err_addr = 0; 1955 1956 /* 1957 * check for ECC errors here, subpage ECC errors are 1958 * retained in ECC error address register 1959 */ 1960 err_addr = brcmnand_get_uncorrecc_addr(ctrl); 1961 if (!err_addr) { 1962 err_addr = brcmnand_get_correcc_addr(ctrl); 1963 if (err_addr) 1964 ret = -EUCLEAN; 1965 } else 1966 ret = -EBADMSG; 1967 } 1968 1969 return ret; 1970 } 1971 1972 /* 1973 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 1974 * following ahead of time: 1975 * - Is this descriptor the beginning or end of a linked list? 1976 * - What is the (DMA) address of the next descriptor in the linked list? 1977 */ 1978 static int brcmnand_fill_dma_desc(struct brcmnand_host *host, 1979 struct brcm_nand_dma_desc *desc, u64 addr, 1980 dma_addr_t buf, u32 len, u8 dma_cmd, 1981 bool begin, bool end, 1982 dma_addr_t next_desc) 1983 { 1984 memset(desc, 0, sizeof(*desc)); 1985 /* Descriptors are written in native byte order (wordwise) */ 1986 desc->next_desc = lower_32_bits(next_desc); 1987 desc->next_desc_ext = upper_32_bits(next_desc); 1988 desc->cmd_irq = (dma_cmd << 24) | 1989 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ 1990 (!!begin) | ((!!end) << 1); /* head, tail */ 1991 #ifdef CONFIG_CPU_BIG_ENDIAN 1992 desc->cmd_irq |= 0x01 << 12; 1993 #endif 1994 desc->dram_addr = lower_32_bits(buf); 1995 desc->dram_addr_ext = upper_32_bits(buf); 1996 desc->tfr_len = len; 1997 desc->total_len = len; 1998 desc->flash_addr = lower_32_bits(addr); 1999 desc->flash_addr_ext = upper_32_bits(addr); 2000 desc->cs = host->cs; 2001 desc->status_valid = 0x01; 2002 return 0; 2003 } 2004 2005 /* 2006 * Kick the FLASH_DMA engine, with a given DMA descriptor 2007 */ 2008 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) 2009 { 2010 struct brcmnand_controller *ctrl = host->ctrl; 2011 unsigned long timeo = msecs_to_jiffies(100); 2012 2013 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); 2014 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); 2015 if (ctrl->nand_version > 0x0602) { 2016 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, 2017 upper_32_bits(desc)); 2018 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); 2019 } 2020 2021 /* Start FLASH_DMA engine */ 2022 ctrl->dma_pending = true; 2023 mb(); /* flush previous writes */ 2024 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ 2025 2026 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { 2027 dev_err(ctrl->dev, 2028 "timeout waiting for DMA; status %#x, error status %#x\n", 2029 flash_dma_readl(ctrl, FLASH_DMA_STATUS), 2030 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); 2031 } 2032 ctrl->dma_pending = false; 2033 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ 2034 } 2035 2036 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 2037 u8 *oob, u32 len, u8 dma_cmd) 2038 { 2039 struct brcmnand_controller *ctrl = host->ctrl; 2040 dma_addr_t buf_pa; 2041 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2042 2043 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); 2044 if (dma_mapping_error(ctrl->dev, buf_pa)) { 2045 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); 2046 return -ENOMEM; 2047 } 2048 2049 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, 2050 dma_cmd, true, true, 0); 2051 2052 brcmnand_dma_run(host, ctrl->dma_pa); 2053 2054 dma_unmap_single(ctrl->dev, buf_pa, len, dir); 2055 2056 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) 2057 return -EBADMSG; 2058 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) 2059 return -EUCLEAN; 2060 2061 return 0; 2062 } 2063 2064 /* 2065 * Assumes proper CS is already set 2066 */ 2067 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 2068 u64 addr, unsigned int trans, u32 *buf, 2069 u8 *oob, u64 *err_addr) 2070 { 2071 struct brcmnand_host *host = nand_get_controller_data(chip); 2072 struct brcmnand_controller *ctrl = host->ctrl; 2073 int i, ret = 0; 2074 2075 brcmnand_clear_ecc_addr(ctrl); 2076 2077 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2078 brcmnand_set_cmd_addr(mtd, addr); 2079 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ 2080 brcmnand_send_cmd(host, CMD_PAGE_READ); 2081 brcmnand_waitfunc(chip); 2082 2083 if (likely(buf)) { 2084 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2085 2086 brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS); 2087 buf += FC_WORDS; 2088 2089 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2090 } 2091 2092 if (oob) 2093 oob += read_oob_from_regs(ctrl, i, oob, 2094 mtd->oobsize / trans, 2095 host->hwcfg.sector_size_1k); 2096 2097 if (ret != -EBADMSG) { 2098 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); 2099 2100 if (*err_addr) 2101 ret = -EBADMSG; 2102 } 2103 2104 if (!ret) { 2105 *err_addr = brcmnand_get_correcc_addr(ctrl); 2106 2107 if (*err_addr) 2108 ret = -EUCLEAN; 2109 } 2110 } 2111 2112 return ret; 2113 } 2114 2115 /* 2116 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC 2117 * error 2118 * 2119 * Because the HW ECC signals an ECC error if an erase paged has even a single 2120 * bitflip, we must check each ECC error to see if it is actually an erased 2121 * page with bitflips, not a truly corrupted page. 2122 * 2123 * On a real error, return a negative error code (-EBADMSG for ECC error), and 2124 * buf will contain raw data. 2125 * Otherwise, buf gets filled with 0xffs and return the maximum number of 2126 * bitflips-per-ECC-sector to the caller. 2127 * 2128 */ 2129 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, 2130 struct nand_chip *chip, void *buf, u64 addr) 2131 { 2132 struct mtd_oob_region ecc; 2133 int i; 2134 int bitflips = 0; 2135 int page = addr >> chip->page_shift; 2136 int ret; 2137 void *ecc_bytes; 2138 void *ecc_chunk; 2139 2140 if (!buf) 2141 buf = nand_get_data_buf(chip); 2142 2143 /* read without ecc for verification */ 2144 ret = chip->ecc.read_page_raw(chip, buf, true, page); 2145 if (ret) 2146 return ret; 2147 2148 for (i = 0; i < chip->ecc.steps; i++) { 2149 ecc_chunk = buf + chip->ecc.size * i; 2150 2151 mtd_ooblayout_ecc(mtd, i, &ecc); 2152 ecc_bytes = chip->oob_poi + ecc.offset; 2153 2154 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, 2155 ecc_bytes, ecc.length, 2156 NULL, 0, 2157 chip->ecc.strength); 2158 if (ret < 0) 2159 return ret; 2160 2161 bitflips = max(bitflips, ret); 2162 } 2163 2164 return bitflips; 2165 } 2166 2167 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, 2168 u64 addr, unsigned int trans, u32 *buf, u8 *oob) 2169 { 2170 struct brcmnand_host *host = nand_get_controller_data(chip); 2171 struct brcmnand_controller *ctrl = host->ctrl; 2172 u64 err_addr = 0; 2173 int err; 2174 bool retry = true; 2175 bool edu_err = false; 2176 2177 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); 2178 2179 try_dmaread: 2180 brcmnand_clear_ecc_addr(ctrl); 2181 2182 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && 2183 flash_dma_buf_ok(buf)) { 2184 err = ctrl->dma_trans(host, addr, buf, oob, 2185 trans * FC_BYTES, 2186 CMD_PAGE_READ); 2187 2188 if (err) { 2189 if (mtd_is_bitflip_or_eccerr(err)) 2190 err_addr = addr; 2191 else 2192 return -EIO; 2193 } 2194 2195 if (has_edu(ctrl) && err_addr) 2196 edu_err = true; 2197 2198 } else { 2199 if (oob) 2200 memset(oob, 0x99, mtd->oobsize); 2201 2202 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2203 oob, &err_addr); 2204 } 2205 2206 if (mtd_is_eccerr(err)) { 2207 /* 2208 * On controller version and 7.0, 7.1 , DMA read after a 2209 * prior PIO read that reported uncorrectable error, 2210 * the DMA engine captures this error following DMA read 2211 * cleared only on subsequent DMA read, so just retry once 2212 * to clear a possible false error reported for current DMA 2213 * read 2214 */ 2215 if ((ctrl->nand_version == 0x0700) || 2216 (ctrl->nand_version == 0x0701)) { 2217 if (retry) { 2218 retry = false; 2219 goto try_dmaread; 2220 } 2221 } 2222 2223 /* 2224 * Controller version 7.2 has hw encoder to detect erased page 2225 * bitflips, apply sw verification for older controllers only 2226 */ 2227 if (ctrl->nand_version < 0x0702) { 2228 err = brcmstb_nand_verify_erased_page(mtd, chip, buf, 2229 addr); 2230 /* erased page bitflips corrected */ 2231 if (err >= 0) 2232 return err; 2233 } 2234 2235 dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n", 2236 (unsigned long long)err_addr); 2237 mtd->ecc_stats.failed++; 2238 /* NAND layer expects zero on ECC errors */ 2239 return 0; 2240 } 2241 2242 if (mtd_is_bitflip(err)) { 2243 unsigned int corrected = brcmnand_count_corrected(ctrl); 2244 2245 /* in case of EDU correctable error we read again using PIO */ 2246 if (edu_err) 2247 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2248 oob, &err_addr); 2249 2250 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", 2251 (unsigned long long)err_addr); 2252 mtd->ecc_stats.corrected += corrected; 2253 /* Always exceed the software-imposed threshold */ 2254 return max(mtd->bitflip_threshold, corrected); 2255 } 2256 2257 return 0; 2258 } 2259 2260 static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf, 2261 int oob_required, int page) 2262 { 2263 struct mtd_info *mtd = nand_to_mtd(chip); 2264 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2265 u64 addr = (u64)page << chip->page_shift; 2266 2267 return brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT, 2268 (u32 *)buf, oob); 2269 } 2270 2271 static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 2272 int oob_required, int page) 2273 { 2274 struct brcmnand_host *host = nand_get_controller_data(chip); 2275 struct mtd_info *mtd = nand_to_mtd(chip); 2276 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2277 int ret; 2278 u64 addr = (u64)page << chip->page_shift; 2279 2280 brcmnand_set_ecc_enabled(host, 0); 2281 ret = brcmnand_read(mtd, chip, addr, mtd->writesize >> FC_SHIFT, 2282 (u32 *)buf, oob); 2283 brcmnand_set_ecc_enabled(host, 1); 2284 return ret; 2285 } 2286 2287 static int brcmnand_read_oob(struct nand_chip *chip, int page) 2288 { 2289 struct mtd_info *mtd = nand_to_mtd(chip); 2290 2291 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2292 mtd->writesize >> FC_SHIFT, 2293 NULL, (u8 *)chip->oob_poi); 2294 } 2295 2296 static int brcmnand_read_oob_raw(struct nand_chip *chip, int page) 2297 { 2298 struct mtd_info *mtd = nand_to_mtd(chip); 2299 struct brcmnand_host *host = nand_get_controller_data(chip); 2300 2301 brcmnand_set_ecc_enabled(host, 0); 2302 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2303 mtd->writesize >> FC_SHIFT, 2304 NULL, (u8 *)chip->oob_poi); 2305 brcmnand_set_ecc_enabled(host, 1); 2306 return 0; 2307 } 2308 2309 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 2310 u64 addr, const u32 *buf, u8 *oob) 2311 { 2312 struct brcmnand_host *host = nand_get_controller_data(chip); 2313 struct brcmnand_controller *ctrl = host->ctrl; 2314 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; 2315 int status, ret = 0; 2316 2317 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); 2318 2319 if (unlikely((unsigned long)buf & 0x03)) { 2320 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); 2321 buf = (u32 *)((unsigned long)buf & ~0x03); 2322 } 2323 2324 brcmnand_wp(mtd, 0); 2325 2326 for (i = 0; i < ctrl->max_oob; i += 4) 2327 oob_reg_write(ctrl, i, 0xffffffff); 2328 2329 if (mtd->oops_panic_write) 2330 /* switch to interrupt polling and PIO mode */ 2331 disable_ctrl_irqs(ctrl); 2332 2333 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) { 2334 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, 2335 CMD_PROGRAM_PAGE)) 2336 2337 ret = -EIO; 2338 2339 goto out; 2340 } 2341 2342 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2343 /* full address MUST be set before populating FC */ 2344 brcmnand_set_cmd_addr(mtd, addr); 2345 2346 if (buf) { 2347 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2348 2349 for (j = 0; j < FC_WORDS; j++, buf++) 2350 brcmnand_write_fc(ctrl, j, *buf); 2351 2352 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2353 } else if (oob) { 2354 for (j = 0; j < FC_WORDS; j++) 2355 brcmnand_write_fc(ctrl, j, 0xffffffff); 2356 } 2357 2358 if (oob) { 2359 oob += write_oob_to_regs(ctrl, i, oob, 2360 mtd->oobsize / trans, 2361 host->hwcfg.sector_size_1k); 2362 } 2363 2364 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ 2365 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); 2366 status = brcmnand_waitfunc(chip); 2367 2368 if (status < 0) { 2369 ret = status; 2370 goto out; 2371 } 2372 2373 if (status & NAND_STATUS_FAIL) { 2374 dev_info(ctrl->dev, "program failed at %llx\n", 2375 (unsigned long long)addr); 2376 ret = -EIO; 2377 goto out; 2378 } 2379 } 2380 out: 2381 brcmnand_wp(mtd, 1); 2382 return ret; 2383 } 2384 2385 static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf, 2386 int oob_required, int page) 2387 { 2388 struct mtd_info *mtd = nand_to_mtd(chip); 2389 void *oob = oob_required ? chip->oob_poi : NULL; 2390 u64 addr = (u64)page << chip->page_shift; 2391 2392 return brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob); 2393 } 2394 2395 static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 2396 int oob_required, int page) 2397 { 2398 struct mtd_info *mtd = nand_to_mtd(chip); 2399 struct brcmnand_host *host = nand_get_controller_data(chip); 2400 void *oob = oob_required ? chip->oob_poi : NULL; 2401 u64 addr = (u64)page << chip->page_shift; 2402 int ret = 0; 2403 2404 brcmnand_set_ecc_enabled(host, 0); 2405 ret = brcmnand_write(mtd, chip, addr, (const u32 *)buf, oob); 2406 brcmnand_set_ecc_enabled(host, 1); 2407 2408 return ret; 2409 } 2410 2411 static int brcmnand_write_oob(struct nand_chip *chip, int page) 2412 { 2413 return brcmnand_write(nand_to_mtd(chip), chip, 2414 (u64)page << chip->page_shift, NULL, 2415 chip->oob_poi); 2416 } 2417 2418 static int brcmnand_write_oob_raw(struct nand_chip *chip, int page) 2419 { 2420 struct mtd_info *mtd = nand_to_mtd(chip); 2421 struct brcmnand_host *host = nand_get_controller_data(chip); 2422 int ret; 2423 2424 brcmnand_set_ecc_enabled(host, 0); 2425 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, 2426 (u8 *)chip->oob_poi); 2427 brcmnand_set_ecc_enabled(host, 1); 2428 2429 return ret; 2430 } 2431 2432 static int brcmnand_exec_instr(struct brcmnand_host *host, int i, 2433 const struct nand_operation *op) 2434 { 2435 const struct nand_op_instr *instr = &op->instrs[i]; 2436 struct brcmnand_controller *ctrl = host->ctrl; 2437 const u8 *out; 2438 bool last_op; 2439 int ret = 0; 2440 u8 *in; 2441 2442 /* 2443 * The controller needs to be aware of the last command in the operation 2444 * (WAITRDY excepted). 2445 */ 2446 last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) || 2447 ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR)); 2448 2449 switch (instr->type) { 2450 case NAND_OP_CMD_INSTR: 2451 brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op); 2452 break; 2453 2454 case NAND_OP_ADDR_INSTR: 2455 for (i = 0; i < instr->ctx.addr.naddrs; i++) 2456 brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i], 2457 last_op && (i == (instr->ctx.addr.naddrs - 1))); 2458 break; 2459 2460 case NAND_OP_DATA_IN_INSTR: 2461 in = instr->ctx.data.buf.in; 2462 for (i = 0; i < instr->ctx.data.len; i++) { 2463 brcmnand_low_level_op(host, LL_OP_RD, 0, 2464 last_op && (i == (instr->ctx.data.len - 1))); 2465 in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA); 2466 } 2467 break; 2468 2469 case NAND_OP_DATA_OUT_INSTR: 2470 out = instr->ctx.data.buf.out; 2471 for (i = 0; i < instr->ctx.data.len; i++) 2472 brcmnand_low_level_op(host, LL_OP_WR, out[i], 2473 last_op && (i == (instr->ctx.data.len - 1))); 2474 break; 2475 2476 case NAND_OP_WAITRDY_INSTR: 2477 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 2478 break; 2479 2480 default: 2481 dev_err(ctrl->dev, "unsupported instruction type: %d\n", 2482 instr->type); 2483 ret = -EINVAL; 2484 break; 2485 } 2486 2487 return ret; 2488 } 2489 2490 static int brcmnand_op_is_status(const struct nand_operation *op) 2491 { 2492 if (op->ninstrs == 2 && 2493 op->instrs[0].type == NAND_OP_CMD_INSTR && 2494 op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS && 2495 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) 2496 return 1; 2497 2498 return 0; 2499 } 2500 2501 static int brcmnand_op_is_reset(const struct nand_operation *op) 2502 { 2503 if (op->ninstrs == 2 && 2504 op->instrs[0].type == NAND_OP_CMD_INSTR && 2505 op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET && 2506 op->instrs[1].type == NAND_OP_WAITRDY_INSTR) 2507 return 1; 2508 2509 return 0; 2510 } 2511 2512 static int brcmnand_check_instructions(struct nand_chip *chip, 2513 const struct nand_operation *op) 2514 { 2515 return 0; 2516 } 2517 2518 static int brcmnand_exec_instructions(struct nand_chip *chip, 2519 const struct nand_operation *op) 2520 { 2521 struct brcmnand_host *host = nand_get_controller_data(chip); 2522 unsigned int i; 2523 int ret = 0; 2524 2525 for (i = 0; i < op->ninstrs; i++) { 2526 ret = brcmnand_exec_instr(host, i, op); 2527 if (ret) 2528 break; 2529 } 2530 2531 return ret; 2532 } 2533 2534 static int brcmnand_check_instructions_legacy(struct nand_chip *chip, 2535 const struct nand_operation *op) 2536 { 2537 const struct nand_op_instr *instr; 2538 unsigned int i; 2539 u8 cmd; 2540 2541 for (i = 0; i < op->ninstrs; i++) { 2542 instr = &op->instrs[i]; 2543 2544 switch (instr->type) { 2545 case NAND_OP_CMD_INSTR: 2546 cmd = native_cmd_conv[instr->ctx.cmd.opcode]; 2547 if (cmd == CMD_NOT_SUPPORTED) 2548 return -EOPNOTSUPP; 2549 break; 2550 case NAND_OP_ADDR_INSTR: 2551 case NAND_OP_DATA_IN_INSTR: 2552 case NAND_OP_WAITRDY_INSTR: 2553 break; 2554 default: 2555 return -EOPNOTSUPP; 2556 } 2557 } 2558 2559 return 0; 2560 } 2561 2562 static int brcmnand_exec_instructions_legacy(struct nand_chip *chip, 2563 const struct nand_operation *op) 2564 { 2565 struct mtd_info *mtd = nand_to_mtd(chip); 2566 struct brcmnand_host *host = nand_get_controller_data(chip); 2567 struct brcmnand_controller *ctrl = host->ctrl; 2568 const struct nand_op_instr *instr; 2569 unsigned int i, j; 2570 u8 cmd = CMD_NULL, last_cmd = CMD_NULL; 2571 int ret = 0; 2572 u64 last_addr; 2573 2574 for (i = 0; i < op->ninstrs; i++) { 2575 instr = &op->instrs[i]; 2576 2577 if (instr->type == NAND_OP_CMD_INSTR) { 2578 cmd = native_cmd_conv[instr->ctx.cmd.opcode]; 2579 if (cmd == CMD_NOT_SUPPORTED) { 2580 dev_err(ctrl->dev, "unsupported cmd=%d\n", 2581 instr->ctx.cmd.opcode); 2582 ret = -EOPNOTSUPP; 2583 break; 2584 } 2585 } else if (instr->type == NAND_OP_ADDR_INSTR) { 2586 u64 addr = 0; 2587 2588 if (cmd == CMD_NULL) 2589 continue; 2590 2591 if (instr->ctx.addr.naddrs > 8) { 2592 dev_err(ctrl->dev, "unsupported naddrs=%u\n", 2593 instr->ctx.addr.naddrs); 2594 ret = -EOPNOTSUPP; 2595 break; 2596 } 2597 2598 for (j = 0; j < instr->ctx.addr.naddrs; j++) 2599 addr |= (instr->ctx.addr.addrs[j]) << (j << 3); 2600 2601 if (cmd == CMD_BLOCK_ERASE) 2602 addr <<= chip->page_shift; 2603 else if (cmd == CMD_PARAMETER_CHANGE_COL) 2604 addr &= ~((u64)(FC_BYTES - 1)); 2605 2606 brcmnand_set_cmd_addr(mtd, addr); 2607 brcmnand_send_cmd(host, cmd); 2608 last_addr = addr; 2609 last_cmd = cmd; 2610 cmd = CMD_NULL; 2611 brcmnand_waitfunc(chip); 2612 2613 if (last_cmd == CMD_PARAMETER_READ || 2614 last_cmd == CMD_PARAMETER_CHANGE_COL) { 2615 /* Copy flash cache word-wise */ 2616 u32 *flash_cache = (u32 *)ctrl->flash_cache; 2617 2618 brcmnand_soc_data_bus_prepare(ctrl->soc, true); 2619 2620 /* 2621 * Must cache the FLASH_CACHE now, since changes in 2622 * SECTOR_SIZE_1K may invalidate it 2623 */ 2624 for (j = 0; j < FC_WORDS; j++) 2625 /* 2626 * Flash cache is big endian for parameter pages, at 2627 * least on STB SoCs 2628 */ 2629 flash_cache[j] = be32_to_cpu(brcmnand_read_fc(ctrl, j)); 2630 2631 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); 2632 } 2633 } else if (instr->type == NAND_OP_DATA_IN_INSTR) { 2634 u8 *in = instr->ctx.data.buf.in; 2635 2636 if (last_cmd == CMD_DEVICE_ID_READ) { 2637 u32 val; 2638 2639 if (instr->ctx.data.len > 8) { 2640 dev_err(ctrl->dev, "unsupported len=%u\n", 2641 instr->ctx.data.len); 2642 ret = -EOPNOTSUPP; 2643 break; 2644 } 2645 2646 for (j = 0; j < instr->ctx.data.len; j++) { 2647 if (j == 0) 2648 val = brcmnand_read_reg(ctrl, BRCMNAND_ID); 2649 else if (j == 4) 2650 val = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT); 2651 2652 in[j] = (val >> (24 - ((j % 4) << 3))) & 0xff; 2653 } 2654 } else if (last_cmd == CMD_PARAMETER_READ || 2655 last_cmd == CMD_PARAMETER_CHANGE_COL) { 2656 u64 addr; 2657 u32 offs; 2658 2659 for (j = 0; j < instr->ctx.data.len; j++) { 2660 addr = last_addr + j; 2661 offs = addr & (FC_BYTES - 1); 2662 2663 if (j > 0 && offs == 0) 2664 nand_change_read_column_op(chip, addr, NULL, 0, 2665 false); 2666 2667 in[j] = ctrl->flash_cache[offs]; 2668 } 2669 } 2670 } else if (instr->type == NAND_OP_WAITRDY_INSTR) { 2671 ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 2672 if (ret) 2673 break; 2674 } else { 2675 dev_err(ctrl->dev, "unsupported instruction type: %d\n", instr->type); 2676 ret = -EOPNOTSUPP; 2677 break; 2678 } 2679 } 2680 2681 return ret; 2682 } 2683 2684 static int brcmnand_exec_op(struct nand_chip *chip, 2685 const struct nand_operation *op, 2686 bool check_only) 2687 { 2688 struct brcmnand_host *host = nand_get_controller_data(chip); 2689 struct brcmnand_controller *ctrl = host->ctrl; 2690 struct mtd_info *mtd = nand_to_mtd(chip); 2691 u8 *status; 2692 int ret = 0; 2693 2694 if (check_only) 2695 return ctrl->check_instr(chip, op); 2696 2697 if (brcmnand_op_is_status(op)) { 2698 status = op->instrs[1].ctx.data.buf.in; 2699 ret = brcmnand_status(host); 2700 if (ret < 0) 2701 return ret; 2702 2703 *status = ret & 0xFF; 2704 2705 return 0; 2706 } else if (brcmnand_op_is_reset(op)) { 2707 ret = brcmnand_reset(host); 2708 if (ret < 0) 2709 return ret; 2710 2711 brcmnand_wp(mtd, 1); 2712 2713 return 0; 2714 } 2715 2716 if (op->deassert_wp) 2717 brcmnand_wp(mtd, 0); 2718 2719 ret = ctrl->exec_instr(chip, op); 2720 2721 if (op->deassert_wp) 2722 brcmnand_wp(mtd, 1); 2723 2724 return ret; 2725 } 2726 2727 /*********************************************************************** 2728 * Per-CS setup (1 NAND device) 2729 ***********************************************************************/ 2730 2731 static int brcmnand_set_cfg(struct brcmnand_host *host, 2732 struct brcmnand_cfg *cfg) 2733 { 2734 struct brcmnand_controller *ctrl = host->ctrl; 2735 struct nand_chip *chip = &host->chip; 2736 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2737 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2738 BRCMNAND_CS_CFG_EXT); 2739 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2740 BRCMNAND_CS_ACC_CONTROL); 2741 u8 block_size = 0, page_size = 0, device_size = 0; 2742 u32 tmp; 2743 2744 if (ctrl->block_sizes) { 2745 int i, found; 2746 2747 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) 2748 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { 2749 block_size = i; 2750 found = 1; 2751 } 2752 if (!found) { 2753 dev_warn(ctrl->dev, "invalid block size %u\n", 2754 cfg->block_size); 2755 return -EINVAL; 2756 } 2757 } else { 2758 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); 2759 } 2760 2761 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && 2762 cfg->block_size > ctrl->max_block_size)) { 2763 dev_warn(ctrl->dev, "invalid block size %u\n", 2764 cfg->block_size); 2765 block_size = 0; 2766 } 2767 2768 if (ctrl->page_sizes) { 2769 int i, found; 2770 2771 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) 2772 if (ctrl->page_sizes[i] == cfg->page_size) { 2773 page_size = i; 2774 found = 1; 2775 } 2776 if (!found) { 2777 dev_warn(ctrl->dev, "invalid page size %u\n", 2778 cfg->page_size); 2779 return -EINVAL; 2780 } 2781 } else { 2782 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); 2783 } 2784 2785 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && 2786 cfg->page_size > ctrl->max_page_size)) { 2787 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); 2788 return -EINVAL; 2789 } 2790 2791 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { 2792 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", 2793 (unsigned long long)cfg->device_size); 2794 return -EINVAL; 2795 } 2796 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); 2797 2798 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | 2799 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | 2800 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | 2801 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | 2802 (device_size << CFG_DEVICE_SIZE_SHIFT); 2803 if (cfg_offs == cfg_ext_offs) { 2804 tmp |= (page_size << ctrl->page_size_shift) | 2805 (block_size << CFG_BLK_SIZE_SHIFT); 2806 nand_writereg(ctrl, cfg_offs, tmp); 2807 } else { 2808 nand_writereg(ctrl, cfg_offs, tmp); 2809 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | 2810 (block_size << CFG_EXT_BLK_SIZE_SHIFT); 2811 nand_writereg(ctrl, cfg_ext_offs, tmp); 2812 } 2813 2814 tmp = nand_readreg(ctrl, acc_control_offs); 2815 tmp &= ~brcmnand_ecc_level_mask(ctrl); 2816 tmp &= ~brcmnand_spare_area_mask(ctrl); 2817 if (ctrl->nand_version >= 0x0302) { 2818 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; 2819 tmp |= cfg->spare_area_size; 2820 } 2821 nand_writereg(ctrl, acc_control_offs, tmp); 2822 2823 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); 2824 2825 /* threshold = ceil(BCH-level * 0.75) */ 2826 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); 2827 2828 return 0; 2829 } 2830 2831 static void brcmnand_print_cfg(struct brcmnand_host *host, 2832 char *buf, struct brcmnand_cfg *cfg) 2833 { 2834 buf += sprintf(buf, 2835 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", 2836 (unsigned long long)cfg->device_size >> 20, 2837 cfg->block_size >> 10, 2838 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, 2839 cfg->page_size >= 1024 ? "KiB" : "B", 2840 cfg->spare_area_size, cfg->device_width); 2841 2842 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ 2843 if (is_hamming_ecc(host->ctrl, cfg)) 2844 sprintf(buf, ", Hamming ECC"); 2845 else if (cfg->sector_size_1k) 2846 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); 2847 else 2848 sprintf(buf, ", BCH-%u", cfg->ecc_level); 2849 } 2850 2851 /* 2852 * Minimum number of bytes to address a page. Calculated as: 2853 * roundup(log2(size / page-size) / 8) 2854 * 2855 * NB: the following does not "round up" for non-power-of-2 'size'; but this is 2856 * OK because many other things will break if 'size' is irregular... 2857 */ 2858 static inline int get_blk_adr_bytes(u64 size, u32 writesize) 2859 { 2860 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; 2861 } 2862 2863 static int brcmnand_setup_dev(struct brcmnand_host *host) 2864 { 2865 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2866 struct nand_chip *chip = &host->chip; 2867 const struct nand_ecc_props *requirements = 2868 nanddev_get_ecc_requirements(&chip->base); 2869 struct nand_memory_organization *memorg = 2870 nanddev_get_memorg(&chip->base); 2871 struct brcmnand_controller *ctrl = host->ctrl; 2872 struct brcmnand_cfg *cfg = &host->hwcfg; 2873 struct device_node *np = nand_get_flash_node(chip); 2874 u32 offs, tmp, oob_sector; 2875 bool use_strap = false; 2876 char msg[128]; 2877 int ret; 2878 2879 memset(cfg, 0, sizeof(*cfg)); 2880 use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap"); 2881 2882 /* 2883 * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out 2884 * if both exist. 2885 */ 2886 if (chip->ecc.strength && use_strap) { 2887 dev_err(ctrl->dev, 2888 "ECC strap and DT ECC configuration properties are mutually exclusive\n"); 2889 return -EINVAL; 2890 } 2891 2892 if (use_strap) 2893 brcmnand_get_ecc_settings(host, chip); 2894 2895 ret = of_property_read_u32(np, "brcm,nand-oob-sector-size", 2896 &oob_sector); 2897 if (ret) { 2898 if (use_strap) 2899 cfg->spare_area_size = brcmnand_get_spare_size(host); 2900 else 2901 /* Use detected size */ 2902 cfg->spare_area_size = mtd->oobsize / 2903 (mtd->writesize >> FC_SHIFT); 2904 } else { 2905 cfg->spare_area_size = oob_sector; 2906 } 2907 if (cfg->spare_area_size > ctrl->max_oob) 2908 cfg->spare_area_size = ctrl->max_oob; 2909 /* 2910 * Set mtd and memorg oobsize to be consistent with controller's 2911 * spare_area_size, as the rest is inaccessible. 2912 */ 2913 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); 2914 memorg->oobsize = mtd->oobsize; 2915 2916 cfg->device_size = mtd->size; 2917 cfg->block_size = mtd->erasesize; 2918 cfg->page_size = mtd->writesize; 2919 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; 2920 cfg->col_adr_bytes = 2; 2921 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 2922 2923 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 2924 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 2925 chip->ecc.engine_type); 2926 return -EINVAL; 2927 } 2928 2929 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { 2930 if (chip->ecc.strength == 1 && chip->ecc.size == 512) 2931 /* Default to Hamming for 1-bit ECC, if unspecified */ 2932 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2933 else 2934 /* Otherwise, BCH */ 2935 chip->ecc.algo = NAND_ECC_ALGO_BCH; 2936 } 2937 2938 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && 2939 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { 2940 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 2941 chip->ecc.strength, chip->ecc.size); 2942 return -EINVAL; 2943 } 2944 2945 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2946 (!chip->ecc.size || !chip->ecc.strength)) { 2947 if (requirements->step_size && requirements->strength) { 2948 /* use detected ECC parameters */ 2949 chip->ecc.size = requirements->step_size; 2950 chip->ecc.strength = requirements->strength; 2951 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", 2952 chip->ecc.size, chip->ecc.strength); 2953 } 2954 } 2955 2956 switch (chip->ecc.size) { 2957 case 512: 2958 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 2959 cfg->ecc_level = 15; 2960 else 2961 cfg->ecc_level = chip->ecc.strength; 2962 cfg->sector_size_1k = 0; 2963 break; 2964 case 1024: 2965 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { 2966 dev_err(ctrl->dev, "1KB sectors not supported\n"); 2967 return -EINVAL; 2968 } 2969 if (chip->ecc.strength & 0x1) { 2970 dev_err(ctrl->dev, 2971 "odd ECC not supported with 1KB sectors\n"); 2972 return -EINVAL; 2973 } 2974 2975 cfg->ecc_level = chip->ecc.strength >> 1; 2976 cfg->sector_size_1k = 1; 2977 break; 2978 default: 2979 dev_err(ctrl->dev, "unsupported ECC size: %d\n", 2980 chip->ecc.size); 2981 return -EINVAL; 2982 } 2983 2984 cfg->ful_adr_bytes = cfg->blk_adr_bytes; 2985 if (mtd->writesize > 512) 2986 cfg->ful_adr_bytes += cfg->col_adr_bytes; 2987 else 2988 cfg->ful_adr_bytes += 1; 2989 2990 ret = brcmnand_set_cfg(host, cfg); 2991 if (ret) 2992 return ret; 2993 2994 brcmnand_set_ecc_enabled(host, 1); 2995 2996 brcmnand_print_cfg(host, msg, cfg); 2997 dev_info(ctrl->dev, "detected %s\n", msg); 2998 2999 /* Configure ACC_CONTROL */ 3000 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 3001 tmp = nand_readreg(ctrl, offs); 3002 tmp &= ~ACC_CONTROL_PARTIAL_PAGE; 3003 tmp &= ~ACC_CONTROL_RD_ERASED; 3004 3005 /* We need to turn on Read from erased paged protected by ECC */ 3006 if (ctrl->nand_version >= 0x0702) 3007 tmp |= ACC_CONTROL_RD_ERASED; 3008 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; 3009 if (ctrl->features & BRCMNAND_HAS_PREFETCH) 3010 tmp &= ~ACC_CONTROL_PREFETCH; 3011 3012 nand_writereg(ctrl, offs, tmp); 3013 3014 return 0; 3015 } 3016 3017 static int brcmnand_attach_chip(struct nand_chip *chip) 3018 { 3019 struct mtd_info *mtd = nand_to_mtd(chip); 3020 struct brcmnand_host *host = nand_get_controller_data(chip); 3021 int ret; 3022 3023 chip->options |= NAND_NO_SUBPAGE_WRITE; 3024 /* 3025 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA 3026 * to/from, and have nand_base pass us a bounce buffer instead, as 3027 * needed. 3028 */ 3029 chip->options |= NAND_USES_DMA; 3030 3031 if (chip->bbt_options & NAND_BBT_USE_FLASH) 3032 chip->bbt_options |= NAND_BBT_NO_OOB; 3033 3034 if (brcmnand_setup_dev(host)) 3035 return -ENXIO; 3036 3037 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; 3038 3039 /* only use our internal HW threshold */ 3040 mtd->bitflip_threshold = 1; 3041 3042 ret = brcmstb_choose_ecc_layout(host); 3043 3044 /* If OOB is written with ECC enabled it will cause ECC errors */ 3045 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { 3046 chip->ecc.write_oob = brcmnand_write_oob_raw; 3047 chip->ecc.read_oob = brcmnand_read_oob_raw; 3048 } 3049 3050 return ret; 3051 } 3052 3053 static const struct nand_controller_ops brcmnand_controller_ops = { 3054 .attach_chip = brcmnand_attach_chip, 3055 .exec_op = brcmnand_exec_op, 3056 }; 3057 3058 static int brcmnand_init_cs(struct brcmnand_host *host, 3059 const char * const *part_probe_types) 3060 { 3061 struct brcmnand_controller *ctrl = host->ctrl; 3062 struct device *dev = ctrl->dev; 3063 struct mtd_info *mtd; 3064 struct nand_chip *chip; 3065 int ret; 3066 u16 cfg_offs; 3067 3068 mtd = nand_to_mtd(&host->chip); 3069 chip = &host->chip; 3070 3071 nand_set_controller_data(chip, host); 3072 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", 3073 host->cs); 3074 if (!mtd->name) 3075 return -ENOMEM; 3076 3077 mtd->owner = THIS_MODULE; 3078 mtd->dev.parent = dev; 3079 3080 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 3081 chip->ecc.read_page = brcmnand_read_page; 3082 chip->ecc.write_page = brcmnand_write_page; 3083 chip->ecc.read_page_raw = brcmnand_read_page_raw; 3084 chip->ecc.write_page_raw = brcmnand_write_page_raw; 3085 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; 3086 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; 3087 chip->ecc.read_oob = brcmnand_read_oob; 3088 chip->ecc.write_oob = brcmnand_write_oob; 3089 3090 chip->controller = &ctrl->controller; 3091 ctrl->controller.controller_wp = 1; 3092 3093 /* 3094 * The bootloader might have configured 16bit mode but 3095 * NAND READID command only works in 8bit mode. We force 3096 * 8bit mode here to ensure that NAND READID commands works. 3097 */ 3098 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 3099 nand_writereg(ctrl, cfg_offs, 3100 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); 3101 3102 ret = nand_scan(chip, 1); 3103 if (ret) 3104 return ret; 3105 3106 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); 3107 if (ret) 3108 nand_cleanup(chip); 3109 3110 return ret; 3111 } 3112 3113 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, 3114 int restore) 3115 { 3116 struct brcmnand_controller *ctrl = host->ctrl; 3117 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 3118 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 3119 BRCMNAND_CS_CFG_EXT); 3120 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 3121 BRCMNAND_CS_ACC_CONTROL); 3122 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); 3123 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); 3124 3125 if (restore) { 3126 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); 3127 if (cfg_offs != cfg_ext_offs) 3128 nand_writereg(ctrl, cfg_ext_offs, 3129 host->hwcfg.config_ext); 3130 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); 3131 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); 3132 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); 3133 } else { 3134 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); 3135 if (cfg_offs != cfg_ext_offs) 3136 host->hwcfg.config_ext = 3137 nand_readreg(ctrl, cfg_ext_offs); 3138 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); 3139 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); 3140 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); 3141 } 3142 } 3143 3144 static int brcmnand_suspend(struct device *dev) 3145 { 3146 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 3147 struct brcmnand_host *host; 3148 3149 list_for_each_entry(host, &ctrl->host_list, node) 3150 brcmnand_save_restore_cs_config(host, 0); 3151 3152 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); 3153 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); 3154 ctrl->corr_stat_threshold = 3155 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); 3156 3157 if (has_flash_dma(ctrl)) 3158 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 3159 else if (has_edu(ctrl)) 3160 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 3161 3162 return 0; 3163 } 3164 3165 static int brcmnand_resume(struct device *dev) 3166 { 3167 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 3168 struct brcmnand_host *host; 3169 3170 if (has_flash_dma(ctrl)) { 3171 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 3172 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 3173 } 3174 3175 if (has_edu(ctrl)) { 3176 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 3177 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); 3178 edu_readl(ctrl, EDU_CONFIG); 3179 brcmnand_edu_init(ctrl); 3180 } 3181 3182 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); 3183 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); 3184 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, 3185 ctrl->corr_stat_threshold); 3186 if (ctrl->soc) { 3187 /* Clear/re-enable interrupt */ 3188 ctrl->soc->ctlrdy_ack(ctrl->soc); 3189 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 3190 } 3191 3192 list_for_each_entry(host, &ctrl->host_list, node) { 3193 struct nand_chip *chip = &host->chip; 3194 3195 brcmnand_save_restore_cs_config(host, 1); 3196 3197 /* Reset the chip, required by some chips after power-up */ 3198 nand_reset(chip, 0); 3199 } 3200 3201 return 0; 3202 } 3203 3204 const struct dev_pm_ops brcmnand_pm_ops = { 3205 .suspend = brcmnand_suspend, 3206 .resume = brcmnand_resume, 3207 }; 3208 EXPORT_SYMBOL_GPL(brcmnand_pm_ops); 3209 3210 static const struct of_device_id __maybe_unused brcmnand_of_match[] = { 3211 { .compatible = "brcm,brcmnand-v2.1" }, 3212 { .compatible = "brcm,brcmnand-v2.2" }, 3213 { .compatible = "brcm,brcmnand-v4.0" }, 3214 { .compatible = "brcm,brcmnand-v5.0" }, 3215 { .compatible = "brcm,brcmnand-v6.0" }, 3216 { .compatible = "brcm,brcmnand-v6.1" }, 3217 { .compatible = "brcm,brcmnand-v6.2" }, 3218 { .compatible = "brcm,brcmnand-v7.0" }, 3219 { .compatible = "brcm,brcmnand-v7.1" }, 3220 { .compatible = "brcm,brcmnand-v7.2" }, 3221 { .compatible = "brcm,brcmnand-v7.3" }, 3222 {}, 3223 }; 3224 MODULE_DEVICE_TABLE(of, brcmnand_of_match); 3225 3226 /*********************************************************************** 3227 * Platform driver setup (per controller) 3228 ***********************************************************************/ 3229 static int brcmnand_edu_setup(struct platform_device *pdev) 3230 { 3231 struct device *dev = &pdev->dev; 3232 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 3233 struct resource *res; 3234 int ret; 3235 3236 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); 3237 if (res) { 3238 ctrl->edu_base = devm_ioremap_resource(dev, res); 3239 if (IS_ERR(ctrl->edu_base)) 3240 return PTR_ERR(ctrl->edu_base); 3241 3242 ctrl->edu_offsets = edu_regs; 3243 3244 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | 3245 EDU_CONFIG_SWAP_CFG); 3246 edu_readl(ctrl, EDU_CONFIG); 3247 3248 /* initialize edu */ 3249 brcmnand_edu_init(ctrl); 3250 3251 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); 3252 if (ctrl->edu_irq < 0) { 3253 dev_warn(dev, 3254 "FLASH EDU enabled, using ctlrdy irq\n"); 3255 } else { 3256 ret = devm_request_irq(dev, ctrl->edu_irq, 3257 brcmnand_edu_irq, 0, 3258 "brcmnand-edu", ctrl); 3259 if (ret < 0) { 3260 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", 3261 ctrl->edu_irq, ret); 3262 return ret; 3263 } 3264 3265 dev_info(dev, "FLASH EDU enabled using irq %u\n", 3266 ctrl->edu_irq); 3267 } 3268 } 3269 3270 return 0; 3271 } 3272 3273 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 3274 { 3275 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); 3276 struct device *dev = &pdev->dev; 3277 struct device_node *dn = dev->of_node, *child; 3278 struct brcmnand_controller *ctrl; 3279 struct brcmnand_host *host; 3280 struct resource *res; 3281 int ret; 3282 3283 if (dn && !of_match_node(brcmnand_of_match, dn)) 3284 return -ENODEV; 3285 3286 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 3287 if (!ctrl) 3288 return -ENOMEM; 3289 3290 dev_set_drvdata(dev, ctrl); 3291 ctrl->dev = dev; 3292 ctrl->soc = soc; 3293 3294 /* Enable the static key if the soc provides I/O operations indicating 3295 * that a non-memory mapped IO access path must be used 3296 */ 3297 if (brcmnand_soc_has_ops(ctrl->soc)) 3298 static_branch_enable(&brcmnand_soc_has_ops_key); 3299 3300 init_completion(&ctrl->done); 3301 init_completion(&ctrl->dma_done); 3302 init_completion(&ctrl->edu_done); 3303 nand_controller_init(&ctrl->controller); 3304 ctrl->controller.ops = &brcmnand_controller_ops; 3305 INIT_LIST_HEAD(&ctrl->host_list); 3306 3307 /* NAND register range */ 3308 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3309 ctrl->nand_base = devm_ioremap_resource(dev, res); 3310 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) 3311 return PTR_ERR(ctrl->nand_base); 3312 3313 /* Enable clock before using NAND registers */ 3314 ctrl->clk = devm_clk_get(dev, "nand"); 3315 if (!IS_ERR(ctrl->clk)) { 3316 ret = clk_prepare_enable(ctrl->clk); 3317 if (ret) 3318 return ret; 3319 } else { 3320 ret = PTR_ERR(ctrl->clk); 3321 if (ret == -EPROBE_DEFER) 3322 return ret; 3323 3324 ctrl->clk = NULL; 3325 } 3326 3327 /* Initialize NAND revision */ 3328 ret = brcmnand_revision_init(ctrl); 3329 if (ret) 3330 goto err; 3331 3332 /* Only v5.0+ controllers have low level ops support */ 3333 if (ctrl->nand_version >= 0x0500) { 3334 ctrl->check_instr = brcmnand_check_instructions; 3335 ctrl->exec_instr = brcmnand_exec_instructions; 3336 } else { 3337 ctrl->check_instr = brcmnand_check_instructions_legacy; 3338 ctrl->exec_instr = brcmnand_exec_instructions_legacy; 3339 } 3340 3341 /* 3342 * Most chips have this cache at a fixed offset within 'nand' block. 3343 * Some must specify this region separately. 3344 */ 3345 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); 3346 if (res) { 3347 ctrl->nand_fc = devm_ioremap_resource(dev, res); 3348 if (IS_ERR(ctrl->nand_fc)) { 3349 ret = PTR_ERR(ctrl->nand_fc); 3350 goto err; 3351 } 3352 } else { 3353 ctrl->nand_fc = ctrl->nand_base + 3354 ctrl->reg_offsets[BRCMNAND_FC_BASE]; 3355 } 3356 3357 /* FLASH_DMA */ 3358 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); 3359 if (res) { 3360 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); 3361 if (IS_ERR(ctrl->flash_dma_base)) { 3362 ret = PTR_ERR(ctrl->flash_dma_base); 3363 goto err; 3364 } 3365 3366 /* initialize the dma version */ 3367 brcmnand_flash_dma_revision_init(ctrl); 3368 3369 ret = -EIO; 3370 if (ctrl->nand_version >= 0x0700) 3371 ret = dma_set_mask_and_coherent(&pdev->dev, 3372 DMA_BIT_MASK(40)); 3373 if (ret) 3374 ret = dma_set_mask_and_coherent(&pdev->dev, 3375 DMA_BIT_MASK(32)); 3376 if (ret) 3377 goto err; 3378 3379 /* linked-list and stop on error */ 3380 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); 3381 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 3382 3383 /* Allocate descriptor(s) */ 3384 ctrl->dma_desc = dmam_alloc_coherent(dev, 3385 sizeof(*ctrl->dma_desc), 3386 &ctrl->dma_pa, GFP_KERNEL); 3387 if (!ctrl->dma_desc) { 3388 ret = -ENOMEM; 3389 goto err; 3390 } 3391 3392 ctrl->dma_irq = platform_get_irq(pdev, 1); 3393 if ((int)ctrl->dma_irq < 0) { 3394 dev_err(dev, "missing FLASH_DMA IRQ\n"); 3395 ret = -ENODEV; 3396 goto err; 3397 } 3398 3399 ret = devm_request_irq(dev, ctrl->dma_irq, 3400 brcmnand_dma_irq, 0, DRV_NAME, 3401 ctrl); 3402 if (ret < 0) { 3403 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3404 ctrl->dma_irq, ret); 3405 goto err; 3406 } 3407 3408 dev_info(dev, "enabling FLASH_DMA\n"); 3409 /* set flash dma transfer function to call */ 3410 ctrl->dma_trans = brcmnand_dma_trans; 3411 } else { 3412 ret = brcmnand_edu_setup(pdev); 3413 if (ret < 0) 3414 goto err; 3415 3416 if (has_edu(ctrl)) 3417 /* set edu transfer function to call */ 3418 ctrl->dma_trans = brcmnand_edu_trans; 3419 } 3420 3421 /* Disable automatic device ID config, direct addressing */ 3422 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, 3423 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); 3424 /* Disable XOR addressing */ 3425 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); 3426 3427 /* Check if the board connects the WP pin */ 3428 if (of_property_read_bool(dn, "brcm,wp-not-connected")) 3429 wp_on = 0; 3430 3431 if (ctrl->features & BRCMNAND_HAS_WP) { 3432 /* Permanently disable write protection */ 3433 if (wp_on == 2) 3434 brcmnand_set_wp(ctrl, false); 3435 } else { 3436 wp_on = 0; 3437 } 3438 3439 /* IRQ */ 3440 ctrl->irq = platform_get_irq_optional(pdev, 0); 3441 if (ctrl->irq > 0) { 3442 /* 3443 * Some SoCs integrate this controller (e.g., its interrupt bits) in 3444 * interesting ways 3445 */ 3446 if (soc) { 3447 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, 3448 DRV_NAME, ctrl); 3449 3450 /* Enable interrupt */ 3451 ctrl->soc->ctlrdy_ack(ctrl->soc); 3452 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 3453 } else { 3454 /* Use standard interrupt infrastructure */ 3455 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, 3456 DRV_NAME, ctrl); 3457 } 3458 if (ret < 0) { 3459 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3460 ctrl->irq, ret); 3461 goto err; 3462 } 3463 } 3464 3465 for_each_available_child_of_node(dn, child) { 3466 if (of_device_is_compatible(child, "brcm,nandcs")) { 3467 3468 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 3469 if (!host) { 3470 of_node_put(child); 3471 ret = -ENOMEM; 3472 goto err; 3473 } 3474 host->pdev = pdev; 3475 host->ctrl = ctrl; 3476 3477 ret = of_property_read_u32(child, "reg", &host->cs); 3478 if (ret) { 3479 dev_err(dev, "can't get chip-select\n"); 3480 devm_kfree(dev, host); 3481 continue; 3482 } 3483 3484 nand_set_flash_node(&host->chip, child); 3485 3486 ret = brcmnand_init_cs(host, NULL); 3487 if (ret) { 3488 if (ret == -EPROBE_DEFER) { 3489 of_node_put(child); 3490 goto err; 3491 } 3492 devm_kfree(dev, host); 3493 continue; /* Try all chip-selects */ 3494 } 3495 3496 list_add_tail(&host->node, &ctrl->host_list); 3497 } 3498 } 3499 3500 if (!list_empty(&ctrl->host_list)) 3501 return 0; 3502 3503 if (!pd) { 3504 ret = -ENODEV; 3505 goto err; 3506 } 3507 3508 /* If we got there we must have been probing via platform data */ 3509 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 3510 if (!host) { 3511 ret = -ENOMEM; 3512 goto err; 3513 } 3514 host->pdev = pdev; 3515 host->ctrl = ctrl; 3516 host->cs = pd->chip_select; 3517 host->chip.ecc.size = pd->ecc_stepsize; 3518 host->chip.ecc.strength = pd->ecc_strength; 3519 3520 ret = brcmnand_init_cs(host, pd->part_probe_types); 3521 if (ret) 3522 goto err; 3523 3524 list_add_tail(&host->node, &ctrl->host_list); 3525 3526 /* No chip-selects could initialize properly */ 3527 if (list_empty(&ctrl->host_list)) { 3528 ret = -ENODEV; 3529 goto err; 3530 } 3531 3532 return 0; 3533 3534 err: 3535 clk_disable_unprepare(ctrl->clk); 3536 return ret; 3537 3538 } 3539 EXPORT_SYMBOL_GPL(brcmnand_probe); 3540 3541 void brcmnand_remove(struct platform_device *pdev) 3542 { 3543 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 3544 struct brcmnand_host *host; 3545 struct nand_chip *chip; 3546 int ret; 3547 3548 list_for_each_entry(host, &ctrl->host_list, node) { 3549 chip = &host->chip; 3550 ret = mtd_device_unregister(nand_to_mtd(chip)); 3551 WARN_ON(ret); 3552 nand_cleanup(chip); 3553 } 3554 3555 clk_disable_unprepare(ctrl->clk); 3556 3557 dev_set_drvdata(&pdev->dev, NULL); 3558 } 3559 EXPORT_SYMBOL_GPL(brcmnand_remove); 3560 3561 MODULE_LICENSE("GPL v2"); 3562 MODULE_AUTHOR("Kevin Cernekee"); 3563 MODULE_AUTHOR("Brian Norris"); 3564 MODULE_DESCRIPTION("NAND driver for Broadcom chips"); 3565 MODULE_ALIAS("platform:brcmnand"); 3566