1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2010-2015 Broadcom Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/init.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/platform_device.h> 12 #include <linux/platform_data/brcmnand.h> 13 #include <linux/err.h> 14 #include <linux/completion.h> 15 #include <linux/interrupt.h> 16 #include <linux/spinlock.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/ioport.h> 19 #include <linux/bug.h> 20 #include <linux/kernel.h> 21 #include <linux/bitops.h> 22 #include <linux/mm.h> 23 #include <linux/mtd/mtd.h> 24 #include <linux/mtd/rawnand.h> 25 #include <linux/mtd/partitions.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/slab.h> 29 #include <linux/static_key.h> 30 #include <linux/list.h> 31 #include <linux/log2.h> 32 33 #include "brcmnand.h" 34 35 /* 36 * This flag controls if WP stays on between erase/write commands to mitigate 37 * flash corruption due to power glitches. Values: 38 * 0: NAND_WP is not used or not available 39 * 1: NAND_WP is set by default, cleared for erase/write operations 40 * 2: NAND_WP is always cleared 41 */ 42 static int wp_on = 1; 43 module_param(wp_on, int, 0444); 44 45 /*********************************************************************** 46 * Definitions 47 ***********************************************************************/ 48 49 #define DRV_NAME "brcmnand" 50 51 #define CMD_NULL 0x00 52 #define CMD_PAGE_READ 0x01 53 #define CMD_SPARE_AREA_READ 0x02 54 #define CMD_STATUS_READ 0x03 55 #define CMD_PROGRAM_PAGE 0x04 56 #define CMD_PROGRAM_SPARE_AREA 0x05 57 #define CMD_COPY_BACK 0x06 58 #define CMD_DEVICE_ID_READ 0x07 59 #define CMD_BLOCK_ERASE 0x08 60 #define CMD_FLASH_RESET 0x09 61 #define CMD_BLOCKS_LOCK 0x0a 62 #define CMD_BLOCKS_LOCK_DOWN 0x0b 63 #define CMD_BLOCKS_UNLOCK 0x0c 64 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d 65 #define CMD_PARAMETER_READ 0x0e 66 #define CMD_PARAMETER_CHANGE_COL 0x0f 67 #define CMD_LOW_LEVEL_OP 0x10 68 69 struct brcm_nand_dma_desc { 70 u32 next_desc; 71 u32 next_desc_ext; 72 u32 cmd_irq; 73 u32 dram_addr; 74 u32 dram_addr_ext; 75 u32 tfr_len; 76 u32 total_len; 77 u32 flash_addr; 78 u32 flash_addr_ext; 79 u32 cs; 80 u32 pad2[5]; 81 u32 status_valid; 82 } __packed; 83 84 /* Bitfields for brcm_nand_dma_desc::status_valid */ 85 #define FLASH_DMA_ECC_ERROR (1 << 8) 86 #define FLASH_DMA_CORR_ERROR (1 << 9) 87 88 /* Bitfields for DMA_MODE */ 89 #define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ 90 #define FLASH_DMA_MODE_MODE BIT(0) /* link list */ 91 #define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \ 92 FLASH_DMA_MODE_MODE) 93 94 /* 512B flash cache in the NAND controller HW */ 95 #define FC_SHIFT 9U 96 #define FC_BYTES 512U 97 #define FC_WORDS (FC_BYTES >> 2) 98 99 #define BRCMNAND_MIN_PAGESIZE 512 100 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) 101 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) 102 103 #define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 104 #define NAND_POLL_STATUS_TIMEOUT_MS 100 105 106 #define EDU_CMD_WRITE 0x00 107 #define EDU_CMD_READ 0x01 108 #define EDU_STATUS_ACTIVE BIT(0) 109 #define EDU_ERR_STATUS_ERRACK BIT(0) 110 #define EDU_DONE_MASK GENMASK(1, 0) 111 112 #define EDU_CONFIG_MODE_NAND BIT(0) 113 #define EDU_CONFIG_SWAP_BYTE BIT(1) 114 #ifdef CONFIG_CPU_BIG_ENDIAN 115 #define EDU_CONFIG_SWAP_CFG EDU_CONFIG_SWAP_BYTE 116 #else 117 #define EDU_CONFIG_SWAP_CFG 0 118 #endif 119 120 /* edu registers */ 121 enum edu_reg { 122 EDU_CONFIG = 0, 123 EDU_DRAM_ADDR, 124 EDU_EXT_ADDR, 125 EDU_LENGTH, 126 EDU_CMD, 127 EDU_STOP, 128 EDU_STATUS, 129 EDU_DONE, 130 EDU_ERR_STATUS, 131 }; 132 133 static const u16 edu_regs[] = { 134 [EDU_CONFIG] = 0x00, 135 [EDU_DRAM_ADDR] = 0x04, 136 [EDU_EXT_ADDR] = 0x08, 137 [EDU_LENGTH] = 0x0c, 138 [EDU_CMD] = 0x10, 139 [EDU_STOP] = 0x14, 140 [EDU_STATUS] = 0x18, 141 [EDU_DONE] = 0x1c, 142 [EDU_ERR_STATUS] = 0x20, 143 }; 144 145 /* flash_dma registers */ 146 enum flash_dma_reg { 147 FLASH_DMA_REVISION = 0, 148 FLASH_DMA_FIRST_DESC, 149 FLASH_DMA_FIRST_DESC_EXT, 150 FLASH_DMA_CTRL, 151 FLASH_DMA_MODE, 152 FLASH_DMA_STATUS, 153 FLASH_DMA_INTERRUPT_DESC, 154 FLASH_DMA_INTERRUPT_DESC_EXT, 155 FLASH_DMA_ERROR_STATUS, 156 FLASH_DMA_CURRENT_DESC, 157 FLASH_DMA_CURRENT_DESC_EXT, 158 }; 159 160 /* flash_dma registers v0*/ 161 static const u16 flash_dma_regs_v0[] = { 162 [FLASH_DMA_REVISION] = 0x00, 163 [FLASH_DMA_FIRST_DESC] = 0x04, 164 [FLASH_DMA_CTRL] = 0x08, 165 [FLASH_DMA_MODE] = 0x0c, 166 [FLASH_DMA_STATUS] = 0x10, 167 [FLASH_DMA_INTERRUPT_DESC] = 0x14, 168 [FLASH_DMA_ERROR_STATUS] = 0x18, 169 [FLASH_DMA_CURRENT_DESC] = 0x1c, 170 }; 171 172 /* flash_dma registers v1*/ 173 static const u16 flash_dma_regs_v1[] = { 174 [FLASH_DMA_REVISION] = 0x00, 175 [FLASH_DMA_FIRST_DESC] = 0x04, 176 [FLASH_DMA_FIRST_DESC_EXT] = 0x08, 177 [FLASH_DMA_CTRL] = 0x0c, 178 [FLASH_DMA_MODE] = 0x10, 179 [FLASH_DMA_STATUS] = 0x14, 180 [FLASH_DMA_INTERRUPT_DESC] = 0x18, 181 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c, 182 [FLASH_DMA_ERROR_STATUS] = 0x20, 183 [FLASH_DMA_CURRENT_DESC] = 0x24, 184 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28, 185 }; 186 187 /* flash_dma registers v4 */ 188 static const u16 flash_dma_regs_v4[] = { 189 [FLASH_DMA_REVISION] = 0x00, 190 [FLASH_DMA_FIRST_DESC] = 0x08, 191 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c, 192 [FLASH_DMA_CTRL] = 0x10, 193 [FLASH_DMA_MODE] = 0x14, 194 [FLASH_DMA_STATUS] = 0x18, 195 [FLASH_DMA_INTERRUPT_DESC] = 0x20, 196 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24, 197 [FLASH_DMA_ERROR_STATUS] = 0x28, 198 [FLASH_DMA_CURRENT_DESC] = 0x30, 199 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, 200 }; 201 202 /* Controller feature flags */ 203 enum { 204 BRCMNAND_HAS_1K_SECTORS = BIT(0), 205 BRCMNAND_HAS_PREFETCH = BIT(1), 206 BRCMNAND_HAS_CACHE_MODE = BIT(2), 207 BRCMNAND_HAS_WP = BIT(3), 208 }; 209 210 struct brcmnand_host; 211 212 static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key); 213 214 struct brcmnand_controller { 215 struct device *dev; 216 struct nand_controller controller; 217 void __iomem *nand_base; 218 void __iomem *nand_fc; /* flash cache */ 219 void __iomem *flash_dma_base; 220 int irq; 221 unsigned int dma_irq; 222 int nand_version; 223 224 /* Some SoCs provide custom interrupt status register(s) */ 225 struct brcmnand_soc *soc; 226 227 /* Some SoCs have a gateable clock for the controller */ 228 struct clk *clk; 229 230 int cmd_pending; 231 bool dma_pending; 232 bool edu_pending; 233 struct completion done; 234 struct completion dma_done; 235 struct completion edu_done; 236 237 /* List of NAND hosts (one for each chip-select) */ 238 struct list_head host_list; 239 240 /* EDU info, per-transaction */ 241 const u16 *edu_offsets; 242 void __iomem *edu_base; 243 int edu_irq; 244 int edu_count; 245 u64 edu_dram_addr; 246 u32 edu_ext_addr; 247 u32 edu_cmd; 248 u32 edu_config; 249 int sas; /* spare area size, per flash cache */ 250 int sector_size_1k; 251 u8 *oob; 252 253 /* flash_dma reg */ 254 const u16 *flash_dma_offsets; 255 struct brcm_nand_dma_desc *dma_desc; 256 dma_addr_t dma_pa; 257 258 int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf, 259 u8 *oob, u32 len, u8 dma_cmd); 260 261 /* in-memory cache of the FLASH_CACHE, used only for some commands */ 262 u8 flash_cache[FC_BYTES]; 263 264 /* Controller revision details */ 265 const u16 *reg_offsets; 266 unsigned int reg_spacing; /* between CS1, CS2, ... regs */ 267 const u8 *cs_offsets; /* within each chip-select */ 268 const u8 *cs0_offsets; /* within CS0, if different */ 269 unsigned int max_block_size; 270 const unsigned int *block_sizes; 271 unsigned int max_page_size; 272 const unsigned int *page_sizes; 273 unsigned int page_size_shift; 274 unsigned int max_oob; 275 u32 ecc_level_shift; 276 u32 features; 277 278 /* for low-power standby/resume only */ 279 u32 nand_cs_nand_select; 280 u32 nand_cs_nand_xor; 281 u32 corr_stat_threshold; 282 u32 flash_dma_mode; 283 u32 flash_edu_mode; 284 bool pio_poll_mode; 285 }; 286 287 struct brcmnand_cfg { 288 u64 device_size; 289 unsigned int block_size; 290 unsigned int page_size; 291 unsigned int spare_area_size; 292 unsigned int device_width; 293 unsigned int col_adr_bytes; 294 unsigned int blk_adr_bytes; 295 unsigned int ful_adr_bytes; 296 unsigned int sector_size_1k; 297 unsigned int ecc_level; 298 /* use for low-power standby/resume only */ 299 u32 acc_control; 300 u32 config; 301 u32 config_ext; 302 u32 timing_1; 303 u32 timing_2; 304 }; 305 306 struct brcmnand_host { 307 struct list_head node; 308 309 struct nand_chip chip; 310 struct platform_device *pdev; 311 int cs; 312 313 unsigned int last_cmd; 314 unsigned int last_byte; 315 u64 last_addr; 316 struct brcmnand_cfg hwcfg; 317 struct brcmnand_controller *ctrl; 318 }; 319 320 enum brcmnand_reg { 321 BRCMNAND_CMD_START = 0, 322 BRCMNAND_CMD_EXT_ADDRESS, 323 BRCMNAND_CMD_ADDRESS, 324 BRCMNAND_INTFC_STATUS, 325 BRCMNAND_CS_SELECT, 326 BRCMNAND_CS_XOR, 327 BRCMNAND_LL_OP, 328 BRCMNAND_CS0_BASE, 329 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ 330 BRCMNAND_CORR_THRESHOLD, 331 BRCMNAND_CORR_THRESHOLD_EXT, 332 BRCMNAND_UNCORR_COUNT, 333 BRCMNAND_CORR_COUNT, 334 BRCMNAND_CORR_EXT_ADDR, 335 BRCMNAND_CORR_ADDR, 336 BRCMNAND_UNCORR_EXT_ADDR, 337 BRCMNAND_UNCORR_ADDR, 338 BRCMNAND_SEMAPHORE, 339 BRCMNAND_ID, 340 BRCMNAND_ID_EXT, 341 BRCMNAND_LL_RDATA, 342 BRCMNAND_OOB_READ_BASE, 343 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ 344 BRCMNAND_OOB_WRITE_BASE, 345 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ 346 BRCMNAND_FC_BASE, 347 }; 348 349 /* BRCMNAND v2.1-v2.2 */ 350 static const u16 brcmnand_regs_v21[] = { 351 [BRCMNAND_CMD_START] = 0x04, 352 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 353 [BRCMNAND_CMD_ADDRESS] = 0x0c, 354 [BRCMNAND_INTFC_STATUS] = 0x5c, 355 [BRCMNAND_CS_SELECT] = 0x14, 356 [BRCMNAND_CS_XOR] = 0x18, 357 [BRCMNAND_LL_OP] = 0, 358 [BRCMNAND_CS0_BASE] = 0x40, 359 [BRCMNAND_CS1_BASE] = 0, 360 [BRCMNAND_CORR_THRESHOLD] = 0, 361 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 362 [BRCMNAND_UNCORR_COUNT] = 0, 363 [BRCMNAND_CORR_COUNT] = 0, 364 [BRCMNAND_CORR_EXT_ADDR] = 0x60, 365 [BRCMNAND_CORR_ADDR] = 0x64, 366 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68, 367 [BRCMNAND_UNCORR_ADDR] = 0x6c, 368 [BRCMNAND_SEMAPHORE] = 0x50, 369 [BRCMNAND_ID] = 0x54, 370 [BRCMNAND_ID_EXT] = 0, 371 [BRCMNAND_LL_RDATA] = 0, 372 [BRCMNAND_OOB_READ_BASE] = 0x20, 373 [BRCMNAND_OOB_READ_10_BASE] = 0, 374 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 375 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 376 [BRCMNAND_FC_BASE] = 0x200, 377 }; 378 379 /* BRCMNAND v3.3-v4.0 */ 380 static const u16 brcmnand_regs_v33[] = { 381 [BRCMNAND_CMD_START] = 0x04, 382 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 383 [BRCMNAND_CMD_ADDRESS] = 0x0c, 384 [BRCMNAND_INTFC_STATUS] = 0x6c, 385 [BRCMNAND_CS_SELECT] = 0x14, 386 [BRCMNAND_CS_XOR] = 0x18, 387 [BRCMNAND_LL_OP] = 0x178, 388 [BRCMNAND_CS0_BASE] = 0x40, 389 [BRCMNAND_CS1_BASE] = 0xd0, 390 [BRCMNAND_CORR_THRESHOLD] = 0x84, 391 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 392 [BRCMNAND_UNCORR_COUNT] = 0, 393 [BRCMNAND_CORR_COUNT] = 0, 394 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 395 [BRCMNAND_CORR_ADDR] = 0x74, 396 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 397 [BRCMNAND_UNCORR_ADDR] = 0x7c, 398 [BRCMNAND_SEMAPHORE] = 0x58, 399 [BRCMNAND_ID] = 0x60, 400 [BRCMNAND_ID_EXT] = 0x64, 401 [BRCMNAND_LL_RDATA] = 0x17c, 402 [BRCMNAND_OOB_READ_BASE] = 0x20, 403 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 404 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 405 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 406 [BRCMNAND_FC_BASE] = 0x200, 407 }; 408 409 /* BRCMNAND v5.0 */ 410 static const u16 brcmnand_regs_v50[] = { 411 [BRCMNAND_CMD_START] = 0x04, 412 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 413 [BRCMNAND_CMD_ADDRESS] = 0x0c, 414 [BRCMNAND_INTFC_STATUS] = 0x6c, 415 [BRCMNAND_CS_SELECT] = 0x14, 416 [BRCMNAND_CS_XOR] = 0x18, 417 [BRCMNAND_LL_OP] = 0x178, 418 [BRCMNAND_CS0_BASE] = 0x40, 419 [BRCMNAND_CS1_BASE] = 0xd0, 420 [BRCMNAND_CORR_THRESHOLD] = 0x84, 421 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 422 [BRCMNAND_UNCORR_COUNT] = 0, 423 [BRCMNAND_CORR_COUNT] = 0, 424 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 425 [BRCMNAND_CORR_ADDR] = 0x74, 426 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 427 [BRCMNAND_UNCORR_ADDR] = 0x7c, 428 [BRCMNAND_SEMAPHORE] = 0x58, 429 [BRCMNAND_ID] = 0x60, 430 [BRCMNAND_ID_EXT] = 0x64, 431 [BRCMNAND_LL_RDATA] = 0x17c, 432 [BRCMNAND_OOB_READ_BASE] = 0x20, 433 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 434 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 435 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, 436 [BRCMNAND_FC_BASE] = 0x200, 437 }; 438 439 /* BRCMNAND v6.0 - v7.1 */ 440 static const u16 brcmnand_regs_v60[] = { 441 [BRCMNAND_CMD_START] = 0x04, 442 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 443 [BRCMNAND_CMD_ADDRESS] = 0x0c, 444 [BRCMNAND_INTFC_STATUS] = 0x14, 445 [BRCMNAND_CS_SELECT] = 0x18, 446 [BRCMNAND_CS_XOR] = 0x1c, 447 [BRCMNAND_LL_OP] = 0x20, 448 [BRCMNAND_CS0_BASE] = 0x50, 449 [BRCMNAND_CS1_BASE] = 0, 450 [BRCMNAND_CORR_THRESHOLD] = 0xc0, 451 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, 452 [BRCMNAND_UNCORR_COUNT] = 0xfc, 453 [BRCMNAND_CORR_COUNT] = 0x100, 454 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 455 [BRCMNAND_CORR_ADDR] = 0x110, 456 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 457 [BRCMNAND_UNCORR_ADDR] = 0x118, 458 [BRCMNAND_SEMAPHORE] = 0x150, 459 [BRCMNAND_ID] = 0x194, 460 [BRCMNAND_ID_EXT] = 0x198, 461 [BRCMNAND_LL_RDATA] = 0x19c, 462 [BRCMNAND_OOB_READ_BASE] = 0x200, 463 [BRCMNAND_OOB_READ_10_BASE] = 0, 464 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 465 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 466 [BRCMNAND_FC_BASE] = 0x400, 467 }; 468 469 /* BRCMNAND v7.1 */ 470 static const u16 brcmnand_regs_v71[] = { 471 [BRCMNAND_CMD_START] = 0x04, 472 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 473 [BRCMNAND_CMD_ADDRESS] = 0x0c, 474 [BRCMNAND_INTFC_STATUS] = 0x14, 475 [BRCMNAND_CS_SELECT] = 0x18, 476 [BRCMNAND_CS_XOR] = 0x1c, 477 [BRCMNAND_LL_OP] = 0x20, 478 [BRCMNAND_CS0_BASE] = 0x50, 479 [BRCMNAND_CS1_BASE] = 0, 480 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 481 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 482 [BRCMNAND_UNCORR_COUNT] = 0xfc, 483 [BRCMNAND_CORR_COUNT] = 0x100, 484 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 485 [BRCMNAND_CORR_ADDR] = 0x110, 486 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 487 [BRCMNAND_UNCORR_ADDR] = 0x118, 488 [BRCMNAND_SEMAPHORE] = 0x150, 489 [BRCMNAND_ID] = 0x194, 490 [BRCMNAND_ID_EXT] = 0x198, 491 [BRCMNAND_LL_RDATA] = 0x19c, 492 [BRCMNAND_OOB_READ_BASE] = 0x200, 493 [BRCMNAND_OOB_READ_10_BASE] = 0, 494 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 495 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 496 [BRCMNAND_FC_BASE] = 0x400, 497 }; 498 499 /* BRCMNAND v7.2 */ 500 static const u16 brcmnand_regs_v72[] = { 501 [BRCMNAND_CMD_START] = 0x04, 502 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 503 [BRCMNAND_CMD_ADDRESS] = 0x0c, 504 [BRCMNAND_INTFC_STATUS] = 0x14, 505 [BRCMNAND_CS_SELECT] = 0x18, 506 [BRCMNAND_CS_XOR] = 0x1c, 507 [BRCMNAND_LL_OP] = 0x20, 508 [BRCMNAND_CS0_BASE] = 0x50, 509 [BRCMNAND_CS1_BASE] = 0, 510 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 511 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 512 [BRCMNAND_UNCORR_COUNT] = 0xfc, 513 [BRCMNAND_CORR_COUNT] = 0x100, 514 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 515 [BRCMNAND_CORR_ADDR] = 0x110, 516 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 517 [BRCMNAND_UNCORR_ADDR] = 0x118, 518 [BRCMNAND_SEMAPHORE] = 0x150, 519 [BRCMNAND_ID] = 0x194, 520 [BRCMNAND_ID_EXT] = 0x198, 521 [BRCMNAND_LL_RDATA] = 0x19c, 522 [BRCMNAND_OOB_READ_BASE] = 0x200, 523 [BRCMNAND_OOB_READ_10_BASE] = 0, 524 [BRCMNAND_OOB_WRITE_BASE] = 0x400, 525 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 526 [BRCMNAND_FC_BASE] = 0x600, 527 }; 528 529 enum brcmnand_cs_reg { 530 BRCMNAND_CS_CFG_EXT = 0, 531 BRCMNAND_CS_CFG, 532 BRCMNAND_CS_ACC_CONTROL, 533 BRCMNAND_CS_TIMING1, 534 BRCMNAND_CS_TIMING2, 535 }; 536 537 /* Per chip-select offsets for v7.1 */ 538 static const u8 brcmnand_cs_offsets_v71[] = { 539 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 540 [BRCMNAND_CS_CFG_EXT] = 0x04, 541 [BRCMNAND_CS_CFG] = 0x08, 542 [BRCMNAND_CS_TIMING1] = 0x0c, 543 [BRCMNAND_CS_TIMING2] = 0x10, 544 }; 545 546 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ 547 static const u8 brcmnand_cs_offsets[] = { 548 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 549 [BRCMNAND_CS_CFG_EXT] = 0x04, 550 [BRCMNAND_CS_CFG] = 0x04, 551 [BRCMNAND_CS_TIMING1] = 0x08, 552 [BRCMNAND_CS_TIMING2] = 0x0c, 553 }; 554 555 /* Per chip-select offset for <= v5.0 on CS0 only */ 556 static const u8 brcmnand_cs_offsets_cs0[] = { 557 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 558 [BRCMNAND_CS_CFG_EXT] = 0x08, 559 [BRCMNAND_CS_CFG] = 0x08, 560 [BRCMNAND_CS_TIMING1] = 0x10, 561 [BRCMNAND_CS_TIMING2] = 0x14, 562 }; 563 564 /* 565 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had 566 * one config register, but once the bitfields overflowed, newer controllers 567 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. 568 */ 569 enum { 570 CFG_BLK_ADR_BYTES_SHIFT = 8, 571 CFG_COL_ADR_BYTES_SHIFT = 12, 572 CFG_FUL_ADR_BYTES_SHIFT = 16, 573 CFG_BUS_WIDTH_SHIFT = 23, 574 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), 575 CFG_DEVICE_SIZE_SHIFT = 24, 576 577 /* Only for v2.1 */ 578 CFG_PAGE_SIZE_SHIFT_v2_1 = 30, 579 580 /* Only for pre-v7.1 (with no CFG_EXT register) */ 581 CFG_PAGE_SIZE_SHIFT = 20, 582 CFG_BLK_SIZE_SHIFT = 28, 583 584 /* Only for v7.1+ (with CFG_EXT register) */ 585 CFG_EXT_PAGE_SIZE_SHIFT = 0, 586 CFG_EXT_BLK_SIZE_SHIFT = 4, 587 }; 588 589 /* BRCMNAND_INTFC_STATUS */ 590 enum { 591 INTFC_FLASH_STATUS = GENMASK(7, 0), 592 593 INTFC_ERASED = BIT(27), 594 INTFC_OOB_VALID = BIT(28), 595 INTFC_CACHE_VALID = BIT(29), 596 INTFC_FLASH_READY = BIT(30), 597 INTFC_CTLR_READY = BIT(31), 598 }; 599 600 /*********************************************************************** 601 * NAND ACC CONTROL bitfield 602 * 603 * Some bits have remained constant throughout hardware revision, while 604 * others have shifted around. 605 ***********************************************************************/ 606 607 /* Constant for all versions (where supported) */ 608 enum { 609 /* See BRCMNAND_HAS_CACHE_MODE */ 610 ACC_CONTROL_CACHE_MODE = BIT(22), 611 612 /* See BRCMNAND_HAS_PREFETCH */ 613 ACC_CONTROL_PREFETCH = BIT(23), 614 615 ACC_CONTROL_PAGE_HIT = BIT(24), 616 ACC_CONTROL_WR_PREEMPT = BIT(25), 617 ACC_CONTROL_PARTIAL_PAGE = BIT(26), 618 ACC_CONTROL_RD_ERASED = BIT(27), 619 ACC_CONTROL_FAST_PGM_RDIN = BIT(28), 620 ACC_CONTROL_WR_ECC = BIT(30), 621 ACC_CONTROL_RD_ECC = BIT(31), 622 }; 623 624 #define ACC_CONTROL_ECC_SHIFT 16 625 /* Only for v7.2 */ 626 #define ACC_CONTROL_ECC_EXT_SHIFT 13 627 628 static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) 629 { 630 #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) 631 return static_branch_unlikely(&brcmnand_soc_has_ops_key); 632 #else 633 return false; 634 #endif 635 } 636 637 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) 638 { 639 if (brcmnand_non_mmio_ops(ctrl)) 640 return brcmnand_soc_read(ctrl->soc, offs); 641 return brcmnand_readl(ctrl->nand_base + offs); 642 } 643 644 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, 645 u32 val) 646 { 647 if (brcmnand_non_mmio_ops(ctrl)) 648 brcmnand_soc_write(ctrl->soc, val, offs); 649 else 650 brcmnand_writel(val, ctrl->nand_base + offs); 651 } 652 653 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) 654 { 655 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; 656 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; 657 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 }; 658 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 }; 659 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 }; 660 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 }; 661 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 }; 662 663 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; 664 665 /* Only support v2.1+ */ 666 if (ctrl->nand_version < 0x0201) { 667 dev_err(ctrl->dev, "version %#x not supported\n", 668 ctrl->nand_version); 669 return -ENODEV; 670 } 671 672 /* Register offsets */ 673 if (ctrl->nand_version >= 0x0702) 674 ctrl->reg_offsets = brcmnand_regs_v72; 675 else if (ctrl->nand_version == 0x0701) 676 ctrl->reg_offsets = brcmnand_regs_v71; 677 else if (ctrl->nand_version >= 0x0600) 678 ctrl->reg_offsets = brcmnand_regs_v60; 679 else if (ctrl->nand_version >= 0x0500) 680 ctrl->reg_offsets = brcmnand_regs_v50; 681 else if (ctrl->nand_version >= 0x0303) 682 ctrl->reg_offsets = brcmnand_regs_v33; 683 else if (ctrl->nand_version >= 0x0201) 684 ctrl->reg_offsets = brcmnand_regs_v21; 685 686 /* Chip-select stride */ 687 if (ctrl->nand_version >= 0x0701) 688 ctrl->reg_spacing = 0x14; 689 else 690 ctrl->reg_spacing = 0x10; 691 692 /* Per chip-select registers */ 693 if (ctrl->nand_version >= 0x0701) { 694 ctrl->cs_offsets = brcmnand_cs_offsets_v71; 695 } else { 696 ctrl->cs_offsets = brcmnand_cs_offsets; 697 698 /* v3.3-5.0 have a different CS0 offset layout */ 699 if (ctrl->nand_version >= 0x0303 && 700 ctrl->nand_version <= 0x0500) 701 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; 702 } 703 704 /* Page / block sizes */ 705 if (ctrl->nand_version >= 0x0701) { 706 /* >= v7.1 use nice power-of-2 values! */ 707 ctrl->max_page_size = 16 * 1024; 708 ctrl->max_block_size = 2 * 1024 * 1024; 709 } else { 710 if (ctrl->nand_version >= 0x0304) 711 ctrl->page_sizes = page_sizes_v3_4; 712 else if (ctrl->nand_version >= 0x0202) 713 ctrl->page_sizes = page_sizes_v2_2; 714 else 715 ctrl->page_sizes = page_sizes_v2_1; 716 717 if (ctrl->nand_version >= 0x0202) 718 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; 719 else 720 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; 721 722 if (ctrl->nand_version >= 0x0600) 723 ctrl->block_sizes = block_sizes_v6; 724 else if (ctrl->nand_version >= 0x0400) 725 ctrl->block_sizes = block_sizes_v4; 726 else if (ctrl->nand_version >= 0x0202) 727 ctrl->block_sizes = block_sizes_v2_2; 728 else 729 ctrl->block_sizes = block_sizes_v2_1; 730 731 if (ctrl->nand_version < 0x0400) { 732 if (ctrl->nand_version < 0x0202) 733 ctrl->max_page_size = 2048; 734 else 735 ctrl->max_page_size = 4096; 736 ctrl->max_block_size = 512 * 1024; 737 } 738 } 739 740 /* Maximum spare area sector size (per 512B) */ 741 if (ctrl->nand_version == 0x0702) 742 ctrl->max_oob = 128; 743 else if (ctrl->nand_version >= 0x0600) 744 ctrl->max_oob = 64; 745 else if (ctrl->nand_version >= 0x0500) 746 ctrl->max_oob = 32; 747 else 748 ctrl->max_oob = 16; 749 750 /* v6.0 and newer (except v6.1) have prefetch support */ 751 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) 752 ctrl->features |= BRCMNAND_HAS_PREFETCH; 753 754 /* 755 * v6.x has cache mode, but it's implemented differently. Ignore it for 756 * now. 757 */ 758 if (ctrl->nand_version >= 0x0700) 759 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; 760 761 if (ctrl->nand_version >= 0x0500) 762 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; 763 764 if (ctrl->nand_version >= 0x0700) 765 ctrl->features |= BRCMNAND_HAS_WP; 766 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) 767 ctrl->features |= BRCMNAND_HAS_WP; 768 769 /* v7.2 has different ecc level shift in the acc register */ 770 if (ctrl->nand_version == 0x0702) 771 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; 772 else 773 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; 774 775 return 0; 776 } 777 778 static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) 779 { 780 /* flash_dma register offsets */ 781 if (ctrl->nand_version >= 0x0703) 782 ctrl->flash_dma_offsets = flash_dma_regs_v4; 783 else if (ctrl->nand_version == 0x0602) 784 ctrl->flash_dma_offsets = flash_dma_regs_v0; 785 else 786 ctrl->flash_dma_offsets = flash_dma_regs_v1; 787 } 788 789 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, 790 enum brcmnand_reg reg) 791 { 792 u16 offs = ctrl->reg_offsets[reg]; 793 794 if (offs) 795 return nand_readreg(ctrl, offs); 796 else 797 return 0; 798 } 799 800 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, 801 enum brcmnand_reg reg, u32 val) 802 { 803 u16 offs = ctrl->reg_offsets[reg]; 804 805 if (offs) 806 nand_writereg(ctrl, offs, val); 807 } 808 809 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, 810 enum brcmnand_reg reg, u32 mask, unsigned 811 int shift, u32 val) 812 { 813 u32 tmp = brcmnand_read_reg(ctrl, reg); 814 815 tmp &= ~mask; 816 tmp |= val << shift; 817 brcmnand_write_reg(ctrl, reg, tmp); 818 } 819 820 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) 821 { 822 if (brcmnand_non_mmio_ops(ctrl)) 823 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); 824 return __raw_readl(ctrl->nand_fc + word * 4); 825 } 826 827 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, 828 int word, u32 val) 829 { 830 if (brcmnand_non_mmio_ops(ctrl)) 831 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); 832 else 833 __raw_writel(val, ctrl->nand_fc + word * 4); 834 } 835 836 static inline void edu_writel(struct brcmnand_controller *ctrl, 837 enum edu_reg reg, u32 val) 838 { 839 u16 offs = ctrl->edu_offsets[reg]; 840 841 brcmnand_writel(val, ctrl->edu_base + offs); 842 } 843 844 static inline u32 edu_readl(struct brcmnand_controller *ctrl, 845 enum edu_reg reg) 846 { 847 u16 offs = ctrl->edu_offsets[reg]; 848 849 return brcmnand_readl(ctrl->edu_base + offs); 850 } 851 852 static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) 853 { 854 855 /* Clear error addresses */ 856 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); 857 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); 858 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); 859 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); 860 } 861 862 static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) 863 { 864 u64 err_addr; 865 866 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); 867 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 868 BRCMNAND_UNCORR_EXT_ADDR) 869 & 0xffff) << 32); 870 871 return err_addr; 872 } 873 874 static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) 875 { 876 u64 err_addr; 877 878 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); 879 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 880 BRCMNAND_CORR_EXT_ADDR) 881 & 0xffff) << 32); 882 883 return err_addr; 884 } 885 886 static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr) 887 { 888 struct nand_chip *chip = mtd_to_nand(mtd); 889 struct brcmnand_host *host = nand_get_controller_data(chip); 890 struct brcmnand_controller *ctrl = host->ctrl; 891 892 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 893 (host->cs << 16) | ((addr >> 32) & 0xffff)); 894 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 895 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 896 lower_32_bits(addr)); 897 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 898 } 899 900 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, 901 enum brcmnand_cs_reg reg) 902 { 903 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; 904 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; 905 u8 cs_offs; 906 907 if (cs == 0 && ctrl->cs0_offsets) 908 cs_offs = ctrl->cs0_offsets[reg]; 909 else 910 cs_offs = ctrl->cs_offsets[reg]; 911 912 if (cs && offs_cs1) 913 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; 914 915 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; 916 } 917 918 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) 919 { 920 if (ctrl->nand_version < 0x0600) 921 return 1; 922 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); 923 } 924 925 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) 926 { 927 struct brcmnand_controller *ctrl = host->ctrl; 928 unsigned int shift = 0, bits; 929 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; 930 int cs = host->cs; 931 932 if (!ctrl->reg_offsets[reg]) 933 return; 934 935 if (ctrl->nand_version == 0x0702) 936 bits = 7; 937 else if (ctrl->nand_version >= 0x0600) 938 bits = 6; 939 else if (ctrl->nand_version >= 0x0500) 940 bits = 5; 941 else 942 bits = 4; 943 944 if (ctrl->nand_version >= 0x0702) { 945 if (cs >= 4) 946 reg = BRCMNAND_CORR_THRESHOLD_EXT; 947 shift = (cs % 4) * bits; 948 } else if (ctrl->nand_version >= 0x0600) { 949 if (cs >= 5) 950 reg = BRCMNAND_CORR_THRESHOLD_EXT; 951 shift = (cs % 5) * bits; 952 } 953 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); 954 } 955 956 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) 957 { 958 /* Kludge for the BCMA-based NAND controller which does not actually 959 * shift the command 960 */ 961 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) 962 return 0; 963 964 if (ctrl->nand_version < 0x0602) 965 return 24; 966 return 0; 967 } 968 969 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) 970 { 971 if (ctrl->nand_version == 0x0702) 972 return GENMASK(7, 0); 973 else if (ctrl->nand_version >= 0x0600) 974 return GENMASK(6, 0); 975 else if (ctrl->nand_version >= 0x0303) 976 return GENMASK(5, 0); 977 else 978 return GENMASK(4, 0); 979 } 980 981 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) 982 { 983 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; 984 985 mask <<= ACC_CONTROL_ECC_SHIFT; 986 987 /* v7.2 includes additional ECC levels */ 988 if (ctrl->nand_version == 0x0702) 989 mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; 990 991 return mask; 992 } 993 994 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) 995 { 996 struct brcmnand_controller *ctrl = host->ctrl; 997 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 998 u32 acc_control = nand_readreg(ctrl, offs); 999 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; 1000 1001 if (en) { 1002 acc_control |= ecc_flags; /* enable RD/WR ECC */ 1003 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 1004 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; 1005 } else { 1006 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ 1007 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 1008 } 1009 1010 nand_writereg(ctrl, offs, acc_control); 1011 } 1012 1013 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) 1014 { 1015 if (ctrl->nand_version >= 0x0702) 1016 return 9; 1017 else if (ctrl->nand_version >= 0x0600) 1018 return 7; 1019 else if (ctrl->nand_version >= 0x0500) 1020 return 6; 1021 else 1022 return -1; 1023 } 1024 1025 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) 1026 { 1027 struct brcmnand_controller *ctrl = host->ctrl; 1028 int shift = brcmnand_sector_1k_shift(ctrl); 1029 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1030 BRCMNAND_CS_ACC_CONTROL); 1031 1032 if (shift < 0) 1033 return 0; 1034 1035 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; 1036 } 1037 1038 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) 1039 { 1040 struct brcmnand_controller *ctrl = host->ctrl; 1041 int shift = brcmnand_sector_1k_shift(ctrl); 1042 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 1043 BRCMNAND_CS_ACC_CONTROL); 1044 u32 tmp; 1045 1046 if (shift < 0) 1047 return; 1048 1049 tmp = nand_readreg(ctrl, acc_control_offs); 1050 tmp &= ~(1 << shift); 1051 tmp |= (!!val) << shift; 1052 nand_writereg(ctrl, acc_control_offs, tmp); 1053 } 1054 1055 /*********************************************************************** 1056 * CS_NAND_SELECT 1057 ***********************************************************************/ 1058 1059 enum { 1060 CS_SELECT_NAND_WP = BIT(29), 1061 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), 1062 }; 1063 1064 static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, 1065 u32 mask, u32 expected_val, 1066 unsigned long timeout_ms) 1067 { 1068 unsigned long limit; 1069 u32 val; 1070 1071 if (!timeout_ms) 1072 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 1073 1074 limit = jiffies + msecs_to_jiffies(timeout_ms); 1075 do { 1076 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1077 if ((val & mask) == expected_val) 1078 return 0; 1079 1080 cpu_relax(); 1081 } while (time_after(limit, jiffies)); 1082 1083 /* 1084 * do a final check after time out in case the CPU was busy and the driver 1085 * did not get enough time to perform the polling to avoid false alarms 1086 */ 1087 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1088 if ((val & mask) == expected_val) 1089 return 0; 1090 1091 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", 1092 expected_val, val & mask); 1093 1094 return -ETIMEDOUT; 1095 } 1096 1097 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) 1098 { 1099 u32 val = en ? CS_SELECT_NAND_WP : 0; 1100 1101 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); 1102 } 1103 1104 /*********************************************************************** 1105 * Flash DMA 1106 ***********************************************************************/ 1107 1108 static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 1109 { 1110 return ctrl->flash_dma_base; 1111 } 1112 1113 static inline bool has_edu(struct brcmnand_controller *ctrl) 1114 { 1115 return ctrl->edu_base; 1116 } 1117 1118 static inline bool use_dma(struct brcmnand_controller *ctrl) 1119 { 1120 return has_flash_dma(ctrl) || has_edu(ctrl); 1121 } 1122 1123 static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl) 1124 { 1125 if (ctrl->pio_poll_mode) 1126 return; 1127 1128 if (has_flash_dma(ctrl)) { 1129 ctrl->flash_dma_base = NULL; 1130 disable_irq(ctrl->dma_irq); 1131 } 1132 1133 disable_irq(ctrl->irq); 1134 ctrl->pio_poll_mode = true; 1135 } 1136 1137 static inline bool flash_dma_buf_ok(const void *buf) 1138 { 1139 return buf && !is_vmalloc_addr(buf) && 1140 likely(IS_ALIGNED((uintptr_t)buf, 4)); 1141 } 1142 1143 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, 1144 enum flash_dma_reg dma_reg, u32 val) 1145 { 1146 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1147 1148 brcmnand_writel(val, ctrl->flash_dma_base + offs); 1149 } 1150 1151 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, 1152 enum flash_dma_reg dma_reg) 1153 { 1154 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1155 1156 return brcmnand_readl(ctrl->flash_dma_base + offs); 1157 } 1158 1159 /* Low-level operation types: command, address, write, or read */ 1160 enum brcmnand_llop_type { 1161 LL_OP_CMD, 1162 LL_OP_ADDR, 1163 LL_OP_WR, 1164 LL_OP_RD, 1165 }; 1166 1167 /*********************************************************************** 1168 * Internal support functions 1169 ***********************************************************************/ 1170 1171 static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, 1172 struct brcmnand_cfg *cfg) 1173 { 1174 if (ctrl->nand_version <= 0x0701) 1175 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && 1176 cfg->ecc_level == 15; 1177 else 1178 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && 1179 cfg->ecc_level == 15) || 1180 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); 1181 } 1182 1183 /* 1184 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given 1185 * the layout/configuration. 1186 * Returns -ERRCODE on failure. 1187 */ 1188 static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section, 1189 struct mtd_oob_region *oobregion) 1190 { 1191 struct nand_chip *chip = mtd_to_nand(mtd); 1192 struct brcmnand_host *host = nand_get_controller_data(chip); 1193 struct brcmnand_cfg *cfg = &host->hwcfg; 1194 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1195 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1196 1197 if (section >= sectors) 1198 return -ERANGE; 1199 1200 oobregion->offset = (section * sas) + 6; 1201 oobregion->length = 3; 1202 1203 return 0; 1204 } 1205 1206 static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section, 1207 struct mtd_oob_region *oobregion) 1208 { 1209 struct nand_chip *chip = mtd_to_nand(mtd); 1210 struct brcmnand_host *host = nand_get_controller_data(chip); 1211 struct brcmnand_cfg *cfg = &host->hwcfg; 1212 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1213 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1214 u32 next; 1215 1216 if (section > sectors) 1217 return -ERANGE; 1218 1219 next = (section * sas); 1220 if (section < sectors) 1221 next += 6; 1222 1223 if (section) { 1224 oobregion->offset = ((section - 1) * sas) + 9; 1225 } else { 1226 if (cfg->page_size > 512) { 1227 /* Large page NAND uses first 2 bytes for BBI */ 1228 oobregion->offset = 2; 1229 } else { 1230 /* Small page NAND uses last byte before ECC for BBI */ 1231 oobregion->offset = 0; 1232 next--; 1233 } 1234 } 1235 1236 oobregion->length = next - oobregion->offset; 1237 1238 return 0; 1239 } 1240 1241 static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = { 1242 .ecc = brcmnand_hamming_ooblayout_ecc, 1243 .free = brcmnand_hamming_ooblayout_free, 1244 }; 1245 1246 static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section, 1247 struct mtd_oob_region *oobregion) 1248 { 1249 struct nand_chip *chip = mtd_to_nand(mtd); 1250 struct brcmnand_host *host = nand_get_controller_data(chip); 1251 struct brcmnand_cfg *cfg = &host->hwcfg; 1252 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1253 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1254 1255 if (section >= sectors) 1256 return -ERANGE; 1257 1258 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; 1259 oobregion->length = chip->ecc.bytes; 1260 1261 return 0; 1262 } 1263 1264 static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section, 1265 struct mtd_oob_region *oobregion) 1266 { 1267 struct nand_chip *chip = mtd_to_nand(mtd); 1268 struct brcmnand_host *host = nand_get_controller_data(chip); 1269 struct brcmnand_cfg *cfg = &host->hwcfg; 1270 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1271 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1272 1273 if (section >= sectors) 1274 return -ERANGE; 1275 1276 if (sas <= chip->ecc.bytes) 1277 return 0; 1278 1279 oobregion->offset = section * sas; 1280 oobregion->length = sas - chip->ecc.bytes; 1281 1282 if (!section) { 1283 oobregion->offset++; 1284 oobregion->length--; 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section, 1291 struct mtd_oob_region *oobregion) 1292 { 1293 struct nand_chip *chip = mtd_to_nand(mtd); 1294 struct brcmnand_host *host = nand_get_controller_data(chip); 1295 struct brcmnand_cfg *cfg = &host->hwcfg; 1296 int sas = cfg->spare_area_size << cfg->sector_size_1k; 1297 1298 if (section > 1 || sas - chip->ecc.bytes < 6 || 1299 (section && sas - chip->ecc.bytes == 6)) 1300 return -ERANGE; 1301 1302 if (!section) { 1303 oobregion->offset = 0; 1304 oobregion->length = 5; 1305 } else { 1306 oobregion->offset = 6; 1307 oobregion->length = sas - chip->ecc.bytes - 6; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = { 1314 .ecc = brcmnand_bch_ooblayout_ecc, 1315 .free = brcmnand_bch_ooblayout_free_lp, 1316 }; 1317 1318 static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = { 1319 .ecc = brcmnand_bch_ooblayout_ecc, 1320 .free = brcmnand_bch_ooblayout_free_sp, 1321 }; 1322 1323 static int brcmstb_choose_ecc_layout(struct brcmnand_host *host) 1324 { 1325 struct brcmnand_cfg *p = &host->hwcfg; 1326 struct mtd_info *mtd = nand_to_mtd(&host->chip); 1327 struct nand_ecc_ctrl *ecc = &host->chip.ecc; 1328 unsigned int ecc_level = p->ecc_level; 1329 int sas = p->spare_area_size << p->sector_size_1k; 1330 int sectors = p->page_size / (512 << p->sector_size_1k); 1331 1332 if (p->sector_size_1k) 1333 ecc_level <<= 1; 1334 1335 if (is_hamming_ecc(host->ctrl, p)) { 1336 ecc->bytes = 3 * sectors; 1337 mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops); 1338 return 0; 1339 } 1340 1341 /* 1342 * CONTROLLER_VERSION: 1343 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) 1344 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) 1345 * But we will just be conservative. 1346 */ 1347 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); 1348 if (p->page_size == 512) 1349 mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops); 1350 else 1351 mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops); 1352 1353 if (ecc->bytes >= sas) { 1354 dev_err(&host->pdev->dev, 1355 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", 1356 ecc->bytes, sas); 1357 return -EINVAL; 1358 } 1359 1360 return 0; 1361 } 1362 1363 static void brcmnand_wp(struct mtd_info *mtd, int wp) 1364 { 1365 struct nand_chip *chip = mtd_to_nand(mtd); 1366 struct brcmnand_host *host = nand_get_controller_data(chip); 1367 struct brcmnand_controller *ctrl = host->ctrl; 1368 1369 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { 1370 static int old_wp = -1; 1371 int ret; 1372 1373 if (old_wp != wp) { 1374 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); 1375 old_wp = wp; 1376 } 1377 1378 /* 1379 * make sure ctrl/flash ready before and after 1380 * changing state of #WP pin 1381 */ 1382 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | 1383 NAND_STATUS_READY, 1384 NAND_CTRL_RDY | 1385 NAND_STATUS_READY, 0); 1386 if (ret) 1387 return; 1388 1389 brcmnand_set_wp(ctrl, wp); 1390 nand_status_op(chip, NULL); 1391 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ 1392 ret = bcmnand_ctrl_poll_status(ctrl, 1393 NAND_CTRL_RDY | 1394 NAND_STATUS_READY | 1395 NAND_STATUS_WP, 1396 NAND_CTRL_RDY | 1397 NAND_STATUS_READY | 1398 (wp ? 0 : NAND_STATUS_WP), 0); 1399 1400 if (ret) 1401 dev_err_ratelimited(&host->pdev->dev, 1402 "nand #WP expected %s\n", 1403 wp ? "on" : "off"); 1404 } 1405 } 1406 1407 /* Helper functions for reading and writing OOB registers */ 1408 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) 1409 { 1410 u16 offset0, offset10, reg_offs; 1411 1412 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; 1413 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; 1414 1415 if (offs >= ctrl->max_oob) 1416 return 0x77; 1417 1418 if (offs >= 16 && offset10) 1419 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1420 else 1421 reg_offs = offset0 + (offs & ~0x03); 1422 1423 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); 1424 } 1425 1426 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, 1427 u32 data) 1428 { 1429 u16 offset0, offset10, reg_offs; 1430 1431 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; 1432 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; 1433 1434 if (offs >= ctrl->max_oob) 1435 return; 1436 1437 if (offs >= 16 && offset10) 1438 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1439 else 1440 reg_offs = offset0 + (offs & ~0x03); 1441 1442 nand_writereg(ctrl, reg_offs, data); 1443 } 1444 1445 /* 1446 * read_oob_from_regs - read data from OOB registers 1447 * @ctrl: NAND controller 1448 * @i: sub-page sector index 1449 * @oob: buffer to read to 1450 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1451 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1452 */ 1453 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, 1454 int sas, int sector_1k) 1455 { 1456 int tbytes = sas << sector_1k; 1457 int j; 1458 1459 /* Adjust OOB values for 1K sector size */ 1460 if (sector_1k && (i & 0x01)) 1461 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1462 tbytes = min_t(int, tbytes, ctrl->max_oob); 1463 1464 for (j = 0; j < tbytes; j++) 1465 oob[j] = oob_reg_read(ctrl, j); 1466 return tbytes; 1467 } 1468 1469 /* 1470 * write_oob_to_regs - write data to OOB registers 1471 * @i: sub-page sector index 1472 * @oob: buffer to write from 1473 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1474 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1475 */ 1476 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, 1477 const u8 *oob, int sas, int sector_1k) 1478 { 1479 int tbytes = sas << sector_1k; 1480 int j, k = 0; 1481 u32 last = 0xffffffff; 1482 u8 *plast = (u8 *)&last; 1483 1484 /* Adjust OOB values for 1K sector size */ 1485 if (sector_1k && (i & 0x01)) 1486 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1487 tbytes = min_t(int, tbytes, ctrl->max_oob); 1488 1489 /* 1490 * tbytes may not be multiple of words. Make sure we don't read out of 1491 * the boundary and stop at last word. 1492 */ 1493 for (j = 0; (j + 3) < tbytes; j += 4) 1494 oob_reg_write(ctrl, j, 1495 (oob[j + 0] << 24) | 1496 (oob[j + 1] << 16) | 1497 (oob[j + 2] << 8) | 1498 (oob[j + 3] << 0)); 1499 1500 /* handle the remaing bytes */ 1501 while (j < tbytes) 1502 plast[k++] = oob[j++]; 1503 1504 if (tbytes & 0x3) 1505 oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); 1506 1507 return tbytes; 1508 } 1509 1510 static void brcmnand_edu_init(struct brcmnand_controller *ctrl) 1511 { 1512 /* initialize edu */ 1513 edu_writel(ctrl, EDU_ERR_STATUS, 0); 1514 edu_readl(ctrl, EDU_ERR_STATUS); 1515 edu_writel(ctrl, EDU_DONE, 0); 1516 edu_writel(ctrl, EDU_DONE, 0); 1517 edu_writel(ctrl, EDU_DONE, 0); 1518 edu_writel(ctrl, EDU_DONE, 0); 1519 edu_readl(ctrl, EDU_DONE); 1520 } 1521 1522 /* edu irq */ 1523 static irqreturn_t brcmnand_edu_irq(int irq, void *data) 1524 { 1525 struct brcmnand_controller *ctrl = data; 1526 1527 if (ctrl->edu_count) { 1528 ctrl->edu_count--; 1529 while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK)) 1530 udelay(1); 1531 edu_writel(ctrl, EDU_DONE, 0); 1532 edu_readl(ctrl, EDU_DONE); 1533 } 1534 1535 if (ctrl->edu_count) { 1536 ctrl->edu_dram_addr += FC_BYTES; 1537 ctrl->edu_ext_addr += FC_BYTES; 1538 1539 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1540 edu_readl(ctrl, EDU_DRAM_ADDR); 1541 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1542 edu_readl(ctrl, EDU_EXT_ADDR); 1543 1544 if (ctrl->oob) { 1545 if (ctrl->edu_cmd == EDU_CMD_READ) { 1546 ctrl->oob += read_oob_from_regs(ctrl, 1547 ctrl->edu_count + 1, 1548 ctrl->oob, ctrl->sas, 1549 ctrl->sector_size_1k); 1550 } else { 1551 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 1552 ctrl->edu_ext_addr); 1553 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1554 ctrl->oob += write_oob_to_regs(ctrl, 1555 ctrl->edu_count, 1556 ctrl->oob, ctrl->sas, 1557 ctrl->sector_size_1k); 1558 } 1559 } 1560 1561 mb(); /* flush previous writes */ 1562 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1563 edu_readl(ctrl, EDU_CMD); 1564 1565 return IRQ_HANDLED; 1566 } 1567 1568 complete(&ctrl->edu_done); 1569 1570 return IRQ_HANDLED; 1571 } 1572 1573 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 1574 { 1575 struct brcmnand_controller *ctrl = data; 1576 1577 /* Discard all NAND_CTLRDY interrupts during DMA */ 1578 if (ctrl->dma_pending) 1579 return IRQ_HANDLED; 1580 1581 /* check if you need to piggy back on the ctrlrdy irq */ 1582 if (ctrl->edu_pending) { 1583 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) 1584 /* Discard interrupts while using dedicated edu irq */ 1585 return IRQ_HANDLED; 1586 1587 /* no registered edu irq, call handler */ 1588 return brcmnand_edu_irq(irq, data); 1589 } 1590 1591 complete(&ctrl->done); 1592 return IRQ_HANDLED; 1593 } 1594 1595 /* Handle SoC-specific interrupt hardware */ 1596 static irqreturn_t brcmnand_irq(int irq, void *data) 1597 { 1598 struct brcmnand_controller *ctrl = data; 1599 1600 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) 1601 return brcmnand_ctlrdy_irq(irq, data); 1602 1603 return IRQ_NONE; 1604 } 1605 1606 static irqreturn_t brcmnand_dma_irq(int irq, void *data) 1607 { 1608 struct brcmnand_controller *ctrl = data; 1609 1610 complete(&ctrl->dma_done); 1611 1612 return IRQ_HANDLED; 1613 } 1614 1615 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) 1616 { 1617 struct brcmnand_controller *ctrl = host->ctrl; 1618 int ret; 1619 u64 cmd_addr; 1620 1621 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1622 1623 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); 1624 1625 /* 1626 * If we came here through _panic_write and there is a pending 1627 * command, try to wait for it. If it times out, rather than 1628 * hitting BUG_ON, just return so we don't crash while crashing. 1629 */ 1630 if (oops_in_progress) { 1631 if (ctrl->cmd_pending && 1632 bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) 1633 return; 1634 } else 1635 BUG_ON(ctrl->cmd_pending != 0); 1636 ctrl->cmd_pending = cmd; 1637 1638 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 1639 WARN_ON(ret); 1640 1641 mb(); /* flush previous writes */ 1642 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, 1643 cmd << brcmnand_cmd_shift(ctrl)); 1644 } 1645 1646 /*********************************************************************** 1647 * NAND MTD API: read/program/erase 1648 ***********************************************************************/ 1649 1650 static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat, 1651 unsigned int ctrl) 1652 { 1653 /* intentionally left blank */ 1654 } 1655 1656 static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip) 1657 { 1658 struct brcmnand_host *host = nand_get_controller_data(chip); 1659 struct brcmnand_controller *ctrl = host->ctrl; 1660 struct mtd_info *mtd = nand_to_mtd(chip); 1661 bool err = false; 1662 int sts; 1663 1664 if (mtd->oops_panic_write || ctrl->irq < 0) { 1665 /* switch to interrupt polling and PIO mode */ 1666 disable_ctrl_irqs(ctrl); 1667 sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, 1668 NAND_CTRL_RDY, 0); 1669 err = sts < 0; 1670 } else { 1671 unsigned long timeo = msecs_to_jiffies( 1672 NAND_POLL_STATUS_TIMEOUT_MS); 1673 /* wait for completion interrupt */ 1674 sts = wait_for_completion_timeout(&ctrl->done, timeo); 1675 err = !sts; 1676 } 1677 1678 return err; 1679 } 1680 1681 static int brcmnand_waitfunc(struct nand_chip *chip) 1682 { 1683 struct brcmnand_host *host = nand_get_controller_data(chip); 1684 struct brcmnand_controller *ctrl = host->ctrl; 1685 bool err = false; 1686 1687 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 1688 if (ctrl->cmd_pending) 1689 err = brcmstb_nand_wait_for_completion(chip); 1690 1691 ctrl->cmd_pending = 0; 1692 if (err) { 1693 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) 1694 >> brcmnand_cmd_shift(ctrl); 1695 1696 dev_err_ratelimited(ctrl->dev, 1697 "timeout waiting for command %#02x\n", cmd); 1698 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", 1699 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); 1700 return -ETIMEDOUT; 1701 } 1702 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1703 INTFC_FLASH_STATUS; 1704 } 1705 1706 enum { 1707 LLOP_RE = BIT(16), 1708 LLOP_WE = BIT(17), 1709 LLOP_ALE = BIT(18), 1710 LLOP_CLE = BIT(19), 1711 LLOP_RETURN_IDLE = BIT(31), 1712 1713 LLOP_DATA_MASK = GENMASK(15, 0), 1714 }; 1715 1716 static int brcmnand_low_level_op(struct brcmnand_host *host, 1717 enum brcmnand_llop_type type, u32 data, 1718 bool last_op) 1719 { 1720 struct nand_chip *chip = &host->chip; 1721 struct brcmnand_controller *ctrl = host->ctrl; 1722 u32 tmp; 1723 1724 tmp = data & LLOP_DATA_MASK; 1725 switch (type) { 1726 case LL_OP_CMD: 1727 tmp |= LLOP_WE | LLOP_CLE; 1728 break; 1729 case LL_OP_ADDR: 1730 /* WE | ALE */ 1731 tmp |= LLOP_WE | LLOP_ALE; 1732 break; 1733 case LL_OP_WR: 1734 /* WE */ 1735 tmp |= LLOP_WE; 1736 break; 1737 case LL_OP_RD: 1738 /* RE */ 1739 tmp |= LLOP_RE; 1740 break; 1741 } 1742 if (last_op) 1743 /* RETURN_IDLE */ 1744 tmp |= LLOP_RETURN_IDLE; 1745 1746 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); 1747 1748 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); 1749 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); 1750 1751 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); 1752 return brcmnand_waitfunc(chip); 1753 } 1754 1755 static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command, 1756 int column, int page_addr) 1757 { 1758 struct mtd_info *mtd = nand_to_mtd(chip); 1759 struct brcmnand_host *host = nand_get_controller_data(chip); 1760 struct brcmnand_controller *ctrl = host->ctrl; 1761 u64 addr = (u64)page_addr << chip->page_shift; 1762 int native_cmd = 0; 1763 1764 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || 1765 command == NAND_CMD_RNDOUT) 1766 addr = (u64)column; 1767 /* Avoid propagating a negative, don't-care address */ 1768 else if (page_addr < 0) 1769 addr = 0; 1770 1771 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, 1772 (unsigned long long)addr); 1773 1774 host->last_cmd = command; 1775 host->last_byte = 0; 1776 host->last_addr = addr; 1777 1778 switch (command) { 1779 case NAND_CMD_RESET: 1780 native_cmd = CMD_FLASH_RESET; 1781 break; 1782 case NAND_CMD_STATUS: 1783 native_cmd = CMD_STATUS_READ; 1784 break; 1785 case NAND_CMD_READID: 1786 native_cmd = CMD_DEVICE_ID_READ; 1787 break; 1788 case NAND_CMD_READOOB: 1789 native_cmd = CMD_SPARE_AREA_READ; 1790 break; 1791 case NAND_CMD_ERASE1: 1792 native_cmd = CMD_BLOCK_ERASE; 1793 brcmnand_wp(mtd, 0); 1794 break; 1795 case NAND_CMD_PARAM: 1796 native_cmd = CMD_PARAMETER_READ; 1797 break; 1798 case NAND_CMD_SET_FEATURES: 1799 case NAND_CMD_GET_FEATURES: 1800 brcmnand_low_level_op(host, LL_OP_CMD, command, false); 1801 brcmnand_low_level_op(host, LL_OP_ADDR, column, false); 1802 break; 1803 case NAND_CMD_RNDOUT: 1804 native_cmd = CMD_PARAMETER_CHANGE_COL; 1805 addr &= ~((u64)(FC_BYTES - 1)); 1806 /* 1807 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 1808 * NB: hwcfg.sector_size_1k may not be initialized yet 1809 */ 1810 if (brcmnand_get_sector_size_1k(host)) { 1811 host->hwcfg.sector_size_1k = 1812 brcmnand_get_sector_size_1k(host); 1813 brcmnand_set_sector_size_1k(host, 0); 1814 } 1815 break; 1816 } 1817 1818 if (!native_cmd) 1819 return; 1820 1821 brcmnand_set_cmd_addr(mtd, addr); 1822 brcmnand_send_cmd(host, native_cmd); 1823 brcmnand_waitfunc(chip); 1824 1825 if (native_cmd == CMD_PARAMETER_READ || 1826 native_cmd == CMD_PARAMETER_CHANGE_COL) { 1827 /* Copy flash cache word-wise */ 1828 u32 *flash_cache = (u32 *)ctrl->flash_cache; 1829 int i; 1830 1831 brcmnand_soc_data_bus_prepare(ctrl->soc, true); 1832 1833 /* 1834 * Must cache the FLASH_CACHE now, since changes in 1835 * SECTOR_SIZE_1K may invalidate it 1836 */ 1837 for (i = 0; i < FC_WORDS; i++) 1838 /* 1839 * Flash cache is big endian for parameter pages, at 1840 * least on STB SoCs 1841 */ 1842 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i)); 1843 1844 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); 1845 1846 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ 1847 if (host->hwcfg.sector_size_1k) 1848 brcmnand_set_sector_size_1k(host, 1849 host->hwcfg.sector_size_1k); 1850 } 1851 1852 /* Re-enable protection is necessary only after erase */ 1853 if (command == NAND_CMD_ERASE1) 1854 brcmnand_wp(mtd, 1); 1855 } 1856 1857 static uint8_t brcmnand_read_byte(struct nand_chip *chip) 1858 { 1859 struct brcmnand_host *host = nand_get_controller_data(chip); 1860 struct brcmnand_controller *ctrl = host->ctrl; 1861 uint8_t ret = 0; 1862 int addr, offs; 1863 1864 switch (host->last_cmd) { 1865 case NAND_CMD_READID: 1866 if (host->last_byte < 4) 1867 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> 1868 (24 - (host->last_byte << 3)); 1869 else if (host->last_byte < 8) 1870 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> 1871 (56 - (host->last_byte << 3)); 1872 break; 1873 1874 case NAND_CMD_READOOB: 1875 ret = oob_reg_read(ctrl, host->last_byte); 1876 break; 1877 1878 case NAND_CMD_STATUS: 1879 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1880 INTFC_FLASH_STATUS; 1881 if (wp_on) /* hide WP status */ 1882 ret |= NAND_STATUS_WP; 1883 break; 1884 1885 case NAND_CMD_PARAM: 1886 case NAND_CMD_RNDOUT: 1887 addr = host->last_addr + host->last_byte; 1888 offs = addr & (FC_BYTES - 1); 1889 1890 /* At FC_BYTES boundary, switch to next column */ 1891 if (host->last_byte > 0 && offs == 0) 1892 nand_change_read_column_op(chip, addr, NULL, 0, false); 1893 1894 ret = ctrl->flash_cache[offs]; 1895 break; 1896 case NAND_CMD_GET_FEATURES: 1897 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { 1898 ret = 0; 1899 } else { 1900 bool last = host->last_byte == 1901 ONFI_SUBFEATURE_PARAM_LEN - 1; 1902 brcmnand_low_level_op(host, LL_OP_RD, 0, last); 1903 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; 1904 } 1905 } 1906 1907 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); 1908 host->last_byte++; 1909 1910 return ret; 1911 } 1912 1913 static void brcmnand_read_buf(struct nand_chip *chip, uint8_t *buf, int len) 1914 { 1915 int i; 1916 1917 for (i = 0; i < len; i++, buf++) 1918 *buf = brcmnand_read_byte(chip); 1919 } 1920 1921 static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf, 1922 int len) 1923 { 1924 int i; 1925 struct brcmnand_host *host = nand_get_controller_data(chip); 1926 1927 switch (host->last_cmd) { 1928 case NAND_CMD_SET_FEATURES: 1929 for (i = 0; i < len; i++) 1930 brcmnand_low_level_op(host, LL_OP_WR, buf[i], 1931 (i + 1) == len); 1932 break; 1933 default: 1934 BUG(); 1935 break; 1936 } 1937 } 1938 1939 /* 1940 * Kick EDU engine 1941 */ 1942 static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 1943 u8 *oob, u32 len, u8 cmd) 1944 { 1945 struct brcmnand_controller *ctrl = host->ctrl; 1946 struct brcmnand_cfg *cfg = &host->hwcfg; 1947 unsigned long timeo = msecs_to_jiffies(200); 1948 int ret = 0; 1949 int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 1950 u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE); 1951 unsigned int trans = len >> FC_SHIFT; 1952 dma_addr_t pa; 1953 1954 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? 1955 "read" : "write"), buf, oob); 1956 1957 pa = dma_map_single(ctrl->dev, buf, len, dir); 1958 if (dma_mapping_error(ctrl->dev, pa)) { 1959 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); 1960 return -ENOMEM; 1961 } 1962 1963 ctrl->edu_pending = true; 1964 ctrl->edu_dram_addr = pa; 1965 ctrl->edu_ext_addr = addr; 1966 ctrl->edu_cmd = edu_cmd; 1967 ctrl->edu_count = trans; 1968 ctrl->sas = cfg->spare_area_size; 1969 ctrl->oob = oob; 1970 1971 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); 1972 edu_readl(ctrl, EDU_DRAM_ADDR); 1973 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); 1974 edu_readl(ctrl, EDU_EXT_ADDR); 1975 edu_writel(ctrl, EDU_LENGTH, FC_BYTES); 1976 edu_readl(ctrl, EDU_LENGTH); 1977 1978 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { 1979 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 1980 ctrl->edu_ext_addr); 1981 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1982 ctrl->oob += write_oob_to_regs(ctrl, 1983 1, 1984 ctrl->oob, ctrl->sas, 1985 ctrl->sector_size_1k); 1986 } 1987 1988 /* Start edu engine */ 1989 mb(); /* flush previous writes */ 1990 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); 1991 edu_readl(ctrl, EDU_CMD); 1992 1993 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { 1994 dev_err(ctrl->dev, 1995 "timeout waiting for EDU; status %#x, error status %#x\n", 1996 edu_readl(ctrl, EDU_STATUS), 1997 edu_readl(ctrl, EDU_ERR_STATUS)); 1998 } 1999 2000 dma_unmap_single(ctrl->dev, pa, len, dir); 2001 2002 /* read last subpage oob */ 2003 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { 2004 ctrl->oob += read_oob_from_regs(ctrl, 2005 1, 2006 ctrl->oob, ctrl->sas, 2007 ctrl->sector_size_1k); 2008 } 2009 2010 /* for program page check NAND status */ 2011 if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 2012 INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) && 2013 edu_cmd == EDU_CMD_WRITE) { 2014 dev_info(ctrl->dev, "program failed at %llx\n", 2015 (unsigned long long)addr); 2016 ret = -EIO; 2017 } 2018 2019 /* Make sure the EDU status is clean */ 2020 if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE) 2021 dev_warn(ctrl->dev, "EDU still active: %#x\n", 2022 edu_readl(ctrl, EDU_STATUS)); 2023 2024 if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) { 2025 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", 2026 (unsigned long long)addr); 2027 ret = -EIO; 2028 } 2029 2030 ctrl->edu_pending = false; 2031 brcmnand_edu_init(ctrl); 2032 edu_writel(ctrl, EDU_STOP, 0); /* force stop */ 2033 edu_readl(ctrl, EDU_STOP); 2034 2035 if (!ret && edu_cmd == EDU_CMD_READ) { 2036 u64 err_addr = 0; 2037 2038 /* 2039 * check for ECC errors here, subpage ECC errors are 2040 * retained in ECC error address register 2041 */ 2042 err_addr = brcmnand_get_uncorrecc_addr(ctrl); 2043 if (!err_addr) { 2044 err_addr = brcmnand_get_correcc_addr(ctrl); 2045 if (err_addr) 2046 ret = -EUCLEAN; 2047 } else 2048 ret = -EBADMSG; 2049 } 2050 2051 return ret; 2052 } 2053 2054 /* 2055 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 2056 * following ahead of time: 2057 * - Is this descriptor the beginning or end of a linked list? 2058 * - What is the (DMA) address of the next descriptor in the linked list? 2059 */ 2060 static int brcmnand_fill_dma_desc(struct brcmnand_host *host, 2061 struct brcm_nand_dma_desc *desc, u64 addr, 2062 dma_addr_t buf, u32 len, u8 dma_cmd, 2063 bool begin, bool end, 2064 dma_addr_t next_desc) 2065 { 2066 memset(desc, 0, sizeof(*desc)); 2067 /* Descriptors are written in native byte order (wordwise) */ 2068 desc->next_desc = lower_32_bits(next_desc); 2069 desc->next_desc_ext = upper_32_bits(next_desc); 2070 desc->cmd_irq = (dma_cmd << 24) | 2071 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ 2072 (!!begin) | ((!!end) << 1); /* head, tail */ 2073 #ifdef CONFIG_CPU_BIG_ENDIAN 2074 desc->cmd_irq |= 0x01 << 12; 2075 #endif 2076 desc->dram_addr = lower_32_bits(buf); 2077 desc->dram_addr_ext = upper_32_bits(buf); 2078 desc->tfr_len = len; 2079 desc->total_len = len; 2080 desc->flash_addr = lower_32_bits(addr); 2081 desc->flash_addr_ext = upper_32_bits(addr); 2082 desc->cs = host->cs; 2083 desc->status_valid = 0x01; 2084 return 0; 2085 } 2086 2087 /* 2088 * Kick the FLASH_DMA engine, with a given DMA descriptor 2089 */ 2090 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) 2091 { 2092 struct brcmnand_controller *ctrl = host->ctrl; 2093 unsigned long timeo = msecs_to_jiffies(100); 2094 2095 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); 2096 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); 2097 if (ctrl->nand_version > 0x0602) { 2098 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, 2099 upper_32_bits(desc)); 2100 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); 2101 } 2102 2103 /* Start FLASH_DMA engine */ 2104 ctrl->dma_pending = true; 2105 mb(); /* flush previous writes */ 2106 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ 2107 2108 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { 2109 dev_err(ctrl->dev, 2110 "timeout waiting for DMA; status %#x, error status %#x\n", 2111 flash_dma_readl(ctrl, FLASH_DMA_STATUS), 2112 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); 2113 } 2114 ctrl->dma_pending = false; 2115 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ 2116 } 2117 2118 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 2119 u8 *oob, u32 len, u8 dma_cmd) 2120 { 2121 struct brcmnand_controller *ctrl = host->ctrl; 2122 dma_addr_t buf_pa; 2123 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2124 2125 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); 2126 if (dma_mapping_error(ctrl->dev, buf_pa)) { 2127 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); 2128 return -ENOMEM; 2129 } 2130 2131 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, 2132 dma_cmd, true, true, 0); 2133 2134 brcmnand_dma_run(host, ctrl->dma_pa); 2135 2136 dma_unmap_single(ctrl->dev, buf_pa, len, dir); 2137 2138 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) 2139 return -EBADMSG; 2140 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) 2141 return -EUCLEAN; 2142 2143 return 0; 2144 } 2145 2146 /* 2147 * Assumes proper CS is already set 2148 */ 2149 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 2150 u64 addr, unsigned int trans, u32 *buf, 2151 u8 *oob, u64 *err_addr) 2152 { 2153 struct brcmnand_host *host = nand_get_controller_data(chip); 2154 struct brcmnand_controller *ctrl = host->ctrl; 2155 int i, j, ret = 0; 2156 2157 brcmnand_clear_ecc_addr(ctrl); 2158 2159 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2160 brcmnand_set_cmd_addr(mtd, addr); 2161 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ 2162 brcmnand_send_cmd(host, CMD_PAGE_READ); 2163 brcmnand_waitfunc(chip); 2164 2165 if (likely(buf)) { 2166 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2167 2168 for (j = 0; j < FC_WORDS; j++, buf++) 2169 *buf = brcmnand_read_fc(ctrl, j); 2170 2171 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2172 } 2173 2174 if (oob) 2175 oob += read_oob_from_regs(ctrl, i, oob, 2176 mtd->oobsize / trans, 2177 host->hwcfg.sector_size_1k); 2178 2179 if (ret != -EBADMSG) { 2180 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); 2181 2182 if (*err_addr) 2183 ret = -EBADMSG; 2184 } 2185 2186 if (!ret) { 2187 *err_addr = brcmnand_get_correcc_addr(ctrl); 2188 2189 if (*err_addr) 2190 ret = -EUCLEAN; 2191 } 2192 } 2193 2194 return ret; 2195 } 2196 2197 /* 2198 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC 2199 * error 2200 * 2201 * Because the HW ECC signals an ECC error if an erase paged has even a single 2202 * bitflip, we must check each ECC error to see if it is actually an erased 2203 * page with bitflips, not a truly corrupted page. 2204 * 2205 * On a real error, return a negative error code (-EBADMSG for ECC error), and 2206 * buf will contain raw data. 2207 * Otherwise, buf gets filled with 0xffs and return the maximum number of 2208 * bitflips-per-ECC-sector to the caller. 2209 * 2210 */ 2211 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, 2212 struct nand_chip *chip, void *buf, u64 addr) 2213 { 2214 struct mtd_oob_region ecc; 2215 int i; 2216 int bitflips = 0; 2217 int page = addr >> chip->page_shift; 2218 int ret; 2219 void *ecc_bytes; 2220 void *ecc_chunk; 2221 2222 if (!buf) 2223 buf = nand_get_data_buf(chip); 2224 2225 /* read without ecc for verification */ 2226 ret = chip->ecc.read_page_raw(chip, buf, true, page); 2227 if (ret) 2228 return ret; 2229 2230 for (i = 0; i < chip->ecc.steps; i++) { 2231 ecc_chunk = buf + chip->ecc.size * i; 2232 2233 mtd_ooblayout_ecc(mtd, i, &ecc); 2234 ecc_bytes = chip->oob_poi + ecc.offset; 2235 2236 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, 2237 ecc_bytes, ecc.length, 2238 NULL, 0, 2239 chip->ecc.strength); 2240 if (ret < 0) 2241 return ret; 2242 2243 bitflips = max(bitflips, ret); 2244 } 2245 2246 return bitflips; 2247 } 2248 2249 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, 2250 u64 addr, unsigned int trans, u32 *buf, u8 *oob) 2251 { 2252 struct brcmnand_host *host = nand_get_controller_data(chip); 2253 struct brcmnand_controller *ctrl = host->ctrl; 2254 u64 err_addr = 0; 2255 int err; 2256 bool retry = true; 2257 bool edu_err = false; 2258 2259 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); 2260 2261 try_dmaread: 2262 brcmnand_clear_ecc_addr(ctrl); 2263 2264 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && 2265 flash_dma_buf_ok(buf)) { 2266 err = ctrl->dma_trans(host, addr, buf, oob, 2267 trans * FC_BYTES, 2268 CMD_PAGE_READ); 2269 2270 if (err) { 2271 if (mtd_is_bitflip_or_eccerr(err)) 2272 err_addr = addr; 2273 else 2274 return -EIO; 2275 } 2276 2277 if (has_edu(ctrl) && err_addr) 2278 edu_err = true; 2279 2280 } else { 2281 if (oob) 2282 memset(oob, 0x99, mtd->oobsize); 2283 2284 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2285 oob, &err_addr); 2286 } 2287 2288 if (mtd_is_eccerr(err)) { 2289 /* 2290 * On controller version and 7.0, 7.1 , DMA read after a 2291 * prior PIO read that reported uncorrectable error, 2292 * the DMA engine captures this error following DMA read 2293 * cleared only on subsequent DMA read, so just retry once 2294 * to clear a possible false error reported for current DMA 2295 * read 2296 */ 2297 if ((ctrl->nand_version == 0x0700) || 2298 (ctrl->nand_version == 0x0701)) { 2299 if (retry) { 2300 retry = false; 2301 goto try_dmaread; 2302 } 2303 } 2304 2305 /* 2306 * Controller version 7.2 has hw encoder to detect erased page 2307 * bitflips, apply sw verification for older controllers only 2308 */ 2309 if (ctrl->nand_version < 0x0702) { 2310 err = brcmstb_nand_verify_erased_page(mtd, chip, buf, 2311 addr); 2312 /* erased page bitflips corrected */ 2313 if (err >= 0) 2314 return err; 2315 } 2316 2317 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", 2318 (unsigned long long)err_addr); 2319 mtd->ecc_stats.failed++; 2320 /* NAND layer expects zero on ECC errors */ 2321 return 0; 2322 } 2323 2324 if (mtd_is_bitflip(err)) { 2325 unsigned int corrected = brcmnand_count_corrected(ctrl); 2326 2327 /* in case of EDU correctable error we read again using PIO */ 2328 if (edu_err) 2329 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 2330 oob, &err_addr); 2331 2332 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", 2333 (unsigned long long)err_addr); 2334 mtd->ecc_stats.corrected += corrected; 2335 /* Always exceed the software-imposed threshold */ 2336 return max(mtd->bitflip_threshold, corrected); 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf, 2343 int oob_required, int page) 2344 { 2345 struct mtd_info *mtd = nand_to_mtd(chip); 2346 struct brcmnand_host *host = nand_get_controller_data(chip); 2347 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2348 2349 nand_read_page_op(chip, page, 0, NULL, 0); 2350 2351 return brcmnand_read(mtd, chip, host->last_addr, 2352 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 2353 } 2354 2355 static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf, 2356 int oob_required, int page) 2357 { 2358 struct brcmnand_host *host = nand_get_controller_data(chip); 2359 struct mtd_info *mtd = nand_to_mtd(chip); 2360 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 2361 int ret; 2362 2363 nand_read_page_op(chip, page, 0, NULL, 0); 2364 2365 brcmnand_set_ecc_enabled(host, 0); 2366 ret = brcmnand_read(mtd, chip, host->last_addr, 2367 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 2368 brcmnand_set_ecc_enabled(host, 1); 2369 return ret; 2370 } 2371 2372 static int brcmnand_read_oob(struct nand_chip *chip, int page) 2373 { 2374 struct mtd_info *mtd = nand_to_mtd(chip); 2375 2376 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2377 mtd->writesize >> FC_SHIFT, 2378 NULL, (u8 *)chip->oob_poi); 2379 } 2380 2381 static int brcmnand_read_oob_raw(struct nand_chip *chip, int page) 2382 { 2383 struct mtd_info *mtd = nand_to_mtd(chip); 2384 struct brcmnand_host *host = nand_get_controller_data(chip); 2385 2386 brcmnand_set_ecc_enabled(host, 0); 2387 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2388 mtd->writesize >> FC_SHIFT, 2389 NULL, (u8 *)chip->oob_poi); 2390 brcmnand_set_ecc_enabled(host, 1); 2391 return 0; 2392 } 2393 2394 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 2395 u64 addr, const u32 *buf, u8 *oob) 2396 { 2397 struct brcmnand_host *host = nand_get_controller_data(chip); 2398 struct brcmnand_controller *ctrl = host->ctrl; 2399 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; 2400 int status, ret = 0; 2401 2402 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); 2403 2404 if (unlikely((unsigned long)buf & 0x03)) { 2405 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); 2406 buf = (u32 *)((unsigned long)buf & ~0x03); 2407 } 2408 2409 brcmnand_wp(mtd, 0); 2410 2411 for (i = 0; i < ctrl->max_oob; i += 4) 2412 oob_reg_write(ctrl, i, 0xffffffff); 2413 2414 if (mtd->oops_panic_write) 2415 /* switch to interrupt polling and PIO mode */ 2416 disable_ctrl_irqs(ctrl); 2417 2418 if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) { 2419 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, 2420 CMD_PROGRAM_PAGE)) 2421 2422 ret = -EIO; 2423 2424 goto out; 2425 } 2426 2427 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2428 /* full address MUST be set before populating FC */ 2429 brcmnand_set_cmd_addr(mtd, addr); 2430 2431 if (buf) { 2432 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2433 2434 for (j = 0; j < FC_WORDS; j++, buf++) 2435 brcmnand_write_fc(ctrl, j, *buf); 2436 2437 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2438 } else if (oob) { 2439 for (j = 0; j < FC_WORDS; j++) 2440 brcmnand_write_fc(ctrl, j, 0xffffffff); 2441 } 2442 2443 if (oob) { 2444 oob += write_oob_to_regs(ctrl, i, oob, 2445 mtd->oobsize / trans, 2446 host->hwcfg.sector_size_1k); 2447 } 2448 2449 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ 2450 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); 2451 status = brcmnand_waitfunc(chip); 2452 2453 if (status & NAND_STATUS_FAIL) { 2454 dev_info(ctrl->dev, "program failed at %llx\n", 2455 (unsigned long long)addr); 2456 ret = -EIO; 2457 goto out; 2458 } 2459 } 2460 out: 2461 brcmnand_wp(mtd, 1); 2462 return ret; 2463 } 2464 2465 static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf, 2466 int oob_required, int page) 2467 { 2468 struct mtd_info *mtd = nand_to_mtd(chip); 2469 struct brcmnand_host *host = nand_get_controller_data(chip); 2470 void *oob = oob_required ? chip->oob_poi : NULL; 2471 2472 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2473 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2474 2475 return nand_prog_page_end_op(chip); 2476 } 2477 2478 static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 2479 int oob_required, int page) 2480 { 2481 struct mtd_info *mtd = nand_to_mtd(chip); 2482 struct brcmnand_host *host = nand_get_controller_data(chip); 2483 void *oob = oob_required ? chip->oob_poi : NULL; 2484 2485 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2486 brcmnand_set_ecc_enabled(host, 0); 2487 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2488 brcmnand_set_ecc_enabled(host, 1); 2489 2490 return nand_prog_page_end_op(chip); 2491 } 2492 2493 static int brcmnand_write_oob(struct nand_chip *chip, int page) 2494 { 2495 return brcmnand_write(nand_to_mtd(chip), chip, 2496 (u64)page << chip->page_shift, NULL, 2497 chip->oob_poi); 2498 } 2499 2500 static int brcmnand_write_oob_raw(struct nand_chip *chip, int page) 2501 { 2502 struct mtd_info *mtd = nand_to_mtd(chip); 2503 struct brcmnand_host *host = nand_get_controller_data(chip); 2504 int ret; 2505 2506 brcmnand_set_ecc_enabled(host, 0); 2507 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, 2508 (u8 *)chip->oob_poi); 2509 brcmnand_set_ecc_enabled(host, 1); 2510 2511 return ret; 2512 } 2513 2514 /*********************************************************************** 2515 * Per-CS setup (1 NAND device) 2516 ***********************************************************************/ 2517 2518 static int brcmnand_set_cfg(struct brcmnand_host *host, 2519 struct brcmnand_cfg *cfg) 2520 { 2521 struct brcmnand_controller *ctrl = host->ctrl; 2522 struct nand_chip *chip = &host->chip; 2523 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2524 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2525 BRCMNAND_CS_CFG_EXT); 2526 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2527 BRCMNAND_CS_ACC_CONTROL); 2528 u8 block_size = 0, page_size = 0, device_size = 0; 2529 u32 tmp; 2530 2531 if (ctrl->block_sizes) { 2532 int i, found; 2533 2534 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) 2535 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { 2536 block_size = i; 2537 found = 1; 2538 } 2539 if (!found) { 2540 dev_warn(ctrl->dev, "invalid block size %u\n", 2541 cfg->block_size); 2542 return -EINVAL; 2543 } 2544 } else { 2545 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); 2546 } 2547 2548 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && 2549 cfg->block_size > ctrl->max_block_size)) { 2550 dev_warn(ctrl->dev, "invalid block size %u\n", 2551 cfg->block_size); 2552 block_size = 0; 2553 } 2554 2555 if (ctrl->page_sizes) { 2556 int i, found; 2557 2558 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) 2559 if (ctrl->page_sizes[i] == cfg->page_size) { 2560 page_size = i; 2561 found = 1; 2562 } 2563 if (!found) { 2564 dev_warn(ctrl->dev, "invalid page size %u\n", 2565 cfg->page_size); 2566 return -EINVAL; 2567 } 2568 } else { 2569 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); 2570 } 2571 2572 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && 2573 cfg->page_size > ctrl->max_page_size)) { 2574 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); 2575 return -EINVAL; 2576 } 2577 2578 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { 2579 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", 2580 (unsigned long long)cfg->device_size); 2581 return -EINVAL; 2582 } 2583 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); 2584 2585 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | 2586 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | 2587 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | 2588 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | 2589 (device_size << CFG_DEVICE_SIZE_SHIFT); 2590 if (cfg_offs == cfg_ext_offs) { 2591 tmp |= (page_size << ctrl->page_size_shift) | 2592 (block_size << CFG_BLK_SIZE_SHIFT); 2593 nand_writereg(ctrl, cfg_offs, tmp); 2594 } else { 2595 nand_writereg(ctrl, cfg_offs, tmp); 2596 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | 2597 (block_size << CFG_EXT_BLK_SIZE_SHIFT); 2598 nand_writereg(ctrl, cfg_ext_offs, tmp); 2599 } 2600 2601 tmp = nand_readreg(ctrl, acc_control_offs); 2602 tmp &= ~brcmnand_ecc_level_mask(ctrl); 2603 tmp &= ~brcmnand_spare_area_mask(ctrl); 2604 if (ctrl->nand_version >= 0x0302) { 2605 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; 2606 tmp |= cfg->spare_area_size; 2607 } 2608 nand_writereg(ctrl, acc_control_offs, tmp); 2609 2610 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); 2611 2612 /* threshold = ceil(BCH-level * 0.75) */ 2613 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); 2614 2615 return 0; 2616 } 2617 2618 static void brcmnand_print_cfg(struct brcmnand_host *host, 2619 char *buf, struct brcmnand_cfg *cfg) 2620 { 2621 buf += sprintf(buf, 2622 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", 2623 (unsigned long long)cfg->device_size >> 20, 2624 cfg->block_size >> 10, 2625 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, 2626 cfg->page_size >= 1024 ? "KiB" : "B", 2627 cfg->spare_area_size, cfg->device_width); 2628 2629 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ 2630 if (is_hamming_ecc(host->ctrl, cfg)) 2631 sprintf(buf, ", Hamming ECC"); 2632 else if (cfg->sector_size_1k) 2633 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); 2634 else 2635 sprintf(buf, ", BCH-%u", cfg->ecc_level); 2636 } 2637 2638 /* 2639 * Minimum number of bytes to address a page. Calculated as: 2640 * roundup(log2(size / page-size) / 8) 2641 * 2642 * NB: the following does not "round up" for non-power-of-2 'size'; but this is 2643 * OK because many other things will break if 'size' is irregular... 2644 */ 2645 static inline int get_blk_adr_bytes(u64 size, u32 writesize) 2646 { 2647 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; 2648 } 2649 2650 static int brcmnand_setup_dev(struct brcmnand_host *host) 2651 { 2652 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2653 struct nand_chip *chip = &host->chip; 2654 const struct nand_ecc_props *requirements = 2655 nanddev_get_ecc_requirements(&chip->base); 2656 struct nand_memory_organization *memorg = 2657 nanddev_get_memorg(&chip->base); 2658 struct brcmnand_controller *ctrl = host->ctrl; 2659 struct brcmnand_cfg *cfg = &host->hwcfg; 2660 char msg[128]; 2661 u32 offs, tmp, oob_sector; 2662 int ret; 2663 2664 memset(cfg, 0, sizeof(*cfg)); 2665 2666 ret = of_property_read_u32(nand_get_flash_node(chip), 2667 "brcm,nand-oob-sector-size", 2668 &oob_sector); 2669 if (ret) { 2670 /* Use detected size */ 2671 cfg->spare_area_size = mtd->oobsize / 2672 (mtd->writesize >> FC_SHIFT); 2673 } else { 2674 cfg->spare_area_size = oob_sector; 2675 } 2676 if (cfg->spare_area_size > ctrl->max_oob) 2677 cfg->spare_area_size = ctrl->max_oob; 2678 /* 2679 * Set mtd and memorg oobsize to be consistent with controller's 2680 * spare_area_size, as the rest is inaccessible. 2681 */ 2682 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); 2683 memorg->oobsize = mtd->oobsize; 2684 2685 cfg->device_size = mtd->size; 2686 cfg->block_size = mtd->erasesize; 2687 cfg->page_size = mtd->writesize; 2688 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; 2689 cfg->col_adr_bytes = 2; 2690 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 2691 2692 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 2693 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 2694 chip->ecc.engine_type); 2695 return -EINVAL; 2696 } 2697 2698 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { 2699 if (chip->ecc.strength == 1 && chip->ecc.size == 512) 2700 /* Default to Hamming for 1-bit ECC, if unspecified */ 2701 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2702 else 2703 /* Otherwise, BCH */ 2704 chip->ecc.algo = NAND_ECC_ALGO_BCH; 2705 } 2706 2707 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && 2708 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { 2709 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 2710 chip->ecc.strength, chip->ecc.size); 2711 return -EINVAL; 2712 } 2713 2714 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2715 (!chip->ecc.size || !chip->ecc.strength)) { 2716 if (requirements->step_size && requirements->strength) { 2717 /* use detected ECC parameters */ 2718 chip->ecc.size = requirements->step_size; 2719 chip->ecc.strength = requirements->strength; 2720 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", 2721 chip->ecc.size, chip->ecc.strength); 2722 } 2723 } 2724 2725 switch (chip->ecc.size) { 2726 case 512: 2727 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 2728 cfg->ecc_level = 15; 2729 else 2730 cfg->ecc_level = chip->ecc.strength; 2731 cfg->sector_size_1k = 0; 2732 break; 2733 case 1024: 2734 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { 2735 dev_err(ctrl->dev, "1KB sectors not supported\n"); 2736 return -EINVAL; 2737 } 2738 if (chip->ecc.strength & 0x1) { 2739 dev_err(ctrl->dev, 2740 "odd ECC not supported with 1KB sectors\n"); 2741 return -EINVAL; 2742 } 2743 2744 cfg->ecc_level = chip->ecc.strength >> 1; 2745 cfg->sector_size_1k = 1; 2746 break; 2747 default: 2748 dev_err(ctrl->dev, "unsupported ECC size: %d\n", 2749 chip->ecc.size); 2750 return -EINVAL; 2751 } 2752 2753 cfg->ful_adr_bytes = cfg->blk_adr_bytes; 2754 if (mtd->writesize > 512) 2755 cfg->ful_adr_bytes += cfg->col_adr_bytes; 2756 else 2757 cfg->ful_adr_bytes += 1; 2758 2759 ret = brcmnand_set_cfg(host, cfg); 2760 if (ret) 2761 return ret; 2762 2763 brcmnand_set_ecc_enabled(host, 1); 2764 2765 brcmnand_print_cfg(host, msg, cfg); 2766 dev_info(ctrl->dev, "detected %s\n", msg); 2767 2768 /* Configure ACC_CONTROL */ 2769 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 2770 tmp = nand_readreg(ctrl, offs); 2771 tmp &= ~ACC_CONTROL_PARTIAL_PAGE; 2772 tmp &= ~ACC_CONTROL_RD_ERASED; 2773 2774 /* We need to turn on Read from erased paged protected by ECC */ 2775 if (ctrl->nand_version >= 0x0702) 2776 tmp |= ACC_CONTROL_RD_ERASED; 2777 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; 2778 if (ctrl->features & BRCMNAND_HAS_PREFETCH) 2779 tmp &= ~ACC_CONTROL_PREFETCH; 2780 2781 nand_writereg(ctrl, offs, tmp); 2782 2783 return 0; 2784 } 2785 2786 static int brcmnand_attach_chip(struct nand_chip *chip) 2787 { 2788 struct mtd_info *mtd = nand_to_mtd(chip); 2789 struct brcmnand_host *host = nand_get_controller_data(chip); 2790 int ret; 2791 2792 chip->options |= NAND_NO_SUBPAGE_WRITE; 2793 /* 2794 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA 2795 * to/from, and have nand_base pass us a bounce buffer instead, as 2796 * needed. 2797 */ 2798 chip->options |= NAND_USES_DMA; 2799 2800 if (chip->bbt_options & NAND_BBT_USE_FLASH) 2801 chip->bbt_options |= NAND_BBT_NO_OOB; 2802 2803 if (brcmnand_setup_dev(host)) 2804 return -ENXIO; 2805 2806 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; 2807 2808 /* only use our internal HW threshold */ 2809 mtd->bitflip_threshold = 1; 2810 2811 ret = brcmstb_choose_ecc_layout(host); 2812 2813 /* If OOB is written with ECC enabled it will cause ECC errors */ 2814 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { 2815 chip->ecc.write_oob = brcmnand_write_oob_raw; 2816 chip->ecc.read_oob = brcmnand_read_oob_raw; 2817 } 2818 2819 return ret; 2820 } 2821 2822 static const struct nand_controller_ops brcmnand_controller_ops = { 2823 .attach_chip = brcmnand_attach_chip, 2824 }; 2825 2826 static int brcmnand_init_cs(struct brcmnand_host *host, 2827 const char * const *part_probe_types) 2828 { 2829 struct brcmnand_controller *ctrl = host->ctrl; 2830 struct device *dev = ctrl->dev; 2831 struct mtd_info *mtd; 2832 struct nand_chip *chip; 2833 int ret; 2834 u16 cfg_offs; 2835 2836 mtd = nand_to_mtd(&host->chip); 2837 chip = &host->chip; 2838 2839 nand_set_controller_data(chip, host); 2840 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", 2841 host->cs); 2842 if (!mtd->name) 2843 return -ENOMEM; 2844 2845 mtd->owner = THIS_MODULE; 2846 mtd->dev.parent = dev; 2847 2848 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; 2849 chip->legacy.cmdfunc = brcmnand_cmdfunc; 2850 chip->legacy.waitfunc = brcmnand_waitfunc; 2851 chip->legacy.read_byte = brcmnand_read_byte; 2852 chip->legacy.read_buf = brcmnand_read_buf; 2853 chip->legacy.write_buf = brcmnand_write_buf; 2854 2855 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2856 chip->ecc.read_page = brcmnand_read_page; 2857 chip->ecc.write_page = brcmnand_write_page; 2858 chip->ecc.read_page_raw = brcmnand_read_page_raw; 2859 chip->ecc.write_page_raw = brcmnand_write_page_raw; 2860 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; 2861 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; 2862 chip->ecc.read_oob = brcmnand_read_oob; 2863 chip->ecc.write_oob = brcmnand_write_oob; 2864 2865 chip->controller = &ctrl->controller; 2866 2867 /* 2868 * The bootloader might have configured 16bit mode but 2869 * NAND READID command only works in 8bit mode. We force 2870 * 8bit mode here to ensure that NAND READID commands works. 2871 */ 2872 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2873 nand_writereg(ctrl, cfg_offs, 2874 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); 2875 2876 ret = nand_scan(chip, 1); 2877 if (ret) 2878 return ret; 2879 2880 ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); 2881 if (ret) 2882 nand_cleanup(chip); 2883 2884 return ret; 2885 } 2886 2887 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, 2888 int restore) 2889 { 2890 struct brcmnand_controller *ctrl = host->ctrl; 2891 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2892 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2893 BRCMNAND_CS_CFG_EXT); 2894 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2895 BRCMNAND_CS_ACC_CONTROL); 2896 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); 2897 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); 2898 2899 if (restore) { 2900 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); 2901 if (cfg_offs != cfg_ext_offs) 2902 nand_writereg(ctrl, cfg_ext_offs, 2903 host->hwcfg.config_ext); 2904 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); 2905 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); 2906 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); 2907 } else { 2908 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); 2909 if (cfg_offs != cfg_ext_offs) 2910 host->hwcfg.config_ext = 2911 nand_readreg(ctrl, cfg_ext_offs); 2912 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); 2913 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); 2914 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); 2915 } 2916 } 2917 2918 static int brcmnand_suspend(struct device *dev) 2919 { 2920 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2921 struct brcmnand_host *host; 2922 2923 list_for_each_entry(host, &ctrl->host_list, node) 2924 brcmnand_save_restore_cs_config(host, 0); 2925 2926 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); 2927 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); 2928 ctrl->corr_stat_threshold = 2929 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); 2930 2931 if (has_flash_dma(ctrl)) 2932 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 2933 else if (has_edu(ctrl)) 2934 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2935 2936 return 0; 2937 } 2938 2939 static int brcmnand_resume(struct device *dev) 2940 { 2941 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2942 struct brcmnand_host *host; 2943 2944 if (has_flash_dma(ctrl)) { 2945 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 2946 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 2947 } 2948 2949 if (has_edu(ctrl)) { 2950 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); 2951 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); 2952 edu_readl(ctrl, EDU_CONFIG); 2953 brcmnand_edu_init(ctrl); 2954 } 2955 2956 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); 2957 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); 2958 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, 2959 ctrl->corr_stat_threshold); 2960 if (ctrl->soc) { 2961 /* Clear/re-enable interrupt */ 2962 ctrl->soc->ctlrdy_ack(ctrl->soc); 2963 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 2964 } 2965 2966 list_for_each_entry(host, &ctrl->host_list, node) { 2967 struct nand_chip *chip = &host->chip; 2968 2969 brcmnand_save_restore_cs_config(host, 1); 2970 2971 /* Reset the chip, required by some chips after power-up */ 2972 nand_reset_op(chip); 2973 } 2974 2975 return 0; 2976 } 2977 2978 const struct dev_pm_ops brcmnand_pm_ops = { 2979 .suspend = brcmnand_suspend, 2980 .resume = brcmnand_resume, 2981 }; 2982 EXPORT_SYMBOL_GPL(brcmnand_pm_ops); 2983 2984 static const struct of_device_id __maybe_unused brcmnand_of_match[] = { 2985 { .compatible = "brcm,brcmnand-v2.1" }, 2986 { .compatible = "brcm,brcmnand-v2.2" }, 2987 { .compatible = "brcm,brcmnand-v4.0" }, 2988 { .compatible = "brcm,brcmnand-v5.0" }, 2989 { .compatible = "brcm,brcmnand-v6.0" }, 2990 { .compatible = "brcm,brcmnand-v6.1" }, 2991 { .compatible = "brcm,brcmnand-v6.2" }, 2992 { .compatible = "brcm,brcmnand-v7.0" }, 2993 { .compatible = "brcm,brcmnand-v7.1" }, 2994 { .compatible = "brcm,brcmnand-v7.2" }, 2995 { .compatible = "brcm,brcmnand-v7.3" }, 2996 {}, 2997 }; 2998 MODULE_DEVICE_TABLE(of, brcmnand_of_match); 2999 3000 /*********************************************************************** 3001 * Platform driver setup (per controller) 3002 ***********************************************************************/ 3003 static int brcmnand_edu_setup(struct platform_device *pdev) 3004 { 3005 struct device *dev = &pdev->dev; 3006 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 3007 struct resource *res; 3008 int ret; 3009 3010 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); 3011 if (res) { 3012 ctrl->edu_base = devm_ioremap_resource(dev, res); 3013 if (IS_ERR(ctrl->edu_base)) 3014 return PTR_ERR(ctrl->edu_base); 3015 3016 ctrl->edu_offsets = edu_regs; 3017 3018 edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND | 3019 EDU_CONFIG_SWAP_CFG); 3020 edu_readl(ctrl, EDU_CONFIG); 3021 3022 /* initialize edu */ 3023 brcmnand_edu_init(ctrl); 3024 3025 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); 3026 if (ctrl->edu_irq < 0) { 3027 dev_warn(dev, 3028 "FLASH EDU enabled, using ctlrdy irq\n"); 3029 } else { 3030 ret = devm_request_irq(dev, ctrl->edu_irq, 3031 brcmnand_edu_irq, 0, 3032 "brcmnand-edu", ctrl); 3033 if (ret < 0) { 3034 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", 3035 ctrl->edu_irq, ret); 3036 return ret; 3037 } 3038 3039 dev_info(dev, "FLASH EDU enabled using irq %u\n", 3040 ctrl->edu_irq); 3041 } 3042 } 3043 3044 return 0; 3045 } 3046 3047 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 3048 { 3049 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); 3050 struct device *dev = &pdev->dev; 3051 struct device_node *dn = dev->of_node, *child; 3052 struct brcmnand_controller *ctrl; 3053 struct brcmnand_host *host; 3054 struct resource *res; 3055 int ret; 3056 3057 if (dn && !of_match_node(brcmnand_of_match, dn)) 3058 return -ENODEV; 3059 3060 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 3061 if (!ctrl) 3062 return -ENOMEM; 3063 3064 dev_set_drvdata(dev, ctrl); 3065 ctrl->dev = dev; 3066 ctrl->soc = soc; 3067 3068 /* Enable the static key if the soc provides I/O operations indicating 3069 * that a non-memory mapped IO access path must be used 3070 */ 3071 if (brcmnand_soc_has_ops(ctrl->soc)) 3072 static_branch_enable(&brcmnand_soc_has_ops_key); 3073 3074 init_completion(&ctrl->done); 3075 init_completion(&ctrl->dma_done); 3076 init_completion(&ctrl->edu_done); 3077 nand_controller_init(&ctrl->controller); 3078 ctrl->controller.ops = &brcmnand_controller_ops; 3079 INIT_LIST_HEAD(&ctrl->host_list); 3080 3081 /* NAND register range */ 3082 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3083 ctrl->nand_base = devm_ioremap_resource(dev, res); 3084 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) 3085 return PTR_ERR(ctrl->nand_base); 3086 3087 /* Enable clock before using NAND registers */ 3088 ctrl->clk = devm_clk_get(dev, "nand"); 3089 if (!IS_ERR(ctrl->clk)) { 3090 ret = clk_prepare_enable(ctrl->clk); 3091 if (ret) 3092 return ret; 3093 } else { 3094 ret = PTR_ERR(ctrl->clk); 3095 if (ret == -EPROBE_DEFER) 3096 return ret; 3097 3098 ctrl->clk = NULL; 3099 } 3100 3101 /* Initialize NAND revision */ 3102 ret = brcmnand_revision_init(ctrl); 3103 if (ret) 3104 goto err; 3105 3106 /* 3107 * Most chips have this cache at a fixed offset within 'nand' block. 3108 * Some must specify this region separately. 3109 */ 3110 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); 3111 if (res) { 3112 ctrl->nand_fc = devm_ioremap_resource(dev, res); 3113 if (IS_ERR(ctrl->nand_fc)) { 3114 ret = PTR_ERR(ctrl->nand_fc); 3115 goto err; 3116 } 3117 } else { 3118 ctrl->nand_fc = ctrl->nand_base + 3119 ctrl->reg_offsets[BRCMNAND_FC_BASE]; 3120 } 3121 3122 /* FLASH_DMA */ 3123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); 3124 if (res) { 3125 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); 3126 if (IS_ERR(ctrl->flash_dma_base)) { 3127 ret = PTR_ERR(ctrl->flash_dma_base); 3128 goto err; 3129 } 3130 3131 /* initialize the dma version */ 3132 brcmnand_flash_dma_revision_init(ctrl); 3133 3134 ret = -EIO; 3135 if (ctrl->nand_version >= 0x0700) 3136 ret = dma_set_mask_and_coherent(&pdev->dev, 3137 DMA_BIT_MASK(40)); 3138 if (ret) 3139 ret = dma_set_mask_and_coherent(&pdev->dev, 3140 DMA_BIT_MASK(32)); 3141 if (ret) 3142 goto err; 3143 3144 /* linked-list and stop on error */ 3145 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); 3146 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 3147 3148 /* Allocate descriptor(s) */ 3149 ctrl->dma_desc = dmam_alloc_coherent(dev, 3150 sizeof(*ctrl->dma_desc), 3151 &ctrl->dma_pa, GFP_KERNEL); 3152 if (!ctrl->dma_desc) { 3153 ret = -ENOMEM; 3154 goto err; 3155 } 3156 3157 ctrl->dma_irq = platform_get_irq(pdev, 1); 3158 if ((int)ctrl->dma_irq < 0) { 3159 dev_err(dev, "missing FLASH_DMA IRQ\n"); 3160 ret = -ENODEV; 3161 goto err; 3162 } 3163 3164 ret = devm_request_irq(dev, ctrl->dma_irq, 3165 brcmnand_dma_irq, 0, DRV_NAME, 3166 ctrl); 3167 if (ret < 0) { 3168 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3169 ctrl->dma_irq, ret); 3170 goto err; 3171 } 3172 3173 dev_info(dev, "enabling FLASH_DMA\n"); 3174 /* set flash dma transfer function to call */ 3175 ctrl->dma_trans = brcmnand_dma_trans; 3176 } else { 3177 ret = brcmnand_edu_setup(pdev); 3178 if (ret < 0) 3179 goto err; 3180 3181 if (has_edu(ctrl)) 3182 /* set edu transfer function to call */ 3183 ctrl->dma_trans = brcmnand_edu_trans; 3184 } 3185 3186 /* Disable automatic device ID config, direct addressing */ 3187 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, 3188 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); 3189 /* Disable XOR addressing */ 3190 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); 3191 3192 if (ctrl->features & BRCMNAND_HAS_WP) { 3193 /* Permanently disable write protection */ 3194 if (wp_on == 2) 3195 brcmnand_set_wp(ctrl, false); 3196 } else { 3197 wp_on = 0; 3198 } 3199 3200 /* IRQ */ 3201 ctrl->irq = platform_get_irq_optional(pdev, 0); 3202 if (ctrl->irq > 0) { 3203 /* 3204 * Some SoCs integrate this controller (e.g., its interrupt bits) in 3205 * interesting ways 3206 */ 3207 if (soc) { 3208 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, 3209 DRV_NAME, ctrl); 3210 3211 /* Enable interrupt */ 3212 ctrl->soc->ctlrdy_ack(ctrl->soc); 3213 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 3214 } else { 3215 /* Use standard interrupt infrastructure */ 3216 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, 3217 DRV_NAME, ctrl); 3218 } 3219 if (ret < 0) { 3220 dev_err(dev, "can't allocate IRQ %d: error %d\n", 3221 ctrl->irq, ret); 3222 goto err; 3223 } 3224 } 3225 3226 for_each_available_child_of_node(dn, child) { 3227 if (of_device_is_compatible(child, "brcm,nandcs")) { 3228 3229 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 3230 if (!host) { 3231 of_node_put(child); 3232 ret = -ENOMEM; 3233 goto err; 3234 } 3235 host->pdev = pdev; 3236 host->ctrl = ctrl; 3237 3238 ret = of_property_read_u32(child, "reg", &host->cs); 3239 if (ret) { 3240 dev_err(dev, "can't get chip-select\n"); 3241 devm_kfree(dev, host); 3242 continue; 3243 } 3244 3245 nand_set_flash_node(&host->chip, child); 3246 3247 ret = brcmnand_init_cs(host, NULL); 3248 if (ret) { 3249 if (ret == -EPROBE_DEFER) { 3250 of_node_put(child); 3251 goto err; 3252 } 3253 devm_kfree(dev, host); 3254 continue; /* Try all chip-selects */ 3255 } 3256 3257 list_add_tail(&host->node, &ctrl->host_list); 3258 } 3259 } 3260 3261 if (!list_empty(&ctrl->host_list)) 3262 return 0; 3263 3264 if (!pd) { 3265 ret = -ENODEV; 3266 goto err; 3267 } 3268 3269 /* If we got there we must have been probing via platform data */ 3270 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 3271 if (!host) { 3272 ret = -ENOMEM; 3273 goto err; 3274 } 3275 host->pdev = pdev; 3276 host->ctrl = ctrl; 3277 host->cs = pd->chip_select; 3278 host->chip.ecc.size = pd->ecc_stepsize; 3279 host->chip.ecc.strength = pd->ecc_strength; 3280 3281 ret = brcmnand_init_cs(host, pd->part_probe_types); 3282 if (ret) 3283 goto err; 3284 3285 list_add_tail(&host->node, &ctrl->host_list); 3286 3287 /* No chip-selects could initialize properly */ 3288 if (list_empty(&ctrl->host_list)) { 3289 ret = -ENODEV; 3290 goto err; 3291 } 3292 3293 return 0; 3294 3295 err: 3296 clk_disable_unprepare(ctrl->clk); 3297 return ret; 3298 3299 } 3300 EXPORT_SYMBOL_GPL(brcmnand_probe); 3301 3302 int brcmnand_remove(struct platform_device *pdev) 3303 { 3304 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 3305 struct brcmnand_host *host; 3306 struct nand_chip *chip; 3307 int ret; 3308 3309 list_for_each_entry(host, &ctrl->host_list, node) { 3310 chip = &host->chip; 3311 ret = mtd_device_unregister(nand_to_mtd(chip)); 3312 WARN_ON(ret); 3313 nand_cleanup(chip); 3314 } 3315 3316 clk_disable_unprepare(ctrl->clk); 3317 3318 dev_set_drvdata(&pdev->dev, NULL); 3319 3320 return 0; 3321 } 3322 EXPORT_SYMBOL_GPL(brcmnand_remove); 3323 3324 MODULE_LICENSE("GPL v2"); 3325 MODULE_AUTHOR("Kevin Cernekee"); 3326 MODULE_AUTHOR("Brian Norris"); 3327 MODULE_DESCRIPTION("NAND driver for Broadcom chips"); 3328 MODULE_ALIAS("platform:brcmnand"); 3329