1config MTD_NAND_ECC_SW_HAMMING 2 tristate 3 4config MTD_NAND_ECC_SW_HAMMING_SMC 5 bool "NAND ECC Smart Media byte order" 6 depends on MTD_NAND_ECC_SW_HAMMING 7 default n 8 help 9 Software ECC according to the Smart Media Specification. 10 The original Linux implementation had byte 0 and 1 swapped. 11 12menuconfig MTD_RAW_NAND 13 tristate "Raw/Parallel NAND Device Support" 14 depends on MTD 15 select MTD_NAND_CORE 16 select MTD_NAND_ECC_SW_HAMMING 17 help 18 This enables support for accessing all type of raw/parallel 19 NAND flash devices. For further information see 20 <http://www.linux-mtd.infradead.org/doc/nand.html>. 21 22if MTD_RAW_NAND 23 24config MTD_NAND_ECC_SW_BCH 25 bool "Support software BCH ECC" 26 select BCH 27 default n 28 help 29 This enables support for software BCH error correction. Binary BCH 30 codes are more powerful and cpu intensive than traditional Hamming 31 ECC codes. They are used with NAND devices requiring more than 1 bit 32 of error correction. 33 34comment "Raw/parallel NAND flash controllers" 35 36config MTD_NAND_DENALI 37 tristate 38 39config MTD_NAND_DENALI_PCI 40 tristate "Denali NAND controller on Intel Moorestown" 41 select MTD_NAND_DENALI 42 depends on PCI 43 help 44 Enable the driver for NAND flash on Intel Moorestown, using the 45 Denali NAND controller core. 46 47config MTD_NAND_DENALI_DT 48 tristate "Denali NAND controller as a DT device" 49 select MTD_NAND_DENALI 50 depends on HAS_DMA && HAVE_CLK && OF 51 help 52 Enable the driver for NAND flash on platforms using a Denali NAND 53 controller as a DT device. 54 55config MTD_NAND_AMS_DELTA 56 tristate "Amstrad E3 NAND controller" 57 depends on MACH_AMS_DELTA || COMPILE_TEST 58 default y 59 help 60 Support for NAND flash on Amstrad E3 (Delta). 61 62config MTD_NAND_OMAP2 63 tristate "OMAP2, OMAP3, OMAP4 and Keystone NAND controller" 64 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || COMPILE_TEST 65 depends on HAS_IOMEM 66 help 67 Support for NAND flash on Texas Instruments OMAP2, OMAP3, OMAP4 68 and Keystone platforms. 69 70config MTD_NAND_OMAP_BCH 71 depends on MTD_NAND_OMAP2 72 bool "Support hardware based BCH error correction" 73 default n 74 select BCH 75 help 76 This config enables the ELM hardware engine, which can be used to 77 locate and correct errors when using BCH ECC scheme. This offloads 78 the cpu from doing ECC error searching and correction. However some 79 legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine 80 so this is optional for them. 81 82config MTD_NAND_OMAP_BCH_BUILD 83 def_tristate MTD_NAND_OMAP2 && MTD_NAND_OMAP_BCH 84 85config MTD_NAND_AU1550 86 tristate "Au1550/1200 NAND support" 87 depends on MIPS_ALCHEMY 88 help 89 This enables the driver for the NAND flash controller on the 90 AMD/Alchemy 1550 SOC. 91 92config MTD_NAND_NDFC 93 tristate "IBM/MCC 4xx NAND controller" 94 depends on 4xx 95 select MTD_NAND_ECC_SW_HAMMING_SMC 96 help 97 NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs 98 99config MTD_NAND_S3C2410 100 tristate "Samsung S3C NAND controller" 101 depends on ARCH_S3C24XX || ARCH_S3C64XX 102 help 103 This enables the NAND flash controller on the S3C24xx and S3C64xx 104 SoCs 105 106 No board specific support is done by this driver, each board 107 must advertise a platform_device for the driver to attach. 108 109config MTD_NAND_S3C2410_DEBUG 110 bool "Samsung S3C NAND controller debug" 111 depends on MTD_NAND_S3C2410 112 help 113 Enable debugging of the S3C NAND driver 114 115config MTD_NAND_S3C2410_CLKSTOP 116 bool "Samsung S3C NAND IDLE clock stop" 117 depends on MTD_NAND_S3C2410 118 default n 119 help 120 Stop the clock to the NAND controller when there is no chip 121 selected to save power. This will mean there is a small delay 122 when the is NAND chip selected or released, but will save 123 approximately 5mA of power when there is nothing happening. 124 125config MTD_NAND_TANGO 126 tristate "Tango NAND controller" 127 depends on ARCH_TANGO || COMPILE_TEST 128 depends on HAS_IOMEM 129 help 130 Enables the NAND Flash controller on Tango chips. 131 132config MTD_NAND_SHARPSL 133 tristate "Sharp SL Series (C7xx + others) NAND controller" 134 depends on ARCH_PXA || COMPILE_TEST 135 depends on HAS_IOMEM 136 137config MTD_NAND_CAFE 138 tristate "OLPC CAFÉ NAND controller" 139 depends on PCI 140 select REED_SOLOMON 141 select REED_SOLOMON_DEC16 142 help 143 Use NAND flash attached to the CAFÉ chip designed for the OLPC 144 laptop. 145 146config MTD_NAND_CS553X 147 tristate "CS5535/CS5536 (AMD Geode companion) NAND controller" 148 depends on X86_32 149 depends on !UML && HAS_IOMEM 150 help 151 The CS553x companion chips for the AMD Geode processor 152 include NAND flash controllers with built-in hardware ECC 153 capabilities; enabling this option will allow you to use 154 these. The driver will check the MSRs to verify that the 155 controller is enabled for NAND, and currently requires that 156 the controller be in MMIO mode. 157 158 If you say "m", the module will be called cs553x_nand. 159 160config MTD_NAND_ATMEL 161 tristate "Atmel AT91 NAND Flash/SmartMedia NAND controller" 162 depends on ARCH_AT91 || COMPILE_TEST 163 depends on HAS_IOMEM 164 select GENERIC_ALLOCATOR 165 select MFD_ATMEL_SMC 166 help 167 Enables support for NAND Flash / Smart Media Card interface 168 on Atmel AT91 processors. 169 170config MTD_NAND_ORION 171 tristate "Marvell Orion NAND controller" 172 depends on PLAT_ORION 173 help 174 This enables the NAND flash controller on Orion machines. 175 176 No board specific support is done by this driver, each board 177 must advertise a platform_device for the driver to attach. 178 179config MTD_NAND_MARVELL 180 tristate "Marvell EBU NAND controller" 181 depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_MVEBU || \ 182 COMPILE_TEST 183 depends on HAS_IOMEM 184 help 185 This enables the NAND flash controller driver for Marvell boards, 186 including: 187 - PXA3xx processors (NFCv1) 188 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) 189 - 64-bit Aramda platforms (7k, 8k) (NFCv2) 190 191config MTD_NAND_SLC_LPC32XX 192 tristate "NXP LPC32xx SLC NAND controller" 193 depends on ARCH_LPC32XX || COMPILE_TEST 194 depends on HAS_IOMEM 195 help 196 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell 197 chips) NAND controller. This is the default for the PHYTEC 3250 198 reference board which contains a NAND256R3A2CZA6 chip. 199 200 Please check the actual NAND chip connected and its support 201 by the SLC NAND controller. 202 203config MTD_NAND_MLC_LPC32XX 204 tristate "NXP LPC32xx MLC NAND controller" 205 depends on ARCH_LPC32XX || COMPILE_TEST 206 depends on HAS_IOMEM 207 help 208 Uses the LPC32XX MLC (i.e. for Multi Level Cell chips) NAND 209 controller. This is the default for the WORK92105 controller 210 board. 211 212 Please check the actual NAND chip connected and its support 213 by the MLC NAND controller. 214 215config MTD_NAND_CM_X270 216 tristate "CM-X270 modules NAND controller" 217 depends on MACH_ARMCORE 218 219config MTD_NAND_PASEMI 220 tristate "PA Semi PWRficient NAND controller" 221 depends on PPC_PASEMI 222 help 223 Enables support for NAND Flash interface on PA Semi PWRficient 224 based boards 225 226config MTD_NAND_TMIO 227 tristate "Toshiba Mobile IO NAND controller" 228 depends on MFD_TMIO 229 help 230 Support for NAND flash connected to a Toshiba Mobile IO 231 Controller in some PDAs, including the Sharp SL6000x. 232 233config MTD_NAND_BRCMNAND 234 tristate "Broadcom STB NAND controller" 235 depends on ARM || ARM64 || MIPS || COMPILE_TEST 236 depends on HAS_IOMEM 237 help 238 Enables the Broadcom NAND controller driver. The controller was 239 originally designed for Set-Top Box but is used on various BCM7xxx, 240 BCM3xxx, BCM63xxx, iProc/Cygnus and more. 241 242config MTD_NAND_BCM47XXNFLASH 243 tristate "BCM4706 BCMA NAND controller" 244 depends on BCMA_NFLASH 245 depends on BCMA 246 help 247 BCMA bus can have various flash memories attached, they are 248 registered by bcma as platform devices. This enables driver for 249 NAND flash memories. For now only BCM4706 is supported. 250 251config MTD_NAND_OXNAS 252 tristate "Oxford Semiconductor NAND controller" 253 depends on ARCH_OXNAS || COMPILE_TEST 254 depends on HAS_IOMEM 255 help 256 This enables the NAND flash controller on Oxford Semiconductor SoCs. 257 258config MTD_NAND_MPC5121_NFC 259 tristate "MPC5121 NAND controller" 260 depends on PPC_MPC512x 261 help 262 This enables the driver for the NAND flash controller on the 263 MPC5121 SoC. 264 265config MTD_NAND_GPMI_NAND 266 tristate "Freescale GPMI NAND controller" 267 depends on MXS_DMA 268 help 269 Enables NAND Flash support for IMX23, IMX28 or IMX6. 270 The GPMI controller is very powerful, with the help of BCH 271 module, it can do the hardware ECC. The GPMI supports several 272 NAND flashs at the same time. 273 274config MTD_NAND_FSL_ELBC 275 tristate "Freescale eLBC NAND controller" 276 depends on FSL_SOC 277 select FSL_LBC 278 help 279 Various Freescale chips, including the 8313, include a NAND Flash 280 Controller Module with built-in hardware ECC capabilities. 281 Enabling this option will enable you to use this to control 282 external NAND devices. 283 284config MTD_NAND_FSL_IFC 285 tristate "Freescale IFC NAND controller" 286 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST 287 depends on HAS_IOMEM 288 select FSL_IFC 289 select MEMORY 290 help 291 Various Freescale chips e.g P1010, include a NAND Flash machine 292 with built-in hardware ECC capabilities. 293 Enabling this option will enable you to use this to control 294 external NAND devices. 295 296config MTD_NAND_FSL_UPM 297 tristate "Freescale UPM NAND controller" 298 depends on PPC_83xx || PPC_85xx 299 select FSL_LBC 300 help 301 Enables support for NAND Flash chips wired onto Freescale PowerPC 302 processor localbus with User-Programmable Machine support. 303 304config MTD_NAND_VF610_NFC 305 tristate "Freescale VF610/MPC5125 NAND controller" 306 depends on (SOC_VF610 || COMPILE_TEST) 307 depends on HAS_IOMEM 308 help 309 Enables support for NAND Flash Controller on some Freescale 310 processors like the VF610, MPC5125, MCF54418 or Kinetis K70. 311 The driver supports a maximum 2k page size. With 2k pages and 312 64 bytes or more of OOB, hardware ECC with up to 32-bit error 313 correction is supported. Hardware ECC is only enabled through 314 device tree. 315 316config MTD_NAND_MXC 317 tristate "Freescale MXC NAND controller" 318 depends on ARCH_MXC || COMPILE_TEST 319 depends on HAS_IOMEM 320 help 321 This enables the driver for the NAND flash controller on the 322 MXC processors. 323 324config MTD_NAND_SH_FLCTL 325 tristate "Renesas SuperH FLCTL NAND controller" 326 depends on SUPERH || COMPILE_TEST 327 depends on HAS_IOMEM 328 help 329 Several Renesas SuperH CPU has FLCTL. This option enables support 330 for NAND Flash using FLCTL. 331 332config MTD_NAND_DAVINCI 333 tristate "DaVinci/Keystone NAND controller" 334 depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST 335 depends on HAS_IOMEM 336 help 337 Enable the driver for NAND flash chips on Texas Instruments 338 DaVinci/Keystone processors. 339 340config MTD_NAND_TXX9NDFMC 341 tristate "TXx9 NAND controller" 342 depends on SOC_TX4938 || SOC_TX4939 || COMPILE_TEST 343 depends on HAS_IOMEM 344 help 345 This enables the NAND flash controller on the TXx9 SoCs. 346 347config MTD_NAND_SOCRATES 348 tristate "Socrates NAND controller" 349 depends on SOCRATES 350 help 351 Enables support for NAND Flash chips wired onto Socrates board. 352 353config MTD_NAND_NUC900 354 tristate "Nuvoton NUC9xx/w90p910 NAND controller" 355 depends on ARCH_W90X900 || COMPILE_TEST 356 depends on HAS_IOMEM 357 help 358 This enables the driver for the NAND Flash on evaluation board based 359 on w90p910 / NUC9xx. 360 361source "drivers/mtd/nand/raw/ingenic/Kconfig" 362 363config MTD_NAND_FSMC 364 tristate "ST Micros FSMC NAND controller" 365 depends on OF && HAS_IOMEM 366 depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 || \ 367 COMPILE_TEST 368 help 369 Enables support for NAND Flash chips on the ST Microelectronics 370 Flexible Static Memory Controller (FSMC) 371 372config MTD_NAND_XWAY 373 bool "Lantiq XWAY NAND controller" 374 depends on LANTIQ && SOC_TYPE_XWAY 375 help 376 Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached 377 to the External Bus Unit (EBU). 378 379config MTD_NAND_SUNXI 380 tristate "Allwinner NAND controller" 381 depends on ARCH_SUNXI || COMPILE_TEST 382 depends on HAS_IOMEM 383 help 384 Enables support for NAND Flash chips on Allwinner SoCs. 385 386config MTD_NAND_HISI504 387 tristate "Hisilicon Hip04 NAND controller" 388 depends on ARCH_HISI || COMPILE_TEST 389 depends on HAS_IOMEM 390 help 391 Enables support for NAND controller on Hisilicon SoC Hip04. 392 393config MTD_NAND_QCOM 394 tristate "QCOM NAND controller" 395 depends on ARCH_QCOM || COMPILE_TEST 396 depends on HAS_IOMEM 397 help 398 Enables support for NAND flash chips on SoCs containing the EBI2 NAND 399 controller. This controller is found on IPQ806x SoC. 400 401config MTD_NAND_MTK 402 tristate "MTK NAND controller" 403 depends on ARCH_MEDIATEK || COMPILE_TEST 404 depends on HAS_IOMEM 405 help 406 Enables support for NAND controller on MTK SoCs. 407 This controller is found on mt27xx, mt81xx, mt65xx SoCs. 408 409config MTD_NAND_TEGRA 410 tristate "NVIDIA Tegra NAND controller" 411 depends on ARCH_TEGRA || COMPILE_TEST 412 depends on HAS_IOMEM 413 help 414 Enables support for NAND flash controller on NVIDIA Tegra SoC. 415 The driver has been developed and tested on a Tegra 2 SoC. DMA 416 support, raw read/write page as well as HW ECC read/write page 417 is supported. Extra OOB bytes when using HW ECC are currently 418 not supported. 419 420config MTD_NAND_STM32_FMC2 421 tristate "Support for NAND controller on STM32MP SoCs" 422 depends on MACH_STM32MP157 || COMPILE_TEST 423 help 424 Enables support for NAND Flash chips on SoCs containing the FMC2 425 NAND controller. This controller is found on STM32MP SoCs. 426 The controller supports a maximum 8k page size and supports 427 a maximum 8-bit correction error per sector of 512 bytes. 428 429config MTD_NAND_MESON 430 tristate "Support for NAND controller on Amlogic's Meson SoCs" 431 depends on ARCH_MESON || COMPILE_TEST 432 select MFD_SYSCON 433 help 434 Enables support for NAND controller on Amlogic's Meson SoCs. 435 This controller is found on Meson SoCs. 436 437config MTD_NAND_GPIO 438 tristate "GPIO assisted NAND controller" 439 depends on GPIOLIB || COMPILE_TEST 440 depends on HAS_IOMEM 441 help 442 This enables a NAND flash driver where control signals are 443 connected to GPIO pins, and commands and data are communicated 444 via a memory mapped interface. 445 446config MTD_NAND_PLATFORM 447 tristate "Generic NAND controller" 448 depends on HAS_IOMEM 449 help 450 This implements a generic NAND driver for on-SOC platform 451 devices. You will need to provide platform-specific functions 452 via platform_data. 453 454comment "Misc" 455 456config MTD_SM_COMMON 457 tristate 458 default n 459 460config MTD_NAND_NANDSIM 461 tristate "Support for NAND Flash Simulator" 462 help 463 The simulator may simulate various NAND flash chips for the 464 MTD nand layer. 465 466config MTD_NAND_RICOH 467 tristate "Ricoh xD card reader" 468 default n 469 depends on PCI 470 select MTD_SM_COMMON 471 help 472 Enable support for Ricoh R5C852 xD card reader 473 You also need to enable ether 474 NAND SSFDC (SmartMedia) read only translation layer' or new 475 expermental, readwrite 476 'SmartMedia/xD new translation layer' 477 478config MTD_NAND_DISKONCHIP 479 tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation)" 480 depends on HAS_IOMEM 481 select REED_SOLOMON 482 select REED_SOLOMON_DEC16 483 help 484 This is a reimplementation of M-Systems DiskOnChip 2000, 485 Millennium and Millennium Plus as a standard NAND device driver, 486 as opposed to the earlier self-contained MTD device drivers. 487 This should enable, among other things, proper JFFS2 operation on 488 these devices. 489 490config MTD_NAND_DISKONCHIP_PROBE_ADVANCED 491 bool "Advanced detection options for DiskOnChip" 492 depends on MTD_NAND_DISKONCHIP 493 help 494 This option allows you to specify nonstandard address at which to 495 probe for a DiskOnChip, or to change the detection options. You 496 are unlikely to need any of this unless you are using LinuxBIOS. 497 Say 'N'. 498 499config MTD_NAND_DISKONCHIP_PROBE_ADDRESS 500 hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED 501 depends on MTD_NAND_DISKONCHIP 502 default "0" 503 help 504 By default, the probe for DiskOnChip devices will look for a 505 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. 506 This option allows you to specify a single address at which to probe 507 for the device, which is useful if you have other devices in that 508 range which get upset when they are probed. 509 510 (Note that on PowerPC, the normal probe will only check at 511 0xE4000000.) 512 513 Normally, you should leave this set to zero, to allow the probe at 514 the normal addresses. 515 516config MTD_NAND_DISKONCHIP_PROBE_HIGH 517 bool "Probe high addresses" 518 depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED 519 help 520 By default, the probe for DiskOnChip devices will look for a 521 DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. 522 This option changes to make it probe between 0xFFFC8000 and 523 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be 524 useful to you. Say 'N'. 525 526config MTD_NAND_DISKONCHIP_BBTWRITE 527 bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP" 528 depends on MTD_NAND_DISKONCHIP 529 help 530 On DiskOnChip devices shipped with the INFTL filesystem (Millennium 531 and 2000 TSOP/Alon), Linux reserves some space at the end of the 532 device for the Bad Block Table (BBT). If you have existing INFTL 533 data on your device (created by non-Linux tools such as M-Systems' 534 DOS drivers), your data might overlap the area Linux wants to use for 535 the BBT. If this is a concern for you, leave this option disabled and 536 Linux will not write BBT data into this area. 537 The downside of leaving this option disabled is that if bad blocks 538 are detected by Linux, they will not be recorded in the BBT, which 539 could cause future problems. 540 Once you enable this option, new filesystems (INFTL or others, created 541 in Linux or other operating systems) will not use the reserved area. 542 The only reason not to enable this option is to prevent damage to 543 preexisting filesystems. 544 Even if you leave this disabled, you can enable BBT writes at module 545 load time (assuming you build diskonchip as a module) with the module 546 parameter "inftl_bbt_write=1". 547 548endif # MTD_RAW_NAND 549