1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller 4 * 5 * Author: Angus Clark <angus.clark@st.com> 6 * 7 * Copyright (C) 2010-2014 STMicroelectronics Limited 8 * 9 * JEDEC probe based on drivers/mtd/devices/m25p80.c 10 */ 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/regmap.h> 14 #include <linux/platform_device.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/partitions.h> 18 #include <linux/mtd/spi-nor.h> 19 #include <linux/sched.h> 20 #include <linux/delay.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/clk.h> 24 25 #include "serial_flash_cmds.h" 26 27 /* 28 * FSM SPI Controller Registers 29 */ 30 #define SPI_CLOCKDIV 0x0010 31 #define SPI_MODESELECT 0x0018 32 #define SPI_CONFIGDATA 0x0020 33 #define SPI_STA_MODE_CHANGE 0x0028 34 #define SPI_FAST_SEQ_TRANSFER_SIZE 0x0100 35 #define SPI_FAST_SEQ_ADD1 0x0104 36 #define SPI_FAST_SEQ_ADD2 0x0108 37 #define SPI_FAST_SEQ_ADD_CFG 0x010c 38 #define SPI_FAST_SEQ_OPC1 0x0110 39 #define SPI_FAST_SEQ_OPC2 0x0114 40 #define SPI_FAST_SEQ_OPC3 0x0118 41 #define SPI_FAST_SEQ_OPC4 0x011c 42 #define SPI_FAST_SEQ_OPC5 0x0120 43 #define SPI_MODE_BITS 0x0124 44 #define SPI_DUMMY_BITS 0x0128 45 #define SPI_FAST_SEQ_FLASH_STA_DATA 0x012c 46 #define SPI_FAST_SEQ_1 0x0130 47 #define SPI_FAST_SEQ_2 0x0134 48 #define SPI_FAST_SEQ_3 0x0138 49 #define SPI_FAST_SEQ_4 0x013c 50 #define SPI_FAST_SEQ_CFG 0x0140 51 #define SPI_FAST_SEQ_STA 0x0144 52 #define SPI_QUAD_BOOT_SEQ_INIT_1 0x0148 53 #define SPI_QUAD_BOOT_SEQ_INIT_2 0x014c 54 #define SPI_QUAD_BOOT_READ_SEQ_1 0x0150 55 #define SPI_QUAD_BOOT_READ_SEQ_2 0x0154 56 #define SPI_PROGRAM_ERASE_TIME 0x0158 57 #define SPI_MULT_PAGE_REPEAT_SEQ_1 0x015c 58 #define SPI_MULT_PAGE_REPEAT_SEQ_2 0x0160 59 #define SPI_STATUS_WR_TIME_REG 0x0164 60 #define SPI_FAST_SEQ_DATA_REG 0x0300 61 62 /* 63 * Register: SPI_MODESELECT 64 */ 65 #define SPI_MODESELECT_CONTIG 0x01 66 #define SPI_MODESELECT_FASTREAD 0x02 67 #define SPI_MODESELECT_DUALIO 0x04 68 #define SPI_MODESELECT_FSM 0x08 69 #define SPI_MODESELECT_QUADBOOT 0x10 70 71 /* 72 * Register: SPI_CONFIGDATA 73 */ 74 #define SPI_CFG_DEVICE_ST 0x1 75 #define SPI_CFG_DEVICE_ATMEL 0x4 76 #define SPI_CFG_MIN_CS_HIGH(x) (((x) & 0xfff) << 4) 77 #define SPI_CFG_CS_SETUPHOLD(x) (((x) & 0xff) << 16) 78 #define SPI_CFG_DATA_HOLD(x) (((x) & 0xff) << 24) 79 80 #define SPI_CFG_DEFAULT_MIN_CS_HIGH SPI_CFG_MIN_CS_HIGH(0x0AA) 81 #define SPI_CFG_DEFAULT_CS_SETUPHOLD SPI_CFG_CS_SETUPHOLD(0xA0) 82 #define SPI_CFG_DEFAULT_DATA_HOLD SPI_CFG_DATA_HOLD(0x00) 83 84 /* 85 * Register: SPI_FAST_SEQ_TRANSFER_SIZE 86 */ 87 #define TRANSFER_SIZE(x) ((x) * 8) 88 89 /* 90 * Register: SPI_FAST_SEQ_ADD_CFG 91 */ 92 #define ADR_CFG_CYCLES_ADD1(x) ((x) << 0) 93 #define ADR_CFG_PADS_1_ADD1 (0x0 << 6) 94 #define ADR_CFG_PADS_2_ADD1 (0x1 << 6) 95 #define ADR_CFG_PADS_4_ADD1 (0x3 << 6) 96 #define ADR_CFG_CSDEASSERT_ADD1 (1 << 8) 97 #define ADR_CFG_CYCLES_ADD2(x) ((x) << (0+16)) 98 #define ADR_CFG_PADS_1_ADD2 (0x0 << (6+16)) 99 #define ADR_CFG_PADS_2_ADD2 (0x1 << (6+16)) 100 #define ADR_CFG_PADS_4_ADD2 (0x3 << (6+16)) 101 #define ADR_CFG_CSDEASSERT_ADD2 (1 << (8+16)) 102 103 /* 104 * Register: SPI_FAST_SEQ_n 105 */ 106 #define SEQ_OPC_OPCODE(x) ((x) << 0) 107 #define SEQ_OPC_CYCLES(x) ((x) << 8) 108 #define SEQ_OPC_PADS_1 (0x0 << 14) 109 #define SEQ_OPC_PADS_2 (0x1 << 14) 110 #define SEQ_OPC_PADS_4 (0x3 << 14) 111 #define SEQ_OPC_CSDEASSERT (1 << 16) 112 113 /* 114 * Register: SPI_FAST_SEQ_CFG 115 */ 116 #define SEQ_CFG_STARTSEQ (1 << 0) 117 #define SEQ_CFG_SWRESET (1 << 5) 118 #define SEQ_CFG_CSDEASSERT (1 << 6) 119 #define SEQ_CFG_READNOTWRITE (1 << 7) 120 #define SEQ_CFG_ERASE (1 << 8) 121 #define SEQ_CFG_PADS_1 (0x0 << 16) 122 #define SEQ_CFG_PADS_2 (0x1 << 16) 123 #define SEQ_CFG_PADS_4 (0x3 << 16) 124 125 /* 126 * Register: SPI_MODE_BITS 127 */ 128 #define MODE_DATA(x) (x & 0xff) 129 #define MODE_CYCLES(x) ((x & 0x3f) << 16) 130 #define MODE_PADS_1 (0x0 << 22) 131 #define MODE_PADS_2 (0x1 << 22) 132 #define MODE_PADS_4 (0x3 << 22) 133 #define DUMMY_CSDEASSERT (1 << 24) 134 135 /* 136 * Register: SPI_DUMMY_BITS 137 */ 138 #define DUMMY_CYCLES(x) ((x & 0x3f) << 16) 139 #define DUMMY_PADS_1 (0x0 << 22) 140 #define DUMMY_PADS_2 (0x1 << 22) 141 #define DUMMY_PADS_4 (0x3 << 22) 142 #define DUMMY_CSDEASSERT (1 << 24) 143 144 /* 145 * Register: SPI_FAST_SEQ_FLASH_STA_DATA 146 */ 147 #define STA_DATA_BYTE1(x) ((x & 0xff) << 0) 148 #define STA_DATA_BYTE2(x) ((x & 0xff) << 8) 149 #define STA_PADS_1 (0x0 << 16) 150 #define STA_PADS_2 (0x1 << 16) 151 #define STA_PADS_4 (0x3 << 16) 152 #define STA_CSDEASSERT (0x1 << 20) 153 #define STA_RDNOTWR (0x1 << 21) 154 155 /* 156 * FSM SPI Instruction Opcodes 157 */ 158 #define STFSM_OPC_CMD 0x1 159 #define STFSM_OPC_ADD 0x2 160 #define STFSM_OPC_STA 0x3 161 #define STFSM_OPC_MODE 0x4 162 #define STFSM_OPC_DUMMY 0x5 163 #define STFSM_OPC_DATA 0x6 164 #define STFSM_OPC_WAIT 0x7 165 #define STFSM_OPC_JUMP 0x8 166 #define STFSM_OPC_GOTO 0x9 167 #define STFSM_OPC_STOP 0xF 168 169 /* 170 * FSM SPI Instructions (== opcode + operand). 171 */ 172 #define STFSM_INSTR(cmd, op) ((cmd) | ((op) << 4)) 173 174 #define STFSM_INST_CMD1 STFSM_INSTR(STFSM_OPC_CMD, 1) 175 #define STFSM_INST_CMD2 STFSM_INSTR(STFSM_OPC_CMD, 2) 176 #define STFSM_INST_CMD3 STFSM_INSTR(STFSM_OPC_CMD, 3) 177 #define STFSM_INST_CMD4 STFSM_INSTR(STFSM_OPC_CMD, 4) 178 #define STFSM_INST_CMD5 STFSM_INSTR(STFSM_OPC_CMD, 5) 179 #define STFSM_INST_ADD1 STFSM_INSTR(STFSM_OPC_ADD, 1) 180 #define STFSM_INST_ADD2 STFSM_INSTR(STFSM_OPC_ADD, 2) 181 182 #define STFSM_INST_DATA_WRITE STFSM_INSTR(STFSM_OPC_DATA, 1) 183 #define STFSM_INST_DATA_READ STFSM_INSTR(STFSM_OPC_DATA, 2) 184 185 #define STFSM_INST_STA_RD1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 186 #define STFSM_INST_STA_WR1 STFSM_INSTR(STFSM_OPC_STA, 0x1) 187 #define STFSM_INST_STA_RD2 STFSM_INSTR(STFSM_OPC_STA, 0x2) 188 #define STFSM_INST_STA_WR1_2 STFSM_INSTR(STFSM_OPC_STA, 0x3) 189 190 #define STFSM_INST_MODE STFSM_INSTR(STFSM_OPC_MODE, 0) 191 #define STFSM_INST_DUMMY STFSM_INSTR(STFSM_OPC_DUMMY, 0) 192 #define STFSM_INST_WAIT STFSM_INSTR(STFSM_OPC_WAIT, 0) 193 #define STFSM_INST_STOP STFSM_INSTR(STFSM_OPC_STOP, 0) 194 195 #define STFSM_DEFAULT_EMI_FREQ 100000000UL /* 100 MHz */ 196 #define STFSM_DEFAULT_WR_TIME (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */ 197 198 #define STFSM_FLASH_SAFE_FREQ 10000000UL /* 10 MHz */ 199 200 #define STFSM_MAX_WAIT_SEQ_MS 1000 /* FSM execution time */ 201 202 /* S25FLxxxS commands */ 203 #define S25FL_CMD_WRITE4_1_1_4 0x34 204 #define S25FL_CMD_SE4 0xdc 205 #define S25FL_CMD_CLSR 0x30 206 #define S25FL_CMD_DYBWR 0xe1 207 #define S25FL_CMD_DYBRD 0xe0 208 #define S25FL_CMD_WRITE4 0x12 /* Note, opcode clashes with 209 * 'SPINOR_OP_WRITE_1_4_4' 210 * as found on N25Qxxx devices! */ 211 212 /* Status register */ 213 #define FLASH_STATUS_BUSY 0x01 214 #define FLASH_STATUS_WEL 0x02 215 #define FLASH_STATUS_BP0 0x04 216 #define FLASH_STATUS_BP1 0x08 217 #define FLASH_STATUS_BP2 0x10 218 #define FLASH_STATUS_SRWP0 0x80 219 #define FLASH_STATUS_TIMEOUT 0xff 220 /* S25FL Error Flags */ 221 #define S25FL_STATUS_E_ERR 0x20 222 #define S25FL_STATUS_P_ERR 0x40 223 224 #define N25Q_CMD_WRVCR 0x81 225 #define N25Q_CMD_RDVCR 0x85 226 #define N25Q_CMD_RDVECR 0x65 227 #define N25Q_CMD_RDNVCR 0xb5 228 #define N25Q_CMD_WRNVCR 0xb1 229 230 #define FLASH_PAGESIZE 256 /* In Bytes */ 231 #define FLASH_PAGESIZE_32 (FLASH_PAGESIZE / 4) /* In uint32_t */ 232 #define FLASH_MAX_BUSY_WAIT (300 * HZ) /* Maximum 'CHIPERASE' time */ 233 234 /* 235 * Flags to tweak operation of default read/write/erase routines 236 */ 237 #define CFG_READ_TOGGLE_32BIT_ADDR 0x00000001 238 #define CFG_WRITE_TOGGLE_32BIT_ADDR 0x00000002 239 #define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008 240 #define CFG_S25FL_CHECK_ERROR_FLAGS 0x00000010 241 242 struct stfsm_seq { 243 uint32_t data_size; 244 uint32_t addr1; 245 uint32_t addr2; 246 uint32_t addr_cfg; 247 uint32_t seq_opc[5]; 248 uint32_t mode; 249 uint32_t dummy; 250 uint32_t status; 251 uint8_t seq[16]; 252 uint32_t seq_cfg; 253 } __packed __aligned(4); 254 255 struct stfsm { 256 struct device *dev; 257 void __iomem *base; 258 struct resource *region; 259 struct mtd_info mtd; 260 struct mutex lock; 261 struct flash_info *info; 262 struct clk *clk; 263 264 uint32_t configuration; 265 uint32_t fifo_dir_delay; 266 bool booted_from_spi; 267 bool reset_signal; 268 bool reset_por; 269 270 struct stfsm_seq stfsm_seq_read; 271 struct stfsm_seq stfsm_seq_write; 272 struct stfsm_seq stfsm_seq_en_32bit_addr; 273 }; 274 275 /* Parameters to configure a READ or WRITE FSM sequence */ 276 struct seq_rw_config { 277 uint32_t flags; /* flags to support config */ 278 uint8_t cmd; /* FLASH command */ 279 int write; /* Write Sequence */ 280 uint8_t addr_pads; /* No. of addr pads (MODE & DUMMY) */ 281 uint8_t data_pads; /* No. of data pads */ 282 uint8_t mode_data; /* MODE data */ 283 uint8_t mode_cycles; /* No. of MODE cycles */ 284 uint8_t dummy_cycles; /* No. of DUMMY cycles */ 285 }; 286 287 /* SPI Flash Device Table */ 288 struct flash_info { 289 char *name; 290 /* 291 * JEDEC id zero means "no ID" (most older chips); otherwise it has 292 * a high byte of zero plus three data bytes: the manufacturer id, 293 * then a two byte device id. 294 */ 295 u32 jedec_id; 296 u16 ext_id; 297 /* 298 * The size listed here is what works with SPINOR_OP_SE, which isn't 299 * necessarily called a "sector" by the vendor. 300 */ 301 unsigned sector_size; 302 u16 n_sectors; 303 u32 flags; 304 /* 305 * Note, where FAST_READ is supported, freq_max specifies the 306 * FAST_READ frequency, not the READ frequency. 307 */ 308 u32 max_freq; 309 int (*config)(struct stfsm *); 310 }; 311 312 static int stfsm_n25q_config(struct stfsm *fsm); 313 static int stfsm_mx25_config(struct stfsm *fsm); 314 static int stfsm_s25fl_config(struct stfsm *fsm); 315 static int stfsm_w25q_config(struct stfsm *fsm); 316 317 static struct flash_info flash_types[] = { 318 /* 319 * ST Microelectronics/Numonyx -- 320 * (newer production versions may have feature updates 321 * (eg faster operating frequency) 322 */ 323 #define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST) 324 { "m25p40", 0x202013, 0, 64 * 1024, 8, M25P_FLAG, 25, NULL }, 325 { "m25p80", 0x202014, 0, 64 * 1024, 16, M25P_FLAG, 25, NULL }, 326 { "m25p16", 0x202015, 0, 64 * 1024, 32, M25P_FLAG, 25, NULL }, 327 { "m25p32", 0x202016, 0, 64 * 1024, 64, M25P_FLAG, 50, NULL }, 328 { "m25p64", 0x202017, 0, 64 * 1024, 128, M25P_FLAG, 50, NULL }, 329 { "m25p128", 0x202018, 0, 256 * 1024, 64, M25P_FLAG, 50, NULL }, 330 331 #define M25PX_FLAG (FLASH_FLAG_READ_WRITE | \ 332 FLASH_FLAG_READ_FAST | \ 333 FLASH_FLAG_READ_1_1_2 | \ 334 FLASH_FLAG_WRITE_1_1_2) 335 { "m25px32", 0x207116, 0, 64 * 1024, 64, M25PX_FLAG, 75, NULL }, 336 { "m25px64", 0x207117, 0, 64 * 1024, 128, M25PX_FLAG, 75, NULL }, 337 338 /* Macronix MX25xxx 339 * - Support for 'FLASH_FLAG_WRITE_1_4_4' is omitted for devices 340 * where operating frequency must be reduced. 341 */ 342 #define MX25_FLAG (FLASH_FLAG_READ_WRITE | \ 343 FLASH_FLAG_READ_FAST | \ 344 FLASH_FLAG_READ_1_1_2 | \ 345 FLASH_FLAG_READ_1_2_2 | \ 346 FLASH_FLAG_READ_1_1_4 | \ 347 FLASH_FLAG_SE_4K | \ 348 FLASH_FLAG_SE_32K) 349 { "mx25l3255e", 0xc29e16, 0, 64 * 1024, 64, 350 (MX25_FLAG | FLASH_FLAG_WRITE_1_4_4), 86, 351 stfsm_mx25_config}, 352 { "mx25l25635e", 0xc22019, 0, 64*1024, 512, 353 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, 354 stfsm_mx25_config }, 355 { "mx25l25655e", 0xc22619, 0, 64*1024, 512, 356 (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70, 357 stfsm_mx25_config}, 358 359 #define N25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 360 FLASH_FLAG_READ_FAST | \ 361 FLASH_FLAG_READ_1_1_2 | \ 362 FLASH_FLAG_READ_1_2_2 | \ 363 FLASH_FLAG_READ_1_1_4 | \ 364 FLASH_FLAG_READ_1_4_4 | \ 365 FLASH_FLAG_WRITE_1_1_2 | \ 366 FLASH_FLAG_WRITE_1_2_2 | \ 367 FLASH_FLAG_WRITE_1_1_4 | \ 368 FLASH_FLAG_WRITE_1_4_4) 369 { "n25q128", 0x20ba18, 0, 64 * 1024, 256, N25Q_FLAG, 108, 370 stfsm_n25q_config }, 371 { "n25q256", 0x20ba19, 0, 64 * 1024, 512, 372 N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config }, 373 374 /* 375 * Spansion S25FLxxxP 376 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 377 */ 378 #define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE | \ 379 FLASH_FLAG_READ_1_1_2 | \ 380 FLASH_FLAG_READ_1_2_2 | \ 381 FLASH_FLAG_READ_1_1_4 | \ 382 FLASH_FLAG_READ_1_4_4 | \ 383 FLASH_FLAG_WRITE_1_1_4 | \ 384 FLASH_FLAG_READ_FAST) 385 { "s25fl032p", 0x010215, 0x4d00, 64 * 1024, 64, S25FLXXXP_FLAG, 80, 386 stfsm_s25fl_config}, 387 { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, S25FLXXXP_FLAG, 80, 388 stfsm_s25fl_config }, 389 { "s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, S25FLXXXP_FLAG, 80, 390 stfsm_s25fl_config }, 391 392 /* 393 * Spansion S25FLxxxS 394 * - 256KiB and 64KiB sector variants (identified by ext. JEDEC) 395 * - RESET# signal supported by die but not bristled out on all 396 * package types. The package type is a function of board design, 397 * so this information is captured in the board's flags. 398 * - Supports 'DYB' sector protection. Depending on variant, sectors 399 * may default to locked state on power-on. 400 */ 401 #define S25FLXXXS_FLAG (S25FLXXXP_FLAG | \ 402 FLASH_FLAG_RESET | \ 403 FLASH_FLAG_DYB_LOCKING) 404 { "s25fl128s0", 0x012018, 0x0300, 256 * 1024, 64, S25FLXXXS_FLAG, 80, 405 stfsm_s25fl_config }, 406 { "s25fl128s1", 0x012018, 0x0301, 64 * 1024, 256, S25FLXXXS_FLAG, 80, 407 stfsm_s25fl_config }, 408 { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, 409 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 410 { "s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, 411 S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config }, 412 413 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 414 #define W25X_FLAG (FLASH_FLAG_READ_WRITE | \ 415 FLASH_FLAG_READ_FAST | \ 416 FLASH_FLAG_READ_1_1_2 | \ 417 FLASH_FLAG_WRITE_1_1_2) 418 { "w25x40", 0xef3013, 0, 64 * 1024, 8, W25X_FLAG, 75, NULL }, 419 { "w25x80", 0xef3014, 0, 64 * 1024, 16, W25X_FLAG, 75, NULL }, 420 { "w25x16", 0xef3015, 0, 64 * 1024, 32, W25X_FLAG, 75, NULL }, 421 { "w25x32", 0xef3016, 0, 64 * 1024, 64, W25X_FLAG, 75, NULL }, 422 { "w25x64", 0xef3017, 0, 64 * 1024, 128, W25X_FLAG, 75, NULL }, 423 424 /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */ 425 #define W25Q_FLAG (FLASH_FLAG_READ_WRITE | \ 426 FLASH_FLAG_READ_FAST | \ 427 FLASH_FLAG_READ_1_1_2 | \ 428 FLASH_FLAG_READ_1_2_2 | \ 429 FLASH_FLAG_READ_1_1_4 | \ 430 FLASH_FLAG_READ_1_4_4 | \ 431 FLASH_FLAG_WRITE_1_1_4) 432 { "w25q80", 0xef4014, 0, 64 * 1024, 16, W25Q_FLAG, 80, 433 stfsm_w25q_config }, 434 { "w25q16", 0xef4015, 0, 64 * 1024, 32, W25Q_FLAG, 80, 435 stfsm_w25q_config }, 436 { "w25q32", 0xef4016, 0, 64 * 1024, 64, W25Q_FLAG, 80, 437 stfsm_w25q_config }, 438 { "w25q64", 0xef4017, 0, 64 * 1024, 128, W25Q_FLAG, 80, 439 stfsm_w25q_config }, 440 441 /* Sentinel */ 442 { NULL, 0x000000, 0, 0, 0, 0, 0, NULL }, 443 }; 444 445 /* 446 * FSM message sequence configurations: 447 * 448 * All configs are presented in order of preference 449 */ 450 451 /* Default READ configurations, in order of preference */ 452 static struct seq_rw_config default_read_configs[] = { 453 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 2, 4}, 454 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 4, 0}, 455 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 4, 0}, 456 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 457 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 458 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, 459 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 460 }; 461 462 /* Default WRITE configurations */ 463 static struct seq_rw_config default_write_configs[] = { 464 {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0}, 465 {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0}, 466 {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0}, 467 {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0}, 468 {FLASH_FLAG_READ_WRITE, SPINOR_OP_WRITE, 1, 1, 1, 0x00, 0, 0}, 469 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 470 }; 471 472 /* 473 * [N25Qxxx] Configuration 474 */ 475 #define N25Q_VCR_DUMMY_CYCLES(x) (((x) & 0xf) << 4) 476 #define N25Q_VCR_XIP_DISABLED ((uint8_t)0x1 << 3) 477 #define N25Q_VCR_WRAP_CONT 0x3 478 479 /* N25Q 3-byte Address READ configurations 480 * - 'FAST' variants configured for 8 dummy cycles. 481 * 482 * Note, the number of dummy cycles used for 'FAST' READ operations is 483 * configurable and would normally be tuned according to the READ command and 484 * operating frequency. However, this applies universally to all 'FAST' READ 485 * commands, including those used by the SPIBoot controller, and remains in 486 * force until the device is power-cycled. Since the SPIBoot controller is 487 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8 488 * cycles. 489 */ 490 static struct seq_rw_config n25q_read3_configs[] = { 491 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4, 0, 4, 4, 0x00, 0, 8}, 492 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4, 0, 1, 4, 0x00, 0, 8}, 493 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2, 0, 2, 2, 0x00, 0, 8}, 494 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2, 0, 1, 2, 0x00, 0, 8}, 495 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST, 0, 1, 1, 0x00, 0, 8}, 496 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ, 0, 1, 1, 0x00, 0, 0}, 497 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 498 }; 499 500 /* N25Q 4-byte Address READ configurations 501 * - use special 4-byte address READ commands (reduces overheads, and 502 * reduces risk of hitting watchdog reset issues). 503 * - 'FAST' variants configured for 8 dummy cycles (see note above.) 504 */ 505 static struct seq_rw_config n25q_read4_configs[] = { 506 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8}, 507 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8}, 508 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8}, 509 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8}, 510 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8}, 511 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0}, 512 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 513 }; 514 515 /* 516 * [MX25xxx] Configuration 517 */ 518 #define MX25_STATUS_QE (0x1 << 6) 519 520 static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq) 521 { 522 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 523 SEQ_OPC_CYCLES(8) | 524 SEQ_OPC_OPCODE(SPINOR_OP_EN4B) | 525 SEQ_OPC_CSDEASSERT); 526 527 seq->seq[0] = STFSM_INST_CMD1; 528 seq->seq[1] = STFSM_INST_WAIT; 529 seq->seq[2] = STFSM_INST_STOP; 530 531 seq->seq_cfg = (SEQ_CFG_PADS_1 | 532 SEQ_CFG_ERASE | 533 SEQ_CFG_READNOTWRITE | 534 SEQ_CFG_CSDEASSERT | 535 SEQ_CFG_STARTSEQ); 536 537 return 0; 538 } 539 540 /* 541 * [S25FLxxx] Configuration 542 */ 543 #define STFSM_S25FL_CONFIG_QE (0x1 << 1) 544 545 /* 546 * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank 547 * Register, Extended Address Modes, and a 32-bit address command set. The 548 * 32-bit address command set is used here, since it avoids any problems with 549 * entering a state that is incompatible with the SPIBoot Controller. 550 */ 551 static struct seq_rw_config stfsm_s25fl_read4_configs[] = { 552 {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4}, 553 {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8}, 554 {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0}, 555 {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8}, 556 {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8}, 557 {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0}, 558 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 559 }; 560 561 static struct seq_rw_config stfsm_s25fl_write4_configs[] = { 562 {FLASH_FLAG_WRITE_1_1_4, S25FL_CMD_WRITE4_1_1_4, 1, 1, 4, 0x00, 0, 0}, 563 {FLASH_FLAG_READ_WRITE, S25FL_CMD_WRITE4, 1, 1, 1, 0x00, 0, 0}, 564 {0x00, 0, 0, 0, 0, 0x00, 0, 0}, 565 }; 566 567 /* 568 * [W25Qxxx] Configuration 569 */ 570 #define W25Q_STATUS_QE (0x1 << 1) 571 572 static struct stfsm_seq stfsm_seq_read_jedec = { 573 .data_size = TRANSFER_SIZE(8), 574 .seq_opc[0] = (SEQ_OPC_PADS_1 | 575 SEQ_OPC_CYCLES(8) | 576 SEQ_OPC_OPCODE(SPINOR_OP_RDID)), 577 .seq = { 578 STFSM_INST_CMD1, 579 STFSM_INST_DATA_READ, 580 STFSM_INST_STOP, 581 }, 582 .seq_cfg = (SEQ_CFG_PADS_1 | 583 SEQ_CFG_READNOTWRITE | 584 SEQ_CFG_CSDEASSERT | 585 SEQ_CFG_STARTSEQ), 586 }; 587 588 static struct stfsm_seq stfsm_seq_read_status_fifo = { 589 .data_size = TRANSFER_SIZE(4), 590 .seq_opc[0] = (SEQ_OPC_PADS_1 | 591 SEQ_OPC_CYCLES(8) | 592 SEQ_OPC_OPCODE(SPINOR_OP_RDSR)), 593 .seq = { 594 STFSM_INST_CMD1, 595 STFSM_INST_DATA_READ, 596 STFSM_INST_STOP, 597 }, 598 .seq_cfg = (SEQ_CFG_PADS_1 | 599 SEQ_CFG_READNOTWRITE | 600 SEQ_CFG_CSDEASSERT | 601 SEQ_CFG_STARTSEQ), 602 }; 603 604 static struct stfsm_seq stfsm_seq_erase_sector = { 605 /* 'addr_cfg' configured during initialisation */ 606 .seq_opc = { 607 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 608 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 609 610 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 611 SEQ_OPC_OPCODE(SPINOR_OP_SE)), 612 }, 613 .seq = { 614 STFSM_INST_CMD1, 615 STFSM_INST_CMD2, 616 STFSM_INST_ADD1, 617 STFSM_INST_ADD2, 618 STFSM_INST_STOP, 619 }, 620 .seq_cfg = (SEQ_CFG_PADS_1 | 621 SEQ_CFG_READNOTWRITE | 622 SEQ_CFG_CSDEASSERT | 623 SEQ_CFG_STARTSEQ), 624 }; 625 626 static struct stfsm_seq stfsm_seq_erase_chip = { 627 .seq_opc = { 628 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 629 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 630 631 (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 632 SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT), 633 }, 634 .seq = { 635 STFSM_INST_CMD1, 636 STFSM_INST_CMD2, 637 STFSM_INST_WAIT, 638 STFSM_INST_STOP, 639 }, 640 .seq_cfg = (SEQ_CFG_PADS_1 | 641 SEQ_CFG_ERASE | 642 SEQ_CFG_READNOTWRITE | 643 SEQ_CFG_CSDEASSERT | 644 SEQ_CFG_STARTSEQ), 645 }; 646 647 static struct stfsm_seq stfsm_seq_write_status = { 648 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 649 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT), 650 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 651 SEQ_OPC_OPCODE(SPINOR_OP_WRSR)), 652 .seq = { 653 STFSM_INST_CMD1, 654 STFSM_INST_CMD2, 655 STFSM_INST_STA_WR1, 656 STFSM_INST_STOP, 657 }, 658 .seq_cfg = (SEQ_CFG_PADS_1 | 659 SEQ_CFG_READNOTWRITE | 660 SEQ_CFG_CSDEASSERT | 661 SEQ_CFG_STARTSEQ), 662 }; 663 664 /* Dummy sequence to read one byte of data from flash into the FIFO */ 665 static const struct stfsm_seq stfsm_seq_load_fifo_byte = { 666 .data_size = TRANSFER_SIZE(1), 667 .seq_opc[0] = (SEQ_OPC_PADS_1 | 668 SEQ_OPC_CYCLES(8) | 669 SEQ_OPC_OPCODE(SPINOR_OP_RDID)), 670 .seq = { 671 STFSM_INST_CMD1, 672 STFSM_INST_DATA_READ, 673 STFSM_INST_STOP, 674 }, 675 .seq_cfg = (SEQ_CFG_PADS_1 | 676 SEQ_CFG_READNOTWRITE | 677 SEQ_CFG_CSDEASSERT | 678 SEQ_CFG_STARTSEQ), 679 }; 680 681 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq) 682 { 683 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 684 SEQ_OPC_OPCODE(SPINOR_OP_EN4B)); 685 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 686 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 687 SEQ_OPC_CSDEASSERT); 688 689 seq->seq[0] = STFSM_INST_CMD2; 690 seq->seq[1] = STFSM_INST_CMD1; 691 seq->seq[2] = STFSM_INST_WAIT; 692 seq->seq[3] = STFSM_INST_STOP; 693 694 seq->seq_cfg = (SEQ_CFG_PADS_1 | 695 SEQ_CFG_ERASE | 696 SEQ_CFG_READNOTWRITE | 697 SEQ_CFG_CSDEASSERT | 698 SEQ_CFG_STARTSEQ); 699 700 return 0; 701 } 702 703 static inline int stfsm_is_idle(struct stfsm *fsm) 704 { 705 return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10; 706 } 707 708 static inline uint32_t stfsm_fifo_available(struct stfsm *fsm) 709 { 710 return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f; 711 } 712 713 static inline void stfsm_load_seq(struct stfsm *fsm, 714 const struct stfsm_seq *seq) 715 { 716 void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE; 717 const uint32_t *src = (const uint32_t *)seq; 718 int words = sizeof(*seq) / sizeof(*src); 719 720 BUG_ON(!stfsm_is_idle(fsm)); 721 722 while (words--) { 723 writel(*src, dst); 724 src++; 725 dst += 4; 726 } 727 } 728 729 static void stfsm_wait_seq(struct stfsm *fsm) 730 { 731 unsigned long deadline; 732 int timeout = 0; 733 734 deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS); 735 736 while (!timeout) { 737 if (time_after_eq(jiffies, deadline)) 738 timeout = 1; 739 740 if (stfsm_is_idle(fsm)) 741 return; 742 743 cond_resched(); 744 } 745 746 dev_err(fsm->dev, "timeout on sequence completion\n"); 747 } 748 749 static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size) 750 { 751 uint32_t remaining = size >> 2; 752 uint32_t avail; 753 uint32_t words; 754 755 dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size); 756 757 BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3)); 758 759 while (remaining) { 760 for (;;) { 761 avail = stfsm_fifo_available(fsm); 762 if (avail) 763 break; 764 udelay(1); 765 } 766 words = min(avail, remaining); 767 remaining -= words; 768 769 readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 770 buf += words; 771 } 772 } 773 774 /* 775 * Clear the data FIFO 776 * 777 * Typically, this is only required during driver initialisation, where no 778 * assumptions can be made regarding the state of the FIFO. 779 * 780 * The process of clearing the FIFO is complicated by fact that while it is 781 * possible for the FIFO to contain an arbitrary number of bytes [1], the 782 * SPI_FAST_SEQ_STA register only reports the number of complete 32-bit words 783 * present. Furthermore, data can only be drained from the FIFO by reading 784 * complete 32-bit words. 785 * 786 * With this in mind, a two stage process is used to the clear the FIFO: 787 * 788 * 1. Read any complete 32-bit words from the FIFO, as reported by the 789 * SPI_FAST_SEQ_STA register. 790 * 791 * 2. Mop up any remaining bytes. At this point, it is not known if there 792 * are 0, 1, 2, or 3 bytes in the FIFO. To handle all cases, a dummy FSM 793 * sequence is used to load one byte at a time, until a complete 32-bit 794 * word is formed; at most, 4 bytes will need to be loaded. 795 * 796 * [1] It is theoretically possible for the FIFO to contain an arbitrary number 797 * of bits. However, since there are no known use-cases that leave 798 * incomplete bytes in the FIFO, only words and bytes are considered here. 799 */ 800 static void stfsm_clear_fifo(struct stfsm *fsm) 801 { 802 const struct stfsm_seq *seq = &stfsm_seq_load_fifo_byte; 803 uint32_t words, i; 804 805 /* 1. Clear any 32-bit words */ 806 words = stfsm_fifo_available(fsm); 807 if (words) { 808 for (i = 0; i < words; i++) 809 readl(fsm->base + SPI_FAST_SEQ_DATA_REG); 810 dev_dbg(fsm->dev, "cleared %d words from FIFO\n", words); 811 } 812 813 /* 814 * 2. Clear any remaining bytes 815 * - Load the FIFO, one byte at a time, until a complete 32-bit word 816 * is available. 817 */ 818 for (i = 0, words = 0; i < 4 && !words; i++) { 819 stfsm_load_seq(fsm, seq); 820 stfsm_wait_seq(fsm); 821 words = stfsm_fifo_available(fsm); 822 } 823 824 /* - A single word must be available now */ 825 if (words != 1) { 826 dev_err(fsm->dev, "failed to clear bytes from the data FIFO\n"); 827 return; 828 } 829 830 /* - Read the 32-bit word */ 831 readl(fsm->base + SPI_FAST_SEQ_DATA_REG); 832 833 dev_dbg(fsm->dev, "cleared %d byte(s) from the data FIFO\n", 4 - i); 834 } 835 836 static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf, 837 uint32_t size) 838 { 839 uint32_t words = size >> 2; 840 841 dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size); 842 843 BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3)); 844 845 writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words); 846 847 return size; 848 } 849 850 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter) 851 { 852 struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr; 853 uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 854 855 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 856 SEQ_OPC_CYCLES(8) | 857 SEQ_OPC_OPCODE(cmd) | 858 SEQ_OPC_CSDEASSERT); 859 860 stfsm_load_seq(fsm, seq); 861 862 stfsm_wait_seq(fsm); 863 864 return 0; 865 } 866 867 static uint8_t stfsm_wait_busy(struct stfsm *fsm) 868 { 869 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 870 unsigned long deadline; 871 uint32_t status; 872 int timeout = 0; 873 874 /* Use RDRS1 */ 875 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | 876 SEQ_OPC_CYCLES(8) | 877 SEQ_OPC_OPCODE(SPINOR_OP_RDSR)); 878 879 /* Load read_status sequence */ 880 stfsm_load_seq(fsm, seq); 881 882 /* 883 * Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS) 884 */ 885 deadline = jiffies + FLASH_MAX_BUSY_WAIT; 886 while (!timeout) { 887 if (time_after_eq(jiffies, deadline)) 888 timeout = 1; 889 890 stfsm_wait_seq(fsm); 891 892 stfsm_read_fifo(fsm, &status, 4); 893 894 if ((status & FLASH_STATUS_BUSY) == 0) 895 return 0; 896 897 if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) && 898 ((status & S25FL_STATUS_P_ERR) || 899 (status & S25FL_STATUS_E_ERR))) 900 return (uint8_t)(status & 0xff); 901 902 if (!timeout) 903 /* Restart */ 904 writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG); 905 906 cond_resched(); 907 } 908 909 dev_err(fsm->dev, "timeout on wait_busy\n"); 910 911 return FLASH_STATUS_TIMEOUT; 912 } 913 914 static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd, 915 uint8_t *data, int bytes) 916 { 917 struct stfsm_seq *seq = &stfsm_seq_read_status_fifo; 918 uint32_t tmp; 919 uint8_t *t = (uint8_t *)&tmp; 920 int i; 921 922 dev_dbg(fsm->dev, "read 'status' register [0x%02x], %d byte(s)\n", 923 cmd, bytes); 924 925 BUG_ON(bytes != 1 && bytes != 2); 926 927 seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 928 SEQ_OPC_OPCODE(cmd)), 929 930 stfsm_load_seq(fsm, seq); 931 932 stfsm_read_fifo(fsm, &tmp, 4); 933 934 for (i = 0; i < bytes; i++) 935 data[i] = t[i]; 936 937 stfsm_wait_seq(fsm); 938 939 return 0; 940 } 941 942 static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd, 943 uint16_t data, int bytes, int wait_busy) 944 { 945 struct stfsm_seq *seq = &stfsm_seq_write_status; 946 947 dev_dbg(fsm->dev, 948 "write 'status' register [0x%02x], %d byte(s), 0x%04x\n" 949 " %s wait-busy\n", cmd, bytes, data, wait_busy ? "with" : "no"); 950 951 BUG_ON(bytes != 1 && bytes != 2); 952 953 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 954 SEQ_OPC_OPCODE(cmd)); 955 956 seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT; 957 seq->seq[2] = (bytes == 1) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2; 958 959 stfsm_load_seq(fsm, seq); 960 961 stfsm_wait_seq(fsm); 962 963 if (wait_busy) 964 stfsm_wait_busy(fsm); 965 966 return 0; 967 } 968 969 /* 970 * SoC reset on 'boot-from-spi' systems 971 * 972 * Certain modes of operation cause the Flash device to enter a particular state 973 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit 974 * Addr' commands). On boot-from-spi systems, it is important to consider what 975 * happens if a warm reset occurs during this period. The SPIBoot controller 976 * assumes that Flash device is in its default reset state, 24-bit address mode, 977 * and ready to accept commands. This can be achieved using some form of 978 * on-board logic/controller to force a device POR in response to a SoC-level 979 * reset or by making use of the device reset signal if available (limited 980 * number of devices only). 981 * 982 * Failure to take such precautions can cause problems following a warm reset. 983 * For some operations (e.g. ERASE), there is little that can be done. For 984 * other modes of operation (e.g. 32-bit addressing), options are often 985 * available that can help minimise the window in which a reset could cause a 986 * problem. 987 * 988 */ 989 static bool stfsm_can_handle_soc_reset(struct stfsm *fsm) 990 { 991 /* Reset signal is available on the board and supported by the device */ 992 if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET) 993 return true; 994 995 /* Board-level logic forces a power-on-reset */ 996 if (fsm->reset_por) 997 return true; 998 999 /* Reset is not properly handled and may result in failure to reboot */ 1000 return false; 1001 } 1002 1003 /* Configure 'addr_cfg' according to addressing mode */ 1004 static void stfsm_prepare_erasesec_seq(struct stfsm *fsm, 1005 struct stfsm_seq *seq) 1006 { 1007 int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8; 1008 1009 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) | 1010 ADR_CFG_PADS_1_ADD1 | 1011 ADR_CFG_CYCLES_ADD2(16) | 1012 ADR_CFG_PADS_1_ADD2 | 1013 ADR_CFG_CSDEASSERT_ADD2); 1014 } 1015 1016 /* Search for preferred configuration based on available flags */ 1017 static struct seq_rw_config * 1018 stfsm_search_seq_rw_configs(struct stfsm *fsm, 1019 struct seq_rw_config cfgs[]) 1020 { 1021 struct seq_rw_config *config; 1022 int flags = fsm->info->flags; 1023 1024 for (config = cfgs; config->cmd != 0; config++) 1025 if ((config->flags & flags) == config->flags) 1026 return config; 1027 1028 return NULL; 1029 } 1030 1031 /* Prepare a READ/WRITE sequence according to configuration parameters */ 1032 static void stfsm_prepare_rw_seq(struct stfsm *fsm, 1033 struct stfsm_seq *seq, 1034 struct seq_rw_config *cfg) 1035 { 1036 int addr1_cycles, addr2_cycles; 1037 int i = 0; 1038 1039 memset(seq, 0, sizeof(*seq)); 1040 1041 /* Add READ/WRITE OPC */ 1042 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 1043 SEQ_OPC_CYCLES(8) | 1044 SEQ_OPC_OPCODE(cfg->cmd)); 1045 1046 /* Add WREN OPC for a WRITE sequence */ 1047 if (cfg->write) 1048 seq->seq_opc[i++] = (SEQ_OPC_PADS_1 | 1049 SEQ_OPC_CYCLES(8) | 1050 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 1051 SEQ_OPC_CSDEASSERT); 1052 1053 /* Address configuration (24 or 32-bit addresses) */ 1054 addr1_cycles = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8; 1055 addr1_cycles /= cfg->addr_pads; 1056 addr2_cycles = 16 / cfg->addr_pads; 1057 seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 | /* ADD1 cycles */ 1058 (cfg->addr_pads - 1) << 6 | /* ADD1 pads */ 1059 (addr2_cycles & 0x3f) << 16 | /* ADD2 cycles */ 1060 ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */ 1061 1062 /* Data/Sequence configuration */ 1063 seq->seq_cfg = ((cfg->data_pads - 1) << 16 | 1064 SEQ_CFG_STARTSEQ | 1065 SEQ_CFG_CSDEASSERT); 1066 if (!cfg->write) 1067 seq->seq_cfg |= SEQ_CFG_READNOTWRITE; 1068 1069 /* Mode configuration (no. of pads taken from addr cfg) */ 1070 seq->mode = ((cfg->mode_data & 0xff) << 0 | /* data */ 1071 (cfg->mode_cycles & 0x3f) << 16 | /* cycles */ 1072 (cfg->addr_pads - 1) << 22); /* pads */ 1073 1074 /* Dummy configuration (no. of pads taken from addr cfg) */ 1075 seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 | /* cycles */ 1076 (cfg->addr_pads - 1) << 22); /* pads */ 1077 1078 1079 /* Instruction sequence */ 1080 i = 0; 1081 if (cfg->write) 1082 seq->seq[i++] = STFSM_INST_CMD2; 1083 1084 seq->seq[i++] = STFSM_INST_CMD1; 1085 1086 seq->seq[i++] = STFSM_INST_ADD1; 1087 seq->seq[i++] = STFSM_INST_ADD2; 1088 1089 if (cfg->mode_cycles) 1090 seq->seq[i++] = STFSM_INST_MODE; 1091 1092 if (cfg->dummy_cycles) 1093 seq->seq[i++] = STFSM_INST_DUMMY; 1094 1095 seq->seq[i++] = 1096 cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ; 1097 seq->seq[i++] = STFSM_INST_STOP; 1098 } 1099 1100 static int stfsm_search_prepare_rw_seq(struct stfsm *fsm, 1101 struct stfsm_seq *seq, 1102 struct seq_rw_config *cfgs) 1103 { 1104 struct seq_rw_config *config; 1105 1106 config = stfsm_search_seq_rw_configs(fsm, cfgs); 1107 if (!config) { 1108 dev_err(fsm->dev, "failed to find suitable config\n"); 1109 return -EINVAL; 1110 } 1111 1112 stfsm_prepare_rw_seq(fsm, seq, config); 1113 1114 return 0; 1115 } 1116 1117 /* Prepare a READ/WRITE/ERASE 'default' sequences */ 1118 static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm) 1119 { 1120 uint32_t flags = fsm->info->flags; 1121 int ret; 1122 1123 /* Configure 'READ' sequence */ 1124 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1125 default_read_configs); 1126 if (ret) { 1127 dev_err(fsm->dev, 1128 "failed to prep READ sequence with flags [0x%08x]\n", 1129 flags); 1130 return ret; 1131 } 1132 1133 /* Configure 'WRITE' sequence */ 1134 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1135 default_write_configs); 1136 if (ret) { 1137 dev_err(fsm->dev, 1138 "failed to prep WRITE sequence with flags [0x%08x]\n", 1139 flags); 1140 return ret; 1141 } 1142 1143 /* Configure 'ERASE_SECTOR' sequence */ 1144 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1145 1146 return 0; 1147 } 1148 1149 static int stfsm_mx25_config(struct stfsm *fsm) 1150 { 1151 uint32_t flags = fsm->info->flags; 1152 uint32_t data_pads; 1153 uint8_t sta; 1154 int ret; 1155 bool soc_reset; 1156 1157 /* 1158 * Use default READ/WRITE sequences 1159 */ 1160 ret = stfsm_prepare_rwe_seqs_default(fsm); 1161 if (ret) 1162 return ret; 1163 1164 /* 1165 * Configure 32-bit Address Support 1166 */ 1167 if (flags & FLASH_FLAG_32BIT_ADDR) { 1168 /* Configure 'enter_32bitaddr' FSM sequence */ 1169 stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1170 1171 soc_reset = stfsm_can_handle_soc_reset(fsm); 1172 if (soc_reset || !fsm->booted_from_spi) 1173 /* If we can handle SoC resets, we enable 32-bit address 1174 * mode pervasively */ 1175 stfsm_enter_32bit_addr(fsm, 1); 1176 1177 else 1178 /* Else, enable/disable 32-bit addressing before/after 1179 * each operation */ 1180 fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR | 1181 CFG_WRITE_TOGGLE_32BIT_ADDR | 1182 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1183 } 1184 1185 /* Check status of 'QE' bit, update if required. */ 1186 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1); 1187 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1188 if (data_pads == 4) { 1189 if (!(sta & MX25_STATUS_QE)) { 1190 /* Set 'QE' */ 1191 sta |= MX25_STATUS_QE; 1192 1193 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); 1194 } 1195 } else { 1196 if (sta & MX25_STATUS_QE) { 1197 /* Clear 'QE' */ 1198 sta &= ~MX25_STATUS_QE; 1199 1200 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1); 1201 } 1202 } 1203 1204 return 0; 1205 } 1206 1207 static int stfsm_n25q_config(struct stfsm *fsm) 1208 { 1209 uint32_t flags = fsm->info->flags; 1210 uint8_t vcr; 1211 int ret = 0; 1212 bool soc_reset; 1213 1214 /* Configure 'READ' sequence */ 1215 if (flags & FLASH_FLAG_32BIT_ADDR) 1216 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1217 n25q_read4_configs); 1218 else 1219 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1220 n25q_read3_configs); 1221 if (ret) { 1222 dev_err(fsm->dev, 1223 "failed to prepare READ sequence with flags [0x%08x]\n", 1224 flags); 1225 return ret; 1226 } 1227 1228 /* Configure 'WRITE' sequence (default configs) */ 1229 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1230 default_write_configs); 1231 if (ret) { 1232 dev_err(fsm->dev, 1233 "preparing WRITE sequence using flags [0x%08x] failed\n", 1234 flags); 1235 return ret; 1236 } 1237 1238 /* * Configure 'ERASE_SECTOR' sequence */ 1239 stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector); 1240 1241 /* Configure 32-bit address support */ 1242 if (flags & FLASH_FLAG_32BIT_ADDR) { 1243 stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr); 1244 1245 soc_reset = stfsm_can_handle_soc_reset(fsm); 1246 if (soc_reset || !fsm->booted_from_spi) { 1247 /* 1248 * If we can handle SoC resets, we enable 32-bit 1249 * address mode pervasively 1250 */ 1251 stfsm_enter_32bit_addr(fsm, 1); 1252 } else { 1253 /* 1254 * If not, enable/disable for WRITE and ERASE 1255 * operations (READ uses special commands) 1256 */ 1257 fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR | 1258 CFG_ERASESEC_TOGGLE_32BIT_ADDR); 1259 } 1260 } 1261 1262 /* 1263 * Configure device to use 8 dummy cycles 1264 */ 1265 vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED | 1266 N25Q_VCR_WRAP_CONT); 1267 stfsm_write_status(fsm, N25Q_CMD_WRVCR, vcr, 1, 0); 1268 1269 return 0; 1270 } 1271 1272 static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq) 1273 { 1274 seq->seq_opc[1] = (SEQ_OPC_PADS_1 | 1275 SEQ_OPC_CYCLES(8) | 1276 SEQ_OPC_OPCODE(S25FL_CMD_SE4)); 1277 1278 seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1279 ADR_CFG_PADS_1_ADD1 | 1280 ADR_CFG_CYCLES_ADD2(16) | 1281 ADR_CFG_PADS_1_ADD2 | 1282 ADR_CFG_CSDEASSERT_ADD2); 1283 } 1284 1285 static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby) 1286 { 1287 uint32_t tmp; 1288 struct stfsm_seq seq = { 1289 .data_size = TRANSFER_SIZE(4), 1290 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1291 SEQ_OPC_CYCLES(8) | 1292 SEQ_OPC_OPCODE(S25FL_CMD_DYBRD)), 1293 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1294 ADR_CFG_PADS_1_ADD1 | 1295 ADR_CFG_CYCLES_ADD2(16) | 1296 ADR_CFG_PADS_1_ADD2), 1297 .addr1 = (offs >> 16) & 0xffff, 1298 .addr2 = offs & 0xffff, 1299 .seq = { 1300 STFSM_INST_CMD1, 1301 STFSM_INST_ADD1, 1302 STFSM_INST_ADD2, 1303 STFSM_INST_DATA_READ, 1304 STFSM_INST_STOP, 1305 }, 1306 .seq_cfg = (SEQ_CFG_PADS_1 | 1307 SEQ_CFG_READNOTWRITE | 1308 SEQ_CFG_CSDEASSERT | 1309 SEQ_CFG_STARTSEQ), 1310 }; 1311 1312 stfsm_load_seq(fsm, &seq); 1313 1314 stfsm_read_fifo(fsm, &tmp, 4); 1315 1316 *dby = (uint8_t)(tmp >> 24); 1317 1318 stfsm_wait_seq(fsm); 1319 } 1320 1321 static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby) 1322 { 1323 struct stfsm_seq seq = { 1324 .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1325 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | 1326 SEQ_OPC_CSDEASSERT), 1327 .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) | 1328 SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)), 1329 .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) | 1330 ADR_CFG_PADS_1_ADD1 | 1331 ADR_CFG_CYCLES_ADD2(16) | 1332 ADR_CFG_PADS_1_ADD2), 1333 .status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT, 1334 .addr1 = (offs >> 16) & 0xffff, 1335 .addr2 = offs & 0xffff, 1336 .seq = { 1337 STFSM_INST_CMD1, 1338 STFSM_INST_CMD2, 1339 STFSM_INST_ADD1, 1340 STFSM_INST_ADD2, 1341 STFSM_INST_STA_WR1, 1342 STFSM_INST_STOP, 1343 }, 1344 .seq_cfg = (SEQ_CFG_PADS_1 | 1345 SEQ_CFG_READNOTWRITE | 1346 SEQ_CFG_CSDEASSERT | 1347 SEQ_CFG_STARTSEQ), 1348 }; 1349 1350 stfsm_load_seq(fsm, &seq); 1351 stfsm_wait_seq(fsm); 1352 1353 stfsm_wait_busy(fsm); 1354 } 1355 1356 static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm) 1357 { 1358 struct stfsm_seq seq = { 1359 .seq_opc[0] = (SEQ_OPC_PADS_1 | 1360 SEQ_OPC_CYCLES(8) | 1361 SEQ_OPC_OPCODE(S25FL_CMD_CLSR) | 1362 SEQ_OPC_CSDEASSERT), 1363 .seq_opc[1] = (SEQ_OPC_PADS_1 | 1364 SEQ_OPC_CYCLES(8) | 1365 SEQ_OPC_OPCODE(SPINOR_OP_WRDI) | 1366 SEQ_OPC_CSDEASSERT), 1367 .seq = { 1368 STFSM_INST_CMD1, 1369 STFSM_INST_CMD2, 1370 STFSM_INST_WAIT, 1371 STFSM_INST_STOP, 1372 }, 1373 .seq_cfg = (SEQ_CFG_PADS_1 | 1374 SEQ_CFG_ERASE | 1375 SEQ_CFG_READNOTWRITE | 1376 SEQ_CFG_CSDEASSERT | 1377 SEQ_CFG_STARTSEQ), 1378 }; 1379 1380 stfsm_load_seq(fsm, &seq); 1381 1382 stfsm_wait_seq(fsm); 1383 1384 return 0; 1385 } 1386 1387 static int stfsm_s25fl_config(struct stfsm *fsm) 1388 { 1389 struct flash_info *info = fsm->info; 1390 uint32_t flags = info->flags; 1391 uint32_t data_pads; 1392 uint32_t offs; 1393 uint16_t sta_wr; 1394 uint8_t sr1, cr1, dyb; 1395 int update_sr = 0; 1396 int ret; 1397 1398 if (flags & FLASH_FLAG_32BIT_ADDR) { 1399 /* 1400 * Prepare Read/Write/Erase sequences according to S25FLxxx 1401 * 32-bit address command set 1402 */ 1403 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read, 1404 stfsm_s25fl_read4_configs); 1405 if (ret) 1406 return ret; 1407 1408 ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write, 1409 stfsm_s25fl_write4_configs); 1410 if (ret) 1411 return ret; 1412 1413 stfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector); 1414 1415 } else { 1416 /* Use default configurations for 24-bit addressing */ 1417 ret = stfsm_prepare_rwe_seqs_default(fsm); 1418 if (ret) 1419 return ret; 1420 } 1421 1422 /* 1423 * For devices that support 'DYB' sector locking, check lock status and 1424 * unlock sectors if necessary (some variants power-on with sectors 1425 * locked by default) 1426 */ 1427 if (flags & FLASH_FLAG_DYB_LOCKING) { 1428 offs = 0; 1429 for (offs = 0; offs < info->sector_size * info->n_sectors;) { 1430 stfsm_s25fl_read_dyb(fsm, offs, &dyb); 1431 if (dyb == 0x00) 1432 stfsm_s25fl_write_dyb(fsm, offs, 0xff); 1433 1434 /* Handle bottom/top 4KiB parameter sectors */ 1435 if ((offs < info->sector_size * 2) || 1436 (offs >= (info->sector_size - info->n_sectors * 4))) 1437 offs += 0x1000; 1438 else 1439 offs += 0x10000; 1440 } 1441 } 1442 1443 /* Check status of 'QE' bit, update if required. */ 1444 stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1); 1445 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1446 if (data_pads == 4) { 1447 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { 1448 /* Set 'QE' */ 1449 cr1 |= STFSM_S25FL_CONFIG_QE; 1450 1451 update_sr = 1; 1452 } 1453 } else { 1454 if (cr1 & STFSM_S25FL_CONFIG_QE) { 1455 /* Clear 'QE' */ 1456 cr1 &= ~STFSM_S25FL_CONFIG_QE; 1457 1458 update_sr = 1; 1459 } 1460 } 1461 if (update_sr) { 1462 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); 1463 sta_wr = ((uint16_t)cr1 << 8) | sr1; 1464 stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1); 1465 } 1466 1467 /* 1468 * S25FLxxx devices support Program and Error error flags. 1469 * Configure driver to check flags and clear if necessary. 1470 */ 1471 fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS; 1472 1473 return 0; 1474 } 1475 1476 static int stfsm_w25q_config(struct stfsm *fsm) 1477 { 1478 uint32_t data_pads; 1479 uint8_t sr1, sr2; 1480 uint16_t sr_wr; 1481 int update_sr = 0; 1482 int ret; 1483 1484 ret = stfsm_prepare_rwe_seqs_default(fsm); 1485 if (ret) 1486 return ret; 1487 1488 /* Check status of 'QE' bit, update if required. */ 1489 stfsm_read_status(fsm, SPINOR_OP_RDCR, &sr2, 1); 1490 data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1; 1491 if (data_pads == 4) { 1492 if (!(sr2 & W25Q_STATUS_QE)) { 1493 /* Set 'QE' */ 1494 sr2 |= W25Q_STATUS_QE; 1495 update_sr = 1; 1496 } 1497 } else { 1498 if (sr2 & W25Q_STATUS_QE) { 1499 /* Clear 'QE' */ 1500 sr2 &= ~W25Q_STATUS_QE; 1501 update_sr = 1; 1502 } 1503 } 1504 if (update_sr) { 1505 /* Write status register */ 1506 stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1); 1507 sr_wr = ((uint16_t)sr2 << 8) | sr1; 1508 stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1); 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size, 1515 uint32_t offset) 1516 { 1517 struct stfsm_seq *seq = &fsm->stfsm_seq_read; 1518 uint32_t data_pads; 1519 uint32_t read_mask; 1520 uint32_t size_ub; 1521 uint32_t size_lb; 1522 uint32_t size_mop; 1523 uint32_t tmp[4]; 1524 uint32_t page_buf[FLASH_PAGESIZE_32]; 1525 uint8_t *p; 1526 1527 dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset); 1528 1529 /* Enter 32-bit address mode, if required */ 1530 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1531 stfsm_enter_32bit_addr(fsm, 1); 1532 1533 /* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */ 1534 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1535 read_mask = (data_pads << 2) - 1; 1536 1537 /* Handle non-aligned buf */ 1538 p = ((uintptr_t)buf & 0x3) ? (uint8_t *)page_buf : buf; 1539 1540 /* Handle non-aligned size */ 1541 size_ub = (size + read_mask) & ~read_mask; 1542 size_lb = size & ~read_mask; 1543 size_mop = size & read_mask; 1544 1545 seq->data_size = TRANSFER_SIZE(size_ub); 1546 seq->addr1 = (offset >> 16) & 0xffff; 1547 seq->addr2 = offset & 0xffff; 1548 1549 stfsm_load_seq(fsm, seq); 1550 1551 if (size_lb) 1552 stfsm_read_fifo(fsm, (uint32_t *)p, size_lb); 1553 1554 if (size_mop) { 1555 stfsm_read_fifo(fsm, tmp, read_mask + 1); 1556 memcpy(p + size_lb, &tmp, size_mop); 1557 } 1558 1559 /* Handle non-aligned buf */ 1560 if ((uintptr_t)buf & 0x3) 1561 memcpy(buf, page_buf, size); 1562 1563 /* Wait for sequence to finish */ 1564 stfsm_wait_seq(fsm); 1565 1566 stfsm_clear_fifo(fsm); 1567 1568 /* Exit 32-bit address mode, if required */ 1569 if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR) 1570 stfsm_enter_32bit_addr(fsm, 0); 1571 1572 return 0; 1573 } 1574 1575 static int stfsm_write(struct stfsm *fsm, const uint8_t *buf, 1576 uint32_t size, uint32_t offset) 1577 { 1578 struct stfsm_seq *seq = &fsm->stfsm_seq_write; 1579 uint32_t data_pads; 1580 uint32_t write_mask; 1581 uint32_t size_ub; 1582 uint32_t size_lb; 1583 uint32_t size_mop; 1584 uint32_t tmp[4]; 1585 uint32_t i; 1586 uint32_t page_buf[FLASH_PAGESIZE_32]; 1587 uint8_t *t = (uint8_t *)&tmp; 1588 const uint8_t *p; 1589 int ret; 1590 1591 dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset); 1592 1593 /* Enter 32-bit address mode, if required */ 1594 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) 1595 stfsm_enter_32bit_addr(fsm, 1); 1596 1597 /* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */ 1598 data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1; 1599 write_mask = (data_pads << 2) - 1; 1600 1601 /* Handle non-aligned buf */ 1602 if ((uintptr_t)buf & 0x3) { 1603 memcpy(page_buf, buf, size); 1604 p = (uint8_t *)page_buf; 1605 } else { 1606 p = buf; 1607 } 1608 1609 /* Handle non-aligned size */ 1610 size_ub = (size + write_mask) & ~write_mask; 1611 size_lb = size & ~write_mask; 1612 size_mop = size & write_mask; 1613 1614 seq->data_size = TRANSFER_SIZE(size_ub); 1615 seq->addr1 = (offset >> 16) & 0xffff; 1616 seq->addr2 = offset & 0xffff; 1617 1618 /* Need to set FIFO to write mode, before writing data to FIFO (see 1619 * GNBvb79594) 1620 */ 1621 writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG); 1622 1623 /* 1624 * Before writing data to the FIFO, apply a small delay to allow a 1625 * potential change of FIFO direction to complete. 1626 */ 1627 if (fsm->fifo_dir_delay == 0) 1628 readl(fsm->base + SPI_FAST_SEQ_CFG); 1629 else 1630 udelay(fsm->fifo_dir_delay); 1631 1632 1633 /* Write data to FIFO, before starting sequence (see GNBvd79593) */ 1634 if (size_lb) { 1635 stfsm_write_fifo(fsm, (uint32_t *)p, size_lb); 1636 p += size_lb; 1637 } 1638 1639 /* Handle non-aligned size */ 1640 if (size_mop) { 1641 memset(t, 0xff, write_mask + 1); /* fill with 0xff's */ 1642 for (i = 0; i < size_mop; i++) 1643 t[i] = *p++; 1644 1645 stfsm_write_fifo(fsm, tmp, write_mask + 1); 1646 } 1647 1648 /* Start sequence */ 1649 stfsm_load_seq(fsm, seq); 1650 1651 /* Wait for sequence to finish */ 1652 stfsm_wait_seq(fsm); 1653 1654 /* Wait for completion */ 1655 ret = stfsm_wait_busy(fsm); 1656 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1657 stfsm_s25fl_clear_status_reg(fsm); 1658 1659 /* Exit 32-bit address mode, if required */ 1660 if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR) 1661 stfsm_enter_32bit_addr(fsm, 0); 1662 1663 return 0; 1664 } 1665 1666 /* 1667 * Read an address range from the flash chip. The address range 1668 * may be any size provided it is within the physical boundaries. 1669 */ 1670 static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, 1671 size_t *retlen, u_char *buf) 1672 { 1673 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1674 uint32_t bytes; 1675 1676 dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n", 1677 __func__, (u32)from, len); 1678 1679 mutex_lock(&fsm->lock); 1680 1681 while (len > 0) { 1682 bytes = min_t(size_t, len, FLASH_PAGESIZE); 1683 1684 stfsm_read(fsm, buf, bytes, from); 1685 1686 buf += bytes; 1687 from += bytes; 1688 len -= bytes; 1689 1690 *retlen += bytes; 1691 } 1692 1693 mutex_unlock(&fsm->lock); 1694 1695 return 0; 1696 } 1697 1698 static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset) 1699 { 1700 struct stfsm_seq *seq = &stfsm_seq_erase_sector; 1701 int ret; 1702 1703 dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset); 1704 1705 /* Enter 32-bit address mode, if required */ 1706 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1707 stfsm_enter_32bit_addr(fsm, 1); 1708 1709 seq->addr1 = (offset >> 16) & 0xffff; 1710 seq->addr2 = offset & 0xffff; 1711 1712 stfsm_load_seq(fsm, seq); 1713 1714 stfsm_wait_seq(fsm); 1715 1716 /* Wait for completion */ 1717 ret = stfsm_wait_busy(fsm); 1718 if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) 1719 stfsm_s25fl_clear_status_reg(fsm); 1720 1721 /* Exit 32-bit address mode, if required */ 1722 if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR) 1723 stfsm_enter_32bit_addr(fsm, 0); 1724 1725 return ret; 1726 } 1727 1728 static int stfsm_erase_chip(struct stfsm *fsm) 1729 { 1730 const struct stfsm_seq *seq = &stfsm_seq_erase_chip; 1731 1732 dev_dbg(fsm->dev, "erasing chip\n"); 1733 1734 stfsm_load_seq(fsm, seq); 1735 1736 stfsm_wait_seq(fsm); 1737 1738 return stfsm_wait_busy(fsm); 1739 } 1740 1741 /* 1742 * Write an address range to the flash chip. Data must be written in 1743 * FLASH_PAGESIZE chunks. The address range may be any size provided 1744 * it is within the physical boundaries. 1745 */ 1746 static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, 1747 size_t *retlen, const u_char *buf) 1748 { 1749 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1750 1751 u32 page_offs; 1752 u32 bytes; 1753 uint8_t *b = (uint8_t *)buf; 1754 int ret = 0; 1755 1756 dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len); 1757 1758 /* Offset within page */ 1759 page_offs = to % FLASH_PAGESIZE; 1760 1761 mutex_lock(&fsm->lock); 1762 1763 while (len) { 1764 /* Write up to page boundary */ 1765 bytes = min_t(size_t, FLASH_PAGESIZE - page_offs, len); 1766 1767 ret = stfsm_write(fsm, b, bytes, to); 1768 if (ret) 1769 goto out1; 1770 1771 b += bytes; 1772 len -= bytes; 1773 to += bytes; 1774 1775 /* We are now page-aligned */ 1776 page_offs = 0; 1777 1778 *retlen += bytes; 1779 1780 } 1781 1782 out1: 1783 mutex_unlock(&fsm->lock); 1784 1785 return ret; 1786 } 1787 1788 /* 1789 * Erase an address range on the flash chip. The address range may extend 1790 * one or more erase sectors. Return an error is there is a problem erasing. 1791 */ 1792 static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) 1793 { 1794 struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent); 1795 u32 addr, len; 1796 int ret; 1797 1798 dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__, 1799 (long long)instr->addr, (long long)instr->len); 1800 1801 addr = instr->addr; 1802 len = instr->len; 1803 1804 mutex_lock(&fsm->lock); 1805 1806 /* Whole-chip erase? */ 1807 if (len == mtd->size) { 1808 ret = stfsm_erase_chip(fsm); 1809 if (ret) 1810 goto out1; 1811 } else { 1812 while (len) { 1813 ret = stfsm_erase_sector(fsm, addr); 1814 if (ret) 1815 goto out1; 1816 1817 addr += mtd->erasesize; 1818 len -= mtd->erasesize; 1819 } 1820 } 1821 1822 mutex_unlock(&fsm->lock); 1823 1824 return 0; 1825 1826 out1: 1827 mutex_unlock(&fsm->lock); 1828 1829 return ret; 1830 } 1831 1832 static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec) 1833 { 1834 const struct stfsm_seq *seq = &stfsm_seq_read_jedec; 1835 uint32_t tmp[2]; 1836 1837 stfsm_load_seq(fsm, seq); 1838 1839 stfsm_read_fifo(fsm, tmp, 8); 1840 1841 memcpy(jedec, tmp, 5); 1842 1843 stfsm_wait_seq(fsm); 1844 } 1845 1846 static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm) 1847 { 1848 struct flash_info *info; 1849 u16 ext_jedec; 1850 u32 jedec; 1851 u8 id[5]; 1852 1853 stfsm_read_jedec(fsm, id); 1854 1855 jedec = id[0] << 16 | id[1] << 8 | id[2]; 1856 /* 1857 * JEDEC also defines an optional "extended device information" 1858 * string for after vendor-specific data, after the three bytes 1859 * we use here. Supporting some chips might require using it. 1860 */ 1861 ext_jedec = id[3] << 8 | id[4]; 1862 1863 dev_dbg(fsm->dev, "JEDEC = 0x%08x [%5ph]\n", jedec, id); 1864 1865 for (info = flash_types; info->name; info++) { 1866 if (info->jedec_id == jedec) { 1867 if (info->ext_id && info->ext_id != ext_jedec) 1868 continue; 1869 return info; 1870 } 1871 } 1872 dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec); 1873 1874 return NULL; 1875 } 1876 1877 static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode) 1878 { 1879 int ret, timeout = 10; 1880 1881 /* Wait for controller to accept mode change */ 1882 while (--timeout) { 1883 ret = readl(fsm->base + SPI_STA_MODE_CHANGE); 1884 if (ret & 0x1) 1885 break; 1886 udelay(1); 1887 } 1888 1889 if (!timeout) 1890 return -EBUSY; 1891 1892 writel(mode, fsm->base + SPI_MODESELECT); 1893 1894 return 0; 1895 } 1896 1897 static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq) 1898 { 1899 uint32_t emi_freq; 1900 uint32_t clk_div; 1901 1902 emi_freq = clk_get_rate(fsm->clk); 1903 1904 /* 1905 * Calculate clk_div - values between 2 and 128 1906 * Multiple of 2, rounded up 1907 */ 1908 clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq); 1909 if (clk_div < 2) 1910 clk_div = 2; 1911 else if (clk_div > 128) 1912 clk_div = 128; 1913 1914 /* 1915 * Determine a suitable delay for the IP to complete a change of 1916 * direction of the FIFO. The required delay is related to the clock 1917 * divider used. The following heuristics are based on empirical tests, 1918 * using a 100MHz EMI clock. 1919 */ 1920 if (clk_div <= 4) 1921 fsm->fifo_dir_delay = 0; 1922 else if (clk_div <= 10) 1923 fsm->fifo_dir_delay = 1; 1924 else 1925 fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10); 1926 1927 dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n", 1928 emi_freq, spi_freq, clk_div); 1929 1930 writel(clk_div, fsm->base + SPI_CLOCKDIV); 1931 } 1932 1933 static int stfsm_init(struct stfsm *fsm) 1934 { 1935 int ret; 1936 1937 /* Perform a soft reset of the FSM controller */ 1938 writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG); 1939 udelay(1); 1940 writel(0, fsm->base + SPI_FAST_SEQ_CFG); 1941 1942 /* Set clock to 'safe' frequency initially */ 1943 stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ); 1944 1945 /* Switch to FSM */ 1946 ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM); 1947 if (ret) 1948 return ret; 1949 1950 /* Set timing parameters */ 1951 writel(SPI_CFG_DEVICE_ST | 1952 SPI_CFG_DEFAULT_MIN_CS_HIGH | 1953 SPI_CFG_DEFAULT_CS_SETUPHOLD | 1954 SPI_CFG_DEFAULT_DATA_HOLD, 1955 fsm->base + SPI_CONFIGDATA); 1956 writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG); 1957 1958 /* 1959 * Set the FSM 'WAIT' delay to the minimum workable value. Note, for 1960 * our purposes, the WAIT instruction is used purely to achieve 1961 * "sequence validity" rather than actually implement a delay. 1962 */ 1963 writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME); 1964 1965 /* Clear FIFO, just in case */ 1966 stfsm_clear_fifo(fsm); 1967 1968 return 0; 1969 } 1970 1971 static void stfsm_fetch_platform_configs(struct platform_device *pdev) 1972 { 1973 struct stfsm *fsm = platform_get_drvdata(pdev); 1974 struct device_node *np = pdev->dev.of_node; 1975 struct regmap *regmap; 1976 uint32_t boot_device_reg; 1977 uint32_t boot_device_spi; 1978 uint32_t boot_device; /* Value we read from *boot_device_reg */ 1979 int ret; 1980 1981 /* Booting from SPI NOR Flash is the default */ 1982 fsm->booted_from_spi = true; 1983 1984 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1985 if (IS_ERR(regmap)) 1986 goto boot_device_fail; 1987 1988 fsm->reset_signal = of_property_read_bool(np, "st,reset-signal"); 1989 1990 fsm->reset_por = of_property_read_bool(np, "st,reset-por"); 1991 1992 /* Where in the syscon the boot device information lives */ 1993 ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg); 1994 if (ret) 1995 goto boot_device_fail; 1996 1997 /* Boot device value when booted from SPI NOR */ 1998 ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi); 1999 if (ret) 2000 goto boot_device_fail; 2001 2002 ret = regmap_read(regmap, boot_device_reg, &boot_device); 2003 if (ret) 2004 goto boot_device_fail; 2005 2006 if (boot_device != boot_device_spi) 2007 fsm->booted_from_spi = false; 2008 2009 return; 2010 2011 boot_device_fail: 2012 dev_warn(&pdev->dev, 2013 "failed to fetch boot device, assuming boot from SPI\n"); 2014 } 2015 2016 static int stfsm_probe(struct platform_device *pdev) 2017 { 2018 struct device_node *np = pdev->dev.of_node; 2019 struct flash_info *info; 2020 struct resource *res; 2021 struct stfsm *fsm; 2022 int ret; 2023 2024 if (!np) { 2025 dev_err(&pdev->dev, "No DT found\n"); 2026 return -EINVAL; 2027 } 2028 2029 fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL); 2030 if (!fsm) 2031 return -ENOMEM; 2032 2033 fsm->dev = &pdev->dev; 2034 2035 platform_set_drvdata(pdev, fsm); 2036 2037 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2038 if (!res) { 2039 dev_err(&pdev->dev, "Resource not found\n"); 2040 return -ENODEV; 2041 } 2042 2043 fsm->base = devm_ioremap_resource(&pdev->dev, res); 2044 if (IS_ERR(fsm->base)) { 2045 dev_err(&pdev->dev, 2046 "Failed to reserve memory region %pR\n", res); 2047 return PTR_ERR(fsm->base); 2048 } 2049 2050 fsm->clk = devm_clk_get(&pdev->dev, NULL); 2051 if (IS_ERR(fsm->clk)) { 2052 dev_err(fsm->dev, "Couldn't find EMI clock.\n"); 2053 return PTR_ERR(fsm->clk); 2054 } 2055 2056 ret = clk_prepare_enable(fsm->clk); 2057 if (ret) { 2058 dev_err(fsm->dev, "Failed to enable EMI clock.\n"); 2059 return ret; 2060 } 2061 2062 mutex_init(&fsm->lock); 2063 2064 ret = stfsm_init(fsm); 2065 if (ret) { 2066 dev_err(&pdev->dev, "Failed to initialise FSM Controller\n"); 2067 goto err_clk_unprepare; 2068 } 2069 2070 stfsm_fetch_platform_configs(pdev); 2071 2072 /* Detect SPI FLASH device */ 2073 info = stfsm_jedec_probe(fsm); 2074 if (!info) { 2075 ret = -ENODEV; 2076 goto err_clk_unprepare; 2077 } 2078 fsm->info = info; 2079 2080 /* Use device size to determine address width */ 2081 if (info->sector_size * info->n_sectors > 0x1000000) 2082 info->flags |= FLASH_FLAG_32BIT_ADDR; 2083 2084 /* 2085 * Configure READ/WRITE/ERASE sequences according to platform and 2086 * device flags. 2087 */ 2088 if (info->config) { 2089 ret = info->config(fsm); 2090 if (ret) 2091 goto err_clk_unprepare; 2092 } else { 2093 ret = stfsm_prepare_rwe_seqs_default(fsm); 2094 if (ret) 2095 goto err_clk_unprepare; 2096 } 2097 2098 fsm->mtd.name = info->name; 2099 fsm->mtd.dev.parent = &pdev->dev; 2100 mtd_set_of_node(&fsm->mtd, np); 2101 fsm->mtd.type = MTD_NORFLASH; 2102 fsm->mtd.writesize = 4; 2103 fsm->mtd.writebufsize = fsm->mtd.writesize; 2104 fsm->mtd.flags = MTD_CAP_NORFLASH; 2105 fsm->mtd.size = info->sector_size * info->n_sectors; 2106 fsm->mtd.erasesize = info->sector_size; 2107 2108 fsm->mtd._read = stfsm_mtd_read; 2109 fsm->mtd._write = stfsm_mtd_write; 2110 fsm->mtd._erase = stfsm_mtd_erase; 2111 2112 dev_info(&pdev->dev, 2113 "Found serial flash device: %s\n" 2114 " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n", 2115 info->name, 2116 (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20), 2117 fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10)); 2118 2119 return mtd_device_register(&fsm->mtd, NULL, 0); 2120 2121 err_clk_unprepare: 2122 clk_disable_unprepare(fsm->clk); 2123 return ret; 2124 } 2125 2126 static int stfsm_remove(struct platform_device *pdev) 2127 { 2128 struct stfsm *fsm = platform_get_drvdata(pdev); 2129 2130 return mtd_device_unregister(&fsm->mtd); 2131 } 2132 2133 #ifdef CONFIG_PM_SLEEP 2134 static int stfsmfsm_suspend(struct device *dev) 2135 { 2136 struct stfsm *fsm = dev_get_drvdata(dev); 2137 2138 clk_disable_unprepare(fsm->clk); 2139 2140 return 0; 2141 } 2142 2143 static int stfsmfsm_resume(struct device *dev) 2144 { 2145 struct stfsm *fsm = dev_get_drvdata(dev); 2146 2147 return clk_prepare_enable(fsm->clk); 2148 } 2149 #endif 2150 2151 static SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume); 2152 2153 static const struct of_device_id stfsm_match[] = { 2154 { .compatible = "st,spi-fsm", }, 2155 {}, 2156 }; 2157 MODULE_DEVICE_TABLE(of, stfsm_match); 2158 2159 static struct platform_driver stfsm_driver = { 2160 .probe = stfsm_probe, 2161 .remove = stfsm_remove, 2162 .driver = { 2163 .name = "st-spi-fsm", 2164 .of_match_table = stfsm_match, 2165 .pm = &stfsm_pm_ops, 2166 }, 2167 }; 2168 module_platform_driver(stfsm_driver); 2169 2170 MODULE_AUTHOR("Angus Clark <angus.clark@st.com>"); 2171 MODULE_DESCRIPTION("ST SPI FSM driver"); 2172 MODULE_LICENSE("GPL"); 2173