1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2019-2025, Intel Corporation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/cleanup.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/intel_dg_nvm_aux.h> 12 #include <linux/io.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/partitions.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/string.h> 20 #include <linux/slab.h> 21 #include <linux/sizes.h> 22 #include <linux/types.h> 23 24 #define INTEL_DG_NVM_RPM_TIMEOUT_MS 500 25 26 struct intel_dg_nvm { 27 struct kref refcnt; 28 struct mtd_info mtd; 29 struct device *dev; 30 struct mutex lock; /* region access lock */ 31 void __iomem *base; 32 void __iomem *base2; 33 bool non_posted_erase; 34 35 size_t size; 36 unsigned int nregions; 37 struct { 38 const char *name; 39 u8 id; 40 u64 offset; 41 u64 size; 42 unsigned int is_readable:1; 43 unsigned int is_writable:1; 44 } regions[] __counted_by(nregions); 45 }; 46 47 #define NVM_TRIGGER_REG 0x00000000 48 #define NVM_VALSIG_REG 0x00000010 49 #define NVM_ADDRESS_REG 0x00000040 50 #define NVM_REGION_ID_REG 0x00000044 51 #define NVM_DEBUG_REG 0x00000000 52 /* 53 * [15:0]-Erase size = 0x0010 4K 0x0080 32K 0x0100 64K 54 * [23:16]-Reserved 55 * [31:24]-Erase MEM RegionID 56 */ 57 #define NVM_ERASE_REG 0x00000048 58 #define NVM_ACCESS_ERROR_REG 0x00000070 59 #define NVM_ADDRESS_ERROR_REG 0x00000074 60 61 /* Flash Valid Signature */ 62 #define NVM_FLVALSIG 0x0FF0A55A 63 64 #define NVM_MAP_ADDR_MASK GENMASK(7, 0) 65 #define NVM_MAP_ADDR_SHIFT 0x00000004 66 67 #define NVM_REGION_ID_DESCRIPTOR 0 68 /* Flash Region Base Address */ 69 #define NVM_FRBA 0x40 70 /* Flash Region __n - Flash Descriptor Record */ 71 #define NVM_FLREG(__n) (NVM_FRBA + ((__n) * 4)) 72 /* Flash Map 1 Register */ 73 #define NVM_FLMAP1_REG 0x18 74 #define NVM_FLMSTR4_OFFSET 0x00C 75 76 #define NVM_ACCESS_ERROR_PCIE_MASK 0x7 77 78 #define NVM_FREG_BASE_MASK GENMASK(15, 0) 79 #define NVM_FREG_ADDR_MASK GENMASK(31, 16) 80 #define NVM_FREG_ADDR_SHIFT 12 81 #define NVM_FREG_MIN_REGION_SIZE 0xFFF 82 83 #define NVM_NON_POSTED_ERASE_DONE BIT(23) 84 #define NVM_NON_POSTED_ERASE_DONE_ITER 3000 85 86 static inline void idg_nvm_set_region_id(struct intel_dg_nvm *nvm, u8 region) 87 { 88 iowrite32((u32)region, nvm->base + NVM_REGION_ID_REG); 89 } 90 91 static inline u32 idg_nvm_error(struct intel_dg_nvm *nvm) 92 { 93 void __iomem *base = nvm->base; 94 95 u32 reg = ioread32(base + NVM_ACCESS_ERROR_REG) & NVM_ACCESS_ERROR_PCIE_MASK; 96 97 /* reset error bits */ 98 if (reg) 99 iowrite32(reg, base + NVM_ACCESS_ERROR_REG); 100 101 return reg; 102 } 103 104 static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address) 105 { 106 void __iomem *base = nvm->base; 107 108 iowrite32(address, base + NVM_ADDRESS_REG); 109 110 return ioread32(base + NVM_TRIGGER_REG); 111 } 112 113 static inline u64 idg_nvm_read64(struct intel_dg_nvm *nvm, u32 address) 114 { 115 void __iomem *base = nvm->base; 116 117 iowrite32(address, base + NVM_ADDRESS_REG); 118 119 return readq(base + NVM_TRIGGER_REG); 120 } 121 122 static void idg_nvm_write32(struct intel_dg_nvm *nvm, u32 address, u32 data) 123 { 124 void __iomem *base = nvm->base; 125 126 iowrite32(address, base + NVM_ADDRESS_REG); 127 128 iowrite32(data, base + NVM_TRIGGER_REG); 129 } 130 131 static void idg_nvm_write64(struct intel_dg_nvm *nvm, u32 address, u64 data) 132 { 133 void __iomem *base = nvm->base; 134 135 iowrite32(address, base + NVM_ADDRESS_REG); 136 137 writeq(data, base + NVM_TRIGGER_REG); 138 } 139 140 static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_map) 141 { 142 u32 fmstr4_addr; 143 u32 fmstr4; 144 u32 flmap1; 145 u32 fmba; 146 147 idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR); 148 149 flmap1 = idg_nvm_read32(nvm, NVM_FLMAP1_REG); 150 if (idg_nvm_error(nvm)) 151 return -EIO; 152 /* Get Flash Master Baser Address (FMBA) */ 153 fmba = (FIELD_GET(NVM_MAP_ADDR_MASK, flmap1) << NVM_MAP_ADDR_SHIFT); 154 fmstr4_addr = fmba + NVM_FLMSTR4_OFFSET; 155 156 fmstr4 = idg_nvm_read32(nvm, fmstr4_addr); 157 if (idg_nvm_error(nvm)) 158 return -EIO; 159 160 *access_map = fmstr4; 161 return 0; 162 } 163 164 /* 165 * Region read/write access encoded in the access map 166 * in the following order from the lower bit: 167 * [3:0] regions 12-15 read state 168 * [7:4] regions 12-15 write state 169 * [19:8] regions 0-11 read state 170 * [31:20] regions 0-11 write state 171 */ 172 static bool idg_nvm_region_readable(u32 access_map, u8 region) 173 { 174 if (region < 12) 175 return access_map & BIT(region + 8); /* [19:8] */ 176 else 177 return access_map & BIT(region - 12); /* [3:0] */ 178 } 179 180 static bool idg_nvm_region_writable(u32 access_map, u8 region) 181 { 182 if (region < 12) 183 return access_map & BIT(region + 20); /* [31:20] */ 184 else 185 return access_map & BIT(region - 8); /* [7:4] */ 186 } 187 188 static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) 189 { 190 u32 is_valid; 191 192 idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR); 193 194 is_valid = idg_nvm_read32(nvm, NVM_VALSIG_REG); 195 if (idg_nvm_error(nvm)) 196 return -EIO; 197 198 if (is_valid != NVM_FLVALSIG) 199 return -ENODEV; 200 201 return 0; 202 } 203 204 static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, loff_t from) 205 { 206 unsigned int i; 207 208 for (i = 0; i < nvm->nregions; i++) { 209 if ((nvm->regions[i].offset + nvm->regions[i].size - 1) >= from && 210 nvm->regions[i].offset <= from && 211 nvm->regions[i].size != 0) 212 break; 213 } 214 215 return i; 216 } 217 218 static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to, 219 loff_t offset, size_t len, const u32 *newdata) 220 { 221 u32 data = idg_nvm_read32(nvm, to); 222 223 if (idg_nvm_error(nvm)) 224 return -EIO; 225 226 memcpy((u8 *)&data + offset, newdata, len); 227 228 idg_nvm_write32(nvm, to, data); 229 if (idg_nvm_error(nvm)) 230 return -EIO; 231 232 return len; 233 } 234 235 static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, 236 loff_t to, size_t len, const unsigned char *buf) 237 { 238 size_t len_s = len; 239 size_t to_shift; 240 size_t len8; 241 size_t len4; 242 ssize_t ret; 243 size_t to4; 244 size_t i; 245 246 idg_nvm_set_region_id(nvm, region); 247 248 to4 = ALIGN_DOWN(to, sizeof(u32)); 249 to_shift = min(sizeof(u32) - ((size_t)to - to4), len); 250 if (to - to4) { 251 ret = idg_nvm_rewrite_partial(nvm, to4, to - to4, to_shift, (u32 *)&buf[0]); 252 if (ret < 0) 253 return ret; 254 255 buf += to_shift; 256 to += to_shift; 257 len_s -= to_shift; 258 } 259 260 if (!IS_ALIGNED(to, sizeof(u64)) && 261 ((to ^ (to + len_s)) & GENMASK(31, 10))) { 262 /* 263 * Workaround reads/writes across 1k-aligned addresses 264 * (start u32 before 1k, end u32 after) 265 * as this fails on hardware. 266 */ 267 u32 data; 268 269 memcpy(&data, &buf[0], sizeof(u32)); 270 idg_nvm_write32(nvm, to, data); 271 if (idg_nvm_error(nvm)) 272 return -EIO; 273 buf += sizeof(u32); 274 to += sizeof(u32); 275 len_s -= sizeof(u32); 276 } 277 278 len8 = ALIGN_DOWN(len_s, sizeof(u64)); 279 for (i = 0; i < len8; i += sizeof(u64)) { 280 u64 data; 281 282 memcpy(&data, &buf[i], sizeof(u64)); 283 idg_nvm_write64(nvm, to + i, data); 284 if (idg_nvm_error(nvm)) 285 return -EIO; 286 } 287 288 len4 = len_s - len8; 289 if (len4 >= sizeof(u32)) { 290 u32 data; 291 292 memcpy(&data, &buf[i], sizeof(u32)); 293 idg_nvm_write32(nvm, to + i, data); 294 if (idg_nvm_error(nvm)) 295 return -EIO; 296 i += sizeof(u32); 297 len4 -= sizeof(u32); 298 } 299 300 if (len4 > 0) { 301 ret = idg_nvm_rewrite_partial(nvm, to + i, 0, len4, (u32 *)&buf[i]); 302 if (ret < 0) 303 return ret; 304 } 305 306 return len; 307 } 308 309 static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, 310 loff_t from, size_t len, unsigned char *buf) 311 { 312 size_t len_s = len; 313 size_t from_shift; 314 size_t from4; 315 size_t len8; 316 size_t len4; 317 size_t i; 318 319 idg_nvm_set_region_id(nvm, region); 320 321 from4 = ALIGN_DOWN(from, sizeof(u32)); 322 from_shift = min(sizeof(u32) - ((size_t)from - from4), len); 323 324 if (from - from4) { 325 u32 data = idg_nvm_read32(nvm, from4); 326 327 if (idg_nvm_error(nvm)) 328 return -EIO; 329 memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift); 330 len_s -= from_shift; 331 buf += from_shift; 332 from += from_shift; 333 } 334 335 if (!IS_ALIGNED(from, sizeof(u64)) && 336 ((from ^ (from + len_s)) & GENMASK(31, 10))) { 337 /* 338 * Workaround reads/writes across 1k-aligned addresses 339 * (start u32 before 1k, end u32 after) 340 * as this fails on hardware. 341 */ 342 u32 data = idg_nvm_read32(nvm, from); 343 344 if (idg_nvm_error(nvm)) 345 return -EIO; 346 memcpy(&buf[0], &data, sizeof(data)); 347 len_s -= sizeof(u32); 348 buf += sizeof(u32); 349 from += sizeof(u32); 350 } 351 352 len8 = ALIGN_DOWN(len_s, sizeof(u64)); 353 for (i = 0; i < len8; i += sizeof(u64)) { 354 u64 data = idg_nvm_read64(nvm, from + i); 355 356 if (idg_nvm_error(nvm)) 357 return -EIO; 358 359 memcpy(&buf[i], &data, sizeof(data)); 360 } 361 362 len4 = len_s - len8; 363 if (len4 >= sizeof(u32)) { 364 u32 data = idg_nvm_read32(nvm, from + i); 365 366 if (idg_nvm_error(nvm)) 367 return -EIO; 368 memcpy(&buf[i], &data, sizeof(data)); 369 i += sizeof(u32); 370 len4 -= sizeof(u32); 371 } 372 373 if (len4 > 0) { 374 u32 data = idg_nvm_read32(nvm, from + i); 375 376 if (idg_nvm_error(nvm)) 377 return -EIO; 378 memcpy(&buf[i], &data, len4); 379 } 380 381 return len; 382 } 383 384 static ssize_t 385 idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_addr) 386 { 387 void __iomem *base2 = nvm->base2; 388 void __iomem *base = nvm->base; 389 const u32 block = 0x10; 390 u32 iter; 391 u32 reg; 392 u64 i; 393 394 for (i = 0; i < len; i += SZ_4K) { 395 iowrite32(from + i, base + NVM_ADDRESS_REG); 396 iowrite32(region << 24 | block, base + NVM_ERASE_REG); 397 if (nvm->non_posted_erase) { 398 /* Wait for Erase Done */ 399 iter = 0; 400 reg = ioread32(base2 + NVM_DEBUG_REG); 401 while (!(reg & NVM_NON_POSTED_ERASE_DONE) && 402 ++iter < NVM_NON_POSTED_ERASE_DONE_ITER) { 403 msleep(10); 404 reg = ioread32(base2 + NVM_DEBUG_REG); 405 } 406 if (reg & NVM_NON_POSTED_ERASE_DONE) { 407 /* Clear Erase Done */ 408 iowrite32(reg, base2 + NVM_DEBUG_REG); 409 } else { 410 *fail_addr = from + i; 411 return -ETIME; 412 } 413 } 414 /* Since the writes are via sgunit 415 * we cannot do back to back erases. 416 */ 417 msleep(50); 418 } 419 return len; 420 } 421 422 static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *device, 423 bool non_posted_erase) 424 { 425 u32 access_map = 0; 426 unsigned int i, n; 427 int ret; 428 429 nvm->dev = device; 430 431 /* clean error register, previous errors are ignored */ 432 idg_nvm_error(nvm); 433 434 ret = idg_nvm_is_valid(nvm); 435 if (ret) { 436 dev_err(device, "The MEM is not valid %d\n", ret); 437 return ret; 438 } 439 440 if (idg_nvm_get_access_map(nvm, &access_map)) 441 return -EIO; 442 443 for (i = 0, n = 0; i < nvm->nregions; i++) { 444 u32 address, base, limit, region; 445 u8 id = nvm->regions[i].id; 446 447 address = NVM_FLREG(id); 448 region = idg_nvm_read32(nvm, address); 449 450 base = FIELD_GET(NVM_FREG_BASE_MASK, region) << NVM_FREG_ADDR_SHIFT; 451 limit = (FIELD_GET(NVM_FREG_ADDR_MASK, region) << NVM_FREG_ADDR_SHIFT) | 452 NVM_FREG_MIN_REGION_SIZE; 453 454 dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n", 455 id, nvm->regions[i].name, region, base, limit); 456 457 if (base >= limit || (i > 0 && limit == 0)) { 458 dev_dbg(device, "[%d] %s: disabled\n", 459 id, nvm->regions[i].name); 460 nvm->regions[i].is_readable = 0; 461 continue; 462 } 463 464 if (nvm->size < limit) 465 nvm->size = limit; 466 467 nvm->regions[i].offset = base; 468 nvm->regions[i].size = limit - base + 1; 469 /* No write access to descriptor; mask it out*/ 470 nvm->regions[i].is_writable = idg_nvm_region_writable(access_map, id); 471 472 nvm->regions[i].is_readable = idg_nvm_region_readable(access_map, id); 473 dev_dbg(device, "Registered, %s id=%d offset=%lld size=%lld rd=%d wr=%d\n", 474 nvm->regions[i].name, 475 nvm->regions[i].id, 476 nvm->regions[i].offset, 477 nvm->regions[i].size, 478 nvm->regions[i].is_readable, 479 nvm->regions[i].is_writable); 480 481 if (nvm->regions[i].is_readable) 482 n++; 483 } 484 485 nvm->non_posted_erase = non_posted_erase; 486 487 dev_dbg(device, "Registered %d regions\n", n); 488 dev_dbg(device, "Non posted erase %d\n", nvm->non_posted_erase); 489 490 /* Need to add 1 to the amount of memory 491 * so it is reported as an even block 492 */ 493 nvm->size += 1; 494 495 return n; 496 } 497 498 static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *info) 499 { 500 struct intel_dg_nvm *nvm = mtd->priv; 501 size_t total_len; 502 unsigned int idx; 503 ssize_t bytes; 504 loff_t from; 505 size_t len; 506 u8 region; 507 u64 addr; 508 int ret; 509 510 if (WARN_ON(!nvm)) 511 return -EINVAL; 512 513 if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) { 514 dev_err(&mtd->dev, "unaligned erase %llx %llx\n", 515 info->addr, info->len); 516 info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; 517 return -EINVAL; 518 } 519 520 total_len = info->len; 521 addr = info->addr; 522 523 ret = pm_runtime_resume_and_get(nvm->dev); 524 if (ret < 0) { 525 dev_err(&mtd->dev, "rpm: get failed %d\n", ret); 526 return ret; 527 } 528 529 ret = 0; 530 guard(mutex)(&nvm->lock); 531 532 while (total_len > 0) { 533 if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) { 534 dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len); 535 info->fail_addr = addr; 536 ret = -ERANGE; 537 break; 538 } 539 540 idx = idg_nvm_get_region(nvm, addr); 541 if (idx >= nvm->nregions) { 542 dev_err(&mtd->dev, "out of range"); 543 info->fail_addr = MTD_FAIL_ADDR_UNKNOWN; 544 ret = -ERANGE; 545 break; 546 } 547 548 from = addr - nvm->regions[idx].offset; 549 region = nvm->regions[idx].id; 550 len = total_len; 551 if (len > nvm->regions[idx].size - from) 552 len = nvm->regions[idx].size - from; 553 554 dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n", 555 region, nvm->regions[idx].name, from, len); 556 557 bytes = idg_erase(nvm, region, from, len, &info->fail_addr); 558 if (bytes < 0) { 559 dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes); 560 info->fail_addr += nvm->regions[idx].offset; 561 ret = bytes; 562 break; 563 } 564 565 addr += len; 566 total_len -= len; 567 } 568 569 pm_runtime_put_autosuspend(nvm->dev); 570 return ret; 571 } 572 573 static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, 574 size_t *retlen, u_char *buf) 575 { 576 struct intel_dg_nvm *nvm = mtd->priv; 577 unsigned int idx; 578 ssize_t ret; 579 u8 region; 580 581 if (WARN_ON(!nvm)) 582 return -EINVAL; 583 584 idx = idg_nvm_get_region(nvm, from); 585 586 dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n", 587 nvm->regions[idx].id, nvm->regions[idx].name, from, len); 588 589 if (idx >= nvm->nregions) { 590 dev_err(&mtd->dev, "out of range"); 591 return -ERANGE; 592 } 593 594 from -= nvm->regions[idx].offset; 595 region = nvm->regions[idx].id; 596 if (len > nvm->regions[idx].size - from) 597 len = nvm->regions[idx].size - from; 598 599 ret = pm_runtime_resume_and_get(nvm->dev); 600 if (ret < 0) { 601 dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); 602 return ret; 603 } 604 605 guard(mutex)(&nvm->lock); 606 607 ret = idg_read(nvm, region, from, len, buf); 608 if (ret < 0) { 609 dev_dbg(&mtd->dev, "read failed with %zd\n", ret); 610 } else { 611 *retlen = ret; 612 ret = 0; 613 } 614 615 pm_runtime_put_autosuspend(nvm->dev); 616 return ret; 617 } 618 619 static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, 620 size_t *retlen, const u_char *buf) 621 { 622 struct intel_dg_nvm *nvm = mtd->priv; 623 unsigned int idx; 624 ssize_t ret; 625 u8 region; 626 627 if (WARN_ON(!nvm)) 628 return -EINVAL; 629 630 idx = idg_nvm_get_region(nvm, to); 631 632 dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n", 633 nvm->regions[idx].id, nvm->regions[idx].name, to, len); 634 635 if (idx >= nvm->nregions) { 636 dev_err(&mtd->dev, "out of range"); 637 return -ERANGE; 638 } 639 640 to -= nvm->regions[idx].offset; 641 region = nvm->regions[idx].id; 642 if (len > nvm->regions[idx].size - to) 643 len = nvm->regions[idx].size - to; 644 645 ret = pm_runtime_resume_and_get(nvm->dev); 646 if (ret < 0) { 647 dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); 648 return ret; 649 } 650 651 guard(mutex)(&nvm->lock); 652 653 ret = idg_write(nvm, region, to, len, buf); 654 if (ret < 0) { 655 dev_dbg(&mtd->dev, "write failed with %zd\n", ret); 656 } else { 657 *retlen = ret; 658 ret = 0; 659 } 660 661 pm_runtime_put_autosuspend(nvm->dev); 662 return ret; 663 } 664 665 static void intel_dg_nvm_release(struct kref *kref) 666 { 667 struct intel_dg_nvm *nvm = container_of(kref, struct intel_dg_nvm, refcnt); 668 int i; 669 670 pr_debug("freeing intel_dg nvm\n"); 671 for (i = 0; i < nvm->nregions; i++) 672 kfree(nvm->regions[i].name); 673 mutex_destroy(&nvm->lock); 674 kfree(nvm); 675 } 676 677 static int intel_dg_mtd_get_device(struct mtd_info *mtd) 678 { 679 struct mtd_info *master = mtd_get_master(mtd); 680 struct intel_dg_nvm *nvm = master->priv; 681 682 if (WARN_ON(!nvm)) 683 return -EINVAL; 684 pr_debug("get mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt)); 685 kref_get(&nvm->refcnt); 686 687 return 0; 688 } 689 690 static void intel_dg_mtd_put_device(struct mtd_info *mtd) 691 { 692 struct mtd_info *master = mtd_get_master(mtd); 693 struct intel_dg_nvm *nvm = master->priv; 694 695 if (WARN_ON(!nvm)) 696 return; 697 pr_debug("put mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt)); 698 kref_put(&nvm->refcnt, intel_dg_nvm_release); 699 } 700 701 static int intel_dg_nvm_init_mtd(struct intel_dg_nvm *nvm, struct device *device, 702 unsigned int nparts, bool writable_override) 703 { 704 struct mtd_partition *parts = NULL; 705 unsigned int i, n; 706 int ret; 707 708 dev_dbg(device, "registering with mtd\n"); 709 710 nvm->mtd.owner = THIS_MODULE; 711 nvm->mtd.dev.parent = device; 712 nvm->mtd.flags = MTD_CAP_NORFLASH; 713 nvm->mtd.type = MTD_DATAFLASH; 714 nvm->mtd.priv = nvm; 715 nvm->mtd._write = intel_dg_mtd_write; 716 nvm->mtd._read = intel_dg_mtd_read; 717 nvm->mtd._erase = intel_dg_mtd_erase; 718 nvm->mtd._get_device = intel_dg_mtd_get_device; 719 nvm->mtd._put_device = intel_dg_mtd_put_device; 720 nvm->mtd.writesize = SZ_1; /* 1 byte granularity */ 721 nvm->mtd.erasesize = SZ_4K; /* 4K bytes granularity */ 722 nvm->mtd.size = nvm->size; 723 724 parts = kzalloc_objs(*parts, nvm->nregions); 725 if (!parts) 726 return -ENOMEM; 727 728 for (i = 0, n = 0; i < nvm->nregions && n < nparts; i++) { 729 if (!nvm->regions[i].is_readable) 730 continue; 731 parts[n].name = nvm->regions[i].name; 732 parts[n].offset = nvm->regions[i].offset; 733 parts[n].size = nvm->regions[i].size; 734 if (!nvm->regions[i].is_writable && !writable_override) 735 parts[n].mask_flags = MTD_WRITEABLE; 736 n++; 737 } 738 739 ret = mtd_device_register(&nvm->mtd, parts, n); 740 741 kfree(parts); 742 return ret; 743 } 744 745 static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev, 746 const struct auxiliary_device_id *aux_dev_id) 747 { 748 struct intel_dg_nvm_dev *invm = auxiliary_dev_to_intel_dg_nvm_dev(aux_dev); 749 struct intel_dg_nvm *nvm; 750 struct device *device; 751 unsigned int nregions; 752 unsigned int i, n; 753 int ret; 754 755 device = &aux_dev->dev; 756 757 /* count available regions */ 758 for (nregions = 0, i = 0; i < INTEL_DG_NVM_REGIONS; i++) { 759 if (invm->regions[i].name) 760 nregions++; 761 } 762 763 if (!nregions) { 764 dev_err(device, "no regions defined\n"); 765 return -ENODEV; 766 } 767 768 nvm = kzalloc_flex(*nvm, regions, nregions); 769 if (!nvm) 770 return -ENOMEM; 771 772 kref_init(&nvm->refcnt); 773 mutex_init(&nvm->lock); 774 nvm->nregions = nregions; 775 776 for (n = 0, i = 0; i < INTEL_DG_NVM_REGIONS; i++) { 777 if (!invm->regions[i].name) 778 continue; 779 780 char *name = kasprintf(GFP_KERNEL, "%s.%s", 781 dev_name(&aux_dev->dev), invm->regions[i].name); 782 if (!name) { 783 ret = -ENOMEM; 784 goto err_norpm; 785 } 786 787 nvm->regions[n].name = name; 788 nvm->regions[n].id = i; 789 n++; 790 } 791 792 ret = devm_pm_runtime_enable(device); 793 if (ret < 0) { 794 dev_err(device, "rpm: enable failed %d\n", ret); 795 goto err_norpm; 796 } 797 798 pm_runtime_set_autosuspend_delay(device, INTEL_DG_NVM_RPM_TIMEOUT_MS); 799 pm_runtime_use_autosuspend(device); 800 801 ret = pm_runtime_resume_and_get(device); 802 if (ret < 0) { 803 dev_err(device, "rpm: get failed %d\n", ret); 804 goto err_norpm; 805 } 806 807 nvm->base = devm_ioremap_resource(device, &invm->bar); 808 if (IS_ERR(nvm->base)) { 809 ret = PTR_ERR(nvm->base); 810 goto err; 811 } 812 813 if (invm->non_posted_erase) { 814 nvm->base2 = devm_ioremap_resource(device, &invm->bar2); 815 if (IS_ERR(nvm->base2)) { 816 ret = PTR_ERR(nvm->base2); 817 goto err; 818 } 819 } 820 821 ret = intel_dg_nvm_init(nvm, device, invm->non_posted_erase); 822 if (ret < 0) { 823 dev_err(device, "cannot initialize nvm %d\n", ret); 824 goto err; 825 } 826 827 ret = intel_dg_nvm_init_mtd(nvm, device, ret, invm->writable_override); 828 if (ret) { 829 dev_err(device, "failed init mtd %d\n", ret); 830 goto err; 831 } 832 833 dev_set_drvdata(&aux_dev->dev, nvm); 834 835 pm_runtime_put(device); 836 return 0; 837 838 err: 839 pm_runtime_put(device); 840 err_norpm: 841 kref_put(&nvm->refcnt, intel_dg_nvm_release); 842 return ret; 843 } 844 845 static void intel_dg_mtd_remove(struct auxiliary_device *aux_dev) 846 { 847 struct intel_dg_nvm *nvm = dev_get_drvdata(&aux_dev->dev); 848 849 if (!nvm) 850 return; 851 852 mtd_device_unregister(&nvm->mtd); 853 854 dev_set_drvdata(&aux_dev->dev, NULL); 855 856 kref_put(&nvm->refcnt, intel_dg_nvm_release); 857 } 858 859 static const struct auxiliary_device_id intel_dg_mtd_id_table[] = { 860 { 861 .name = "i915.nvm", 862 }, 863 { 864 .name = "xe.nvm", 865 }, 866 { 867 /* sentinel */ 868 } 869 }; 870 MODULE_DEVICE_TABLE(auxiliary, intel_dg_mtd_id_table); 871 872 static struct auxiliary_driver intel_dg_mtd_driver = { 873 .probe = intel_dg_mtd_probe, 874 .remove = intel_dg_mtd_remove, 875 .driver = { 876 /* auxiliary_driver_register() sets .name to be the modname */ 877 }, 878 .id_table = intel_dg_mtd_id_table 879 }; 880 module_auxiliary_driver(intel_dg_mtd_driver); 881 882 MODULE_LICENSE("GPL"); 883 MODULE_AUTHOR("Intel Corporation"); 884 MODULE_DESCRIPTION("Intel DGFX MTD driver"); 885