1 /* 2 Common Flash Interface probe code. 3 (C) 2000 Red Hat. GPL'd. 4 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) 5 for the standard this probe goes back to. 6 7 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 8 */ 9 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/kernel.h> 14 #include <asm/io.h> 15 #include <asm/byteorder.h> 16 #include <linux/errno.h> 17 #include <linux/slab.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/map.h> 22 #include <linux/mtd/cfi.h> 23 #include <linux/mtd/gen_probe.h> 24 25 /* Manufacturers */ 26 #define MANUFACTURER_AMD 0x0001 27 #define MANUFACTURER_ATMEL 0x001f 28 #define MANUFACTURER_EON 0x001c 29 #define MANUFACTURER_FUJITSU 0x0004 30 #define MANUFACTURER_HYUNDAI 0x00AD 31 #define MANUFACTURER_INTEL 0x0089 32 #define MANUFACTURER_MACRONIX 0x00C2 33 #define MANUFACTURER_NEC 0x0010 34 #define MANUFACTURER_PMC 0x009D 35 #define MANUFACTURER_SHARP 0x00b0 36 #define MANUFACTURER_SST 0x00BF 37 #define MANUFACTURER_ST 0x0020 38 #define MANUFACTURER_TOSHIBA 0x0098 39 #define MANUFACTURER_WINBOND 0x00da 40 #define CONTINUATION_CODE 0x007f 41 42 43 /* AMD */ 44 #define AM29DL800BB 0x22CB 45 #define AM29DL800BT 0x224A 46 47 #define AM29F800BB 0x2258 48 #define AM29F800BT 0x22D6 49 #define AM29LV400BB 0x22BA 50 #define AM29LV400BT 0x22B9 51 #define AM29LV800BB 0x225B 52 #define AM29LV800BT 0x22DA 53 #define AM29LV160DT 0x22C4 54 #define AM29LV160DB 0x2249 55 #define AM29F017D 0x003D 56 #define AM29F016D 0x00AD 57 #define AM29F080 0x00D5 58 #define AM29F040 0x00A4 59 #define AM29LV040B 0x004F 60 #define AM29F032B 0x0041 61 #define AM29F002T 0x00B0 62 #define AM29SL800DB 0x226B 63 #define AM29SL800DT 0x22EA 64 65 /* Atmel */ 66 #define AT49BV512 0x0003 67 #define AT29LV512 0x003d 68 #define AT49BV16X 0x00C0 69 #define AT49BV16XT 0x00C2 70 #define AT49BV32X 0x00C8 71 #define AT49BV32XT 0x00C9 72 73 /* Eon */ 74 #define EN29SL800BB 0x226B 75 #define EN29SL800BT 0x22EA 76 77 /* Fujitsu */ 78 #define MBM29F040C 0x00A4 79 #define MBM29F800BA 0x2258 80 #define MBM29LV650UE 0x22D7 81 #define MBM29LV320TE 0x22F6 82 #define MBM29LV320BE 0x22F9 83 #define MBM29LV160TE 0x22C4 84 #define MBM29LV160BE 0x2249 85 #define MBM29LV800BA 0x225B 86 #define MBM29LV800TA 0x22DA 87 #define MBM29LV400TC 0x22B9 88 #define MBM29LV400BC 0x22BA 89 90 /* Hyundai */ 91 #define HY29F002T 0x00B0 92 93 /* Intel */ 94 #define I28F004B3T 0x00d4 95 #define I28F004B3B 0x00d5 96 #define I28F400B3T 0x8894 97 #define I28F400B3B 0x8895 98 #define I28F008S5 0x00a6 99 #define I28F016S5 0x00a0 100 #define I28F008SA 0x00a2 101 #define I28F008B3T 0x00d2 102 #define I28F008B3B 0x00d3 103 #define I28F800B3T 0x8892 104 #define I28F800B3B 0x8893 105 #define I28F016S3 0x00aa 106 #define I28F016B3T 0x00d0 107 #define I28F016B3B 0x00d1 108 #define I28F160B3T 0x8890 109 #define I28F160B3B 0x8891 110 #define I28F320B3T 0x8896 111 #define I28F320B3B 0x8897 112 #define I28F640B3T 0x8898 113 #define I28F640B3B 0x8899 114 #define I82802AB 0x00ad 115 #define I82802AC 0x00ac 116 117 /* Macronix */ 118 #define MX29LV040C 0x004F 119 #define MX29LV160T 0x22C4 120 #define MX29LV160B 0x2249 121 #define MX29F040 0x00A4 122 #define MX29F016 0x00AD 123 #define MX29F002T 0x00B0 124 #define MX29F004T 0x0045 125 #define MX29F004B 0x0046 126 127 /* NEC */ 128 #define UPD29F064115 0x221C 129 130 /* PMC */ 131 #define PM49FL002 0x006D 132 #define PM49FL004 0x006E 133 #define PM49FL008 0x006A 134 135 /* Sharp */ 136 #define LH28F640BF 0x00b0 137 138 /* ST - www.st.com */ 139 #define M29F800AB 0x0058 140 #define M29W800DT 0x00D7 141 #define M29W800DB 0x005B 142 #define M29W400DT 0x00EE 143 #define M29W400DB 0x00EF 144 #define M29W160DT 0x22C4 145 #define M29W160DB 0x2249 146 #define M29W040B 0x00E3 147 #define M50FW040 0x002C 148 #define M50FW080 0x002D 149 #define M50FW016 0x002E 150 #define M50LPW080 0x002F 151 #define M50FLW080A 0x0080 152 #define M50FLW080B 0x0081 153 154 /* SST */ 155 #define SST29EE020 0x0010 156 #define SST29LE020 0x0012 157 #define SST29EE512 0x005d 158 #define SST29LE512 0x003d 159 #define SST39LF800 0x2781 160 #define SST39LF160 0x2782 161 #define SST39VF1601 0x234b 162 #define SST39LF512 0x00D4 163 #define SST39LF010 0x00D5 164 #define SST39LF020 0x00D6 165 #define SST39LF040 0x00D7 166 #define SST39SF010A 0x00B5 167 #define SST39SF020A 0x00B6 168 #define SST49LF004B 0x0060 169 #define SST49LF040B 0x0050 170 #define SST49LF008A 0x005a 171 #define SST49LF030A 0x001C 172 #define SST49LF040A 0x0051 173 #define SST49LF080A 0x005B 174 #define SST36VF3203 0x7354 175 176 /* Toshiba */ 177 #define TC58FVT160 0x00C2 178 #define TC58FVB160 0x0043 179 #define TC58FVT321 0x009A 180 #define TC58FVB321 0x009C 181 #define TC58FVT641 0x0093 182 #define TC58FVB641 0x0095 183 184 /* Winbond */ 185 #define W49V002A 0x00b0 186 187 188 /* 189 * Unlock address sets for AMD command sets. 190 * Intel command sets use the MTD_UADDR_UNNECESSARY. 191 * Each identifier, except MTD_UADDR_UNNECESSARY, and 192 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 193 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 194 * initialization need not require initializing all of the 195 * unlock addresses for all bit widths. 196 */ 197 enum uaddr { 198 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 199 MTD_UADDR_0x0555_0x02AA, 200 MTD_UADDR_0x0555_0x0AAA, 201 MTD_UADDR_0x5555_0x2AAA, 202 MTD_UADDR_0x0AAA_0x0555, 203 MTD_UADDR_0xAAAA_0x5555, 204 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 205 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 206 }; 207 208 209 struct unlock_addr { 210 uint32_t addr1; 211 uint32_t addr2; 212 }; 213 214 215 /* 216 * I don't like the fact that the first entry in unlock_addrs[] 217 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 218 * should not be used. The problem is that structures with 219 * initializers have extra fields initialized to 0. It is _very_ 220 * desireable to have the unlock address entries for unsupported 221 * data widths automatically initialized - that means that 222 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 223 * must go unused. 224 */ 225 static const struct unlock_addr unlock_addrs[] = { 226 [MTD_UADDR_NOT_SUPPORTED] = { 227 .addr1 = 0xffff, 228 .addr2 = 0xffff 229 }, 230 231 [MTD_UADDR_0x0555_0x02AA] = { 232 .addr1 = 0x0555, 233 .addr2 = 0x02aa 234 }, 235 236 [MTD_UADDR_0x0555_0x0AAA] = { 237 .addr1 = 0x0555, 238 .addr2 = 0x0aaa 239 }, 240 241 [MTD_UADDR_0x5555_0x2AAA] = { 242 .addr1 = 0x5555, 243 .addr2 = 0x2aaa 244 }, 245 246 [MTD_UADDR_0x0AAA_0x0555] = { 247 .addr1 = 0x0AAA, 248 .addr2 = 0x0555 249 }, 250 251 [MTD_UADDR_0xAAAA_0x5555] = { 252 .addr1 = 0xaaaa, 253 .addr2 = 0x5555 254 }, 255 256 [MTD_UADDR_DONT_CARE] = { 257 .addr1 = 0x0000, /* Doesn't matter which address */ 258 .addr2 = 0x0000 /* is used - must be last entry */ 259 }, 260 261 [MTD_UADDR_UNNECESSARY] = { 262 .addr1 = 0x0000, 263 .addr2 = 0x0000 264 } 265 }; 266 267 struct amd_flash_info { 268 const char *name; 269 const uint16_t mfr_id; 270 const uint16_t dev_id; 271 const uint8_t dev_size; 272 const uint8_t nr_regions; 273 const uint16_t cmd_set; 274 const uint32_t regions[6]; 275 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ 276 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ 277 }; 278 279 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 280 281 #define SIZE_64KiB 16 282 #define SIZE_128KiB 17 283 #define SIZE_256KiB 18 284 #define SIZE_512KiB 19 285 #define SIZE_1MiB 20 286 #define SIZE_2MiB 21 287 #define SIZE_4MiB 22 288 #define SIZE_8MiB 23 289 290 291 /* 292 * Please keep this list ordered by manufacturer! 293 * Fortunately, the list isn't searched often and so a 294 * slow, linear search isn't so bad. 295 */ 296 static const struct amd_flash_info jedec_table[] = { 297 { 298 .mfr_id = MANUFACTURER_AMD, 299 .dev_id = AM29F032B, 300 .name = "AMD AM29F032B", 301 .uaddr = MTD_UADDR_0x0555_0x02AA, 302 .devtypes = CFI_DEVICETYPE_X8, 303 .dev_size = SIZE_4MiB, 304 .cmd_set = P_ID_AMD_STD, 305 .nr_regions = 1, 306 .regions = { 307 ERASEINFO(0x10000,64) 308 } 309 }, { 310 .mfr_id = MANUFACTURER_AMD, 311 .dev_id = AM29LV160DT, 312 .name = "AMD AM29LV160DT", 313 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 314 .uaddr = MTD_UADDR_0x0AAA_0x0555, 315 .dev_size = SIZE_2MiB, 316 .cmd_set = P_ID_AMD_STD, 317 .nr_regions = 4, 318 .regions = { 319 ERASEINFO(0x10000,31), 320 ERASEINFO(0x08000,1), 321 ERASEINFO(0x02000,2), 322 ERASEINFO(0x04000,1) 323 } 324 }, { 325 .mfr_id = MANUFACTURER_AMD, 326 .dev_id = AM29LV160DB, 327 .name = "AMD AM29LV160DB", 328 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 329 .uaddr = MTD_UADDR_0x0AAA_0x0555, 330 .dev_size = SIZE_2MiB, 331 .cmd_set = P_ID_AMD_STD, 332 .nr_regions = 4, 333 .regions = { 334 ERASEINFO(0x04000,1), 335 ERASEINFO(0x02000,2), 336 ERASEINFO(0x08000,1), 337 ERASEINFO(0x10000,31) 338 } 339 }, { 340 .mfr_id = MANUFACTURER_AMD, 341 .dev_id = AM29LV400BB, 342 .name = "AMD AM29LV400BB", 343 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 344 .uaddr = MTD_UADDR_0x0AAA_0x0555, 345 .dev_size = SIZE_512KiB, 346 .cmd_set = P_ID_AMD_STD, 347 .nr_regions = 4, 348 .regions = { 349 ERASEINFO(0x04000,1), 350 ERASEINFO(0x02000,2), 351 ERASEINFO(0x08000,1), 352 ERASEINFO(0x10000,7) 353 } 354 }, { 355 .mfr_id = MANUFACTURER_AMD, 356 .dev_id = AM29LV400BT, 357 .name = "AMD AM29LV400BT", 358 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 359 .uaddr = MTD_UADDR_0x0AAA_0x0555, 360 .dev_size = SIZE_512KiB, 361 .cmd_set = P_ID_AMD_STD, 362 .nr_regions = 4, 363 .regions = { 364 ERASEINFO(0x10000,7), 365 ERASEINFO(0x08000,1), 366 ERASEINFO(0x02000,2), 367 ERASEINFO(0x04000,1) 368 } 369 }, { 370 .mfr_id = MANUFACTURER_AMD, 371 .dev_id = AM29LV800BB, 372 .name = "AMD AM29LV800BB", 373 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 374 .uaddr = MTD_UADDR_0x0AAA_0x0555, 375 .dev_size = SIZE_1MiB, 376 .cmd_set = P_ID_AMD_STD, 377 .nr_regions = 4, 378 .regions = { 379 ERASEINFO(0x04000,1), 380 ERASEINFO(0x02000,2), 381 ERASEINFO(0x08000,1), 382 ERASEINFO(0x10000,15), 383 } 384 }, { 385 /* add DL */ 386 .mfr_id = MANUFACTURER_AMD, 387 .dev_id = AM29DL800BB, 388 .name = "AMD AM29DL800BB", 389 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 390 .uaddr = MTD_UADDR_0x0AAA_0x0555, 391 .dev_size = SIZE_1MiB, 392 .cmd_set = P_ID_AMD_STD, 393 .nr_regions = 6, 394 .regions = { 395 ERASEINFO(0x04000,1), 396 ERASEINFO(0x08000,1), 397 ERASEINFO(0x02000,4), 398 ERASEINFO(0x08000,1), 399 ERASEINFO(0x04000,1), 400 ERASEINFO(0x10000,14) 401 } 402 }, { 403 .mfr_id = MANUFACTURER_AMD, 404 .dev_id = AM29DL800BT, 405 .name = "AMD AM29DL800BT", 406 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 407 .uaddr = MTD_UADDR_0x0AAA_0x0555, 408 .dev_size = SIZE_1MiB, 409 .cmd_set = P_ID_AMD_STD, 410 .nr_regions = 6, 411 .regions = { 412 ERASEINFO(0x10000,14), 413 ERASEINFO(0x04000,1), 414 ERASEINFO(0x08000,1), 415 ERASEINFO(0x02000,4), 416 ERASEINFO(0x08000,1), 417 ERASEINFO(0x04000,1) 418 } 419 }, { 420 .mfr_id = MANUFACTURER_AMD, 421 .dev_id = AM29F800BB, 422 .name = "AMD AM29F800BB", 423 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 424 .uaddr = MTD_UADDR_0x0AAA_0x0555, 425 .dev_size = SIZE_1MiB, 426 .cmd_set = P_ID_AMD_STD, 427 .nr_regions = 4, 428 .regions = { 429 ERASEINFO(0x04000,1), 430 ERASEINFO(0x02000,2), 431 ERASEINFO(0x08000,1), 432 ERASEINFO(0x10000,15), 433 } 434 }, { 435 .mfr_id = MANUFACTURER_AMD, 436 .dev_id = AM29LV800BT, 437 .name = "AMD AM29LV800BT", 438 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 439 .uaddr = MTD_UADDR_0x0AAA_0x0555, 440 .dev_size = SIZE_1MiB, 441 .cmd_set = P_ID_AMD_STD, 442 .nr_regions = 4, 443 .regions = { 444 ERASEINFO(0x10000,15), 445 ERASEINFO(0x08000,1), 446 ERASEINFO(0x02000,2), 447 ERASEINFO(0x04000,1) 448 } 449 }, { 450 .mfr_id = MANUFACTURER_AMD, 451 .dev_id = AM29F800BT, 452 .name = "AMD AM29F800BT", 453 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 454 .uaddr = MTD_UADDR_0x0AAA_0x0555, 455 .dev_size = SIZE_1MiB, 456 .cmd_set = P_ID_AMD_STD, 457 .nr_regions = 4, 458 .regions = { 459 ERASEINFO(0x10000,15), 460 ERASEINFO(0x08000,1), 461 ERASEINFO(0x02000,2), 462 ERASEINFO(0x04000,1) 463 } 464 }, { 465 .mfr_id = MANUFACTURER_AMD, 466 .dev_id = AM29F017D, 467 .name = "AMD AM29F017D", 468 .devtypes = CFI_DEVICETYPE_X8, 469 .uaddr = MTD_UADDR_DONT_CARE, 470 .dev_size = SIZE_2MiB, 471 .cmd_set = P_ID_AMD_STD, 472 .nr_regions = 1, 473 .regions = { 474 ERASEINFO(0x10000,32), 475 } 476 }, { 477 .mfr_id = MANUFACTURER_AMD, 478 .dev_id = AM29F016D, 479 .name = "AMD AM29F016D", 480 .devtypes = CFI_DEVICETYPE_X8, 481 .uaddr = MTD_UADDR_0x0555_0x02AA, 482 .dev_size = SIZE_2MiB, 483 .cmd_set = P_ID_AMD_STD, 484 .nr_regions = 1, 485 .regions = { 486 ERASEINFO(0x10000,32), 487 } 488 }, { 489 .mfr_id = MANUFACTURER_AMD, 490 .dev_id = AM29F080, 491 .name = "AMD AM29F080", 492 .devtypes = CFI_DEVICETYPE_X8, 493 .uaddr = MTD_UADDR_0x0555_0x02AA, 494 .dev_size = SIZE_1MiB, 495 .cmd_set = P_ID_AMD_STD, 496 .nr_regions = 1, 497 .regions = { 498 ERASEINFO(0x10000,16), 499 } 500 }, { 501 .mfr_id = MANUFACTURER_AMD, 502 .dev_id = AM29F040, 503 .name = "AMD AM29F040", 504 .devtypes = CFI_DEVICETYPE_X8, 505 .uaddr = MTD_UADDR_0x0555_0x02AA, 506 .dev_size = SIZE_512KiB, 507 .cmd_set = P_ID_AMD_STD, 508 .nr_regions = 1, 509 .regions = { 510 ERASEINFO(0x10000,8), 511 } 512 }, { 513 .mfr_id = MANUFACTURER_AMD, 514 .dev_id = AM29LV040B, 515 .name = "AMD AM29LV040B", 516 .devtypes = CFI_DEVICETYPE_X8, 517 .uaddr = MTD_UADDR_0x0555_0x02AA, 518 .dev_size = SIZE_512KiB, 519 .cmd_set = P_ID_AMD_STD, 520 .nr_regions = 1, 521 .regions = { 522 ERASEINFO(0x10000,8), 523 } 524 }, { 525 .mfr_id = MANUFACTURER_AMD, 526 .dev_id = AM29F002T, 527 .name = "AMD AM29F002T", 528 .devtypes = CFI_DEVICETYPE_X8, 529 .uaddr = MTD_UADDR_0x0555_0x02AA, 530 .dev_size = SIZE_256KiB, 531 .cmd_set = P_ID_AMD_STD, 532 .nr_regions = 4, 533 .regions = { 534 ERASEINFO(0x10000,3), 535 ERASEINFO(0x08000,1), 536 ERASEINFO(0x02000,2), 537 ERASEINFO(0x04000,1), 538 } 539 }, { 540 .mfr_id = MANUFACTURER_AMD, 541 .dev_id = AM29SL800DT, 542 .name = "AMD AM29SL800DT", 543 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 544 .uaddr = MTD_UADDR_0x0AAA_0x0555, 545 .dev_size = SIZE_1MiB, 546 .cmd_set = P_ID_AMD_STD, 547 .nr_regions = 4, 548 .regions = { 549 ERASEINFO(0x10000,15), 550 ERASEINFO(0x08000,1), 551 ERASEINFO(0x02000,2), 552 ERASEINFO(0x04000,1), 553 } 554 }, { 555 .mfr_id = MANUFACTURER_AMD, 556 .dev_id = AM29SL800DB, 557 .name = "AMD AM29SL800DB", 558 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 559 .uaddr = MTD_UADDR_0x0AAA_0x0555, 560 .dev_size = SIZE_1MiB, 561 .cmd_set = P_ID_AMD_STD, 562 .nr_regions = 4, 563 .regions = { 564 ERASEINFO(0x04000,1), 565 ERASEINFO(0x02000,2), 566 ERASEINFO(0x08000,1), 567 ERASEINFO(0x10000,15), 568 } 569 }, { 570 .mfr_id = MANUFACTURER_ATMEL, 571 .dev_id = AT49BV512, 572 .name = "Atmel AT49BV512", 573 .devtypes = CFI_DEVICETYPE_X8, 574 .uaddr = MTD_UADDR_0x5555_0x2AAA, 575 .dev_size = SIZE_64KiB, 576 .cmd_set = P_ID_AMD_STD, 577 .nr_regions = 1, 578 .regions = { 579 ERASEINFO(0x10000,1) 580 } 581 }, { 582 .mfr_id = MANUFACTURER_ATMEL, 583 .dev_id = AT29LV512, 584 .name = "Atmel AT29LV512", 585 .devtypes = CFI_DEVICETYPE_X8, 586 .uaddr = MTD_UADDR_0x5555_0x2AAA, 587 .dev_size = SIZE_64KiB, 588 .cmd_set = P_ID_AMD_STD, 589 .nr_regions = 1, 590 .regions = { 591 ERASEINFO(0x80,256), 592 ERASEINFO(0x80,256) 593 } 594 }, { 595 .mfr_id = MANUFACTURER_ATMEL, 596 .dev_id = AT49BV16X, 597 .name = "Atmel AT49BV16X", 598 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 599 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 600 .dev_size = SIZE_2MiB, 601 .cmd_set = P_ID_AMD_STD, 602 .nr_regions = 2, 603 .regions = { 604 ERASEINFO(0x02000,8), 605 ERASEINFO(0x10000,31) 606 } 607 }, { 608 .mfr_id = MANUFACTURER_ATMEL, 609 .dev_id = AT49BV16XT, 610 .name = "Atmel AT49BV16XT", 611 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 612 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 613 .dev_size = SIZE_2MiB, 614 .cmd_set = P_ID_AMD_STD, 615 .nr_regions = 2, 616 .regions = { 617 ERASEINFO(0x10000,31), 618 ERASEINFO(0x02000,8) 619 } 620 }, { 621 .mfr_id = MANUFACTURER_ATMEL, 622 .dev_id = AT49BV32X, 623 .name = "Atmel AT49BV32X", 624 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 625 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 626 .dev_size = SIZE_4MiB, 627 .cmd_set = P_ID_AMD_STD, 628 .nr_regions = 2, 629 .regions = { 630 ERASEINFO(0x02000,8), 631 ERASEINFO(0x10000,63) 632 } 633 }, { 634 .mfr_id = MANUFACTURER_ATMEL, 635 .dev_id = AT49BV32XT, 636 .name = "Atmel AT49BV32XT", 637 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 638 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 639 .dev_size = SIZE_4MiB, 640 .cmd_set = P_ID_AMD_STD, 641 .nr_regions = 2, 642 .regions = { 643 ERASEINFO(0x10000,63), 644 ERASEINFO(0x02000,8) 645 } 646 }, { 647 .mfr_id = MANUFACTURER_EON, 648 .dev_id = EN29SL800BT, 649 .name = "Eon EN29SL800BT", 650 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 651 .uaddr = MTD_UADDR_0x0AAA_0x0555, 652 .dev_size = SIZE_1MiB, 653 .cmd_set = P_ID_AMD_STD, 654 .nr_regions = 4, 655 .regions = { 656 ERASEINFO(0x10000,15), 657 ERASEINFO(0x08000,1), 658 ERASEINFO(0x02000,2), 659 ERASEINFO(0x04000,1), 660 } 661 }, { 662 .mfr_id = MANUFACTURER_EON, 663 .dev_id = EN29SL800BB, 664 .name = "Eon EN29SL800BB", 665 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 666 .uaddr = MTD_UADDR_0x0AAA_0x0555, 667 .dev_size = SIZE_1MiB, 668 .cmd_set = P_ID_AMD_STD, 669 .nr_regions = 4, 670 .regions = { 671 ERASEINFO(0x04000,1), 672 ERASEINFO(0x02000,2), 673 ERASEINFO(0x08000,1), 674 ERASEINFO(0x10000,15), 675 } 676 }, { 677 .mfr_id = MANUFACTURER_FUJITSU, 678 .dev_id = MBM29F040C, 679 .name = "Fujitsu MBM29F040C", 680 .devtypes = CFI_DEVICETYPE_X8, 681 .uaddr = MTD_UADDR_0x0AAA_0x0555, 682 .dev_size = SIZE_512KiB, 683 .cmd_set = P_ID_AMD_STD, 684 .nr_regions = 1, 685 .regions = { 686 ERASEINFO(0x10000,8) 687 } 688 }, { 689 .mfr_id = MANUFACTURER_FUJITSU, 690 .dev_id = MBM29F800BA, 691 .name = "Fujitsu MBM29F800BA", 692 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 693 .uaddr = MTD_UADDR_0x0AAA_0x0555, 694 .dev_size = SIZE_1MiB, 695 .cmd_set = P_ID_AMD_STD, 696 .nr_regions = 4, 697 .regions = { 698 ERASEINFO(0x04000,1), 699 ERASEINFO(0x02000,2), 700 ERASEINFO(0x08000,1), 701 ERASEINFO(0x10000,15), 702 } 703 }, { 704 .mfr_id = MANUFACTURER_FUJITSU, 705 .dev_id = MBM29LV650UE, 706 .name = "Fujitsu MBM29LV650UE", 707 .devtypes = CFI_DEVICETYPE_X8, 708 .uaddr = MTD_UADDR_DONT_CARE, 709 .dev_size = SIZE_8MiB, 710 .cmd_set = P_ID_AMD_STD, 711 .nr_regions = 1, 712 .regions = { 713 ERASEINFO(0x10000,128) 714 } 715 }, { 716 .mfr_id = MANUFACTURER_FUJITSU, 717 .dev_id = MBM29LV320TE, 718 .name = "Fujitsu MBM29LV320TE", 719 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 720 .uaddr = MTD_UADDR_0x0AAA_0x0555, 721 .dev_size = SIZE_4MiB, 722 .cmd_set = P_ID_AMD_STD, 723 .nr_regions = 2, 724 .regions = { 725 ERASEINFO(0x10000,63), 726 ERASEINFO(0x02000,8) 727 } 728 }, { 729 .mfr_id = MANUFACTURER_FUJITSU, 730 .dev_id = MBM29LV320BE, 731 .name = "Fujitsu MBM29LV320BE", 732 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 733 .uaddr = MTD_UADDR_0x0AAA_0x0555, 734 .dev_size = SIZE_4MiB, 735 .cmd_set = P_ID_AMD_STD, 736 .nr_regions = 2, 737 .regions = { 738 ERASEINFO(0x02000,8), 739 ERASEINFO(0x10000,63) 740 } 741 }, { 742 .mfr_id = MANUFACTURER_FUJITSU, 743 .dev_id = MBM29LV160TE, 744 .name = "Fujitsu MBM29LV160TE", 745 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 746 .uaddr = MTD_UADDR_0x0AAA_0x0555, 747 .dev_size = SIZE_2MiB, 748 .cmd_set = P_ID_AMD_STD, 749 .nr_regions = 4, 750 .regions = { 751 ERASEINFO(0x10000,31), 752 ERASEINFO(0x08000,1), 753 ERASEINFO(0x02000,2), 754 ERASEINFO(0x04000,1) 755 } 756 }, { 757 .mfr_id = MANUFACTURER_FUJITSU, 758 .dev_id = MBM29LV160BE, 759 .name = "Fujitsu MBM29LV160BE", 760 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 761 .uaddr = MTD_UADDR_0x0AAA_0x0555, 762 .dev_size = SIZE_2MiB, 763 .cmd_set = P_ID_AMD_STD, 764 .nr_regions = 4, 765 .regions = { 766 ERASEINFO(0x04000,1), 767 ERASEINFO(0x02000,2), 768 ERASEINFO(0x08000,1), 769 ERASEINFO(0x10000,31) 770 } 771 }, { 772 .mfr_id = MANUFACTURER_FUJITSU, 773 .dev_id = MBM29LV800BA, 774 .name = "Fujitsu MBM29LV800BA", 775 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 776 .uaddr = MTD_UADDR_0x0AAA_0x0555, 777 .dev_size = SIZE_1MiB, 778 .cmd_set = P_ID_AMD_STD, 779 .nr_regions = 4, 780 .regions = { 781 ERASEINFO(0x04000,1), 782 ERASEINFO(0x02000,2), 783 ERASEINFO(0x08000,1), 784 ERASEINFO(0x10000,15) 785 } 786 }, { 787 .mfr_id = MANUFACTURER_FUJITSU, 788 .dev_id = MBM29LV800TA, 789 .name = "Fujitsu MBM29LV800TA", 790 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 791 .uaddr = MTD_UADDR_0x0AAA_0x0555, 792 .dev_size = SIZE_1MiB, 793 .cmd_set = P_ID_AMD_STD, 794 .nr_regions = 4, 795 .regions = { 796 ERASEINFO(0x10000,15), 797 ERASEINFO(0x08000,1), 798 ERASEINFO(0x02000,2), 799 ERASEINFO(0x04000,1) 800 } 801 }, { 802 .mfr_id = MANUFACTURER_FUJITSU, 803 .dev_id = MBM29LV400BC, 804 .name = "Fujitsu MBM29LV400BC", 805 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 806 .uaddr = MTD_UADDR_0x0AAA_0x0555, 807 .dev_size = SIZE_512KiB, 808 .cmd_set = P_ID_AMD_STD, 809 .nr_regions = 4, 810 .regions = { 811 ERASEINFO(0x04000,1), 812 ERASEINFO(0x02000,2), 813 ERASEINFO(0x08000,1), 814 ERASEINFO(0x10000,7) 815 } 816 }, { 817 .mfr_id = MANUFACTURER_FUJITSU, 818 .dev_id = MBM29LV400TC, 819 .name = "Fujitsu MBM29LV400TC", 820 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 821 .uaddr = MTD_UADDR_0x0AAA_0x0555, 822 .dev_size = SIZE_512KiB, 823 .cmd_set = P_ID_AMD_STD, 824 .nr_regions = 4, 825 .regions = { 826 ERASEINFO(0x10000,7), 827 ERASEINFO(0x08000,1), 828 ERASEINFO(0x02000,2), 829 ERASEINFO(0x04000,1) 830 } 831 }, { 832 .mfr_id = MANUFACTURER_HYUNDAI, 833 .dev_id = HY29F002T, 834 .name = "Hyundai HY29F002T", 835 .devtypes = CFI_DEVICETYPE_X8, 836 .uaddr = MTD_UADDR_0x0555_0x02AA, 837 .dev_size = SIZE_256KiB, 838 .cmd_set = P_ID_AMD_STD, 839 .nr_regions = 4, 840 .regions = { 841 ERASEINFO(0x10000,3), 842 ERASEINFO(0x08000,1), 843 ERASEINFO(0x02000,2), 844 ERASEINFO(0x04000,1), 845 } 846 }, { 847 .mfr_id = MANUFACTURER_INTEL, 848 .dev_id = I28F004B3B, 849 .name = "Intel 28F004B3B", 850 .devtypes = CFI_DEVICETYPE_X8, 851 .uaddr = MTD_UADDR_UNNECESSARY, 852 .dev_size = SIZE_512KiB, 853 .cmd_set = P_ID_INTEL_STD, 854 .nr_regions = 2, 855 .regions = { 856 ERASEINFO(0x02000, 8), 857 ERASEINFO(0x10000, 7), 858 } 859 }, { 860 .mfr_id = MANUFACTURER_INTEL, 861 .dev_id = I28F004B3T, 862 .name = "Intel 28F004B3T", 863 .devtypes = CFI_DEVICETYPE_X8, 864 .uaddr = MTD_UADDR_UNNECESSARY, 865 .dev_size = SIZE_512KiB, 866 .cmd_set = P_ID_INTEL_STD, 867 .nr_regions = 2, 868 .regions = { 869 ERASEINFO(0x10000, 7), 870 ERASEINFO(0x02000, 8), 871 } 872 }, { 873 .mfr_id = MANUFACTURER_INTEL, 874 .dev_id = I28F400B3B, 875 .name = "Intel 28F400B3B", 876 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 877 .uaddr = MTD_UADDR_UNNECESSARY, 878 .dev_size = SIZE_512KiB, 879 .cmd_set = P_ID_INTEL_STD, 880 .nr_regions = 2, 881 .regions = { 882 ERASEINFO(0x02000, 8), 883 ERASEINFO(0x10000, 7), 884 } 885 }, { 886 .mfr_id = MANUFACTURER_INTEL, 887 .dev_id = I28F400B3T, 888 .name = "Intel 28F400B3T", 889 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 890 .uaddr = MTD_UADDR_UNNECESSARY, 891 .dev_size = SIZE_512KiB, 892 .cmd_set = P_ID_INTEL_STD, 893 .nr_regions = 2, 894 .regions = { 895 ERASEINFO(0x10000, 7), 896 ERASEINFO(0x02000, 8), 897 } 898 }, { 899 .mfr_id = MANUFACTURER_INTEL, 900 .dev_id = I28F008B3B, 901 .name = "Intel 28F008B3B", 902 .devtypes = CFI_DEVICETYPE_X8, 903 .uaddr = MTD_UADDR_UNNECESSARY, 904 .dev_size = SIZE_1MiB, 905 .cmd_set = P_ID_INTEL_STD, 906 .nr_regions = 2, 907 .regions = { 908 ERASEINFO(0x02000, 8), 909 ERASEINFO(0x10000, 15), 910 } 911 }, { 912 .mfr_id = MANUFACTURER_INTEL, 913 .dev_id = I28F008B3T, 914 .name = "Intel 28F008B3T", 915 .devtypes = CFI_DEVICETYPE_X8, 916 .uaddr = MTD_UADDR_UNNECESSARY, 917 .dev_size = SIZE_1MiB, 918 .cmd_set = P_ID_INTEL_STD, 919 .nr_regions = 2, 920 .regions = { 921 ERASEINFO(0x10000, 15), 922 ERASEINFO(0x02000, 8), 923 } 924 }, { 925 .mfr_id = MANUFACTURER_INTEL, 926 .dev_id = I28F008S5, 927 .name = "Intel 28F008S5", 928 .devtypes = CFI_DEVICETYPE_X8, 929 .uaddr = MTD_UADDR_UNNECESSARY, 930 .dev_size = SIZE_1MiB, 931 .cmd_set = P_ID_INTEL_EXT, 932 .nr_regions = 1, 933 .regions = { 934 ERASEINFO(0x10000,16), 935 } 936 }, { 937 .mfr_id = MANUFACTURER_INTEL, 938 .dev_id = I28F016S5, 939 .name = "Intel 28F016S5", 940 .devtypes = CFI_DEVICETYPE_X8, 941 .uaddr = MTD_UADDR_UNNECESSARY, 942 .dev_size = SIZE_2MiB, 943 .cmd_set = P_ID_INTEL_EXT, 944 .nr_regions = 1, 945 .regions = { 946 ERASEINFO(0x10000,32), 947 } 948 }, { 949 .mfr_id = MANUFACTURER_INTEL, 950 .dev_id = I28F008SA, 951 .name = "Intel 28F008SA", 952 .devtypes = CFI_DEVICETYPE_X8, 953 .uaddr = MTD_UADDR_UNNECESSARY, 954 .dev_size = SIZE_1MiB, 955 .cmd_set = P_ID_INTEL_STD, 956 .nr_regions = 1, 957 .regions = { 958 ERASEINFO(0x10000, 16), 959 } 960 }, { 961 .mfr_id = MANUFACTURER_INTEL, 962 .dev_id = I28F800B3B, 963 .name = "Intel 28F800B3B", 964 .devtypes = CFI_DEVICETYPE_X16, 965 .uaddr = MTD_UADDR_UNNECESSARY, 966 .dev_size = SIZE_1MiB, 967 .cmd_set = P_ID_INTEL_STD, 968 .nr_regions = 2, 969 .regions = { 970 ERASEINFO(0x02000, 8), 971 ERASEINFO(0x10000, 15), 972 } 973 }, { 974 .mfr_id = MANUFACTURER_INTEL, 975 .dev_id = I28F800B3T, 976 .name = "Intel 28F800B3T", 977 .devtypes = CFI_DEVICETYPE_X16, 978 .uaddr = MTD_UADDR_UNNECESSARY, 979 .dev_size = SIZE_1MiB, 980 .cmd_set = P_ID_INTEL_STD, 981 .nr_regions = 2, 982 .regions = { 983 ERASEINFO(0x10000, 15), 984 ERASEINFO(0x02000, 8), 985 } 986 }, { 987 .mfr_id = MANUFACTURER_INTEL, 988 .dev_id = I28F016B3B, 989 .name = "Intel 28F016B3B", 990 .devtypes = CFI_DEVICETYPE_X8, 991 .uaddr = MTD_UADDR_UNNECESSARY, 992 .dev_size = SIZE_2MiB, 993 .cmd_set = P_ID_INTEL_STD, 994 .nr_regions = 2, 995 .regions = { 996 ERASEINFO(0x02000, 8), 997 ERASEINFO(0x10000, 31), 998 } 999 }, { 1000 .mfr_id = MANUFACTURER_INTEL, 1001 .dev_id = I28F016S3, 1002 .name = "Intel I28F016S3", 1003 .devtypes = CFI_DEVICETYPE_X8, 1004 .uaddr = MTD_UADDR_UNNECESSARY, 1005 .dev_size = SIZE_2MiB, 1006 .cmd_set = P_ID_INTEL_STD, 1007 .nr_regions = 1, 1008 .regions = { 1009 ERASEINFO(0x10000, 32), 1010 } 1011 }, { 1012 .mfr_id = MANUFACTURER_INTEL, 1013 .dev_id = I28F016B3T, 1014 .name = "Intel 28F016B3T", 1015 .devtypes = CFI_DEVICETYPE_X8, 1016 .uaddr = MTD_UADDR_UNNECESSARY, 1017 .dev_size = SIZE_2MiB, 1018 .cmd_set = P_ID_INTEL_STD, 1019 .nr_regions = 2, 1020 .regions = { 1021 ERASEINFO(0x10000, 31), 1022 ERASEINFO(0x02000, 8), 1023 } 1024 }, { 1025 .mfr_id = MANUFACTURER_INTEL, 1026 .dev_id = I28F160B3B, 1027 .name = "Intel 28F160B3B", 1028 .devtypes = CFI_DEVICETYPE_X16, 1029 .uaddr = MTD_UADDR_UNNECESSARY, 1030 .dev_size = SIZE_2MiB, 1031 .cmd_set = P_ID_INTEL_STD, 1032 .nr_regions = 2, 1033 .regions = { 1034 ERASEINFO(0x02000, 8), 1035 ERASEINFO(0x10000, 31), 1036 } 1037 }, { 1038 .mfr_id = MANUFACTURER_INTEL, 1039 .dev_id = I28F160B3T, 1040 .name = "Intel 28F160B3T", 1041 .devtypes = CFI_DEVICETYPE_X16, 1042 .uaddr = MTD_UADDR_UNNECESSARY, 1043 .dev_size = SIZE_2MiB, 1044 .cmd_set = P_ID_INTEL_STD, 1045 .nr_regions = 2, 1046 .regions = { 1047 ERASEINFO(0x10000, 31), 1048 ERASEINFO(0x02000, 8), 1049 } 1050 }, { 1051 .mfr_id = MANUFACTURER_INTEL, 1052 .dev_id = I28F320B3B, 1053 .name = "Intel 28F320B3B", 1054 .devtypes = CFI_DEVICETYPE_X16, 1055 .uaddr = MTD_UADDR_UNNECESSARY, 1056 .dev_size = SIZE_4MiB, 1057 .cmd_set = P_ID_INTEL_STD, 1058 .nr_regions = 2, 1059 .regions = { 1060 ERASEINFO(0x02000, 8), 1061 ERASEINFO(0x10000, 63), 1062 } 1063 }, { 1064 .mfr_id = MANUFACTURER_INTEL, 1065 .dev_id = I28F320B3T, 1066 .name = "Intel 28F320B3T", 1067 .devtypes = CFI_DEVICETYPE_X16, 1068 .uaddr = MTD_UADDR_UNNECESSARY, 1069 .dev_size = SIZE_4MiB, 1070 .cmd_set = P_ID_INTEL_STD, 1071 .nr_regions = 2, 1072 .regions = { 1073 ERASEINFO(0x10000, 63), 1074 ERASEINFO(0x02000, 8), 1075 } 1076 }, { 1077 .mfr_id = MANUFACTURER_INTEL, 1078 .dev_id = I28F640B3B, 1079 .name = "Intel 28F640B3B", 1080 .devtypes = CFI_DEVICETYPE_X16, 1081 .uaddr = MTD_UADDR_UNNECESSARY, 1082 .dev_size = SIZE_8MiB, 1083 .cmd_set = P_ID_INTEL_STD, 1084 .nr_regions = 2, 1085 .regions = { 1086 ERASEINFO(0x02000, 8), 1087 ERASEINFO(0x10000, 127), 1088 } 1089 }, { 1090 .mfr_id = MANUFACTURER_INTEL, 1091 .dev_id = I28F640B3T, 1092 .name = "Intel 28F640B3T", 1093 .devtypes = CFI_DEVICETYPE_X16, 1094 .uaddr = MTD_UADDR_UNNECESSARY, 1095 .dev_size = SIZE_8MiB, 1096 .cmd_set = P_ID_INTEL_STD, 1097 .nr_regions = 2, 1098 .regions = { 1099 ERASEINFO(0x10000, 127), 1100 ERASEINFO(0x02000, 8), 1101 } 1102 }, { 1103 .mfr_id = MANUFACTURER_INTEL, 1104 .dev_id = I82802AB, 1105 .name = "Intel 82802AB", 1106 .devtypes = CFI_DEVICETYPE_X8, 1107 .uaddr = MTD_UADDR_UNNECESSARY, 1108 .dev_size = SIZE_512KiB, 1109 .cmd_set = P_ID_INTEL_EXT, 1110 .nr_regions = 1, 1111 .regions = { 1112 ERASEINFO(0x10000,8), 1113 } 1114 }, { 1115 .mfr_id = MANUFACTURER_INTEL, 1116 .dev_id = I82802AC, 1117 .name = "Intel 82802AC", 1118 .devtypes = CFI_DEVICETYPE_X8, 1119 .uaddr = MTD_UADDR_UNNECESSARY, 1120 .dev_size = SIZE_1MiB, 1121 .cmd_set = P_ID_INTEL_EXT, 1122 .nr_regions = 1, 1123 .regions = { 1124 ERASEINFO(0x10000,16), 1125 } 1126 }, { 1127 .mfr_id = MANUFACTURER_MACRONIX, 1128 .dev_id = MX29LV040C, 1129 .name = "Macronix MX29LV040C", 1130 .devtypes = CFI_DEVICETYPE_X8, 1131 .uaddr = MTD_UADDR_0x0555_0x02AA, 1132 .dev_size = SIZE_512KiB, 1133 .cmd_set = P_ID_AMD_STD, 1134 .nr_regions = 1, 1135 .regions = { 1136 ERASEINFO(0x10000,8), 1137 } 1138 }, { 1139 .mfr_id = MANUFACTURER_MACRONIX, 1140 .dev_id = MX29LV160T, 1141 .name = "MXIC MX29LV160T", 1142 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1143 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1144 .dev_size = SIZE_2MiB, 1145 .cmd_set = P_ID_AMD_STD, 1146 .nr_regions = 4, 1147 .regions = { 1148 ERASEINFO(0x10000,31), 1149 ERASEINFO(0x08000,1), 1150 ERASEINFO(0x02000,2), 1151 ERASEINFO(0x04000,1) 1152 } 1153 }, { 1154 .mfr_id = MANUFACTURER_NEC, 1155 .dev_id = UPD29F064115, 1156 .name = "NEC uPD29F064115", 1157 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1158 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1159 .dev_size = SIZE_8MiB, 1160 .cmd_set = P_ID_AMD_STD, 1161 .nr_regions = 3, 1162 .regions = { 1163 ERASEINFO(0x2000,8), 1164 ERASEINFO(0x10000,126), 1165 ERASEINFO(0x2000,8), 1166 } 1167 }, { 1168 .mfr_id = MANUFACTURER_MACRONIX, 1169 .dev_id = MX29LV160B, 1170 .name = "MXIC MX29LV160B", 1171 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1172 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1173 .dev_size = SIZE_2MiB, 1174 .cmd_set = P_ID_AMD_STD, 1175 .nr_regions = 4, 1176 .regions = { 1177 ERASEINFO(0x04000,1), 1178 ERASEINFO(0x02000,2), 1179 ERASEINFO(0x08000,1), 1180 ERASEINFO(0x10000,31) 1181 } 1182 }, { 1183 .mfr_id = MANUFACTURER_MACRONIX, 1184 .dev_id = MX29F040, 1185 .name = "Macronix MX29F040", 1186 .devtypes = CFI_DEVICETYPE_X8, 1187 .uaddr = MTD_UADDR_0x0555_0x02AA, 1188 .dev_size = SIZE_512KiB, 1189 .cmd_set = P_ID_AMD_STD, 1190 .nr_regions = 1, 1191 .regions = { 1192 ERASEINFO(0x10000,8), 1193 } 1194 }, { 1195 .mfr_id = MANUFACTURER_MACRONIX, 1196 .dev_id = MX29F016, 1197 .name = "Macronix MX29F016", 1198 .devtypes = CFI_DEVICETYPE_X8, 1199 .uaddr = MTD_UADDR_0x0555_0x02AA, 1200 .dev_size = SIZE_2MiB, 1201 .cmd_set = P_ID_AMD_STD, 1202 .nr_regions = 1, 1203 .regions = { 1204 ERASEINFO(0x10000,32), 1205 } 1206 }, { 1207 .mfr_id = MANUFACTURER_MACRONIX, 1208 .dev_id = MX29F004T, 1209 .name = "Macronix MX29F004T", 1210 .devtypes = CFI_DEVICETYPE_X8, 1211 .uaddr = MTD_UADDR_0x0555_0x02AA, 1212 .dev_size = SIZE_512KiB, 1213 .cmd_set = P_ID_AMD_STD, 1214 .nr_regions = 4, 1215 .regions = { 1216 ERASEINFO(0x10000,7), 1217 ERASEINFO(0x08000,1), 1218 ERASEINFO(0x02000,2), 1219 ERASEINFO(0x04000,1), 1220 } 1221 }, { 1222 .mfr_id = MANUFACTURER_MACRONIX, 1223 .dev_id = MX29F004B, 1224 .name = "Macronix MX29F004B", 1225 .devtypes = CFI_DEVICETYPE_X8, 1226 .uaddr = MTD_UADDR_0x0555_0x02AA, 1227 .dev_size = SIZE_512KiB, 1228 .cmd_set = P_ID_AMD_STD, 1229 .nr_regions = 4, 1230 .regions = { 1231 ERASEINFO(0x04000,1), 1232 ERASEINFO(0x02000,2), 1233 ERASEINFO(0x08000,1), 1234 ERASEINFO(0x10000,7), 1235 } 1236 }, { 1237 .mfr_id = MANUFACTURER_MACRONIX, 1238 .dev_id = MX29F002T, 1239 .name = "Macronix MX29F002T", 1240 .devtypes = CFI_DEVICETYPE_X8, 1241 .uaddr = MTD_UADDR_0x0555_0x02AA, 1242 .dev_size = SIZE_256KiB, 1243 .cmd_set = P_ID_AMD_STD, 1244 .nr_regions = 4, 1245 .regions = { 1246 ERASEINFO(0x10000,3), 1247 ERASEINFO(0x08000,1), 1248 ERASEINFO(0x02000,2), 1249 ERASEINFO(0x04000,1), 1250 } 1251 }, { 1252 .mfr_id = MANUFACTURER_PMC, 1253 .dev_id = PM49FL002, 1254 .name = "PMC Pm49FL002", 1255 .devtypes = CFI_DEVICETYPE_X8, 1256 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1257 .dev_size = SIZE_256KiB, 1258 .cmd_set = P_ID_AMD_STD, 1259 .nr_regions = 1, 1260 .regions = { 1261 ERASEINFO( 0x01000, 64 ) 1262 } 1263 }, { 1264 .mfr_id = MANUFACTURER_PMC, 1265 .dev_id = PM49FL004, 1266 .name = "PMC Pm49FL004", 1267 .devtypes = CFI_DEVICETYPE_X8, 1268 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1269 .dev_size = SIZE_512KiB, 1270 .cmd_set = P_ID_AMD_STD, 1271 .nr_regions = 1, 1272 .regions = { 1273 ERASEINFO( 0x01000, 128 ) 1274 } 1275 }, { 1276 .mfr_id = MANUFACTURER_PMC, 1277 .dev_id = PM49FL008, 1278 .name = "PMC Pm49FL008", 1279 .devtypes = CFI_DEVICETYPE_X8, 1280 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1281 .dev_size = SIZE_1MiB, 1282 .cmd_set = P_ID_AMD_STD, 1283 .nr_regions = 1, 1284 .regions = { 1285 ERASEINFO( 0x01000, 256 ) 1286 } 1287 }, { 1288 .mfr_id = MANUFACTURER_SHARP, 1289 .dev_id = LH28F640BF, 1290 .name = "LH28F640BF", 1291 .devtypes = CFI_DEVICETYPE_X8, 1292 .uaddr = MTD_UADDR_UNNECESSARY, 1293 .dev_size = SIZE_4MiB, 1294 .cmd_set = P_ID_INTEL_STD, 1295 .nr_regions = 1, 1296 .regions = { 1297 ERASEINFO(0x40000,16), 1298 } 1299 }, { 1300 .mfr_id = MANUFACTURER_SST, 1301 .dev_id = SST39LF512, 1302 .name = "SST 39LF512", 1303 .devtypes = CFI_DEVICETYPE_X8, 1304 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1305 .dev_size = SIZE_64KiB, 1306 .cmd_set = P_ID_AMD_STD, 1307 .nr_regions = 1, 1308 .regions = { 1309 ERASEINFO(0x01000,16), 1310 } 1311 }, { 1312 .mfr_id = MANUFACTURER_SST, 1313 .dev_id = SST39LF010, 1314 .name = "SST 39LF010", 1315 .devtypes = CFI_DEVICETYPE_X8, 1316 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1317 .dev_size = SIZE_128KiB, 1318 .cmd_set = P_ID_AMD_STD, 1319 .nr_regions = 1, 1320 .regions = { 1321 ERASEINFO(0x01000,32), 1322 } 1323 }, { 1324 .mfr_id = MANUFACTURER_SST, 1325 .dev_id = SST29EE020, 1326 .name = "SST 29EE020", 1327 .devtypes = CFI_DEVICETYPE_X8, 1328 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1329 .dev_size = SIZE_256KiB, 1330 .cmd_set = P_ID_SST_PAGE, 1331 .nr_regions = 1, 1332 .regions = {ERASEINFO(0x01000,64), 1333 } 1334 }, { 1335 .mfr_id = MANUFACTURER_SST, 1336 .dev_id = SST29LE020, 1337 .name = "SST 29LE020", 1338 .devtypes = CFI_DEVICETYPE_X8, 1339 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1340 .dev_size = SIZE_256KiB, 1341 .cmd_set = P_ID_SST_PAGE, 1342 .nr_regions = 1, 1343 .regions = {ERASEINFO(0x01000,64), 1344 } 1345 }, { 1346 .mfr_id = MANUFACTURER_SST, 1347 .dev_id = SST39LF020, 1348 .name = "SST 39LF020", 1349 .devtypes = CFI_DEVICETYPE_X8, 1350 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1351 .dev_size = SIZE_256KiB, 1352 .cmd_set = P_ID_AMD_STD, 1353 .nr_regions = 1, 1354 .regions = { 1355 ERASEINFO(0x01000,64), 1356 } 1357 }, { 1358 .mfr_id = MANUFACTURER_SST, 1359 .dev_id = SST39LF040, 1360 .name = "SST 39LF040", 1361 .devtypes = CFI_DEVICETYPE_X8, 1362 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1363 .dev_size = SIZE_512KiB, 1364 .cmd_set = P_ID_AMD_STD, 1365 .nr_regions = 1, 1366 .regions = { 1367 ERASEINFO(0x01000,128), 1368 } 1369 }, { 1370 .mfr_id = MANUFACTURER_SST, 1371 .dev_id = SST39SF010A, 1372 .name = "SST 39SF010A", 1373 .devtypes = CFI_DEVICETYPE_X8, 1374 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1375 .dev_size = SIZE_128KiB, 1376 .cmd_set = P_ID_AMD_STD, 1377 .nr_regions = 1, 1378 .regions = { 1379 ERASEINFO(0x01000,32), 1380 } 1381 }, { 1382 .mfr_id = MANUFACTURER_SST, 1383 .dev_id = SST39SF020A, 1384 .name = "SST 39SF020A", 1385 .devtypes = CFI_DEVICETYPE_X8, 1386 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1387 .dev_size = SIZE_256KiB, 1388 .cmd_set = P_ID_AMD_STD, 1389 .nr_regions = 1, 1390 .regions = { 1391 ERASEINFO(0x01000,64), 1392 } 1393 }, { 1394 .mfr_id = MANUFACTURER_SST, 1395 .dev_id = SST49LF040B, 1396 .name = "SST 49LF040B", 1397 .devtypes = CFI_DEVICETYPE_X8, 1398 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1399 .dev_size = SIZE_512KiB, 1400 .cmd_set = P_ID_AMD_STD, 1401 .nr_regions = 1, 1402 .regions = { 1403 ERASEINFO(0x01000,128), 1404 } 1405 }, { 1406 1407 .mfr_id = MANUFACTURER_SST, 1408 .dev_id = SST49LF004B, 1409 .name = "SST 49LF004B", 1410 .devtypes = CFI_DEVICETYPE_X8, 1411 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1412 .dev_size = SIZE_512KiB, 1413 .cmd_set = P_ID_AMD_STD, 1414 .nr_regions = 1, 1415 .regions = { 1416 ERASEINFO(0x01000,128), 1417 } 1418 }, { 1419 .mfr_id = MANUFACTURER_SST, 1420 .dev_id = SST49LF008A, 1421 .name = "SST 49LF008A", 1422 .devtypes = CFI_DEVICETYPE_X8, 1423 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1424 .dev_size = SIZE_1MiB, 1425 .cmd_set = P_ID_AMD_STD, 1426 .nr_regions = 1, 1427 .regions = { 1428 ERASEINFO(0x01000,256), 1429 } 1430 }, { 1431 .mfr_id = MANUFACTURER_SST, 1432 .dev_id = SST49LF030A, 1433 .name = "SST 49LF030A", 1434 .devtypes = CFI_DEVICETYPE_X8, 1435 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1436 .dev_size = SIZE_512KiB, 1437 .cmd_set = P_ID_AMD_STD, 1438 .nr_regions = 1, 1439 .regions = { 1440 ERASEINFO(0x01000,96), 1441 } 1442 }, { 1443 .mfr_id = MANUFACTURER_SST, 1444 .dev_id = SST49LF040A, 1445 .name = "SST 49LF040A", 1446 .devtypes = CFI_DEVICETYPE_X8, 1447 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1448 .dev_size = SIZE_512KiB, 1449 .cmd_set = P_ID_AMD_STD, 1450 .nr_regions = 1, 1451 .regions = { 1452 ERASEINFO(0x01000,128), 1453 } 1454 }, { 1455 .mfr_id = MANUFACTURER_SST, 1456 .dev_id = SST49LF080A, 1457 .name = "SST 49LF080A", 1458 .devtypes = CFI_DEVICETYPE_X8, 1459 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1460 .dev_size = SIZE_1MiB, 1461 .cmd_set = P_ID_AMD_STD, 1462 .nr_regions = 1, 1463 .regions = { 1464 ERASEINFO(0x01000,256), 1465 } 1466 }, { 1467 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1468 .dev_id = SST39LF160, 1469 .name = "SST 39LF160", 1470 .devtypes = CFI_DEVICETYPE_X16, 1471 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1472 .dev_size = SIZE_2MiB, 1473 .cmd_set = P_ID_AMD_STD, 1474 .nr_regions = 2, 1475 .regions = { 1476 ERASEINFO(0x1000,256), 1477 ERASEINFO(0x1000,256) 1478 } 1479 }, { 1480 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1481 .dev_id = SST39VF1601, 1482 .name = "SST 39VF1601", 1483 .devtypes = CFI_DEVICETYPE_X16, 1484 .uaddr = MTD_UADDR_0xAAAA_0x5555, 1485 .dev_size = SIZE_2MiB, 1486 .cmd_set = P_ID_AMD_STD, 1487 .nr_regions = 2, 1488 .regions = { 1489 ERASEINFO(0x1000,256), 1490 ERASEINFO(0x1000,256) 1491 } 1492 }, { 1493 .mfr_id = MANUFACTURER_SST, 1494 .dev_id = SST36VF3203, 1495 .name = "SST 36VF3203", 1496 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1497 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1498 .dev_size = SIZE_4MiB, 1499 .cmd_set = P_ID_AMD_STD, 1500 .nr_regions = 1, 1501 .regions = { 1502 ERASEINFO(0x10000,64), 1503 } 1504 }, { 1505 .mfr_id = MANUFACTURER_ST, 1506 .dev_id = M29F800AB, 1507 .name = "ST M29F800AB", 1508 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1509 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1510 .dev_size = SIZE_1MiB, 1511 .cmd_set = P_ID_AMD_STD, 1512 .nr_regions = 4, 1513 .regions = { 1514 ERASEINFO(0x04000,1), 1515 ERASEINFO(0x02000,2), 1516 ERASEINFO(0x08000,1), 1517 ERASEINFO(0x10000,15), 1518 } 1519 }, { 1520 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1521 .dev_id = M29W800DT, 1522 .name = "ST M29W800DT", 1523 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1524 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1525 .dev_size = SIZE_1MiB, 1526 .cmd_set = P_ID_AMD_STD, 1527 .nr_regions = 4, 1528 .regions = { 1529 ERASEINFO(0x10000,15), 1530 ERASEINFO(0x08000,1), 1531 ERASEINFO(0x02000,2), 1532 ERASEINFO(0x04000,1) 1533 } 1534 }, { 1535 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1536 .dev_id = M29W800DB, 1537 .name = "ST M29W800DB", 1538 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1539 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1540 .dev_size = SIZE_1MiB, 1541 .cmd_set = P_ID_AMD_STD, 1542 .nr_regions = 4, 1543 .regions = { 1544 ERASEINFO(0x04000,1), 1545 ERASEINFO(0x02000,2), 1546 ERASEINFO(0x08000,1), 1547 ERASEINFO(0x10000,15) 1548 } 1549 }, { 1550 .mfr_id = MANUFACTURER_ST, 1551 .dev_id = M29W400DT, 1552 .name = "ST M29W400DT", 1553 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1554 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1555 .dev_size = SIZE_512KiB, 1556 .cmd_set = P_ID_AMD_STD, 1557 .nr_regions = 4, 1558 .regions = { 1559 ERASEINFO(0x04000,7), 1560 ERASEINFO(0x02000,1), 1561 ERASEINFO(0x08000,2), 1562 ERASEINFO(0x10000,1) 1563 } 1564 }, { 1565 .mfr_id = MANUFACTURER_ST, 1566 .dev_id = M29W400DB, 1567 .name = "ST M29W400DB", 1568 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1569 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1570 .dev_size = SIZE_512KiB, 1571 .cmd_set = P_ID_AMD_STD, 1572 .nr_regions = 4, 1573 .regions = { 1574 ERASEINFO(0x04000,1), 1575 ERASEINFO(0x02000,2), 1576 ERASEINFO(0x08000,1), 1577 ERASEINFO(0x10000,7) 1578 } 1579 }, { 1580 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1581 .dev_id = M29W160DT, 1582 .name = "ST M29W160DT", 1583 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1584 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1585 .dev_size = SIZE_2MiB, 1586 .cmd_set = P_ID_AMD_STD, 1587 .nr_regions = 4, 1588 .regions = { 1589 ERASEINFO(0x10000,31), 1590 ERASEINFO(0x08000,1), 1591 ERASEINFO(0x02000,2), 1592 ERASEINFO(0x04000,1) 1593 } 1594 }, { 1595 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1596 .dev_id = M29W160DB, 1597 .name = "ST M29W160DB", 1598 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1599 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1600 .dev_size = SIZE_2MiB, 1601 .cmd_set = P_ID_AMD_STD, 1602 .nr_regions = 4, 1603 .regions = { 1604 ERASEINFO(0x04000,1), 1605 ERASEINFO(0x02000,2), 1606 ERASEINFO(0x08000,1), 1607 ERASEINFO(0x10000,31) 1608 } 1609 }, { 1610 .mfr_id = MANUFACTURER_ST, 1611 .dev_id = M29W040B, 1612 .name = "ST M29W040B", 1613 .devtypes = CFI_DEVICETYPE_X8, 1614 .uaddr = MTD_UADDR_0x0555_0x02AA, 1615 .dev_size = SIZE_512KiB, 1616 .cmd_set = P_ID_AMD_STD, 1617 .nr_regions = 1, 1618 .regions = { 1619 ERASEINFO(0x10000,8), 1620 } 1621 }, { 1622 .mfr_id = MANUFACTURER_ST, 1623 .dev_id = M50FW040, 1624 .name = "ST M50FW040", 1625 .devtypes = CFI_DEVICETYPE_X8, 1626 .uaddr = MTD_UADDR_UNNECESSARY, 1627 .dev_size = SIZE_512KiB, 1628 .cmd_set = P_ID_INTEL_EXT, 1629 .nr_regions = 1, 1630 .regions = { 1631 ERASEINFO(0x10000,8), 1632 } 1633 }, { 1634 .mfr_id = MANUFACTURER_ST, 1635 .dev_id = M50FW080, 1636 .name = "ST M50FW080", 1637 .devtypes = CFI_DEVICETYPE_X8, 1638 .uaddr = MTD_UADDR_UNNECESSARY, 1639 .dev_size = SIZE_1MiB, 1640 .cmd_set = P_ID_INTEL_EXT, 1641 .nr_regions = 1, 1642 .regions = { 1643 ERASEINFO(0x10000,16), 1644 } 1645 }, { 1646 .mfr_id = MANUFACTURER_ST, 1647 .dev_id = M50FW016, 1648 .name = "ST M50FW016", 1649 .devtypes = CFI_DEVICETYPE_X8, 1650 .uaddr = MTD_UADDR_UNNECESSARY, 1651 .dev_size = SIZE_2MiB, 1652 .cmd_set = P_ID_INTEL_EXT, 1653 .nr_regions = 1, 1654 .regions = { 1655 ERASEINFO(0x10000,32), 1656 } 1657 }, { 1658 .mfr_id = MANUFACTURER_ST, 1659 .dev_id = M50LPW080, 1660 .name = "ST M50LPW080", 1661 .devtypes = CFI_DEVICETYPE_X8, 1662 .uaddr = MTD_UADDR_UNNECESSARY, 1663 .dev_size = SIZE_1MiB, 1664 .cmd_set = P_ID_INTEL_EXT, 1665 .nr_regions = 1, 1666 .regions = { 1667 ERASEINFO(0x10000,16), 1668 }, 1669 }, { 1670 .mfr_id = MANUFACTURER_ST, 1671 .dev_id = M50FLW080A, 1672 .name = "ST M50FLW080A", 1673 .devtypes = CFI_DEVICETYPE_X8, 1674 .uaddr = MTD_UADDR_UNNECESSARY, 1675 .dev_size = SIZE_1MiB, 1676 .cmd_set = P_ID_INTEL_EXT, 1677 .nr_regions = 4, 1678 .regions = { 1679 ERASEINFO(0x1000,16), 1680 ERASEINFO(0x10000,13), 1681 ERASEINFO(0x1000,16), 1682 ERASEINFO(0x1000,16), 1683 } 1684 }, { 1685 .mfr_id = MANUFACTURER_ST, 1686 .dev_id = M50FLW080B, 1687 .name = "ST M50FLW080B", 1688 .devtypes = CFI_DEVICETYPE_X8, 1689 .uaddr = MTD_UADDR_UNNECESSARY, 1690 .dev_size = SIZE_1MiB, 1691 .cmd_set = P_ID_INTEL_EXT, 1692 .nr_regions = 4, 1693 .regions = { 1694 ERASEINFO(0x1000,16), 1695 ERASEINFO(0x1000,16), 1696 ERASEINFO(0x10000,13), 1697 ERASEINFO(0x1000,16), 1698 } 1699 }, { 1700 .mfr_id = MANUFACTURER_TOSHIBA, 1701 .dev_id = TC58FVT160, 1702 .name = "Toshiba TC58FVT160", 1703 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1704 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1705 .dev_size = SIZE_2MiB, 1706 .cmd_set = P_ID_AMD_STD, 1707 .nr_regions = 4, 1708 .regions = { 1709 ERASEINFO(0x10000,31), 1710 ERASEINFO(0x08000,1), 1711 ERASEINFO(0x02000,2), 1712 ERASEINFO(0x04000,1) 1713 } 1714 }, { 1715 .mfr_id = MANUFACTURER_TOSHIBA, 1716 .dev_id = TC58FVB160, 1717 .name = "Toshiba TC58FVB160", 1718 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1719 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1720 .dev_size = SIZE_2MiB, 1721 .cmd_set = P_ID_AMD_STD, 1722 .nr_regions = 4, 1723 .regions = { 1724 ERASEINFO(0x04000,1), 1725 ERASEINFO(0x02000,2), 1726 ERASEINFO(0x08000,1), 1727 ERASEINFO(0x10000,31) 1728 } 1729 }, { 1730 .mfr_id = MANUFACTURER_TOSHIBA, 1731 .dev_id = TC58FVB321, 1732 .name = "Toshiba TC58FVB321", 1733 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1734 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1735 .dev_size = SIZE_4MiB, 1736 .cmd_set = P_ID_AMD_STD, 1737 .nr_regions = 2, 1738 .regions = { 1739 ERASEINFO(0x02000,8), 1740 ERASEINFO(0x10000,63) 1741 } 1742 }, { 1743 .mfr_id = MANUFACTURER_TOSHIBA, 1744 .dev_id = TC58FVT321, 1745 .name = "Toshiba TC58FVT321", 1746 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1747 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1748 .dev_size = SIZE_4MiB, 1749 .cmd_set = P_ID_AMD_STD, 1750 .nr_regions = 2, 1751 .regions = { 1752 ERASEINFO(0x10000,63), 1753 ERASEINFO(0x02000,8) 1754 } 1755 }, { 1756 .mfr_id = MANUFACTURER_TOSHIBA, 1757 .dev_id = TC58FVB641, 1758 .name = "Toshiba TC58FVB641", 1759 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1760 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1761 .dev_size = SIZE_8MiB, 1762 .cmd_set = P_ID_AMD_STD, 1763 .nr_regions = 2, 1764 .regions = { 1765 ERASEINFO(0x02000,8), 1766 ERASEINFO(0x10000,127) 1767 } 1768 }, { 1769 .mfr_id = MANUFACTURER_TOSHIBA, 1770 .dev_id = TC58FVT641, 1771 .name = "Toshiba TC58FVT641", 1772 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1773 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1774 .dev_size = SIZE_8MiB, 1775 .cmd_set = P_ID_AMD_STD, 1776 .nr_regions = 2, 1777 .regions = { 1778 ERASEINFO(0x10000,127), 1779 ERASEINFO(0x02000,8) 1780 } 1781 }, { 1782 .mfr_id = MANUFACTURER_WINBOND, 1783 .dev_id = W49V002A, 1784 .name = "Winbond W49V002A", 1785 .devtypes = CFI_DEVICETYPE_X8, 1786 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1787 .dev_size = SIZE_256KiB, 1788 .cmd_set = P_ID_AMD_STD, 1789 .nr_regions = 4, 1790 .regions = { 1791 ERASEINFO(0x10000, 3), 1792 ERASEINFO(0x08000, 1), 1793 ERASEINFO(0x02000, 2), 1794 ERASEINFO(0x04000, 1), 1795 } 1796 } 1797 }; 1798 1799 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, 1800 struct cfi_private *cfi) 1801 { 1802 map_word result; 1803 unsigned long mask; 1804 int bank = 0; 1805 1806 /* According to JEDEC "Standard Manufacturer's Identification Code" 1807 * (http://www.jedec.org/download/search/jep106W.pdf) 1808 * several first banks can contain 0x7f instead of actual ID 1809 */ 1810 do { 1811 uint32_t ofs = cfi_build_cmd_addr(0 + (bank << 8), map, cfi); 1812 mask = (1 << (cfi->device_type * 8)) - 1; 1813 result = map_read(map, base + ofs); 1814 bank++; 1815 } while ((result.x[0] & mask) == CONTINUATION_CODE); 1816 1817 return result.x[0] & mask; 1818 } 1819 1820 static inline u32 jedec_read_id(struct map_info *map, uint32_t base, 1821 struct cfi_private *cfi) 1822 { 1823 map_word result; 1824 unsigned long mask; 1825 u32 ofs = cfi_build_cmd_addr(1, map, cfi); 1826 mask = (1 << (cfi->device_type * 8)) -1; 1827 result = map_read(map, base + ofs); 1828 return result.x[0] & mask; 1829 } 1830 1831 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) 1832 { 1833 /* Reset */ 1834 1835 /* after checking the datasheets for SST, MACRONIX and ATMEL 1836 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset 1837 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at 1838 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1839 * as they will ignore the writes and dont care what address 1840 * the F0 is written to */ 1841 if (cfi->addr_unlock1) { 1842 DEBUG( MTD_DEBUG_LEVEL3, 1843 "reset unlock called %x %x \n", 1844 cfi->addr_unlock1,cfi->addr_unlock2); 1845 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1846 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1847 } 1848 1849 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1850 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, 1851 * so ensure we're in read mode. Send both the Intel and the AMD command 1852 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1853 * this should be safe. 1854 */ 1855 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); 1856 /* FIXME - should have reset delay before continuing */ 1857 } 1858 1859 1860 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1861 { 1862 int i,num_erase_regions; 1863 uint8_t uaddr; 1864 1865 if (! (jedec_table[index].devtypes & p_cfi->device_type)) { 1866 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", 1867 jedec_table[index].name, 4 * (1<<p_cfi->device_type)); 1868 return 0; 1869 } 1870 1871 printk(KERN_INFO "Found: %s\n",jedec_table[index].name); 1872 1873 num_erase_regions = jedec_table[index].nr_regions; 1874 1875 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1876 if (!p_cfi->cfiq) { 1877 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); 1878 return 0; 1879 } 1880 1881 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1882 1883 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; 1884 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; 1885 p_cfi->cfiq->DevSize = jedec_table[index].dev_size; 1886 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1887 1888 for (i=0; i<num_erase_regions; i++){ 1889 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; 1890 } 1891 p_cfi->cmdset_priv = NULL; 1892 1893 /* This may be redundant for some cases, but it doesn't hurt */ 1894 p_cfi->mfr = jedec_table[index].mfr_id; 1895 p_cfi->id = jedec_table[index].dev_id; 1896 1897 uaddr = jedec_table[index].uaddr; 1898 1899 /* The table has unlock addresses in _bytes_, and we try not to let 1900 our brains explode when we see the datasheets talking about address 1901 lines numbered from A-1 to A18. The CFI table has unlock addresses 1902 in device-words according to the mode the device is connected in */ 1903 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; 1904 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; 1905 1906 return 1; /* ok */ 1907 } 1908 1909 1910 /* 1911 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing 1912 * the mapped address, unlock addresses, and proper chip ID. This function 1913 * attempts to minimize errors. It is doubtfull that this probe will ever 1914 * be perfect - consequently there should be some module parameters that 1915 * could be manually specified to force the chip info. 1916 */ 1917 static inline int jedec_match( uint32_t base, 1918 struct map_info *map, 1919 struct cfi_private *cfi, 1920 const struct amd_flash_info *finfo ) 1921 { 1922 int rc = 0; /* failure until all tests pass */ 1923 u32 mfr, id; 1924 uint8_t uaddr; 1925 1926 /* 1927 * The IDs must match. For X16 and X32 devices operating in 1928 * a lower width ( X8 or X16 ), the device ID's are usually just 1929 * the lower byte(s) of the larger device ID for wider mode. If 1930 * a part is found that doesn't fit this assumption (device id for 1931 * smaller width mode is completely unrealated to full-width mode) 1932 * then the jedec_table[] will have to be augmented with the IDs 1933 * for different widths. 1934 */ 1935 switch (cfi->device_type) { 1936 case CFI_DEVICETYPE_X8: 1937 mfr = (uint8_t)finfo->mfr_id; 1938 id = (uint8_t)finfo->dev_id; 1939 1940 /* bjd: it seems that if we do this, we can end up 1941 * detecting 16bit flashes as an 8bit device, even though 1942 * there aren't. 1943 */ 1944 if (finfo->dev_id > 0xff) { 1945 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", 1946 __func__); 1947 goto match_done; 1948 } 1949 break; 1950 case CFI_DEVICETYPE_X16: 1951 mfr = (uint16_t)finfo->mfr_id; 1952 id = (uint16_t)finfo->dev_id; 1953 break; 1954 case CFI_DEVICETYPE_X32: 1955 mfr = (uint16_t)finfo->mfr_id; 1956 id = (uint32_t)finfo->dev_id; 1957 break; 1958 default: 1959 printk(KERN_WARNING 1960 "MTD %s(): Unsupported device type %d\n", 1961 __func__, cfi->device_type); 1962 goto match_done; 1963 } 1964 if ( cfi->mfr != mfr || cfi->id != id ) { 1965 goto match_done; 1966 } 1967 1968 /* the part size must fit in the memory window */ 1969 DEBUG( MTD_DEBUG_LEVEL3, 1970 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 1971 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); 1972 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { 1973 DEBUG( MTD_DEBUG_LEVEL3, 1974 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 1975 __func__, finfo->mfr_id, finfo->dev_id, 1976 1 << finfo->dev_size ); 1977 goto match_done; 1978 } 1979 1980 if (! (finfo->devtypes & cfi->device_type)) 1981 goto match_done; 1982 1983 uaddr = finfo->uaddr; 1984 1985 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 1986 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 1987 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 1988 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || 1989 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { 1990 DEBUG( MTD_DEBUG_LEVEL3, 1991 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 1992 __func__, 1993 unlock_addrs[uaddr].addr1, 1994 unlock_addrs[uaddr].addr2); 1995 goto match_done; 1996 } 1997 1998 /* 1999 * Make sure the ID's dissappear when the device is taken out of 2000 * ID mode. The only time this should fail when it should succeed 2001 * is when the ID's are written as data to the same 2002 * addresses. For this rare and unfortunate case the chip 2003 * cannot be probed correctly. 2004 * FIXME - write a driver that takes all of the chip info as 2005 * module parameters, doesn't probe but forces a load. 2006 */ 2007 DEBUG( MTD_DEBUG_LEVEL3, 2008 "MTD %s(): check ID's disappear when not in ID mode\n", 2009 __func__ ); 2010 jedec_reset( base, map, cfi ); 2011 mfr = jedec_read_mfr( map, base, cfi ); 2012 id = jedec_read_id( map, base, cfi ); 2013 if ( mfr == cfi->mfr && id == cfi->id ) { 2014 DEBUG( MTD_DEBUG_LEVEL3, 2015 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" 2016 "You might need to manually specify JEDEC parameters.\n", 2017 __func__, cfi->mfr, cfi->id ); 2018 goto match_done; 2019 } 2020 2021 /* all tests passed - mark as success */ 2022 rc = 1; 2023 2024 /* 2025 * Put the device back in ID mode - only need to do this if we 2026 * were truly frobbing a real device. 2027 */ 2028 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 2029 if (cfi->addr_unlock1) { 2030 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2031 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2032 } 2033 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2034 /* FIXME - should have a delay before continuing */ 2035 2036 match_done: 2037 return rc; 2038 } 2039 2040 2041 static int jedec_probe_chip(struct map_info *map, __u32 base, 2042 unsigned long *chip_map, struct cfi_private *cfi) 2043 { 2044 int i; 2045 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 2046 u32 probe_offset1, probe_offset2; 2047 2048 retry: 2049 if (!cfi->numchips) { 2050 uaddr_idx++; 2051 2052 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 2053 return 0; 2054 2055 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; 2056 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; 2057 } 2058 2059 /* Make certain we aren't probing past the end of map */ 2060 if (base >= map->size) { 2061 printk(KERN_NOTICE 2062 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", 2063 base, map->size -1); 2064 return 0; 2065 2066 } 2067 /* Ensure the unlock addresses we try stay inside the map */ 2068 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, map, cfi); 2069 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, map, cfi); 2070 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 2071 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 2072 goto retry; 2073 2074 /* Reset */ 2075 jedec_reset(base, map, cfi); 2076 2077 /* Autoselect Mode */ 2078 if(cfi->addr_unlock1) { 2079 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2080 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 2081 } 2082 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 2083 /* FIXME - should have a delay before continuing */ 2084 2085 if (!cfi->numchips) { 2086 /* This is the first time we're called. Set up the CFI 2087 stuff accordingly and return */ 2088 2089 cfi->mfr = jedec_read_mfr(map, base, cfi); 2090 cfi->id = jedec_read_id(map, base, cfi); 2091 DEBUG(MTD_DEBUG_LEVEL3, 2092 "Search for id:(%02x %02x) interleave(%d) type(%d)\n", 2093 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); 2094 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 2095 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { 2096 DEBUG( MTD_DEBUG_LEVEL3, 2097 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", 2098 __func__, cfi->mfr, cfi->id, 2099 cfi->addr_unlock1, cfi->addr_unlock2 ); 2100 if (!cfi_jedec_setup(cfi, i)) 2101 return 0; 2102 goto ok_out; 2103 } 2104 } 2105 goto retry; 2106 } else { 2107 uint16_t mfr; 2108 uint16_t id; 2109 2110 /* Make sure it is a chip of the same manufacturer and id */ 2111 mfr = jedec_read_mfr(map, base, cfi); 2112 id = jedec_read_id(map, base, cfi); 2113 2114 if ((mfr != cfi->mfr) || (id != cfi->id)) { 2115 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", 2116 map->name, mfr, id, base); 2117 jedec_reset(base, map, cfi); 2118 return 0; 2119 } 2120 } 2121 2122 /* Check each previous chip locations to see if it's an alias */ 2123 for (i=0; i < (base >> cfi->chipshift); i++) { 2124 unsigned long start; 2125 if(!test_bit(i, chip_map)) { 2126 continue; /* Skip location; no valid chip at this address */ 2127 } 2128 start = i << cfi->chipshift; 2129 if (jedec_read_mfr(map, start, cfi) == cfi->mfr && 2130 jedec_read_id(map, start, cfi) == cfi->id) { 2131 /* Eep. This chip also looks like it's in autoselect mode. 2132 Is it an alias for the new one? */ 2133 jedec_reset(start, map, cfi); 2134 2135 /* If the device IDs go away, it's an alias */ 2136 if (jedec_read_mfr(map, base, cfi) != cfi->mfr || 2137 jedec_read_id(map, base, cfi) != cfi->id) { 2138 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2139 map->name, base, start); 2140 return 0; 2141 } 2142 2143 /* Yes, it's actually got the device IDs as data. Most 2144 * unfortunate. Stick the new chip in read mode 2145 * too and if it's the same, assume it's an alias. */ 2146 /* FIXME: Use other modes to do a proper check */ 2147 jedec_reset(base, map, cfi); 2148 if (jedec_read_mfr(map, base, cfi) == cfi->mfr && 2149 jedec_read_id(map, base, cfi) == cfi->id) { 2150 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2151 map->name, base, start); 2152 return 0; 2153 } 2154 } 2155 } 2156 2157 /* OK, if we got to here, then none of the previous chips appear to 2158 be aliases for the current one. */ 2159 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ 2160 cfi->numchips++; 2161 2162 ok_out: 2163 /* Put it back into Read Mode */ 2164 jedec_reset(base, map, cfi); 2165 2166 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", 2167 map->name, cfi_interleave(cfi), cfi->device_type*8, base, 2168 map->bankwidth*8); 2169 2170 return 1; 2171 } 2172 2173 static struct chip_probe jedec_chip_probe = { 2174 .name = "JEDEC", 2175 .probe_chip = jedec_probe_chip 2176 }; 2177 2178 static struct mtd_info *jedec_probe(struct map_info *map) 2179 { 2180 /* 2181 * Just use the generic probe stuff to call our CFI-specific 2182 * chip_probe routine in all the possible permutations, etc. 2183 */ 2184 return mtd_do_chip_probe(map, &jedec_chip_probe); 2185 } 2186 2187 static struct mtd_chip_driver jedec_chipdrv = { 2188 .probe = jedec_probe, 2189 .name = "jedec_probe", 2190 .module = THIS_MODULE 2191 }; 2192 2193 static int __init jedec_probe_init(void) 2194 { 2195 register_mtd_chip_driver(&jedec_chipdrv); 2196 return 0; 2197 } 2198 2199 static void __exit jedec_probe_exit(void) 2200 { 2201 unregister_mtd_chip_driver(&jedec_chipdrv); 2202 } 2203 2204 module_init(jedec_probe_init); 2205 module_exit(jedec_probe_exit); 2206 2207 MODULE_LICENSE("GPL"); 2208 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); 2209 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); 2210