1 /* 2 Common Flash Interface probe code. 3 (C) 2000 Red Hat. GPL'd. 4 $Id: jedec_probe.c,v 1.66 2005/11/07 11:14:23 gleixner Exp $ 5 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5) 6 for the standard this probe goes back to. 7 8 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 9 */ 10 11 #include <linux/module.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/kernel.h> 15 #include <asm/io.h> 16 #include <asm/byteorder.h> 17 #include <linux/errno.h> 18 #include <linux/slab.h> 19 #include <linux/interrupt.h> 20 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/map.h> 23 #include <linux/mtd/cfi.h> 24 #include <linux/mtd/gen_probe.h> 25 26 /* Manufacturers */ 27 #define MANUFACTURER_AMD 0x0001 28 #define MANUFACTURER_ATMEL 0x001f 29 #define MANUFACTURER_FUJITSU 0x0004 30 #define MANUFACTURER_HYUNDAI 0x00AD 31 #define MANUFACTURER_INTEL 0x0089 32 #define MANUFACTURER_MACRONIX 0x00C2 33 #define MANUFACTURER_NEC 0x0010 34 #define MANUFACTURER_PMC 0x009D 35 #define MANUFACTURER_SHARP 0x00b0 36 #define MANUFACTURER_SST 0x00BF 37 #define MANUFACTURER_ST 0x0020 38 #define MANUFACTURER_TOSHIBA 0x0098 39 #define MANUFACTURER_WINBOND 0x00da 40 41 42 /* AMD */ 43 #define AM29DL800BB 0x22C8 44 #define AM29DL800BT 0x224A 45 46 #define AM29F800BB 0x2258 47 #define AM29F800BT 0x22D6 48 #define AM29LV400BB 0x22BA 49 #define AM29LV400BT 0x22B9 50 #define AM29LV800BB 0x225B 51 #define AM29LV800BT 0x22DA 52 #define AM29LV160DT 0x22C4 53 #define AM29LV160DB 0x2249 54 #define AM29F017D 0x003D 55 #define AM29F016D 0x00AD 56 #define AM29F080 0x00D5 57 #define AM29F040 0x00A4 58 #define AM29LV040B 0x004F 59 #define AM29F032B 0x0041 60 #define AM29F002T 0x00B0 61 62 /* Atmel */ 63 #define AT49BV512 0x0003 64 #define AT29LV512 0x003d 65 #define AT49BV16X 0x00C0 66 #define AT49BV16XT 0x00C2 67 #define AT49BV32X 0x00C8 68 #define AT49BV32XT 0x00C9 69 70 /* Fujitsu */ 71 #define MBM29F040C 0x00A4 72 #define MBM29F800BA 0x2258 73 #define MBM29LV650UE 0x22D7 74 #define MBM29LV320TE 0x22F6 75 #define MBM29LV320BE 0x22F9 76 #define MBM29LV160TE 0x22C4 77 #define MBM29LV160BE 0x2249 78 #define MBM29LV800BA 0x225B 79 #define MBM29LV800TA 0x22DA 80 #define MBM29LV400TC 0x22B9 81 #define MBM29LV400BC 0x22BA 82 83 /* Hyundai */ 84 #define HY29F002T 0x00B0 85 86 /* Intel */ 87 #define I28F004B3T 0x00d4 88 #define I28F004B3B 0x00d5 89 #define I28F400B3T 0x8894 90 #define I28F400B3B 0x8895 91 #define I28F008S5 0x00a6 92 #define I28F016S5 0x00a0 93 #define I28F008SA 0x00a2 94 #define I28F008B3T 0x00d2 95 #define I28F008B3B 0x00d3 96 #define I28F800B3T 0x8892 97 #define I28F800B3B 0x8893 98 #define I28F016S3 0x00aa 99 #define I28F016B3T 0x00d0 100 #define I28F016B3B 0x00d1 101 #define I28F160B3T 0x8890 102 #define I28F160B3B 0x8891 103 #define I28F320B3T 0x8896 104 #define I28F320B3B 0x8897 105 #define I28F640B3T 0x8898 106 #define I28F640B3B 0x8899 107 #define I82802AB 0x00ad 108 #define I82802AC 0x00ac 109 110 /* Macronix */ 111 #define MX29LV040C 0x004F 112 #define MX29LV160T 0x22C4 113 #define MX29LV160B 0x2249 114 #define MX29F040 0x00A4 115 #define MX29F016 0x00AD 116 #define MX29F002T 0x00B0 117 #define MX29F004T 0x0045 118 #define MX29F004B 0x0046 119 120 /* NEC */ 121 #define UPD29F064115 0x221C 122 123 /* PMC */ 124 #define PM49FL002 0x006D 125 #define PM49FL004 0x006E 126 #define PM49FL008 0x006A 127 128 /* Sharp */ 129 #define LH28F640BF 0x00b0 130 131 /* ST - www.st.com */ 132 #define M29F800AB 0x0058 133 #define M29W800DT 0x00D7 134 #define M29W800DB 0x005B 135 #define M29W400DT 0x00EE 136 #define M29W400DB 0x00EF 137 #define M29W160DT 0x22C4 138 #define M29W160DB 0x2249 139 #define M29W040B 0x00E3 140 #define M50FW040 0x002C 141 #define M50FW080 0x002D 142 #define M50FW016 0x002E 143 #define M50LPW080 0x002F 144 145 /* SST */ 146 #define SST29EE020 0x0010 147 #define SST29LE020 0x0012 148 #define SST29EE512 0x005d 149 #define SST29LE512 0x003d 150 #define SST39LF800 0x2781 151 #define SST39LF160 0x2782 152 #define SST39VF1601 0x234b 153 #define SST39LF512 0x00D4 154 #define SST39LF010 0x00D5 155 #define SST39LF020 0x00D6 156 #define SST39LF040 0x00D7 157 #define SST39SF010A 0x00B5 158 #define SST39SF020A 0x00B6 159 #define SST49LF004B 0x0060 160 #define SST49LF040B 0x0050 161 #define SST49LF008A 0x005a 162 #define SST49LF030A 0x001C 163 #define SST49LF040A 0x0051 164 #define SST49LF080A 0x005B 165 #define SST36VF3203 0x7354 166 167 /* Toshiba */ 168 #define TC58FVT160 0x00C2 169 #define TC58FVB160 0x0043 170 #define TC58FVT321 0x009A 171 #define TC58FVB321 0x009C 172 #define TC58FVT641 0x0093 173 #define TC58FVB641 0x0095 174 175 /* Winbond */ 176 #define W49V002A 0x00b0 177 178 179 /* 180 * Unlock address sets for AMD command sets. 181 * Intel command sets use the MTD_UADDR_UNNECESSARY. 182 * Each identifier, except MTD_UADDR_UNNECESSARY, and 183 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 184 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 185 * initialization need not require initializing all of the 186 * unlock addresses for all bit widths. 187 */ 188 enum uaddr { 189 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 190 MTD_UADDR_0x0555_0x02AA, 191 MTD_UADDR_0x0555_0x0AAA, 192 MTD_UADDR_0x5555_0x2AAA, 193 MTD_UADDR_0x0AAA_0x0555, 194 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 195 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 196 }; 197 198 199 struct unlock_addr { 200 uint32_t addr1; 201 uint32_t addr2; 202 }; 203 204 205 /* 206 * I don't like the fact that the first entry in unlock_addrs[] 207 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 208 * should not be used. The problem is that structures with 209 * initializers have extra fields initialized to 0. It is _very_ 210 * desireable to have the unlock address entries for unsupported 211 * data widths automatically initialized - that means that 212 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 213 * must go unused. 214 */ 215 static const struct unlock_addr unlock_addrs[] = { 216 [MTD_UADDR_NOT_SUPPORTED] = { 217 .addr1 = 0xffff, 218 .addr2 = 0xffff 219 }, 220 221 [MTD_UADDR_0x0555_0x02AA] = { 222 .addr1 = 0x0555, 223 .addr2 = 0x02aa 224 }, 225 226 [MTD_UADDR_0x0555_0x0AAA] = { 227 .addr1 = 0x0555, 228 .addr2 = 0x0aaa 229 }, 230 231 [MTD_UADDR_0x5555_0x2AAA] = { 232 .addr1 = 0x5555, 233 .addr2 = 0x2aaa 234 }, 235 236 [MTD_UADDR_0x0AAA_0x0555] = { 237 .addr1 = 0x0AAA, 238 .addr2 = 0x0555 239 }, 240 241 [MTD_UADDR_DONT_CARE] = { 242 .addr1 = 0x0000, /* Doesn't matter which address */ 243 .addr2 = 0x0000 /* is used - must be last entry */ 244 }, 245 246 [MTD_UADDR_UNNECESSARY] = { 247 .addr1 = 0x0000, 248 .addr2 = 0x0000 249 } 250 }; 251 252 struct amd_flash_info { 253 const char *name; 254 const uint16_t mfr_id; 255 const uint16_t dev_id; 256 const uint8_t dev_size; 257 const uint8_t nr_regions; 258 const uint16_t cmd_set; 259 const uint32_t regions[6]; 260 const uint8_t devtypes; /* Bitmask for x8, x16 etc. */ 261 const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */ 262 }; 263 264 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 265 266 #define SIZE_64KiB 16 267 #define SIZE_128KiB 17 268 #define SIZE_256KiB 18 269 #define SIZE_512KiB 19 270 #define SIZE_1MiB 20 271 #define SIZE_2MiB 21 272 #define SIZE_4MiB 22 273 #define SIZE_8MiB 23 274 275 276 /* 277 * Please keep this list ordered by manufacturer! 278 * Fortunately, the list isn't searched often and so a 279 * slow, linear search isn't so bad. 280 */ 281 static const struct amd_flash_info jedec_table[] = { 282 { 283 .mfr_id = MANUFACTURER_AMD, 284 .dev_id = AM29F032B, 285 .name = "AMD AM29F032B", 286 .uaddr = MTD_UADDR_0x0555_0x02AA, 287 .devtypes = CFI_DEVICETYPE_X8, 288 .dev_size = SIZE_4MiB, 289 .cmd_set = P_ID_AMD_STD, 290 .nr_regions = 1, 291 .regions = { 292 ERASEINFO(0x10000,64) 293 } 294 }, { 295 .mfr_id = MANUFACTURER_AMD, 296 .dev_id = AM29LV160DT, 297 .name = "AMD AM29LV160DT", 298 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 299 .uaddr = MTD_UADDR_0x0AAA_0x0555, 300 .dev_size = SIZE_2MiB, 301 .cmd_set = P_ID_AMD_STD, 302 .nr_regions = 4, 303 .regions = { 304 ERASEINFO(0x10000,31), 305 ERASEINFO(0x08000,1), 306 ERASEINFO(0x02000,2), 307 ERASEINFO(0x04000,1) 308 } 309 }, { 310 .mfr_id = MANUFACTURER_AMD, 311 .dev_id = AM29LV160DB, 312 .name = "AMD AM29LV160DB", 313 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 314 .uaddr = MTD_UADDR_0x0AAA_0x0555, 315 .dev_size = SIZE_2MiB, 316 .cmd_set = P_ID_AMD_STD, 317 .nr_regions = 4, 318 .regions = { 319 ERASEINFO(0x04000,1), 320 ERASEINFO(0x02000,2), 321 ERASEINFO(0x08000,1), 322 ERASEINFO(0x10000,31) 323 } 324 }, { 325 .mfr_id = MANUFACTURER_AMD, 326 .dev_id = AM29LV400BB, 327 .name = "AMD AM29LV400BB", 328 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 329 .uaddr = MTD_UADDR_0x0AAA_0x0555, 330 .dev_size = SIZE_512KiB, 331 .cmd_set = P_ID_AMD_STD, 332 .nr_regions = 4, 333 .regions = { 334 ERASEINFO(0x04000,1), 335 ERASEINFO(0x02000,2), 336 ERASEINFO(0x08000,1), 337 ERASEINFO(0x10000,7) 338 } 339 }, { 340 .mfr_id = MANUFACTURER_AMD, 341 .dev_id = AM29LV400BT, 342 .name = "AMD AM29LV400BT", 343 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 344 .uaddr = MTD_UADDR_0x0AAA_0x0555, 345 .dev_size = SIZE_512KiB, 346 .cmd_set = P_ID_AMD_STD, 347 .nr_regions = 4, 348 .regions = { 349 ERASEINFO(0x10000,7), 350 ERASEINFO(0x08000,1), 351 ERASEINFO(0x02000,2), 352 ERASEINFO(0x04000,1) 353 } 354 }, { 355 .mfr_id = MANUFACTURER_AMD, 356 .dev_id = AM29LV800BB, 357 .name = "AMD AM29LV800BB", 358 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 359 .uaddr = MTD_UADDR_0x0AAA_0x0555, 360 .dev_size = SIZE_1MiB, 361 .cmd_set = P_ID_AMD_STD, 362 .nr_regions = 4, 363 .regions = { 364 ERASEINFO(0x04000,1), 365 ERASEINFO(0x02000,2), 366 ERASEINFO(0x08000,1), 367 ERASEINFO(0x10000,15), 368 } 369 }, { 370 /* add DL */ 371 .mfr_id = MANUFACTURER_AMD, 372 .dev_id = AM29DL800BB, 373 .name = "AMD AM29DL800BB", 374 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 375 .uaddr = MTD_UADDR_0x0AAA_0x0555, 376 .dev_size = SIZE_1MiB, 377 .cmd_set = P_ID_AMD_STD, 378 .nr_regions = 6, 379 .regions = { 380 ERASEINFO(0x04000,1), 381 ERASEINFO(0x08000,1), 382 ERASEINFO(0x02000,4), 383 ERASEINFO(0x08000,1), 384 ERASEINFO(0x04000,1), 385 ERASEINFO(0x10000,14) 386 } 387 }, { 388 .mfr_id = MANUFACTURER_AMD, 389 .dev_id = AM29DL800BT, 390 .name = "AMD AM29DL800BT", 391 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 392 .uaddr = MTD_UADDR_0x0AAA_0x0555, 393 .dev_size = SIZE_1MiB, 394 .cmd_set = P_ID_AMD_STD, 395 .nr_regions = 6, 396 .regions = { 397 ERASEINFO(0x10000,14), 398 ERASEINFO(0x04000,1), 399 ERASEINFO(0x08000,1), 400 ERASEINFO(0x02000,4), 401 ERASEINFO(0x08000,1), 402 ERASEINFO(0x04000,1) 403 } 404 }, { 405 .mfr_id = MANUFACTURER_AMD, 406 .dev_id = AM29F800BB, 407 .name = "AMD AM29F800BB", 408 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 409 .uaddr = MTD_UADDR_0x0AAA_0x0555, 410 .dev_size = SIZE_1MiB, 411 .cmd_set = P_ID_AMD_STD, 412 .nr_regions = 4, 413 .regions = { 414 ERASEINFO(0x04000,1), 415 ERASEINFO(0x02000,2), 416 ERASEINFO(0x08000,1), 417 ERASEINFO(0x10000,15), 418 } 419 }, { 420 .mfr_id = MANUFACTURER_AMD, 421 .dev_id = AM29LV800BT, 422 .name = "AMD AM29LV800BT", 423 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 424 .uaddr = MTD_UADDR_0x0AAA_0x0555, 425 .dev_size = SIZE_1MiB, 426 .cmd_set = P_ID_AMD_STD, 427 .nr_regions = 4, 428 .regions = { 429 ERASEINFO(0x10000,15), 430 ERASEINFO(0x08000,1), 431 ERASEINFO(0x02000,2), 432 ERASEINFO(0x04000,1) 433 } 434 }, { 435 .mfr_id = MANUFACTURER_AMD, 436 .dev_id = AM29F800BT, 437 .name = "AMD AM29F800BT", 438 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 439 .uaddr = MTD_UADDR_0x0AAA_0x0555, 440 .dev_size = SIZE_1MiB, 441 .cmd_set = P_ID_AMD_STD, 442 .nr_regions = 4, 443 .regions = { 444 ERASEINFO(0x10000,15), 445 ERASEINFO(0x08000,1), 446 ERASEINFO(0x02000,2), 447 ERASEINFO(0x04000,1) 448 } 449 }, { 450 .mfr_id = MANUFACTURER_AMD, 451 .dev_id = AM29F017D, 452 .name = "AMD AM29F017D", 453 .devtypes = CFI_DEVICETYPE_X8, 454 .uaddr = MTD_UADDR_DONT_CARE, 455 .dev_size = SIZE_2MiB, 456 .cmd_set = P_ID_AMD_STD, 457 .nr_regions = 1, 458 .regions = { 459 ERASEINFO(0x10000,32), 460 } 461 }, { 462 .mfr_id = MANUFACTURER_AMD, 463 .dev_id = AM29F016D, 464 .name = "AMD AM29F016D", 465 .devtypes = CFI_DEVICETYPE_X8, 466 .uaddr = MTD_UADDR_0x0555_0x02AA, 467 .dev_size = SIZE_2MiB, 468 .cmd_set = P_ID_AMD_STD, 469 .nr_regions = 1, 470 .regions = { 471 ERASEINFO(0x10000,32), 472 } 473 }, { 474 .mfr_id = MANUFACTURER_AMD, 475 .dev_id = AM29F080, 476 .name = "AMD AM29F080", 477 .devtypes = CFI_DEVICETYPE_X8, 478 .uaddr = MTD_UADDR_0x0555_0x02AA, 479 .dev_size = SIZE_1MiB, 480 .cmd_set = P_ID_AMD_STD, 481 .nr_regions = 1, 482 .regions = { 483 ERASEINFO(0x10000,16), 484 } 485 }, { 486 .mfr_id = MANUFACTURER_AMD, 487 .dev_id = AM29F040, 488 .name = "AMD AM29F040", 489 .devtypes = CFI_DEVICETYPE_X8, 490 .uaddr = MTD_UADDR_0x0555_0x02AA, 491 .dev_size = SIZE_512KiB, 492 .cmd_set = P_ID_AMD_STD, 493 .nr_regions = 1, 494 .regions = { 495 ERASEINFO(0x10000,8), 496 } 497 }, { 498 .mfr_id = MANUFACTURER_AMD, 499 .dev_id = AM29LV040B, 500 .name = "AMD AM29LV040B", 501 .devtypes = CFI_DEVICETYPE_X8, 502 .uaddr = MTD_UADDR_0x0555_0x02AA, 503 .dev_size = SIZE_512KiB, 504 .cmd_set = P_ID_AMD_STD, 505 .nr_regions = 1, 506 .regions = { 507 ERASEINFO(0x10000,8), 508 } 509 }, { 510 .mfr_id = MANUFACTURER_AMD, 511 .dev_id = AM29F002T, 512 .name = "AMD AM29F002T", 513 .devtypes = CFI_DEVICETYPE_X8, 514 .uaddr = MTD_UADDR_0x0555_0x02AA, 515 .dev_size = SIZE_256KiB, 516 .cmd_set = P_ID_AMD_STD, 517 .nr_regions = 4, 518 .regions = { 519 ERASEINFO(0x10000,3), 520 ERASEINFO(0x08000,1), 521 ERASEINFO(0x02000,2), 522 ERASEINFO(0x04000,1), 523 } 524 }, { 525 .mfr_id = MANUFACTURER_ATMEL, 526 .dev_id = AT49BV512, 527 .name = "Atmel AT49BV512", 528 .devtypes = CFI_DEVICETYPE_X8, 529 .uaddr = MTD_UADDR_0x5555_0x2AAA, 530 .dev_size = SIZE_64KiB, 531 .cmd_set = P_ID_AMD_STD, 532 .nr_regions = 1, 533 .regions = { 534 ERASEINFO(0x10000,1) 535 } 536 }, { 537 .mfr_id = MANUFACTURER_ATMEL, 538 .dev_id = AT29LV512, 539 .name = "Atmel AT29LV512", 540 .devtypes = CFI_DEVICETYPE_X8, 541 .uaddr = MTD_UADDR_0x5555_0x2AAA, 542 .dev_size = SIZE_64KiB, 543 .cmd_set = P_ID_AMD_STD, 544 .nr_regions = 1, 545 .regions = { 546 ERASEINFO(0x80,256), 547 ERASEINFO(0x80,256) 548 } 549 }, { 550 .mfr_id = MANUFACTURER_ATMEL, 551 .dev_id = AT49BV16X, 552 .name = "Atmel AT49BV16X", 553 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 554 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 555 .dev_size = SIZE_2MiB, 556 .cmd_set = P_ID_AMD_STD, 557 .nr_regions = 2, 558 .regions = { 559 ERASEINFO(0x02000,8), 560 ERASEINFO(0x10000,31) 561 } 562 }, { 563 .mfr_id = MANUFACTURER_ATMEL, 564 .dev_id = AT49BV16XT, 565 .name = "Atmel AT49BV16XT", 566 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 567 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 568 .dev_size = SIZE_2MiB, 569 .cmd_set = P_ID_AMD_STD, 570 .nr_regions = 2, 571 .regions = { 572 ERASEINFO(0x10000,31), 573 ERASEINFO(0x02000,8) 574 } 575 }, { 576 .mfr_id = MANUFACTURER_ATMEL, 577 .dev_id = AT49BV32X, 578 .name = "Atmel AT49BV32X", 579 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 580 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 581 .dev_size = SIZE_4MiB, 582 .cmd_set = P_ID_AMD_STD, 583 .nr_regions = 2, 584 .regions = { 585 ERASEINFO(0x02000,8), 586 ERASEINFO(0x10000,63) 587 } 588 }, { 589 .mfr_id = MANUFACTURER_ATMEL, 590 .dev_id = AT49BV32XT, 591 .name = "Atmel AT49BV32XT", 592 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 593 .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */ 594 .dev_size = SIZE_4MiB, 595 .cmd_set = P_ID_AMD_STD, 596 .nr_regions = 2, 597 .regions = { 598 ERASEINFO(0x10000,63), 599 ERASEINFO(0x02000,8) 600 } 601 }, { 602 .mfr_id = MANUFACTURER_FUJITSU, 603 .dev_id = MBM29F040C, 604 .name = "Fujitsu MBM29F040C", 605 .devtypes = CFI_DEVICETYPE_X8, 606 .uaddr = MTD_UADDR_0x0AAA_0x0555, 607 .dev_size = SIZE_512KiB, 608 .cmd_set = P_ID_AMD_STD, 609 .nr_regions = 1, 610 .regions = { 611 ERASEINFO(0x10000,8) 612 } 613 }, { 614 .mfr_id = MANUFACTURER_FUJITSU, 615 .dev_id = MBM29F800BA, 616 .name = "Fujitsu MBM29F800BA", 617 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 618 .uaddr = MTD_UADDR_0x0AAA_0x0555, 619 .dev_size = SIZE_1MiB, 620 .cmd_set = P_ID_AMD_STD, 621 .nr_regions = 4, 622 .regions = { 623 ERASEINFO(0x04000,1), 624 ERASEINFO(0x02000,2), 625 ERASEINFO(0x08000,1), 626 ERASEINFO(0x10000,15), 627 } 628 }, { 629 .mfr_id = MANUFACTURER_FUJITSU, 630 .dev_id = MBM29LV650UE, 631 .name = "Fujitsu MBM29LV650UE", 632 .devtypes = CFI_DEVICETYPE_X8, 633 .uaddr = MTD_UADDR_DONT_CARE, 634 .dev_size = SIZE_8MiB, 635 .cmd_set = P_ID_AMD_STD, 636 .nr_regions = 1, 637 .regions = { 638 ERASEINFO(0x10000,128) 639 } 640 }, { 641 .mfr_id = MANUFACTURER_FUJITSU, 642 .dev_id = MBM29LV320TE, 643 .name = "Fujitsu MBM29LV320TE", 644 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 645 .uaddr = MTD_UADDR_0x0AAA_0x0555, 646 .dev_size = SIZE_4MiB, 647 .cmd_set = P_ID_AMD_STD, 648 .nr_regions = 2, 649 .regions = { 650 ERASEINFO(0x10000,63), 651 ERASEINFO(0x02000,8) 652 } 653 }, { 654 .mfr_id = MANUFACTURER_FUJITSU, 655 .dev_id = MBM29LV320BE, 656 .name = "Fujitsu MBM29LV320BE", 657 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 658 .uaddr = MTD_UADDR_0x0AAA_0x0555, 659 .dev_size = SIZE_4MiB, 660 .cmd_set = P_ID_AMD_STD, 661 .nr_regions = 2, 662 .regions = { 663 ERASEINFO(0x02000,8), 664 ERASEINFO(0x10000,63) 665 } 666 }, { 667 .mfr_id = MANUFACTURER_FUJITSU, 668 .dev_id = MBM29LV160TE, 669 .name = "Fujitsu MBM29LV160TE", 670 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 671 .uaddr = MTD_UADDR_0x0AAA_0x0555, 672 .dev_size = SIZE_2MiB, 673 .cmd_set = P_ID_AMD_STD, 674 .nr_regions = 4, 675 .regions = { 676 ERASEINFO(0x10000,31), 677 ERASEINFO(0x08000,1), 678 ERASEINFO(0x02000,2), 679 ERASEINFO(0x04000,1) 680 } 681 }, { 682 .mfr_id = MANUFACTURER_FUJITSU, 683 .dev_id = MBM29LV160BE, 684 .name = "Fujitsu MBM29LV160BE", 685 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 686 .uaddr = MTD_UADDR_0x0AAA_0x0555, 687 .dev_size = SIZE_2MiB, 688 .cmd_set = P_ID_AMD_STD, 689 .nr_regions = 4, 690 .regions = { 691 ERASEINFO(0x04000,1), 692 ERASEINFO(0x02000,2), 693 ERASEINFO(0x08000,1), 694 ERASEINFO(0x10000,31) 695 } 696 }, { 697 .mfr_id = MANUFACTURER_FUJITSU, 698 .dev_id = MBM29LV800BA, 699 .name = "Fujitsu MBM29LV800BA", 700 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 701 .uaddr = MTD_UADDR_0x0AAA_0x0555, 702 .dev_size = SIZE_1MiB, 703 .cmd_set = P_ID_AMD_STD, 704 .nr_regions = 4, 705 .regions = { 706 ERASEINFO(0x04000,1), 707 ERASEINFO(0x02000,2), 708 ERASEINFO(0x08000,1), 709 ERASEINFO(0x10000,15) 710 } 711 }, { 712 .mfr_id = MANUFACTURER_FUJITSU, 713 .dev_id = MBM29LV800TA, 714 .name = "Fujitsu MBM29LV800TA", 715 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 716 .uaddr = MTD_UADDR_0x0AAA_0x0555, 717 .dev_size = SIZE_1MiB, 718 .cmd_set = P_ID_AMD_STD, 719 .nr_regions = 4, 720 .regions = { 721 ERASEINFO(0x10000,15), 722 ERASEINFO(0x08000,1), 723 ERASEINFO(0x02000,2), 724 ERASEINFO(0x04000,1) 725 } 726 }, { 727 .mfr_id = MANUFACTURER_FUJITSU, 728 .dev_id = MBM29LV400BC, 729 .name = "Fujitsu MBM29LV400BC", 730 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 731 .uaddr = MTD_UADDR_0x0AAA_0x0555, 732 .dev_size = SIZE_512KiB, 733 .cmd_set = P_ID_AMD_STD, 734 .nr_regions = 4, 735 .regions = { 736 ERASEINFO(0x04000,1), 737 ERASEINFO(0x02000,2), 738 ERASEINFO(0x08000,1), 739 ERASEINFO(0x10000,7) 740 } 741 }, { 742 .mfr_id = MANUFACTURER_FUJITSU, 743 .dev_id = MBM29LV400TC, 744 .name = "Fujitsu MBM29LV400TC", 745 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 746 .uaddr = MTD_UADDR_0x0AAA_0x0555, 747 .dev_size = SIZE_512KiB, 748 .cmd_set = P_ID_AMD_STD, 749 .nr_regions = 4, 750 .regions = { 751 ERASEINFO(0x10000,7), 752 ERASEINFO(0x08000,1), 753 ERASEINFO(0x02000,2), 754 ERASEINFO(0x04000,1) 755 } 756 }, { 757 .mfr_id = MANUFACTURER_HYUNDAI, 758 .dev_id = HY29F002T, 759 .name = "Hyundai HY29F002T", 760 .devtypes = CFI_DEVICETYPE_X8, 761 .uaddr = MTD_UADDR_0x0555_0x02AA, 762 .dev_size = SIZE_256KiB, 763 .cmd_set = P_ID_AMD_STD, 764 .nr_regions = 4, 765 .regions = { 766 ERASEINFO(0x10000,3), 767 ERASEINFO(0x08000,1), 768 ERASEINFO(0x02000,2), 769 ERASEINFO(0x04000,1), 770 } 771 }, { 772 .mfr_id = MANUFACTURER_INTEL, 773 .dev_id = I28F004B3B, 774 .name = "Intel 28F004B3B", 775 .devtypes = CFI_DEVICETYPE_X8, 776 .uaddr = MTD_UADDR_UNNECESSARY, 777 .dev_size = SIZE_512KiB, 778 .cmd_set = P_ID_INTEL_STD, 779 .nr_regions = 2, 780 .regions = { 781 ERASEINFO(0x02000, 8), 782 ERASEINFO(0x10000, 7), 783 } 784 }, { 785 .mfr_id = MANUFACTURER_INTEL, 786 .dev_id = I28F004B3T, 787 .name = "Intel 28F004B3T", 788 .devtypes = CFI_DEVICETYPE_X8, 789 .uaddr = MTD_UADDR_UNNECESSARY, 790 .dev_size = SIZE_512KiB, 791 .cmd_set = P_ID_INTEL_STD, 792 .nr_regions = 2, 793 .regions = { 794 ERASEINFO(0x10000, 7), 795 ERASEINFO(0x02000, 8), 796 } 797 }, { 798 .mfr_id = MANUFACTURER_INTEL, 799 .dev_id = I28F400B3B, 800 .name = "Intel 28F400B3B", 801 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 802 .uaddr = MTD_UADDR_UNNECESSARY, 803 .dev_size = SIZE_512KiB, 804 .cmd_set = P_ID_INTEL_STD, 805 .nr_regions = 2, 806 .regions = { 807 ERASEINFO(0x02000, 8), 808 ERASEINFO(0x10000, 7), 809 } 810 }, { 811 .mfr_id = MANUFACTURER_INTEL, 812 .dev_id = I28F400B3T, 813 .name = "Intel 28F400B3T", 814 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 815 .uaddr = MTD_UADDR_UNNECESSARY, 816 .dev_size = SIZE_512KiB, 817 .cmd_set = P_ID_INTEL_STD, 818 .nr_regions = 2, 819 .regions = { 820 ERASEINFO(0x10000, 7), 821 ERASEINFO(0x02000, 8), 822 } 823 }, { 824 .mfr_id = MANUFACTURER_INTEL, 825 .dev_id = I28F008B3B, 826 .name = "Intel 28F008B3B", 827 .devtypes = CFI_DEVICETYPE_X8, 828 .uaddr = MTD_UADDR_UNNECESSARY, 829 .dev_size = SIZE_1MiB, 830 .cmd_set = P_ID_INTEL_STD, 831 .nr_regions = 2, 832 .regions = { 833 ERASEINFO(0x02000, 8), 834 ERASEINFO(0x10000, 15), 835 } 836 }, { 837 .mfr_id = MANUFACTURER_INTEL, 838 .dev_id = I28F008B3T, 839 .name = "Intel 28F008B3T", 840 .devtypes = CFI_DEVICETYPE_X8, 841 .uaddr = MTD_UADDR_UNNECESSARY, 842 .dev_size = SIZE_1MiB, 843 .cmd_set = P_ID_INTEL_STD, 844 .nr_regions = 2, 845 .regions = { 846 ERASEINFO(0x10000, 15), 847 ERASEINFO(0x02000, 8), 848 } 849 }, { 850 .mfr_id = MANUFACTURER_INTEL, 851 .dev_id = I28F008S5, 852 .name = "Intel 28F008S5", 853 .devtypes = CFI_DEVICETYPE_X8, 854 .uaddr = MTD_UADDR_UNNECESSARY, 855 .dev_size = SIZE_1MiB, 856 .cmd_set = P_ID_INTEL_EXT, 857 .nr_regions = 1, 858 .regions = { 859 ERASEINFO(0x10000,16), 860 } 861 }, { 862 .mfr_id = MANUFACTURER_INTEL, 863 .dev_id = I28F016S5, 864 .name = "Intel 28F016S5", 865 .devtypes = CFI_DEVICETYPE_X8, 866 .uaddr = MTD_UADDR_UNNECESSARY, 867 .dev_size = SIZE_2MiB, 868 .cmd_set = P_ID_INTEL_EXT, 869 .nr_regions = 1, 870 .regions = { 871 ERASEINFO(0x10000,32), 872 } 873 }, { 874 .mfr_id = MANUFACTURER_INTEL, 875 .dev_id = I28F008SA, 876 .name = "Intel 28F008SA", 877 .devtypes = CFI_DEVICETYPE_X8, 878 .uaddr = MTD_UADDR_UNNECESSARY, 879 .dev_size = SIZE_1MiB, 880 .cmd_set = P_ID_INTEL_STD, 881 .nr_regions = 1, 882 .regions = { 883 ERASEINFO(0x10000, 16), 884 } 885 }, { 886 .mfr_id = MANUFACTURER_INTEL, 887 .dev_id = I28F800B3B, 888 .name = "Intel 28F800B3B", 889 .devtypes = CFI_DEVICETYPE_X16, 890 .uaddr = MTD_UADDR_UNNECESSARY, 891 .dev_size = SIZE_1MiB, 892 .cmd_set = P_ID_INTEL_STD, 893 .nr_regions = 2, 894 .regions = { 895 ERASEINFO(0x02000, 8), 896 ERASEINFO(0x10000, 15), 897 } 898 }, { 899 .mfr_id = MANUFACTURER_INTEL, 900 .dev_id = I28F800B3T, 901 .name = "Intel 28F800B3T", 902 .devtypes = CFI_DEVICETYPE_X16, 903 .uaddr = MTD_UADDR_UNNECESSARY, 904 .dev_size = SIZE_1MiB, 905 .cmd_set = P_ID_INTEL_STD, 906 .nr_regions = 2, 907 .regions = { 908 ERASEINFO(0x10000, 15), 909 ERASEINFO(0x02000, 8), 910 } 911 }, { 912 .mfr_id = MANUFACTURER_INTEL, 913 .dev_id = I28F016B3B, 914 .name = "Intel 28F016B3B", 915 .devtypes = CFI_DEVICETYPE_X8, 916 .uaddr = MTD_UADDR_UNNECESSARY, 917 .dev_size = SIZE_2MiB, 918 .cmd_set = P_ID_INTEL_STD, 919 .nr_regions = 2, 920 .regions = { 921 ERASEINFO(0x02000, 8), 922 ERASEINFO(0x10000, 31), 923 } 924 }, { 925 .mfr_id = MANUFACTURER_INTEL, 926 .dev_id = I28F016S3, 927 .name = "Intel I28F016S3", 928 .devtypes = CFI_DEVICETYPE_X8, 929 .uaddr = MTD_UADDR_UNNECESSARY, 930 .dev_size = SIZE_2MiB, 931 .cmd_set = P_ID_INTEL_STD, 932 .nr_regions = 1, 933 .regions = { 934 ERASEINFO(0x10000, 32), 935 } 936 }, { 937 .mfr_id = MANUFACTURER_INTEL, 938 .dev_id = I28F016B3T, 939 .name = "Intel 28F016B3T", 940 .devtypes = CFI_DEVICETYPE_X8, 941 .uaddr = MTD_UADDR_UNNECESSARY, 942 .dev_size = SIZE_2MiB, 943 .cmd_set = P_ID_INTEL_STD, 944 .nr_regions = 2, 945 .regions = { 946 ERASEINFO(0x10000, 31), 947 ERASEINFO(0x02000, 8), 948 } 949 }, { 950 .mfr_id = MANUFACTURER_INTEL, 951 .dev_id = I28F160B3B, 952 .name = "Intel 28F160B3B", 953 .devtypes = CFI_DEVICETYPE_X16, 954 .uaddr = MTD_UADDR_UNNECESSARY, 955 .dev_size = SIZE_2MiB, 956 .cmd_set = P_ID_INTEL_STD, 957 .nr_regions = 2, 958 .regions = { 959 ERASEINFO(0x02000, 8), 960 ERASEINFO(0x10000, 31), 961 } 962 }, { 963 .mfr_id = MANUFACTURER_INTEL, 964 .dev_id = I28F160B3T, 965 .name = "Intel 28F160B3T", 966 .devtypes = CFI_DEVICETYPE_X16, 967 .uaddr = MTD_UADDR_UNNECESSARY, 968 .dev_size = SIZE_2MiB, 969 .cmd_set = P_ID_INTEL_STD, 970 .nr_regions = 2, 971 .regions = { 972 ERASEINFO(0x10000, 31), 973 ERASEINFO(0x02000, 8), 974 } 975 }, { 976 .mfr_id = MANUFACTURER_INTEL, 977 .dev_id = I28F320B3B, 978 .name = "Intel 28F320B3B", 979 .devtypes = CFI_DEVICETYPE_X16, 980 .uaddr = MTD_UADDR_UNNECESSARY, 981 .dev_size = SIZE_4MiB, 982 .cmd_set = P_ID_INTEL_STD, 983 .nr_regions = 2, 984 .regions = { 985 ERASEINFO(0x02000, 8), 986 ERASEINFO(0x10000, 63), 987 } 988 }, { 989 .mfr_id = MANUFACTURER_INTEL, 990 .dev_id = I28F320B3T, 991 .name = "Intel 28F320B3T", 992 .devtypes = CFI_DEVICETYPE_X16, 993 .uaddr = MTD_UADDR_UNNECESSARY, 994 .dev_size = SIZE_4MiB, 995 .cmd_set = P_ID_INTEL_STD, 996 .nr_regions = 2, 997 .regions = { 998 ERASEINFO(0x10000, 63), 999 ERASEINFO(0x02000, 8), 1000 } 1001 }, { 1002 .mfr_id = MANUFACTURER_INTEL, 1003 .dev_id = I28F640B3B, 1004 .name = "Intel 28F640B3B", 1005 .devtypes = CFI_DEVICETYPE_X16, 1006 .uaddr = MTD_UADDR_UNNECESSARY, 1007 .dev_size = SIZE_8MiB, 1008 .cmd_set = P_ID_INTEL_STD, 1009 .nr_regions = 2, 1010 .regions = { 1011 ERASEINFO(0x02000, 8), 1012 ERASEINFO(0x10000, 127), 1013 } 1014 }, { 1015 .mfr_id = MANUFACTURER_INTEL, 1016 .dev_id = I28F640B3T, 1017 .name = "Intel 28F640B3T", 1018 .devtypes = CFI_DEVICETYPE_X16, 1019 .uaddr = MTD_UADDR_UNNECESSARY, 1020 .dev_size = SIZE_8MiB, 1021 .cmd_set = P_ID_INTEL_STD, 1022 .nr_regions = 2, 1023 .regions = { 1024 ERASEINFO(0x10000, 127), 1025 ERASEINFO(0x02000, 8), 1026 } 1027 }, { 1028 .mfr_id = MANUFACTURER_INTEL, 1029 .dev_id = I82802AB, 1030 .name = "Intel 82802AB", 1031 .devtypes = CFI_DEVICETYPE_X8, 1032 .uaddr = MTD_UADDR_UNNECESSARY, 1033 .dev_size = SIZE_512KiB, 1034 .cmd_set = P_ID_INTEL_EXT, 1035 .nr_regions = 1, 1036 .regions = { 1037 ERASEINFO(0x10000,8), 1038 } 1039 }, { 1040 .mfr_id = MANUFACTURER_INTEL, 1041 .dev_id = I82802AC, 1042 .name = "Intel 82802AC", 1043 .devtypes = CFI_DEVICETYPE_X8, 1044 .uaddr = MTD_UADDR_UNNECESSARY, 1045 .dev_size = SIZE_1MiB, 1046 .cmd_set = P_ID_INTEL_EXT, 1047 .nr_regions = 1, 1048 .regions = { 1049 ERASEINFO(0x10000,16), 1050 } 1051 }, { 1052 .mfr_id = MANUFACTURER_MACRONIX, 1053 .dev_id = MX29LV040C, 1054 .name = "Macronix MX29LV040C", 1055 .devtypes = CFI_DEVICETYPE_X8, 1056 .uaddr = MTD_UADDR_0x0555_0x02AA, 1057 .dev_size = SIZE_512KiB, 1058 .cmd_set = P_ID_AMD_STD, 1059 .nr_regions = 1, 1060 .regions = { 1061 ERASEINFO(0x10000,8), 1062 } 1063 }, { 1064 .mfr_id = MANUFACTURER_MACRONIX, 1065 .dev_id = MX29LV160T, 1066 .name = "MXIC MX29LV160T", 1067 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1068 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1069 .dev_size = SIZE_2MiB, 1070 .cmd_set = P_ID_AMD_STD, 1071 .nr_regions = 4, 1072 .regions = { 1073 ERASEINFO(0x10000,31), 1074 ERASEINFO(0x08000,1), 1075 ERASEINFO(0x02000,2), 1076 ERASEINFO(0x04000,1) 1077 } 1078 }, { 1079 .mfr_id = MANUFACTURER_NEC, 1080 .dev_id = UPD29F064115, 1081 .name = "NEC uPD29F064115", 1082 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1083 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1084 .dev_size = SIZE_8MiB, 1085 .cmd_set = P_ID_AMD_STD, 1086 .nr_regions = 3, 1087 .regions = { 1088 ERASEINFO(0x2000,8), 1089 ERASEINFO(0x10000,126), 1090 ERASEINFO(0x2000,8), 1091 } 1092 }, { 1093 .mfr_id = MANUFACTURER_MACRONIX, 1094 .dev_id = MX29LV160B, 1095 .name = "MXIC MX29LV160B", 1096 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1097 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1098 .dev_size = SIZE_2MiB, 1099 .cmd_set = P_ID_AMD_STD, 1100 .nr_regions = 4, 1101 .regions = { 1102 ERASEINFO(0x04000,1), 1103 ERASEINFO(0x02000,2), 1104 ERASEINFO(0x08000,1), 1105 ERASEINFO(0x10000,31) 1106 } 1107 }, { 1108 .mfr_id = MANUFACTURER_MACRONIX, 1109 .dev_id = MX29F040, 1110 .name = "Macronix MX29F040", 1111 .devtypes = CFI_DEVICETYPE_X8, 1112 .uaddr = MTD_UADDR_0x0555_0x02AA, 1113 .dev_size = SIZE_512KiB, 1114 .cmd_set = P_ID_AMD_STD, 1115 .nr_regions = 1, 1116 .regions = { 1117 ERASEINFO(0x10000,8), 1118 } 1119 }, { 1120 .mfr_id = MANUFACTURER_MACRONIX, 1121 .dev_id = MX29F016, 1122 .name = "Macronix MX29F016", 1123 .devtypes = CFI_DEVICETYPE_X8, 1124 .uaddr = MTD_UADDR_0x0555_0x02AA, 1125 .dev_size = SIZE_2MiB, 1126 .cmd_set = P_ID_AMD_STD, 1127 .nr_regions = 1, 1128 .regions = { 1129 ERASEINFO(0x10000,32), 1130 } 1131 }, { 1132 .mfr_id = MANUFACTURER_MACRONIX, 1133 .dev_id = MX29F004T, 1134 .name = "Macronix MX29F004T", 1135 .devtypes = CFI_DEVICETYPE_X8, 1136 .uaddr = MTD_UADDR_0x0555_0x02AA, 1137 .dev_size = SIZE_512KiB, 1138 .cmd_set = P_ID_AMD_STD, 1139 .nr_regions = 4, 1140 .regions = { 1141 ERASEINFO(0x10000,7), 1142 ERASEINFO(0x08000,1), 1143 ERASEINFO(0x02000,2), 1144 ERASEINFO(0x04000,1), 1145 } 1146 }, { 1147 .mfr_id = MANUFACTURER_MACRONIX, 1148 .dev_id = MX29F004B, 1149 .name = "Macronix MX29F004B", 1150 .devtypes = CFI_DEVICETYPE_X8, 1151 .uaddr = MTD_UADDR_0x0555_0x02AA, 1152 .dev_size = SIZE_512KiB, 1153 .cmd_set = P_ID_AMD_STD, 1154 .nr_regions = 4, 1155 .regions = { 1156 ERASEINFO(0x04000,1), 1157 ERASEINFO(0x02000,2), 1158 ERASEINFO(0x08000,1), 1159 ERASEINFO(0x10000,7), 1160 } 1161 }, { 1162 .mfr_id = MANUFACTURER_MACRONIX, 1163 .dev_id = MX29F002T, 1164 .name = "Macronix MX29F002T", 1165 .devtypes = CFI_DEVICETYPE_X8, 1166 .uaddr = MTD_UADDR_0x0555_0x02AA, 1167 .dev_size = SIZE_256KiB, 1168 .cmd_set = P_ID_AMD_STD, 1169 .nr_regions = 4, 1170 .regions = { 1171 ERASEINFO(0x10000,3), 1172 ERASEINFO(0x08000,1), 1173 ERASEINFO(0x02000,2), 1174 ERASEINFO(0x04000,1), 1175 } 1176 }, { 1177 .mfr_id = MANUFACTURER_PMC, 1178 .dev_id = PM49FL002, 1179 .name = "PMC Pm49FL002", 1180 .devtypes = CFI_DEVICETYPE_X8, 1181 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1182 .dev_size = SIZE_256KiB, 1183 .cmd_set = P_ID_AMD_STD, 1184 .nr_regions = 1, 1185 .regions = { 1186 ERASEINFO( 0x01000, 64 ) 1187 } 1188 }, { 1189 .mfr_id = MANUFACTURER_PMC, 1190 .dev_id = PM49FL004, 1191 .name = "PMC Pm49FL004", 1192 .devtypes = CFI_DEVICETYPE_X8, 1193 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1194 .dev_size = SIZE_512KiB, 1195 .cmd_set = P_ID_AMD_STD, 1196 .nr_regions = 1, 1197 .regions = { 1198 ERASEINFO( 0x01000, 128 ) 1199 } 1200 }, { 1201 .mfr_id = MANUFACTURER_PMC, 1202 .dev_id = PM49FL008, 1203 .name = "PMC Pm49FL008", 1204 .devtypes = CFI_DEVICETYPE_X8, 1205 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1206 .dev_size = SIZE_1MiB, 1207 .cmd_set = P_ID_AMD_STD, 1208 .nr_regions = 1, 1209 .regions = { 1210 ERASEINFO( 0x01000, 256 ) 1211 } 1212 }, { 1213 .mfr_id = MANUFACTURER_SHARP, 1214 .dev_id = LH28F640BF, 1215 .name = "LH28F640BF", 1216 .devtypes = CFI_DEVICETYPE_X8, 1217 .uaddr = MTD_UADDR_UNNECESSARY, 1218 .dev_size = SIZE_4MiB, 1219 .cmd_set = P_ID_INTEL_STD, 1220 .nr_regions = 1, 1221 .regions = { 1222 ERASEINFO(0x40000,16), 1223 } 1224 }, { 1225 .mfr_id = MANUFACTURER_SST, 1226 .dev_id = SST39LF512, 1227 .name = "SST 39LF512", 1228 .devtypes = CFI_DEVICETYPE_X8, 1229 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1230 .dev_size = SIZE_64KiB, 1231 .cmd_set = P_ID_AMD_STD, 1232 .nr_regions = 1, 1233 .regions = { 1234 ERASEINFO(0x01000,16), 1235 } 1236 }, { 1237 .mfr_id = MANUFACTURER_SST, 1238 .dev_id = SST39LF010, 1239 .name = "SST 39LF010", 1240 .devtypes = CFI_DEVICETYPE_X8, 1241 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1242 .dev_size = SIZE_128KiB, 1243 .cmd_set = P_ID_AMD_STD, 1244 .nr_regions = 1, 1245 .regions = { 1246 ERASEINFO(0x01000,32), 1247 } 1248 }, { 1249 .mfr_id = MANUFACTURER_SST, 1250 .dev_id = SST29EE020, 1251 .name = "SST 29EE020", 1252 .devtypes = CFI_DEVICETYPE_X8, 1253 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1254 .dev_size = SIZE_256KiB, 1255 .cmd_set = P_ID_SST_PAGE, 1256 .nr_regions = 1, 1257 .regions = {ERASEINFO(0x01000,64), 1258 } 1259 }, { 1260 .mfr_id = MANUFACTURER_SST, 1261 .dev_id = SST29LE020, 1262 .name = "SST 29LE020", 1263 .devtypes = CFI_DEVICETYPE_X8, 1264 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1265 .dev_size = SIZE_256KiB, 1266 .cmd_set = P_ID_SST_PAGE, 1267 .nr_regions = 1, 1268 .regions = {ERASEINFO(0x01000,64), 1269 } 1270 }, { 1271 .mfr_id = MANUFACTURER_SST, 1272 .dev_id = SST39LF020, 1273 .name = "SST 39LF020", 1274 .devtypes = CFI_DEVICETYPE_X8, 1275 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1276 .dev_size = SIZE_256KiB, 1277 .cmd_set = P_ID_AMD_STD, 1278 .nr_regions = 1, 1279 .regions = { 1280 ERASEINFO(0x01000,64), 1281 } 1282 }, { 1283 .mfr_id = MANUFACTURER_SST, 1284 .dev_id = SST39LF040, 1285 .name = "SST 39LF040", 1286 .devtypes = CFI_DEVICETYPE_X8, 1287 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1288 .dev_size = SIZE_512KiB, 1289 .cmd_set = P_ID_AMD_STD, 1290 .nr_regions = 1, 1291 .regions = { 1292 ERASEINFO(0x01000,128), 1293 } 1294 }, { 1295 .mfr_id = MANUFACTURER_SST, 1296 .dev_id = SST39SF010A, 1297 .name = "SST 39SF010A", 1298 .devtypes = CFI_DEVICETYPE_X8, 1299 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1300 .dev_size = SIZE_128KiB, 1301 .cmd_set = P_ID_AMD_STD, 1302 .nr_regions = 1, 1303 .regions = { 1304 ERASEINFO(0x01000,32), 1305 } 1306 }, { 1307 .mfr_id = MANUFACTURER_SST, 1308 .dev_id = SST39SF020A, 1309 .name = "SST 39SF020A", 1310 .devtypes = CFI_DEVICETYPE_X8, 1311 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1312 .dev_size = SIZE_256KiB, 1313 .cmd_set = P_ID_AMD_STD, 1314 .nr_regions = 1, 1315 .regions = { 1316 ERASEINFO(0x01000,64), 1317 } 1318 }, { 1319 .mfr_id = MANUFACTURER_SST, 1320 .dev_id = SST49LF040B, 1321 .name = "SST 49LF040B", 1322 .devtypes = CFI_DEVICETYPE_X8, 1323 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1324 .dev_size = SIZE_512KiB, 1325 .cmd_set = P_ID_AMD_STD, 1326 .nr_regions = 1, 1327 .regions = { 1328 ERASEINFO(0x01000,128), 1329 } 1330 }, { 1331 1332 .mfr_id = MANUFACTURER_SST, 1333 .dev_id = SST49LF004B, 1334 .name = "SST 49LF004B", 1335 .devtypes = CFI_DEVICETYPE_X8, 1336 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1337 .dev_size = SIZE_512KiB, 1338 .cmd_set = P_ID_AMD_STD, 1339 .nr_regions = 1, 1340 .regions = { 1341 ERASEINFO(0x01000,128), 1342 } 1343 }, { 1344 .mfr_id = MANUFACTURER_SST, 1345 .dev_id = SST49LF008A, 1346 .name = "SST 49LF008A", 1347 .devtypes = CFI_DEVICETYPE_X8, 1348 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1349 .dev_size = SIZE_1MiB, 1350 .cmd_set = P_ID_AMD_STD, 1351 .nr_regions = 1, 1352 .regions = { 1353 ERASEINFO(0x01000,256), 1354 } 1355 }, { 1356 .mfr_id = MANUFACTURER_SST, 1357 .dev_id = SST49LF030A, 1358 .name = "SST 49LF030A", 1359 .devtypes = CFI_DEVICETYPE_X8, 1360 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1361 .dev_size = SIZE_512KiB, 1362 .cmd_set = P_ID_AMD_STD, 1363 .nr_regions = 1, 1364 .regions = { 1365 ERASEINFO(0x01000,96), 1366 } 1367 }, { 1368 .mfr_id = MANUFACTURER_SST, 1369 .dev_id = SST49LF040A, 1370 .name = "SST 49LF040A", 1371 .devtypes = CFI_DEVICETYPE_X8, 1372 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1373 .dev_size = SIZE_512KiB, 1374 .cmd_set = P_ID_AMD_STD, 1375 .nr_regions = 1, 1376 .regions = { 1377 ERASEINFO(0x01000,128), 1378 } 1379 }, { 1380 .mfr_id = MANUFACTURER_SST, 1381 .dev_id = SST49LF080A, 1382 .name = "SST 49LF080A", 1383 .devtypes = CFI_DEVICETYPE_X8, 1384 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1385 .dev_size = SIZE_1MiB, 1386 .cmd_set = P_ID_AMD_STD, 1387 .nr_regions = 1, 1388 .regions = { 1389 ERASEINFO(0x01000,256), 1390 } 1391 }, { 1392 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1393 .dev_id = SST39LF160, 1394 .name = "SST 39LF160", 1395 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1396 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1397 .dev_size = SIZE_2MiB, 1398 .cmd_set = P_ID_AMD_STD, 1399 .nr_regions = 2, 1400 .regions = { 1401 ERASEINFO(0x1000,256), 1402 ERASEINFO(0x1000,256) 1403 } 1404 }, { 1405 .mfr_id = MANUFACTURER_SST, /* should be CFI */ 1406 .dev_id = SST39VF1601, 1407 .name = "SST 39VF1601", 1408 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1409 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1410 .dev_size = SIZE_2MiB, 1411 .cmd_set = P_ID_AMD_STD, 1412 .nr_regions = 2, 1413 .regions = { 1414 ERASEINFO(0x1000,256), 1415 ERASEINFO(0x1000,256) 1416 } 1417 }, { 1418 .mfr_id = MANUFACTURER_SST, 1419 .dev_id = SST36VF3203, 1420 .name = "SST 36VF3203", 1421 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1422 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1423 .dev_size = SIZE_4MiB, 1424 .cmd_set = P_ID_AMD_STD, 1425 .nr_regions = 1, 1426 .regions = { 1427 ERASEINFO(0x10000,64), 1428 } 1429 }, { 1430 .mfr_id = MANUFACTURER_ST, 1431 .dev_id = M29F800AB, 1432 .name = "ST M29F800AB", 1433 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1434 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1435 .dev_size = SIZE_1MiB, 1436 .cmd_set = P_ID_AMD_STD, 1437 .nr_regions = 4, 1438 .regions = { 1439 ERASEINFO(0x04000,1), 1440 ERASEINFO(0x02000,2), 1441 ERASEINFO(0x08000,1), 1442 ERASEINFO(0x10000,15), 1443 } 1444 }, { 1445 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1446 .dev_id = M29W800DT, 1447 .name = "ST M29W800DT", 1448 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1449 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1450 .dev_size = SIZE_1MiB, 1451 .cmd_set = P_ID_AMD_STD, 1452 .nr_regions = 4, 1453 .regions = { 1454 ERASEINFO(0x10000,15), 1455 ERASEINFO(0x08000,1), 1456 ERASEINFO(0x02000,2), 1457 ERASEINFO(0x04000,1) 1458 } 1459 }, { 1460 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1461 .dev_id = M29W800DB, 1462 .name = "ST M29W800DB", 1463 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1464 .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */ 1465 .dev_size = SIZE_1MiB, 1466 .cmd_set = P_ID_AMD_STD, 1467 .nr_regions = 4, 1468 .regions = { 1469 ERASEINFO(0x04000,1), 1470 ERASEINFO(0x02000,2), 1471 ERASEINFO(0x08000,1), 1472 ERASEINFO(0x10000,15) 1473 } 1474 }, { 1475 .mfr_id = MANUFACTURER_ST, 1476 .dev_id = M29W400DT, 1477 .name = "ST M29W400DT", 1478 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1479 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1480 .dev_size = SIZE_512KiB, 1481 .cmd_set = P_ID_AMD_STD, 1482 .nr_regions = 4, 1483 .regions = { 1484 ERASEINFO(0x04000,7), 1485 ERASEINFO(0x02000,1), 1486 ERASEINFO(0x08000,2), 1487 ERASEINFO(0x10000,1) 1488 } 1489 }, { 1490 .mfr_id = MANUFACTURER_ST, 1491 .dev_id = M29W400DB, 1492 .name = "ST M29W400DB", 1493 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1494 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1495 .dev_size = SIZE_512KiB, 1496 .cmd_set = P_ID_AMD_STD, 1497 .nr_regions = 4, 1498 .regions = { 1499 ERASEINFO(0x04000,1), 1500 ERASEINFO(0x02000,2), 1501 ERASEINFO(0x08000,1), 1502 ERASEINFO(0x10000,7) 1503 } 1504 }, { 1505 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1506 .dev_id = M29W160DT, 1507 .name = "ST M29W160DT", 1508 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1509 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1510 .dev_size = SIZE_2MiB, 1511 .cmd_set = P_ID_AMD_STD, 1512 .nr_regions = 4, 1513 .regions = { 1514 ERASEINFO(0x10000,31), 1515 ERASEINFO(0x08000,1), 1516 ERASEINFO(0x02000,2), 1517 ERASEINFO(0x04000,1) 1518 } 1519 }, { 1520 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */ 1521 .dev_id = M29W160DB, 1522 .name = "ST M29W160DB", 1523 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1524 .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */ 1525 .dev_size = SIZE_2MiB, 1526 .cmd_set = P_ID_AMD_STD, 1527 .nr_regions = 4, 1528 .regions = { 1529 ERASEINFO(0x04000,1), 1530 ERASEINFO(0x02000,2), 1531 ERASEINFO(0x08000,1), 1532 ERASEINFO(0x10000,31) 1533 } 1534 }, { 1535 .mfr_id = MANUFACTURER_ST, 1536 .dev_id = M29W040B, 1537 .name = "ST M29W040B", 1538 .devtypes = CFI_DEVICETYPE_X8, 1539 .uaddr = MTD_UADDR_0x0555_0x02AA, 1540 .dev_size = SIZE_512KiB, 1541 .cmd_set = P_ID_AMD_STD, 1542 .nr_regions = 1, 1543 .regions = { 1544 ERASEINFO(0x10000,8), 1545 } 1546 }, { 1547 .mfr_id = MANUFACTURER_ST, 1548 .dev_id = M50FW040, 1549 .name = "ST M50FW040", 1550 .devtypes = CFI_DEVICETYPE_X8, 1551 .uaddr = MTD_UADDR_UNNECESSARY, 1552 .dev_size = SIZE_512KiB, 1553 .cmd_set = P_ID_INTEL_EXT, 1554 .nr_regions = 1, 1555 .regions = { 1556 ERASEINFO(0x10000,8), 1557 } 1558 }, { 1559 .mfr_id = MANUFACTURER_ST, 1560 .dev_id = M50FW080, 1561 .name = "ST M50FW080", 1562 .devtypes = CFI_DEVICETYPE_X8, 1563 .uaddr = MTD_UADDR_UNNECESSARY, 1564 .dev_size = SIZE_1MiB, 1565 .cmd_set = P_ID_INTEL_EXT, 1566 .nr_regions = 1, 1567 .regions = { 1568 ERASEINFO(0x10000,16), 1569 } 1570 }, { 1571 .mfr_id = MANUFACTURER_ST, 1572 .dev_id = M50FW016, 1573 .name = "ST M50FW016", 1574 .devtypes = CFI_DEVICETYPE_X8, 1575 .uaddr = MTD_UADDR_UNNECESSARY, 1576 .dev_size = SIZE_2MiB, 1577 .cmd_set = P_ID_INTEL_EXT, 1578 .nr_regions = 1, 1579 .regions = { 1580 ERASEINFO(0x10000,32), 1581 } 1582 }, { 1583 .mfr_id = MANUFACTURER_ST, 1584 .dev_id = M50LPW080, 1585 .name = "ST M50LPW080", 1586 .devtypes = CFI_DEVICETYPE_X8, 1587 .uaddr = MTD_UADDR_UNNECESSARY, 1588 .dev_size = SIZE_1MiB, 1589 .cmd_set = P_ID_INTEL_EXT, 1590 .nr_regions = 1, 1591 .regions = { 1592 ERASEINFO(0x10000,16), 1593 } 1594 }, { 1595 .mfr_id = MANUFACTURER_TOSHIBA, 1596 .dev_id = TC58FVT160, 1597 .name = "Toshiba TC58FVT160", 1598 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1599 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1600 .dev_size = SIZE_2MiB, 1601 .cmd_set = P_ID_AMD_STD, 1602 .nr_regions = 4, 1603 .regions = { 1604 ERASEINFO(0x10000,31), 1605 ERASEINFO(0x08000,1), 1606 ERASEINFO(0x02000,2), 1607 ERASEINFO(0x04000,1) 1608 } 1609 }, { 1610 .mfr_id = MANUFACTURER_TOSHIBA, 1611 .dev_id = TC58FVB160, 1612 .name = "Toshiba TC58FVB160", 1613 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1614 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1615 .dev_size = SIZE_2MiB, 1616 .cmd_set = P_ID_AMD_STD, 1617 .nr_regions = 4, 1618 .regions = { 1619 ERASEINFO(0x04000,1), 1620 ERASEINFO(0x02000,2), 1621 ERASEINFO(0x08000,1), 1622 ERASEINFO(0x10000,31) 1623 } 1624 }, { 1625 .mfr_id = MANUFACTURER_TOSHIBA, 1626 .dev_id = TC58FVB321, 1627 .name = "Toshiba TC58FVB321", 1628 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1629 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1630 .dev_size = SIZE_4MiB, 1631 .cmd_set = P_ID_AMD_STD, 1632 .nr_regions = 2, 1633 .regions = { 1634 ERASEINFO(0x02000,8), 1635 ERASEINFO(0x10000,63) 1636 } 1637 }, { 1638 .mfr_id = MANUFACTURER_TOSHIBA, 1639 .dev_id = TC58FVT321, 1640 .name = "Toshiba TC58FVT321", 1641 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1642 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1643 .dev_size = SIZE_4MiB, 1644 .cmd_set = P_ID_AMD_STD, 1645 .nr_regions = 2, 1646 .regions = { 1647 ERASEINFO(0x10000,63), 1648 ERASEINFO(0x02000,8) 1649 } 1650 }, { 1651 .mfr_id = MANUFACTURER_TOSHIBA, 1652 .dev_id = TC58FVB641, 1653 .name = "Toshiba TC58FVB641", 1654 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1655 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1656 .dev_size = SIZE_8MiB, 1657 .cmd_set = P_ID_AMD_STD, 1658 .nr_regions = 2, 1659 .regions = { 1660 ERASEINFO(0x02000,8), 1661 ERASEINFO(0x10000,127) 1662 } 1663 }, { 1664 .mfr_id = MANUFACTURER_TOSHIBA, 1665 .dev_id = TC58FVT641, 1666 .name = "Toshiba TC58FVT641", 1667 .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8, 1668 .uaddr = MTD_UADDR_0x0AAA_0x0555, 1669 .dev_size = SIZE_8MiB, 1670 .cmd_set = P_ID_AMD_STD, 1671 .nr_regions = 2, 1672 .regions = { 1673 ERASEINFO(0x10000,127), 1674 ERASEINFO(0x02000,8) 1675 } 1676 }, { 1677 .mfr_id = MANUFACTURER_WINBOND, 1678 .dev_id = W49V002A, 1679 .name = "Winbond W49V002A", 1680 .devtypes = CFI_DEVICETYPE_X8, 1681 .uaddr = MTD_UADDR_0x5555_0x2AAA, 1682 .dev_size = SIZE_256KiB, 1683 .cmd_set = P_ID_AMD_STD, 1684 .nr_regions = 4, 1685 .regions = { 1686 ERASEINFO(0x10000, 3), 1687 ERASEINFO(0x08000, 1), 1688 ERASEINFO(0x02000, 2), 1689 ERASEINFO(0x04000, 1), 1690 } 1691 } 1692 }; 1693 1694 static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base, 1695 struct cfi_private *cfi) 1696 { 1697 map_word result; 1698 unsigned long mask; 1699 u32 ofs = cfi_build_cmd_addr(0, cfi_interleave(cfi), cfi->device_type); 1700 mask = (1 << (cfi->device_type * 8)) -1; 1701 result = map_read(map, base + ofs); 1702 return result.x[0] & mask; 1703 } 1704 1705 static inline u32 jedec_read_id(struct map_info *map, uint32_t base, 1706 struct cfi_private *cfi) 1707 { 1708 map_word result; 1709 unsigned long mask; 1710 u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type); 1711 mask = (1 << (cfi->device_type * 8)) -1; 1712 result = map_read(map, base + ofs); 1713 return result.x[0] & mask; 1714 } 1715 1716 static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi) 1717 { 1718 /* Reset */ 1719 1720 /* after checking the datasheets for SST, MACRONIX and ATMEL 1721 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset 1722 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at 1723 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips 1724 * as they will ignore the writes and dont care what address 1725 * the F0 is written to */ 1726 if (cfi->addr_unlock1) { 1727 DEBUG( MTD_DEBUG_LEVEL3, 1728 "reset unlock called %x %x \n", 1729 cfi->addr_unlock1,cfi->addr_unlock2); 1730 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1731 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1732 } 1733 1734 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1735 /* Some misdesigned Intel chips do not respond for 0xF0 for a reset, 1736 * so ensure we're in read mode. Send both the Intel and the AMD command 1737 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so 1738 * this should be safe. 1739 */ 1740 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); 1741 /* FIXME - should have reset delay before continuing */ 1742 } 1743 1744 1745 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index) 1746 { 1747 int i,num_erase_regions; 1748 uint8_t uaddr; 1749 1750 if (! (jedec_table[index].devtypes & p_cfi->device_type)) { 1751 DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n", 1752 jedec_table[index].name, 4 * (1<<p_cfi->device_type)); 1753 return 0; 1754 } 1755 1756 printk(KERN_INFO "Found: %s\n",jedec_table[index].name); 1757 1758 num_erase_regions = jedec_table[index].nr_regions; 1759 1760 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL); 1761 if (!p_cfi->cfiq) { 1762 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name); 1763 return 0; 1764 } 1765 1766 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident)); 1767 1768 p_cfi->cfiq->P_ID = jedec_table[index].cmd_set; 1769 p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions; 1770 p_cfi->cfiq->DevSize = jedec_table[index].dev_size; 1771 p_cfi->cfi_mode = CFI_MODE_JEDEC; 1772 1773 for (i=0; i<num_erase_regions; i++){ 1774 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i]; 1775 } 1776 p_cfi->cmdset_priv = NULL; 1777 1778 /* This may be redundant for some cases, but it doesn't hurt */ 1779 p_cfi->mfr = jedec_table[index].mfr_id; 1780 p_cfi->id = jedec_table[index].dev_id; 1781 1782 uaddr = jedec_table[index].uaddr; 1783 1784 /* The table has unlock addresses in _bytes_, and we try not to let 1785 our brains explode when we see the datasheets talking about address 1786 lines numbered from A-1 to A18. The CFI table has unlock addresses 1787 in device-words according to the mode the device is connected in */ 1788 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type; 1789 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type; 1790 1791 return 1; /* ok */ 1792 } 1793 1794 1795 /* 1796 * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing 1797 * the mapped address, unlock addresses, and proper chip ID. This function 1798 * attempts to minimize errors. It is doubtfull that this probe will ever 1799 * be perfect - consequently there should be some module parameters that 1800 * could be manually specified to force the chip info. 1801 */ 1802 static inline int jedec_match( uint32_t base, 1803 struct map_info *map, 1804 struct cfi_private *cfi, 1805 const struct amd_flash_info *finfo ) 1806 { 1807 int rc = 0; /* failure until all tests pass */ 1808 u32 mfr, id; 1809 uint8_t uaddr; 1810 1811 /* 1812 * The IDs must match. For X16 and X32 devices operating in 1813 * a lower width ( X8 or X16 ), the device ID's are usually just 1814 * the lower byte(s) of the larger device ID for wider mode. If 1815 * a part is found that doesn't fit this assumption (device id for 1816 * smaller width mode is completely unrealated to full-width mode) 1817 * then the jedec_table[] will have to be augmented with the IDs 1818 * for different widths. 1819 */ 1820 switch (cfi->device_type) { 1821 case CFI_DEVICETYPE_X8: 1822 mfr = (uint8_t)finfo->mfr_id; 1823 id = (uint8_t)finfo->dev_id; 1824 1825 /* bjd: it seems that if we do this, we can end up 1826 * detecting 16bit flashes as an 8bit device, even though 1827 * there aren't. 1828 */ 1829 if (finfo->dev_id > 0xff) { 1830 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n", 1831 __func__); 1832 goto match_done; 1833 } 1834 break; 1835 case CFI_DEVICETYPE_X16: 1836 mfr = (uint16_t)finfo->mfr_id; 1837 id = (uint16_t)finfo->dev_id; 1838 break; 1839 case CFI_DEVICETYPE_X32: 1840 mfr = (uint16_t)finfo->mfr_id; 1841 id = (uint32_t)finfo->dev_id; 1842 break; 1843 default: 1844 printk(KERN_WARNING 1845 "MTD %s(): Unsupported device type %d\n", 1846 __func__, cfi->device_type); 1847 goto match_done; 1848 } 1849 if ( cfi->mfr != mfr || cfi->id != id ) { 1850 goto match_done; 1851 } 1852 1853 /* the part size must fit in the memory window */ 1854 DEBUG( MTD_DEBUG_LEVEL3, 1855 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n", 1856 __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) ); 1857 if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) { 1858 DEBUG( MTD_DEBUG_LEVEL3, 1859 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n", 1860 __func__, finfo->mfr_id, finfo->dev_id, 1861 1 << finfo->dev_size ); 1862 goto match_done; 1863 } 1864 1865 if (! (finfo->devtypes & cfi->device_type)) 1866 goto match_done; 1867 1868 uaddr = finfo->uaddr; 1869 1870 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n", 1871 __func__, cfi->addr_unlock1, cfi->addr_unlock2 ); 1872 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr 1873 && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 || 1874 unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) { 1875 DEBUG( MTD_DEBUG_LEVEL3, 1876 "MTD %s(): 0x%.4x 0x%.4x did not match\n", 1877 __func__, 1878 unlock_addrs[uaddr].addr1, 1879 unlock_addrs[uaddr].addr2); 1880 goto match_done; 1881 } 1882 1883 /* 1884 * Make sure the ID's dissappear when the device is taken out of 1885 * ID mode. The only time this should fail when it should succeed 1886 * is when the ID's are written as data to the same 1887 * addresses. For this rare and unfortunate case the chip 1888 * cannot be probed correctly. 1889 * FIXME - write a driver that takes all of the chip info as 1890 * module parameters, doesn't probe but forces a load. 1891 */ 1892 DEBUG( MTD_DEBUG_LEVEL3, 1893 "MTD %s(): check ID's disappear when not in ID mode\n", 1894 __func__ ); 1895 jedec_reset( base, map, cfi ); 1896 mfr = jedec_read_mfr( map, base, cfi ); 1897 id = jedec_read_id( map, base, cfi ); 1898 if ( mfr == cfi->mfr && id == cfi->id ) { 1899 DEBUG( MTD_DEBUG_LEVEL3, 1900 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n" 1901 "You might need to manually specify JEDEC parameters.\n", 1902 __func__, cfi->mfr, cfi->id ); 1903 goto match_done; 1904 } 1905 1906 /* all tests passed - mark as success */ 1907 rc = 1; 1908 1909 /* 1910 * Put the device back in ID mode - only need to do this if we 1911 * were truly frobbing a real device. 1912 */ 1913 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ ); 1914 if (cfi->addr_unlock1) { 1915 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1916 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1917 } 1918 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1919 /* FIXME - should have a delay before continuing */ 1920 1921 match_done: 1922 return rc; 1923 } 1924 1925 1926 static int jedec_probe_chip(struct map_info *map, __u32 base, 1927 unsigned long *chip_map, struct cfi_private *cfi) 1928 { 1929 int i; 1930 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 1931 u32 probe_offset1, probe_offset2; 1932 1933 retry: 1934 if (!cfi->numchips) { 1935 uaddr_idx++; 1936 1937 if (MTD_UADDR_UNNECESSARY == uaddr_idx) 1938 return 0; 1939 1940 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type; 1941 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type; 1942 } 1943 1944 /* Make certain we aren't probing past the end of map */ 1945 if (base >= map->size) { 1946 printk(KERN_NOTICE 1947 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n", 1948 base, map->size -1); 1949 return 0; 1950 1951 } 1952 /* Ensure the unlock addresses we try stay inside the map */ 1953 probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type); 1954 probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type); 1955 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) || 1956 ((base + probe_offset2 + map_bankwidth(map)) >= map->size)) 1957 goto retry; 1958 1959 /* Reset */ 1960 jedec_reset(base, map, cfi); 1961 1962 /* Autoselect Mode */ 1963 if(cfi->addr_unlock1) { 1964 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1965 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL); 1966 } 1967 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL); 1968 /* FIXME - should have a delay before continuing */ 1969 1970 if (!cfi->numchips) { 1971 /* This is the first time we're called. Set up the CFI 1972 stuff accordingly and return */ 1973 1974 cfi->mfr = jedec_read_mfr(map, base, cfi); 1975 cfi->id = jedec_read_id(map, base, cfi); 1976 DEBUG(MTD_DEBUG_LEVEL3, 1977 "Search for id:(%02x %02x) interleave(%d) type(%d)\n", 1978 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type); 1979 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 1980 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) { 1981 DEBUG( MTD_DEBUG_LEVEL3, 1982 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n", 1983 __func__, cfi->mfr, cfi->id, 1984 cfi->addr_unlock1, cfi->addr_unlock2 ); 1985 if (!cfi_jedec_setup(cfi, i)) 1986 return 0; 1987 goto ok_out; 1988 } 1989 } 1990 goto retry; 1991 } else { 1992 uint16_t mfr; 1993 uint16_t id; 1994 1995 /* Make sure it is a chip of the same manufacturer and id */ 1996 mfr = jedec_read_mfr(map, base, cfi); 1997 id = jedec_read_id(map, base, cfi); 1998 1999 if ((mfr != cfi->mfr) || (id != cfi->id)) { 2000 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n", 2001 map->name, mfr, id, base); 2002 jedec_reset(base, map, cfi); 2003 return 0; 2004 } 2005 } 2006 2007 /* Check each previous chip locations to see if it's an alias */ 2008 for (i=0; i < (base >> cfi->chipshift); i++) { 2009 unsigned long start; 2010 if(!test_bit(i, chip_map)) { 2011 continue; /* Skip location; no valid chip at this address */ 2012 } 2013 start = i << cfi->chipshift; 2014 if (jedec_read_mfr(map, start, cfi) == cfi->mfr && 2015 jedec_read_id(map, start, cfi) == cfi->id) { 2016 /* Eep. This chip also looks like it's in autoselect mode. 2017 Is it an alias for the new one? */ 2018 jedec_reset(start, map, cfi); 2019 2020 /* If the device IDs go away, it's an alias */ 2021 if (jedec_read_mfr(map, base, cfi) != cfi->mfr || 2022 jedec_read_id(map, base, cfi) != cfi->id) { 2023 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2024 map->name, base, start); 2025 return 0; 2026 } 2027 2028 /* Yes, it's actually got the device IDs as data. Most 2029 * unfortunate. Stick the new chip in read mode 2030 * too and if it's the same, assume it's an alias. */ 2031 /* FIXME: Use other modes to do a proper check */ 2032 jedec_reset(base, map, cfi); 2033 if (jedec_read_mfr(map, base, cfi) == cfi->mfr && 2034 jedec_read_id(map, base, cfi) == cfi->id) { 2035 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n", 2036 map->name, base, start); 2037 return 0; 2038 } 2039 } 2040 } 2041 2042 /* OK, if we got to here, then none of the previous chips appear to 2043 be aliases for the current one. */ 2044 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */ 2045 cfi->numchips++; 2046 2047 ok_out: 2048 /* Put it back into Read Mode */ 2049 jedec_reset(base, map, cfi); 2050 2051 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n", 2052 map->name, cfi_interleave(cfi), cfi->device_type*8, base, 2053 map->bankwidth*8); 2054 2055 return 1; 2056 } 2057 2058 static struct chip_probe jedec_chip_probe = { 2059 .name = "JEDEC", 2060 .probe_chip = jedec_probe_chip 2061 }; 2062 2063 static struct mtd_info *jedec_probe(struct map_info *map) 2064 { 2065 /* 2066 * Just use the generic probe stuff to call our CFI-specific 2067 * chip_probe routine in all the possible permutations, etc. 2068 */ 2069 return mtd_do_chip_probe(map, &jedec_chip_probe); 2070 } 2071 2072 static struct mtd_chip_driver jedec_chipdrv = { 2073 .probe = jedec_probe, 2074 .name = "jedec_probe", 2075 .module = THIS_MODULE 2076 }; 2077 2078 static int __init jedec_probe_init(void) 2079 { 2080 register_mtd_chip_driver(&jedec_chipdrv); 2081 return 0; 2082 } 2083 2084 static void __exit jedec_probe_exit(void) 2085 { 2086 unregister_mtd_chip_driver(&jedec_chipdrv); 2087 } 2088 2089 module_init(jedec_probe_init); 2090 module_exit(jedec_probe_exit); 2091 2092 MODULE_LICENSE("GPL"); 2093 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al."); 2094 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips"); 2095