1 /* 2 * Common Flash Interface support: 3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) 4 * 5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> 6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> 7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> 8 * 9 * 2_by_8 routines added by Simon Munton 10 * 11 * 4_by_16 work by Carolyn J. Smith 12 * 13 * XIP support hooks by Vitaly Wool (based on code for Intel flash 14 * by Nicolas Pitre) 15 * 16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 17 * 18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 19 * 20 * This code is GPL 21 */ 22 23 #include <linux/module.h> 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <asm/io.h> 28 #include <asm/byteorder.h> 29 30 #include <linux/errno.h> 31 #include <linux/slab.h> 32 #include <linux/delay.h> 33 #include <linux/interrupt.h> 34 #include <linux/reboot.h> 35 #include <linux/of.h> 36 #include <linux/of_platform.h> 37 #include <linux/mtd/map.h> 38 #include <linux/mtd/mtd.h> 39 #include <linux/mtd/cfi.h> 40 #include <linux/mtd/xip.h> 41 42 #define AMD_BOOTLOC_BUG 43 #define FORCE_WORD_WRITE 0 44 45 #define MAX_RETRIES 3 46 47 #define SST49LF004B 0x0060 48 #define SST49LF040B 0x0050 49 #define SST49LF008A 0x005a 50 #define AT49BV6416 0x00d6 51 52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); 56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); 57 static void cfi_amdstd_sync (struct mtd_info *); 58 static int cfi_amdstd_suspend (struct mtd_info *); 59 static void cfi_amdstd_resume (struct mtd_info *); 60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *); 61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t, 62 size_t *, struct otp_info *); 63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t, 64 size_t *, struct otp_info *); 65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t, 67 size_t *, u_char *); 68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t, 69 size_t *, u_char *); 70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t, 71 size_t *, u_char *); 72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t); 73 74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 75 size_t *retlen, const u_char *buf); 76 77 static void cfi_amdstd_destroy(struct mtd_info *); 78 79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int); 80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); 81 82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); 83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); 84 #include "fwh_lock.h" 85 86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 88 89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); 92 93 static struct mtd_chip_driver cfi_amdstd_chipdrv = { 94 .probe = NULL, /* Not usable directly */ 95 .destroy = cfi_amdstd_destroy, 96 .name = "cfi_cmdset_0002", 97 .module = THIS_MODULE 98 }; 99 100 101 /* #define DEBUG_CFI_FEATURES */ 102 103 104 #ifdef DEBUG_CFI_FEATURES 105 static void cfi_tell_features(struct cfi_pri_amdstd *extp) 106 { 107 const char* erase_suspend[3] = { 108 "Not supported", "Read only", "Read/write" 109 }; 110 const char* top_bottom[6] = { 111 "No WP", "8x8KiB sectors at top & bottom, no WP", 112 "Bottom boot", "Top boot", 113 "Uniform, Bottom WP", "Uniform, Top WP" 114 }; 115 116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); 117 printk(" Address sensitive unlock: %s\n", 118 (extp->SiliconRevision & 1) ? "Not required" : "Required"); 119 120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) 121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); 122 else 123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); 124 125 if (extp->BlkProt == 0) 126 printk(" Block protection: Not supported\n"); 127 else 128 printk(" Block protection: %d sectors per group\n", extp->BlkProt); 129 130 131 printk(" Temporary block unprotect: %s\n", 132 extp->TmpBlkUnprotect ? "Supported" : "Not supported"); 133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); 134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); 135 printk(" Burst mode: %s\n", 136 extp->BurstMode ? "Supported" : "Not supported"); 137 if (extp->PageMode == 0) 138 printk(" Page mode: Not supported\n"); 139 else 140 printk(" Page mode: %d word page\n", extp->PageMode << 2); 141 142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", 143 extp->VppMin >> 4, extp->VppMin & 0xf); 144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", 145 extp->VppMax >> 4, extp->VppMax & 0xf); 146 147 if (extp->TopBottom < ARRAY_SIZE(top_bottom)) 148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); 149 else 150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); 151 } 152 #endif 153 154 #ifdef AMD_BOOTLOC_BUG 155 /* Wheee. Bring me the head of someone at AMD. */ 156 static void fixup_amd_bootblock(struct mtd_info *mtd) 157 { 158 struct map_info *map = mtd->priv; 159 struct cfi_private *cfi = map->fldrv_priv; 160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 161 __u8 major = extp->MajorVersion; 162 __u8 minor = extp->MinorVersion; 163 164 if (((major << 8) | minor) < 0x3131) { 165 /* CFI version 1.0 => don't trust bootloc */ 166 167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", 168 map->name, cfi->mfr, cfi->id); 169 170 /* AFAICS all 29LV400 with a bottom boot block have a device ID 171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. 172 * These were badly detected as they have the 0x80 bit set 173 * so treat them as a special case. 174 */ 175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && 176 177 /* Macronix added CFI to their 2nd generation 178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, 179 * Fujitsu, Spansion, EON, ESI and older Macronix) 180 * has CFI. 181 * 182 * Therefore also check the manufacturer. 183 * This reduces the risk of false detection due to 184 * the 8-bit device ID. 185 */ 186 (cfi->mfr == CFI_MFR_MACRONIX)) { 187 pr_debug("%s: Macronix MX29LV400C with bottom boot block" 188 " detected\n", map->name); 189 extp->TopBottom = 2; /* bottom boot */ 190 } else 191 if (cfi->id & 0x80) { 192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); 193 extp->TopBottom = 3; /* top boot */ 194 } else { 195 extp->TopBottom = 2; /* bottom boot */ 196 } 197 198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;" 199 " deduced %s from Device ID\n", map->name, major, minor, 200 extp->TopBottom == 2 ? "bottom" : "top"); 201 } 202 } 203 #endif 204 205 static void fixup_use_write_buffers(struct mtd_info *mtd) 206 { 207 struct map_info *map = mtd->priv; 208 struct cfi_private *cfi = map->fldrv_priv; 209 if (cfi->cfiq->BufWriteTimeoutTyp) { 210 pr_debug("Using buffer write method\n"); 211 mtd->_write = cfi_amdstd_write_buffers; 212 } 213 } 214 215 /* Atmel chips don't use the same PRI format as AMD chips */ 216 static void fixup_convert_atmel_pri(struct mtd_info *mtd) 217 { 218 struct map_info *map = mtd->priv; 219 struct cfi_private *cfi = map->fldrv_priv; 220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 221 struct cfi_pri_atmel atmel_pri; 222 223 memcpy(&atmel_pri, extp, sizeof(atmel_pri)); 224 memset((char *)extp + 5, 0, sizeof(*extp) - 5); 225 226 if (atmel_pri.Features & 0x02) 227 extp->EraseSuspend = 2; 228 229 /* Some chips got it backwards... */ 230 if (cfi->id == AT49BV6416) { 231 if (atmel_pri.BottomBoot) 232 extp->TopBottom = 3; 233 else 234 extp->TopBottom = 2; 235 } else { 236 if (atmel_pri.BottomBoot) 237 extp->TopBottom = 2; 238 else 239 extp->TopBottom = 3; 240 } 241 242 /* burst write mode not supported */ 243 cfi->cfiq->BufWriteTimeoutTyp = 0; 244 cfi->cfiq->BufWriteTimeoutMax = 0; 245 } 246 247 static void fixup_use_secsi(struct mtd_info *mtd) 248 { 249 /* Setup for chips with a secsi area */ 250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read; 251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read; 252 } 253 254 static void fixup_use_erase_chip(struct mtd_info *mtd) 255 { 256 struct map_info *map = mtd->priv; 257 struct cfi_private *cfi = map->fldrv_priv; 258 if ((cfi->cfiq->NumEraseRegions == 1) && 259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { 260 mtd->_erase = cfi_amdstd_erase_chip; 261 } 262 263 } 264 265 /* 266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors 267 * locked by default. 268 */ 269 static void fixup_use_atmel_lock(struct mtd_info *mtd) 270 { 271 mtd->_lock = cfi_atmel_lock; 272 mtd->_unlock = cfi_atmel_unlock; 273 mtd->flags |= MTD_POWERUP_LOCK; 274 } 275 276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd) 277 { 278 struct map_info *map = mtd->priv; 279 struct cfi_private *cfi = map->fldrv_priv; 280 281 /* 282 * These flashes report two separate eraseblock regions based on the 283 * sector_erase-size and block_erase-size, although they both operate on the 284 * same memory. This is not allowed according to CFI, so we just pick the 285 * sector_erase-size. 286 */ 287 cfi->cfiq->NumEraseRegions = 1; 288 } 289 290 static void fixup_sst39vf(struct mtd_info *mtd) 291 { 292 struct map_info *map = mtd->priv; 293 struct cfi_private *cfi = map->fldrv_priv; 294 295 fixup_old_sst_eraseregion(mtd); 296 297 cfi->addr_unlock1 = 0x5555; 298 cfi->addr_unlock2 = 0x2AAA; 299 } 300 301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd) 302 { 303 struct map_info *map = mtd->priv; 304 struct cfi_private *cfi = map->fldrv_priv; 305 306 fixup_old_sst_eraseregion(mtd); 307 308 cfi->addr_unlock1 = 0x555; 309 cfi->addr_unlock2 = 0x2AA; 310 311 cfi->sector_erase_cmd = CMD(0x50); 312 } 313 314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd) 315 { 316 struct map_info *map = mtd->priv; 317 struct cfi_private *cfi = map->fldrv_priv; 318 319 fixup_sst39vf_rev_b(mtd); 320 321 /* 322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where 323 * it should report a size of 8KBytes (0x0020*256). 324 */ 325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff; 326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", 327 mtd->name); 328 } 329 330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd) 331 { 332 struct map_info *map = mtd->priv; 333 struct cfi_private *cfi = map->fldrv_priv; 334 335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { 336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040; 337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", 338 mtd->name); 339 } 340 } 341 342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd) 343 { 344 struct map_info *map = mtd->priv; 345 struct cfi_private *cfi = map->fldrv_priv; 346 347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { 348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; 349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", 350 mtd->name); 351 } 352 } 353 354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd) 355 { 356 struct map_info *map = mtd->priv; 357 struct cfi_private *cfi = map->fldrv_priv; 358 359 /* 360 * S29NS512P flash uses more than 8bits to report number of sectors, 361 * which is not permitted by CFI. 362 */ 363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff; 364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", 365 mtd->name); 366 } 367 368 /* Used to fix CFI-Tables of chips without Extended Query Tables */ 369 static struct cfi_fixup cfi_nopri_fixup_table[] = { 370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */ 371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */ 372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */ 373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */ 374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */ 375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */ 376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */ 377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */ 378 { 0, 0, NULL } 379 }; 380 381 static struct cfi_fixup cfi_fixup_table[] = { 382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri }, 383 #ifdef AMD_BOOTLOC_BUG 384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock }, 385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock }, 386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock }, 387 #endif 388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi }, 389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi }, 390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi }, 391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi }, 392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi }, 393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi }, 394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors }, 395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors }, 396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors }, 397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors }, 398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors }, 399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */ 400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */ 401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */ 402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */ 403 #if !FORCE_WORD_WRITE 404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers }, 405 #endif 406 { 0, 0, NULL } 407 }; 408 static struct cfi_fixup jedec_fixup_table[] = { 409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock }, 410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock }, 411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock }, 412 { 0, 0, NULL } 413 }; 414 415 static struct cfi_fixup fixup_table[] = { 416 /* The CFI vendor ids and the JEDEC vendor IDs appear 417 * to be common. It is like the devices id's are as 418 * well. This table is to pick all cases where 419 * we know that is the case. 420 */ 421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip }, 422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock }, 423 { 0, 0, NULL } 424 }; 425 426 427 static void cfi_fixup_major_minor(struct cfi_private *cfi, 428 struct cfi_pri_amdstd *extp) 429 { 430 if (cfi->mfr == CFI_MFR_SAMSUNG) { 431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') || 432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) { 433 /* 434 * Samsung K8P2815UQB and K8D6x16UxM chips 435 * report major=0 / minor=0. 436 * K8D3x16UxC chips report major=3 / minor=3. 437 */ 438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu" 439 " Extended Query version to 1.%c\n", 440 extp->MinorVersion); 441 extp->MajorVersion = '1'; 442 } 443 } 444 445 /* 446 * SST 38VF640x chips report major=0xFF / minor=0xFF. 447 */ 448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) { 449 extp->MajorVersion = '1'; 450 extp->MinorVersion = '0'; 451 } 452 } 453 454 static int is_m29ew(struct cfi_private *cfi) 455 { 456 if (cfi->mfr == CFI_MFR_INTEL && 457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) || 458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e))) 459 return 1; 460 return 0; 461 } 462 463 /* 464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20: 465 * Some revisions of the M29EW suffer from erase suspend hang ups. In 466 * particular, it can occur when the sequence 467 * Erase Confirm -> Suspend -> Program -> Resume 468 * causes a lockup due to internal timing issues. The consequence is that the 469 * erase cannot be resumed without inserting a dummy command after programming 470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle 471 * that writes an F0 command code before the RESUME command. 472 */ 473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map, 474 unsigned long adr) 475 { 476 struct cfi_private *cfi = map->fldrv_priv; 477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */ 478 if (is_m29ew(cfi)) 479 map_write(map, CMD(0xF0), adr); 480 } 481 482 /* 483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22: 484 * 485 * Some revisions of the M29EW (for example, A1 and A2 step revisions) 486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND 487 * command is issued after an ERASE RESUME operation without waiting for a 488 * minimum delay. The result is that once the ERASE seems to be completed 489 * (no bits are toggling), the contents of the Flash memory block on which 490 * the erase was ongoing could be inconsistent with the expected values 491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84 492 * values), causing a consequent failure of the ERASE operation. 493 * The occurrence of this issue could be high, especially when file system 494 * operations on the Flash are intensive. As a result, it is recommended 495 * that a patch be applied. Intensive file system operations can cause many 496 * calls to the garbage routine to free Flash space (also by erasing physical 497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME 498 * commands can occur. The problem disappears when a delay is inserted after 499 * the RESUME command by using the udelay() function available in Linux. 500 * The DELAY value must be tuned based on the customer's platform. 501 * The maximum value that fixes the problem in all cases is 500us. 502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient 503 * in most cases. 504 * We have chosen 500µs because this latency is acceptable. 505 */ 506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi) 507 { 508 /* 509 * Resolving the Delay After Resume Issue see Micron TN-13-07 510 * Worst case delay must be 500µs but 30-50µs should be ok as well 511 */ 512 if (is_m29ew(cfi)) 513 cfi_udelay(500); 514 } 515 516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) 517 { 518 struct cfi_private *cfi = map->fldrv_priv; 519 struct device_node __maybe_unused *np = map->device_node; 520 struct mtd_info *mtd; 521 int i; 522 523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); 524 if (!mtd) 525 return NULL; 526 mtd->priv = map; 527 mtd->type = MTD_NORFLASH; 528 529 /* Fill in the default mtd operations */ 530 mtd->_erase = cfi_amdstd_erase_varsize; 531 mtd->_write = cfi_amdstd_write_words; 532 mtd->_read = cfi_amdstd_read; 533 mtd->_sync = cfi_amdstd_sync; 534 mtd->_suspend = cfi_amdstd_suspend; 535 mtd->_resume = cfi_amdstd_resume; 536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg; 537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg; 538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info; 539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info; 540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg; 541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg; 542 mtd->flags = MTD_CAP_NORFLASH; 543 mtd->name = map->name; 544 mtd->writesize = 1; 545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 546 547 pr_debug("MTD %s(): write buffer size %d\n", __func__, 548 mtd->writebufsize); 549 550 mtd->_panic_write = cfi_amdstd_panic_write; 551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot; 552 553 if (cfi->cfi_mode==CFI_MODE_CFI){ 554 unsigned char bootloc; 555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; 556 struct cfi_pri_amdstd *extp; 557 558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); 559 if (extp) { 560 /* 561 * It's a real CFI chip, not one for which the probe 562 * routine faked a CFI structure. 563 */ 564 cfi_fixup_major_minor(cfi, extp); 565 566 /* 567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5 568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19 569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf 570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf 571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf 572 */ 573 if (extp->MajorVersion != '1' || 574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) { 575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " 576 "version %c.%c (%#02x/%#02x).\n", 577 extp->MajorVersion, extp->MinorVersion, 578 extp->MajorVersion, extp->MinorVersion); 579 kfree(extp); 580 kfree(mtd); 581 return NULL; 582 } 583 584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n", 585 extp->MajorVersion, extp->MinorVersion); 586 587 /* Install our own private info structure */ 588 cfi->cmdset_priv = extp; 589 590 /* Apply cfi device specific fixups */ 591 cfi_fixup(mtd, cfi_fixup_table); 592 593 #ifdef DEBUG_CFI_FEATURES 594 /* Tell the user about it in lots of lovely detail */ 595 cfi_tell_features(extp); 596 #endif 597 598 #ifdef CONFIG_OF 599 if (np && of_property_read_bool( 600 np, "use-advanced-sector-protection") 601 && extp->BlkProtUnprot == 8) { 602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n"); 603 mtd->_lock = cfi_ppb_lock; 604 mtd->_unlock = cfi_ppb_unlock; 605 mtd->_is_locked = cfi_ppb_is_locked; 606 } 607 #endif 608 609 bootloc = extp->TopBottom; 610 if ((bootloc < 2) || (bootloc > 5)) { 611 printk(KERN_WARNING "%s: CFI contains unrecognised boot " 612 "bank location (%d). Assuming bottom.\n", 613 map->name, bootloc); 614 bootloc = 2; 615 } 616 617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { 618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name); 619 620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { 621 int j = (cfi->cfiq->NumEraseRegions-1)-i; 622 623 swap(cfi->cfiq->EraseRegionInfo[i], 624 cfi->cfiq->EraseRegionInfo[j]); 625 } 626 } 627 /* Set the default CFI lock/unlock addresses */ 628 cfi->addr_unlock1 = 0x555; 629 cfi->addr_unlock2 = 0x2aa; 630 } 631 cfi_fixup(mtd, cfi_nopri_fixup_table); 632 633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) { 634 kfree(mtd); 635 return NULL; 636 } 637 638 } /* CFI mode */ 639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) { 640 /* Apply jedec specific fixups */ 641 cfi_fixup(mtd, jedec_fixup_table); 642 } 643 /* Apply generic fixups */ 644 cfi_fixup(mtd, fixup_table); 645 646 for (i=0; i< cfi->numchips; i++) { 647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; 648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; 649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; 650 /* 651 * First calculate the timeout max according to timeout field 652 * of struct cfi_ident that probed from chip's CFI aera, if 653 * available. Specify a minimum of 2000us, in case the CFI data 654 * is wrong. 655 */ 656 if (cfi->cfiq->BufWriteTimeoutTyp && 657 cfi->cfiq->BufWriteTimeoutMax) 658 cfi->chips[i].buffer_write_time_max = 659 1 << (cfi->cfiq->BufWriteTimeoutTyp + 660 cfi->cfiq->BufWriteTimeoutMax); 661 else 662 cfi->chips[i].buffer_write_time_max = 0; 663 664 cfi->chips[i].buffer_write_time_max = 665 max(cfi->chips[i].buffer_write_time_max, 2000); 666 667 cfi->chips[i].ref_point_counter = 0; 668 init_waitqueue_head(&(cfi->chips[i].wq)); 669 } 670 671 map->fldrv = &cfi_amdstd_chipdrv; 672 673 return cfi_amdstd_setup(mtd); 674 } 675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002); 678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006); 679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701); 680 681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) 682 { 683 struct map_info *map = mtd->priv; 684 struct cfi_private *cfi = map->fldrv_priv; 685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; 686 unsigned long offset = 0; 687 int i,j; 688 689 printk(KERN_NOTICE "number of %s chips: %d\n", 690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); 691 /* Select the correct geometry setup */ 692 mtd->size = devsize * cfi->numchips; 693 694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; 695 mtd->eraseregions = kmalloc_array(mtd->numeraseregions, 696 sizeof(struct mtd_erase_region_info), 697 GFP_KERNEL); 698 if (!mtd->eraseregions) 699 goto setup_err; 700 701 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { 702 unsigned long ernum, ersize; 703 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; 704 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; 705 706 if (mtd->erasesize < ersize) { 707 mtd->erasesize = ersize; 708 } 709 for (j=0; j<cfi->numchips; j++) { 710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; 711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; 712 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; 713 } 714 offset += (ersize * ernum); 715 } 716 if (offset != devsize) { 717 /* Argh */ 718 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); 719 goto setup_err; 720 } 721 722 __module_get(THIS_MODULE); 723 register_reboot_notifier(&mtd->reboot_notifier); 724 return mtd; 725 726 setup_err: 727 kfree(mtd->eraseregions); 728 kfree(mtd); 729 kfree(cfi->cmdset_priv); 730 kfree(cfi->cfiq); 731 return NULL; 732 } 733 734 /* 735 * Return true if the chip is ready. 736 * 737 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 738 * non-suspended sector) and is indicated by no toggle bits toggling. 739 * 740 * Note that anything more complicated than checking if no bits are toggling 741 * (including checking DQ5 for an error status) is tricky to get working 742 * correctly and is therefore not done (particularly with interleaved chips 743 * as each chip must be checked independently of the others). 744 */ 745 static int __xipram chip_ready(struct map_info *map, unsigned long addr) 746 { 747 map_word d, t; 748 749 d = map_read(map, addr); 750 t = map_read(map, addr); 751 752 return map_word_equal(map, d, t); 753 } 754 755 /* 756 * Return true if the chip is ready and has the correct value. 757 * 758 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 759 * non-suspended sector) and it is indicated by no bits toggling. 760 * 761 * Error are indicated by toggling bits or bits held with the wrong value, 762 * or with bits toggling. 763 * 764 * Note that anything more complicated than checking if no bits are toggling 765 * (including checking DQ5 for an error status) is tricky to get working 766 * correctly and is therefore not done (particularly with interleaved chips 767 * as each chip must be checked independently of the others). 768 * 769 */ 770 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) 771 { 772 map_word oldd, curd; 773 774 oldd = map_read(map, addr); 775 curd = map_read(map, addr); 776 777 return map_word_equal(map, oldd, curd) && 778 map_word_equal(map, curd, expected); 779 } 780 781 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) 782 { 783 DECLARE_WAITQUEUE(wait, current); 784 struct cfi_private *cfi = map->fldrv_priv; 785 unsigned long timeo; 786 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; 787 788 resettime: 789 timeo = jiffies + HZ; 790 retry: 791 switch (chip->state) { 792 793 case FL_STATUS: 794 for (;;) { 795 if (chip_ready(map, adr)) 796 break; 797 798 if (time_after(jiffies, timeo)) { 799 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 800 return -EIO; 801 } 802 mutex_unlock(&chip->mutex); 803 cfi_udelay(1); 804 mutex_lock(&chip->mutex); 805 /* Someone else might have been playing with it. */ 806 goto retry; 807 } 808 809 case FL_READY: 810 case FL_CFI_QUERY: 811 case FL_JEDEC_QUERY: 812 return 0; 813 814 case FL_ERASING: 815 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || 816 !(mode == FL_READY || mode == FL_POINT || 817 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) 818 goto sleep; 819 820 /* Do not allow suspend iff read/write to EB address */ 821 if ((adr & chip->in_progress_block_mask) == 822 chip->in_progress_block_addr) 823 goto sleep; 824 825 /* Erase suspend */ 826 /* It's harmless to issue the Erase-Suspend and Erase-Resume 827 * commands when the erase algorithm isn't in progress. */ 828 map_write(map, CMD(0xB0), chip->in_progress_block_addr); 829 chip->oldstate = FL_ERASING; 830 chip->state = FL_ERASE_SUSPENDING; 831 chip->erase_suspended = 1; 832 for (;;) { 833 if (chip_ready(map, adr)) 834 break; 835 836 if (time_after(jiffies, timeo)) { 837 /* Should have suspended the erase by now. 838 * Send an Erase-Resume command as either 839 * there was an error (so leave the erase 840 * routine to recover from it) or we trying to 841 * use the erase-in-progress sector. */ 842 put_chip(map, chip, adr); 843 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); 844 return -EIO; 845 } 846 847 mutex_unlock(&chip->mutex); 848 cfi_udelay(1); 849 mutex_lock(&chip->mutex); 850 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. 851 So we can just loop here. */ 852 } 853 chip->state = FL_READY; 854 return 0; 855 856 case FL_XIP_WHILE_ERASING: 857 if (mode != FL_READY && mode != FL_POINT && 858 (!cfip || !(cfip->EraseSuspend&2))) 859 goto sleep; 860 chip->oldstate = chip->state; 861 chip->state = FL_READY; 862 return 0; 863 864 case FL_SHUTDOWN: 865 /* The machine is rebooting */ 866 return -EIO; 867 868 case FL_POINT: 869 /* Only if there's no operation suspended... */ 870 if (mode == FL_READY && chip->oldstate == FL_READY) 871 return 0; 872 873 default: 874 sleep: 875 set_current_state(TASK_UNINTERRUPTIBLE); 876 add_wait_queue(&chip->wq, &wait); 877 mutex_unlock(&chip->mutex); 878 schedule(); 879 remove_wait_queue(&chip->wq, &wait); 880 mutex_lock(&chip->mutex); 881 goto resettime; 882 } 883 } 884 885 886 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) 887 { 888 struct cfi_private *cfi = map->fldrv_priv; 889 890 switch(chip->oldstate) { 891 case FL_ERASING: 892 cfi_fixup_m29ew_erase_suspend(map, 893 chip->in_progress_block_addr); 894 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr); 895 cfi_fixup_m29ew_delay_after_resume(cfi); 896 chip->oldstate = FL_READY; 897 chip->state = FL_ERASING; 898 break; 899 900 case FL_XIP_WHILE_ERASING: 901 chip->state = chip->oldstate; 902 chip->oldstate = FL_READY; 903 break; 904 905 case FL_READY: 906 case FL_STATUS: 907 break; 908 default: 909 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); 910 } 911 wake_up(&chip->wq); 912 } 913 914 #ifdef CONFIG_MTD_XIP 915 916 /* 917 * No interrupt what so ever can be serviced while the flash isn't in array 918 * mode. This is ensured by the xip_disable() and xip_enable() functions 919 * enclosing any code path where the flash is known not to be in array mode. 920 * And within a XIP disabled code path, only functions marked with __xipram 921 * may be called and nothing else (it's a good thing to inspect generated 922 * assembly to make sure inline functions were actually inlined and that gcc 923 * didn't emit calls to its own support functions). Also configuring MTD CFI 924 * support to a single buswidth and a single interleave is also recommended. 925 */ 926 927 static void xip_disable(struct map_info *map, struct flchip *chip, 928 unsigned long adr) 929 { 930 /* TODO: chips with no XIP use should ignore and return */ 931 (void) map_read(map, adr); /* ensure mmu mapping is up to date */ 932 local_irq_disable(); 933 } 934 935 static void __xipram xip_enable(struct map_info *map, struct flchip *chip, 936 unsigned long adr) 937 { 938 struct cfi_private *cfi = map->fldrv_priv; 939 940 if (chip->state != FL_POINT && chip->state != FL_READY) { 941 map_write(map, CMD(0xf0), adr); 942 chip->state = FL_READY; 943 } 944 (void) map_read(map, adr); 945 xip_iprefetch(); 946 local_irq_enable(); 947 } 948 949 /* 950 * When a delay is required for the flash operation to complete, the 951 * xip_udelay() function is polling for both the given timeout and pending 952 * (but still masked) hardware interrupts. Whenever there is an interrupt 953 * pending then the flash erase operation is suspended, array mode restored 954 * and interrupts unmasked. Task scheduling might also happen at that 955 * point. The CPU eventually returns from the interrupt or the call to 956 * schedule() and the suspended flash operation is resumed for the remaining 957 * of the delay period. 958 * 959 * Warning: this function _will_ fool interrupt latency tracing tools. 960 */ 961 962 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, 963 unsigned long adr, int usec) 964 { 965 struct cfi_private *cfi = map->fldrv_priv; 966 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 967 map_word status, OK = CMD(0x80); 968 unsigned long suspended, start = xip_currtime(); 969 flstate_t oldstate; 970 971 do { 972 cpu_relax(); 973 if (xip_irqpending() && extp && 974 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && 975 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { 976 /* 977 * Let's suspend the erase operation when supported. 978 * Note that we currently don't try to suspend 979 * interleaved chips if there is already another 980 * operation suspended (imagine what happens 981 * when one chip was already done with the current 982 * operation while another chip suspended it, then 983 * we resume the whole thing at once). Yes, it 984 * can happen! 985 */ 986 map_write(map, CMD(0xb0), adr); 987 usec -= xip_elapsed_since(start); 988 suspended = xip_currtime(); 989 do { 990 if (xip_elapsed_since(suspended) > 100000) { 991 /* 992 * The chip doesn't want to suspend 993 * after waiting for 100 msecs. 994 * This is a critical error but there 995 * is not much we can do here. 996 */ 997 return; 998 } 999 status = map_read(map, adr); 1000 } while (!map_word_andequal(map, status, OK, OK)); 1001 1002 /* Suspend succeeded */ 1003 oldstate = chip->state; 1004 if (!map_word_bitsset(map, status, CMD(0x40))) 1005 break; 1006 chip->state = FL_XIP_WHILE_ERASING; 1007 chip->erase_suspended = 1; 1008 map_write(map, CMD(0xf0), adr); 1009 (void) map_read(map, adr); 1010 xip_iprefetch(); 1011 local_irq_enable(); 1012 mutex_unlock(&chip->mutex); 1013 xip_iprefetch(); 1014 cond_resched(); 1015 1016 /* 1017 * We're back. However someone else might have 1018 * decided to go write to the chip if we are in 1019 * a suspended erase state. If so let's wait 1020 * until it's done. 1021 */ 1022 mutex_lock(&chip->mutex); 1023 while (chip->state != FL_XIP_WHILE_ERASING) { 1024 DECLARE_WAITQUEUE(wait, current); 1025 set_current_state(TASK_UNINTERRUPTIBLE); 1026 add_wait_queue(&chip->wq, &wait); 1027 mutex_unlock(&chip->mutex); 1028 schedule(); 1029 remove_wait_queue(&chip->wq, &wait); 1030 mutex_lock(&chip->mutex); 1031 } 1032 /* Disallow XIP again */ 1033 local_irq_disable(); 1034 1035 /* Correct Erase Suspend Hangups for M29EW */ 1036 cfi_fixup_m29ew_erase_suspend(map, adr); 1037 /* Resume the write or erase operation */ 1038 map_write(map, cfi->sector_erase_cmd, adr); 1039 chip->state = oldstate; 1040 start = xip_currtime(); 1041 } else if (usec >= 1000000/HZ) { 1042 /* 1043 * Try to save on CPU power when waiting delay 1044 * is at least a system timer tick period. 1045 * No need to be extremely accurate here. 1046 */ 1047 xip_cpu_idle(); 1048 } 1049 status = map_read(map, adr); 1050 } while (!map_word_andequal(map, status, OK, OK) 1051 && xip_elapsed_since(start) < usec); 1052 } 1053 1054 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) 1055 1056 /* 1057 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while 1058 * the flash is actively programming or erasing since we have to poll for 1059 * the operation to complete anyway. We can't do that in a generic way with 1060 * a XIP setup so do it before the actual flash operation in this case 1061 * and stub it out from INVALIDATE_CACHE_UDELAY. 1062 */ 1063 #define XIP_INVAL_CACHED_RANGE(map, from, size) \ 1064 INVALIDATE_CACHED_RANGE(map, from, size) 1065 1066 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1067 UDELAY(map, chip, adr, usec) 1068 1069 /* 1070 * Extra notes: 1071 * 1072 * Activating this XIP support changes the way the code works a bit. For 1073 * example the code to suspend the current process when concurrent access 1074 * happens is never executed because xip_udelay() will always return with the 1075 * same chip state as it was entered with. This is why there is no care for 1076 * the presence of add_wait_queue() or schedule() calls from within a couple 1077 * xip_disable()'d areas of code, like in do_erase_oneblock for example. 1078 * The queueing and scheduling are always happening within xip_udelay(). 1079 * 1080 * Similarly, get_chip() and put_chip() just happen to always be executed 1081 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state 1082 * is in array mode, therefore never executing many cases therein and not 1083 * causing any problem with XIP. 1084 */ 1085 1086 #else 1087 1088 #define xip_disable(map, chip, adr) 1089 #define xip_enable(map, chip, adr) 1090 #define XIP_INVAL_CACHED_RANGE(x...) 1091 1092 #define UDELAY(map, chip, adr, usec) \ 1093 do { \ 1094 mutex_unlock(&chip->mutex); \ 1095 cfi_udelay(usec); \ 1096 mutex_lock(&chip->mutex); \ 1097 } while (0) 1098 1099 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1100 do { \ 1101 mutex_unlock(&chip->mutex); \ 1102 INVALIDATE_CACHED_RANGE(map, adr, len); \ 1103 cfi_udelay(usec); \ 1104 mutex_lock(&chip->mutex); \ 1105 } while (0) 1106 1107 #endif 1108 1109 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) 1110 { 1111 unsigned long cmd_addr; 1112 struct cfi_private *cfi = map->fldrv_priv; 1113 int ret; 1114 1115 adr += chip->start; 1116 1117 /* Ensure cmd read/writes are aligned. */ 1118 cmd_addr = adr & ~(map_bankwidth(map)-1); 1119 1120 mutex_lock(&chip->mutex); 1121 ret = get_chip(map, chip, cmd_addr, FL_READY); 1122 if (ret) { 1123 mutex_unlock(&chip->mutex); 1124 return ret; 1125 } 1126 1127 if (chip->state != FL_POINT && chip->state != FL_READY) { 1128 map_write(map, CMD(0xf0), cmd_addr); 1129 chip->state = FL_READY; 1130 } 1131 1132 map_copy_from(map, buf, adr, len); 1133 1134 put_chip(map, chip, cmd_addr); 1135 1136 mutex_unlock(&chip->mutex); 1137 return 0; 1138 } 1139 1140 1141 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1142 { 1143 struct map_info *map = mtd->priv; 1144 struct cfi_private *cfi = map->fldrv_priv; 1145 unsigned long ofs; 1146 int chipnum; 1147 int ret = 0; 1148 1149 /* ofs: offset within the first chip that the first read should start */ 1150 chipnum = (from >> cfi->chipshift); 1151 ofs = from - (chipnum << cfi->chipshift); 1152 1153 while (len) { 1154 unsigned long thislen; 1155 1156 if (chipnum >= cfi->numchips) 1157 break; 1158 1159 if ((len + ofs -1) >> cfi->chipshift) 1160 thislen = (1<<cfi->chipshift) - ofs; 1161 else 1162 thislen = len; 1163 1164 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); 1165 if (ret) 1166 break; 1167 1168 *retlen += thislen; 1169 len -= thislen; 1170 buf += thislen; 1171 1172 ofs = 0; 1173 chipnum++; 1174 } 1175 return ret; 1176 } 1177 1178 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip, 1179 loff_t adr, size_t len, u_char *buf, size_t grouplen); 1180 1181 static inline void otp_enter(struct map_info *map, struct flchip *chip, 1182 loff_t adr, size_t len) 1183 { 1184 struct cfi_private *cfi = map->fldrv_priv; 1185 1186 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1187 cfi->device_type, NULL); 1188 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1189 cfi->device_type, NULL); 1190 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, 1191 cfi->device_type, NULL); 1192 1193 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1194 } 1195 1196 static inline void otp_exit(struct map_info *map, struct flchip *chip, 1197 loff_t adr, size_t len) 1198 { 1199 struct cfi_private *cfi = map->fldrv_priv; 1200 1201 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1202 cfi->device_type, NULL); 1203 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1204 cfi->device_type, NULL); 1205 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, 1206 cfi->device_type, NULL); 1207 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, 1208 cfi->device_type, NULL); 1209 1210 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1211 } 1212 1213 static inline int do_read_secsi_onechip(struct map_info *map, 1214 struct flchip *chip, loff_t adr, 1215 size_t len, u_char *buf, 1216 size_t grouplen) 1217 { 1218 DECLARE_WAITQUEUE(wait, current); 1219 1220 retry: 1221 mutex_lock(&chip->mutex); 1222 1223 if (chip->state != FL_READY){ 1224 set_current_state(TASK_UNINTERRUPTIBLE); 1225 add_wait_queue(&chip->wq, &wait); 1226 1227 mutex_unlock(&chip->mutex); 1228 1229 schedule(); 1230 remove_wait_queue(&chip->wq, &wait); 1231 1232 goto retry; 1233 } 1234 1235 adr += chip->start; 1236 1237 chip->state = FL_READY; 1238 1239 otp_enter(map, chip, adr, len); 1240 map_copy_from(map, buf, adr, len); 1241 otp_exit(map, chip, adr, len); 1242 1243 wake_up(&chip->wq); 1244 mutex_unlock(&chip->mutex); 1245 1246 return 0; 1247 } 1248 1249 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1250 { 1251 struct map_info *map = mtd->priv; 1252 struct cfi_private *cfi = map->fldrv_priv; 1253 unsigned long ofs; 1254 int chipnum; 1255 int ret = 0; 1256 1257 /* ofs: offset within the first chip that the first read should start */ 1258 /* 8 secsi bytes per chip */ 1259 chipnum=from>>3; 1260 ofs=from & 7; 1261 1262 while (len) { 1263 unsigned long thislen; 1264 1265 if (chipnum >= cfi->numchips) 1266 break; 1267 1268 if ((len + ofs -1) >> 3) 1269 thislen = (1<<3) - ofs; 1270 else 1271 thislen = len; 1272 1273 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, 1274 thislen, buf, 0); 1275 if (ret) 1276 break; 1277 1278 *retlen += thislen; 1279 len -= thislen; 1280 buf += thislen; 1281 1282 ofs = 0; 1283 chipnum++; 1284 } 1285 return ret; 1286 } 1287 1288 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1289 unsigned long adr, map_word datum, 1290 int mode); 1291 1292 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr, 1293 size_t len, u_char *buf, size_t grouplen) 1294 { 1295 int ret; 1296 while (len) { 1297 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1); 1298 int gap = adr - bus_ofs; 1299 int n = min_t(int, len, map_bankwidth(map) - gap); 1300 map_word datum = map_word_ff(map); 1301 1302 if (n != map_bankwidth(map)) { 1303 /* partial write of a word, load old contents */ 1304 otp_enter(map, chip, bus_ofs, map_bankwidth(map)); 1305 datum = map_read(map, bus_ofs); 1306 otp_exit(map, chip, bus_ofs, map_bankwidth(map)); 1307 } 1308 1309 datum = map_word_load_partial(map, datum, buf, gap, n); 1310 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE); 1311 if (ret) 1312 return ret; 1313 1314 adr += n; 1315 buf += n; 1316 len -= n; 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr, 1323 size_t len, u_char *buf, size_t grouplen) 1324 { 1325 struct cfi_private *cfi = map->fldrv_priv; 1326 uint8_t lockreg; 1327 unsigned long timeo; 1328 int ret; 1329 1330 /* make sure area matches group boundaries */ 1331 if ((adr != 0) || (len != grouplen)) 1332 return -EINVAL; 1333 1334 mutex_lock(&chip->mutex); 1335 ret = get_chip(map, chip, chip->start, FL_LOCKING); 1336 if (ret) { 1337 mutex_unlock(&chip->mutex); 1338 return ret; 1339 } 1340 chip->state = FL_LOCKING; 1341 1342 /* Enter lock register command */ 1343 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1344 cfi->device_type, NULL); 1345 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1346 cfi->device_type, NULL); 1347 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi, 1348 cfi->device_type, NULL); 1349 1350 /* read lock register */ 1351 lockreg = cfi_read_query(map, 0); 1352 1353 /* set bit 0 to protect extended memory block */ 1354 lockreg &= ~0x01; 1355 1356 /* set bit 0 to protect extended memory block */ 1357 /* write lock register */ 1358 map_write(map, CMD(0xA0), chip->start); 1359 map_write(map, CMD(lockreg), chip->start); 1360 1361 /* wait for chip to become ready */ 1362 timeo = jiffies + msecs_to_jiffies(2); 1363 for (;;) { 1364 if (chip_ready(map, adr)) 1365 break; 1366 1367 if (time_after(jiffies, timeo)) { 1368 pr_err("Waiting for chip to be ready timed out.\n"); 1369 ret = -EIO; 1370 break; 1371 } 1372 UDELAY(map, chip, 0, 1); 1373 } 1374 1375 /* exit protection commands */ 1376 map_write(map, CMD(0x90), chip->start); 1377 map_write(map, CMD(0x00), chip->start); 1378 1379 chip->state = FL_READY; 1380 put_chip(map, chip, chip->start); 1381 mutex_unlock(&chip->mutex); 1382 1383 return ret; 1384 } 1385 1386 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, 1387 size_t *retlen, u_char *buf, 1388 otp_op_t action, int user_regs) 1389 { 1390 struct map_info *map = mtd->priv; 1391 struct cfi_private *cfi = map->fldrv_priv; 1392 int ofs_factor = cfi->interleave * cfi->device_type; 1393 unsigned long base; 1394 int chipnum; 1395 struct flchip *chip; 1396 uint8_t otp, lockreg; 1397 int ret; 1398 1399 size_t user_size, factory_size, otpsize; 1400 loff_t user_offset, factory_offset, otpoffset; 1401 int user_locked = 0, otplocked; 1402 1403 *retlen = 0; 1404 1405 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) { 1406 chip = &cfi->chips[chipnum]; 1407 factory_size = 0; 1408 user_size = 0; 1409 1410 /* Micron M29EW family */ 1411 if (is_m29ew(cfi)) { 1412 base = chip->start; 1413 1414 /* check whether secsi area is factory locked 1415 or user lockable */ 1416 mutex_lock(&chip->mutex); 1417 ret = get_chip(map, chip, base, FL_CFI_QUERY); 1418 if (ret) { 1419 mutex_unlock(&chip->mutex); 1420 return ret; 1421 } 1422 cfi_qry_mode_on(base, map, cfi); 1423 otp = cfi_read_query(map, base + 0x3 * ofs_factor); 1424 cfi_qry_mode_off(base, map, cfi); 1425 put_chip(map, chip, base); 1426 mutex_unlock(&chip->mutex); 1427 1428 if (otp & 0x80) { 1429 /* factory locked */ 1430 factory_offset = 0; 1431 factory_size = 0x100; 1432 } else { 1433 /* customer lockable */ 1434 user_offset = 0; 1435 user_size = 0x100; 1436 1437 mutex_lock(&chip->mutex); 1438 ret = get_chip(map, chip, base, FL_LOCKING); 1439 if (ret) { 1440 mutex_unlock(&chip->mutex); 1441 return ret; 1442 } 1443 1444 /* Enter lock register command */ 1445 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, 1446 chip->start, map, cfi, 1447 cfi->device_type, NULL); 1448 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, 1449 chip->start, map, cfi, 1450 cfi->device_type, NULL); 1451 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, 1452 chip->start, map, cfi, 1453 cfi->device_type, NULL); 1454 /* read lock register */ 1455 lockreg = cfi_read_query(map, 0); 1456 /* exit protection commands */ 1457 map_write(map, CMD(0x90), chip->start); 1458 map_write(map, CMD(0x00), chip->start); 1459 put_chip(map, chip, chip->start); 1460 mutex_unlock(&chip->mutex); 1461 1462 user_locked = ((lockreg & 0x01) == 0x00); 1463 } 1464 } 1465 1466 otpsize = user_regs ? user_size : factory_size; 1467 if (!otpsize) 1468 continue; 1469 otpoffset = user_regs ? user_offset : factory_offset; 1470 otplocked = user_regs ? user_locked : 1; 1471 1472 if (!action) { 1473 /* return otpinfo */ 1474 struct otp_info *otpinfo; 1475 len -= sizeof(*otpinfo); 1476 if (len <= 0) 1477 return -ENOSPC; 1478 otpinfo = (struct otp_info *)buf; 1479 otpinfo->start = from; 1480 otpinfo->length = otpsize; 1481 otpinfo->locked = otplocked; 1482 buf += sizeof(*otpinfo); 1483 *retlen += sizeof(*otpinfo); 1484 from += otpsize; 1485 } else if ((from < otpsize) && (len > 0)) { 1486 size_t size; 1487 size = (len < otpsize - from) ? len : otpsize - from; 1488 ret = action(map, chip, otpoffset + from, size, buf, 1489 otpsize); 1490 if (ret < 0) 1491 return ret; 1492 1493 buf += size; 1494 len -= size; 1495 *retlen += size; 1496 from = 0; 1497 } else { 1498 from -= otpsize; 1499 } 1500 } 1501 return 0; 1502 } 1503 1504 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len, 1505 size_t *retlen, struct otp_info *buf) 1506 { 1507 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1508 NULL, 0); 1509 } 1510 1511 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len, 1512 size_t *retlen, struct otp_info *buf) 1513 { 1514 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1515 NULL, 1); 1516 } 1517 1518 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, 1519 size_t len, size_t *retlen, 1520 u_char *buf) 1521 { 1522 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1523 buf, do_read_secsi_onechip, 0); 1524 } 1525 1526 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, 1527 size_t len, size_t *retlen, 1528 u_char *buf) 1529 { 1530 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1531 buf, do_read_secsi_onechip, 1); 1532 } 1533 1534 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from, 1535 size_t len, size_t *retlen, 1536 u_char *buf) 1537 { 1538 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf, 1539 do_otp_write, 1); 1540 } 1541 1542 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, 1543 size_t len) 1544 { 1545 size_t retlen; 1546 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL, 1547 do_otp_lock, 1); 1548 } 1549 1550 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1551 unsigned long adr, map_word datum, 1552 int mode) 1553 { 1554 struct cfi_private *cfi = map->fldrv_priv; 1555 unsigned long timeo = jiffies + HZ; 1556 /* 1557 * We use a 1ms + 1 jiffies generic timeout for writes (most devices 1558 * have a max write time of a few hundreds usec). However, we should 1559 * use the maximum timeout value given by the chip at probe time 1560 * instead. Unfortunately, struct flchip does have a field for 1561 * maximum timeout, only for typical which can be far too short 1562 * depending of the conditions. The ' + 1' is to avoid having a 1563 * timeout of 0 jiffies if HZ is smaller than 1000. 1564 */ 1565 unsigned long uWriteTimeout = (HZ / 1000) + 1; 1566 int ret = 0; 1567 map_word oldd; 1568 int retry_cnt = 0; 1569 1570 adr += chip->start; 1571 1572 mutex_lock(&chip->mutex); 1573 ret = get_chip(map, chip, adr, mode); 1574 if (ret) { 1575 mutex_unlock(&chip->mutex); 1576 return ret; 1577 } 1578 1579 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1580 __func__, adr, datum.x[0]); 1581 1582 if (mode == FL_OTP_WRITE) 1583 otp_enter(map, chip, adr, map_bankwidth(map)); 1584 1585 /* 1586 * Check for a NOP for the case when the datum to write is already 1587 * present - it saves time and works around buggy chips that corrupt 1588 * data at other locations when 0xff is written to a location that 1589 * already contains 0xff. 1590 */ 1591 oldd = map_read(map, adr); 1592 if (map_word_equal(map, oldd, datum)) { 1593 pr_debug("MTD %s(): NOP\n", 1594 __func__); 1595 goto op_done; 1596 } 1597 1598 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); 1599 ENABLE_VPP(map); 1600 xip_disable(map, chip, adr); 1601 1602 retry: 1603 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1604 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1605 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1606 map_write(map, datum, adr); 1607 chip->state = mode; 1608 1609 INVALIDATE_CACHE_UDELAY(map, chip, 1610 adr, map_bankwidth(map), 1611 chip->word_write_time); 1612 1613 /* See comment above for timeout value. */ 1614 timeo = jiffies + uWriteTimeout; 1615 for (;;) { 1616 if (chip->state != mode) { 1617 /* Someone's suspended the write. Sleep */ 1618 DECLARE_WAITQUEUE(wait, current); 1619 1620 set_current_state(TASK_UNINTERRUPTIBLE); 1621 add_wait_queue(&chip->wq, &wait); 1622 mutex_unlock(&chip->mutex); 1623 schedule(); 1624 remove_wait_queue(&chip->wq, &wait); 1625 timeo = jiffies + (HZ / 2); /* FIXME */ 1626 mutex_lock(&chip->mutex); 1627 continue; 1628 } 1629 1630 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ 1631 xip_enable(map, chip, adr); 1632 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); 1633 xip_disable(map, chip, adr); 1634 break; 1635 } 1636 1637 if (chip_ready(map, adr)) 1638 break; 1639 1640 /* Latency issues. Drop the lock, wait a while and retry */ 1641 UDELAY(map, chip, adr, 1); 1642 } 1643 /* Did we succeed? */ 1644 if (!chip_good(map, adr, datum)) { 1645 /* reset on all failures. */ 1646 map_write(map, CMD(0xF0), chip->start); 1647 /* FIXME - should have reset delay before continuing */ 1648 1649 if (++retry_cnt <= MAX_RETRIES) 1650 goto retry; 1651 1652 ret = -EIO; 1653 } 1654 xip_enable(map, chip, adr); 1655 op_done: 1656 if (mode == FL_OTP_WRITE) 1657 otp_exit(map, chip, adr, map_bankwidth(map)); 1658 chip->state = FL_READY; 1659 DISABLE_VPP(map); 1660 put_chip(map, chip, adr); 1661 mutex_unlock(&chip->mutex); 1662 1663 return ret; 1664 } 1665 1666 1667 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, 1668 size_t *retlen, const u_char *buf) 1669 { 1670 struct map_info *map = mtd->priv; 1671 struct cfi_private *cfi = map->fldrv_priv; 1672 int ret = 0; 1673 int chipnum; 1674 unsigned long ofs, chipstart; 1675 DECLARE_WAITQUEUE(wait, current); 1676 1677 chipnum = to >> cfi->chipshift; 1678 ofs = to - (chipnum << cfi->chipshift); 1679 chipstart = cfi->chips[chipnum].start; 1680 1681 /* If it's not bus-aligned, do the first byte write */ 1682 if (ofs & (map_bankwidth(map)-1)) { 1683 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); 1684 int i = ofs - bus_ofs; 1685 int n = 0; 1686 map_word tmp_buf; 1687 1688 retry: 1689 mutex_lock(&cfi->chips[chipnum].mutex); 1690 1691 if (cfi->chips[chipnum].state != FL_READY) { 1692 set_current_state(TASK_UNINTERRUPTIBLE); 1693 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1694 1695 mutex_unlock(&cfi->chips[chipnum].mutex); 1696 1697 schedule(); 1698 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1699 goto retry; 1700 } 1701 1702 /* Load 'tmp_buf' with old contents of flash */ 1703 tmp_buf = map_read(map, bus_ofs+chipstart); 1704 1705 mutex_unlock(&cfi->chips[chipnum].mutex); 1706 1707 /* Number of bytes to copy from buffer */ 1708 n = min_t(int, len, map_bankwidth(map)-i); 1709 1710 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 1711 1712 ret = do_write_oneword(map, &cfi->chips[chipnum], 1713 bus_ofs, tmp_buf, FL_WRITING); 1714 if (ret) 1715 return ret; 1716 1717 ofs += n; 1718 buf += n; 1719 (*retlen) += n; 1720 len -= n; 1721 1722 if (ofs >> cfi->chipshift) { 1723 chipnum ++; 1724 ofs = 0; 1725 if (chipnum == cfi->numchips) 1726 return 0; 1727 } 1728 } 1729 1730 /* We are now aligned, write as much as possible */ 1731 while(len >= map_bankwidth(map)) { 1732 map_word datum; 1733 1734 datum = map_word_load(map, buf); 1735 1736 ret = do_write_oneword(map, &cfi->chips[chipnum], 1737 ofs, datum, FL_WRITING); 1738 if (ret) 1739 return ret; 1740 1741 ofs += map_bankwidth(map); 1742 buf += map_bankwidth(map); 1743 (*retlen) += map_bankwidth(map); 1744 len -= map_bankwidth(map); 1745 1746 if (ofs >> cfi->chipshift) { 1747 chipnum ++; 1748 ofs = 0; 1749 if (chipnum == cfi->numchips) 1750 return 0; 1751 chipstart = cfi->chips[chipnum].start; 1752 } 1753 } 1754 1755 /* Write the trailing bytes if any */ 1756 if (len & (map_bankwidth(map)-1)) { 1757 map_word tmp_buf; 1758 1759 retry1: 1760 mutex_lock(&cfi->chips[chipnum].mutex); 1761 1762 if (cfi->chips[chipnum].state != FL_READY) { 1763 set_current_state(TASK_UNINTERRUPTIBLE); 1764 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1765 1766 mutex_unlock(&cfi->chips[chipnum].mutex); 1767 1768 schedule(); 1769 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1770 goto retry1; 1771 } 1772 1773 tmp_buf = map_read(map, ofs + chipstart); 1774 1775 mutex_unlock(&cfi->chips[chipnum].mutex); 1776 1777 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 1778 1779 ret = do_write_oneword(map, &cfi->chips[chipnum], 1780 ofs, tmp_buf, FL_WRITING); 1781 if (ret) 1782 return ret; 1783 1784 (*retlen) += len; 1785 } 1786 1787 return 0; 1788 } 1789 1790 1791 /* 1792 * FIXME: interleaved mode not tested, and probably not supported! 1793 */ 1794 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, 1795 unsigned long adr, const u_char *buf, 1796 int len) 1797 { 1798 struct cfi_private *cfi = map->fldrv_priv; 1799 unsigned long timeo = jiffies + HZ; 1800 /* 1801 * Timeout is calculated according to CFI data, if available. 1802 * See more comments in cfi_cmdset_0002(). 1803 */ 1804 unsigned long uWriteTimeout = 1805 usecs_to_jiffies(chip->buffer_write_time_max); 1806 int ret = -EIO; 1807 unsigned long cmd_adr; 1808 int z, words; 1809 map_word datum; 1810 1811 adr += chip->start; 1812 cmd_adr = adr; 1813 1814 mutex_lock(&chip->mutex); 1815 ret = get_chip(map, chip, adr, FL_WRITING); 1816 if (ret) { 1817 mutex_unlock(&chip->mutex); 1818 return ret; 1819 } 1820 1821 datum = map_word_load(map, buf); 1822 1823 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1824 __func__, adr, datum.x[0]); 1825 1826 XIP_INVAL_CACHED_RANGE(map, adr, len); 1827 ENABLE_VPP(map); 1828 xip_disable(map, chip, cmd_adr); 1829 1830 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1831 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1832 1833 /* Write Buffer Load */ 1834 map_write(map, CMD(0x25), cmd_adr); 1835 1836 chip->state = FL_WRITING_TO_BUFFER; 1837 1838 /* Write length of data to come */ 1839 words = len / map_bankwidth(map); 1840 map_write(map, CMD(words - 1), cmd_adr); 1841 /* Write data */ 1842 z = 0; 1843 while(z < words * map_bankwidth(map)) { 1844 datum = map_word_load(map, buf); 1845 map_write(map, datum, adr + z); 1846 1847 z += map_bankwidth(map); 1848 buf += map_bankwidth(map); 1849 } 1850 z -= map_bankwidth(map); 1851 1852 adr += z; 1853 1854 /* Write Buffer Program Confirm: GO GO GO */ 1855 map_write(map, CMD(0x29), cmd_adr); 1856 chip->state = FL_WRITING; 1857 1858 INVALIDATE_CACHE_UDELAY(map, chip, 1859 adr, map_bankwidth(map), 1860 chip->word_write_time); 1861 1862 timeo = jiffies + uWriteTimeout; 1863 1864 for (;;) { 1865 if (chip->state != FL_WRITING) { 1866 /* Someone's suspended the write. Sleep */ 1867 DECLARE_WAITQUEUE(wait, current); 1868 1869 set_current_state(TASK_UNINTERRUPTIBLE); 1870 add_wait_queue(&chip->wq, &wait); 1871 mutex_unlock(&chip->mutex); 1872 schedule(); 1873 remove_wait_queue(&chip->wq, &wait); 1874 timeo = jiffies + (HZ / 2); /* FIXME */ 1875 mutex_lock(&chip->mutex); 1876 continue; 1877 } 1878 1879 if (time_after(jiffies, timeo) && !chip_ready(map, adr)) 1880 break; 1881 1882 if (chip_good(map, adr, datum)) { 1883 xip_enable(map, chip, adr); 1884 goto op_done; 1885 } 1886 1887 /* Latency issues. Drop the lock, wait a while and retry */ 1888 UDELAY(map, chip, adr, 1); 1889 } 1890 1891 /* 1892 * Recovery from write-buffer programming failures requires 1893 * the write-to-buffer-reset sequence. Since the last part 1894 * of the sequence also works as a normal reset, we can run 1895 * the same commands regardless of why we are here. 1896 * See e.g. 1897 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf 1898 */ 1899 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1900 cfi->device_type, NULL); 1901 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1902 cfi->device_type, NULL); 1903 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi, 1904 cfi->device_type, NULL); 1905 xip_enable(map, chip, adr); 1906 /* FIXME - should have reset delay before continuing */ 1907 1908 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n", 1909 __func__, adr); 1910 1911 ret = -EIO; 1912 op_done: 1913 chip->state = FL_READY; 1914 DISABLE_VPP(map); 1915 put_chip(map, chip, adr); 1916 mutex_unlock(&chip->mutex); 1917 1918 return ret; 1919 } 1920 1921 1922 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, 1923 size_t *retlen, const u_char *buf) 1924 { 1925 struct map_info *map = mtd->priv; 1926 struct cfi_private *cfi = map->fldrv_priv; 1927 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 1928 int ret = 0; 1929 int chipnum; 1930 unsigned long ofs; 1931 1932 chipnum = to >> cfi->chipshift; 1933 ofs = to - (chipnum << cfi->chipshift); 1934 1935 /* If it's not bus-aligned, do the first word write */ 1936 if (ofs & (map_bankwidth(map)-1)) { 1937 size_t local_len = (-ofs)&(map_bankwidth(map)-1); 1938 if (local_len > len) 1939 local_len = len; 1940 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1941 local_len, retlen, buf); 1942 if (ret) 1943 return ret; 1944 ofs += local_len; 1945 buf += local_len; 1946 len -= local_len; 1947 1948 if (ofs >> cfi->chipshift) { 1949 chipnum ++; 1950 ofs = 0; 1951 if (chipnum == cfi->numchips) 1952 return 0; 1953 } 1954 } 1955 1956 /* Write buffer is worth it only if more than one word to write... */ 1957 while (len >= map_bankwidth(map) * 2) { 1958 /* We must not cross write block boundaries */ 1959 int size = wbufsize - (ofs & (wbufsize-1)); 1960 1961 if (size > len) 1962 size = len; 1963 if (size % map_bankwidth(map)) 1964 size -= size % map_bankwidth(map); 1965 1966 ret = do_write_buffer(map, &cfi->chips[chipnum], 1967 ofs, buf, size); 1968 if (ret) 1969 return ret; 1970 1971 ofs += size; 1972 buf += size; 1973 (*retlen) += size; 1974 len -= size; 1975 1976 if (ofs >> cfi->chipshift) { 1977 chipnum ++; 1978 ofs = 0; 1979 if (chipnum == cfi->numchips) 1980 return 0; 1981 } 1982 } 1983 1984 if (len) { 1985 size_t retlen_dregs = 0; 1986 1987 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1988 len, &retlen_dregs, buf); 1989 1990 *retlen += retlen_dregs; 1991 return ret; 1992 } 1993 1994 return 0; 1995 } 1996 1997 /* 1998 * Wait for the flash chip to become ready to write data 1999 * 2000 * This is only called during the panic_write() path. When panic_write() 2001 * is called, the kernel is in the process of a panic, and will soon be 2002 * dead. Therefore we don't take any locks, and attempt to get access 2003 * to the chip as soon as possible. 2004 */ 2005 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip, 2006 unsigned long adr) 2007 { 2008 struct cfi_private *cfi = map->fldrv_priv; 2009 int retries = 10; 2010 int i; 2011 2012 /* 2013 * If the driver thinks the chip is idle, and no toggle bits 2014 * are changing, then the chip is actually idle for sure. 2015 */ 2016 if (chip->state == FL_READY && chip_ready(map, adr)) 2017 return 0; 2018 2019 /* 2020 * Try several times to reset the chip and then wait for it 2021 * to become idle. The upper limit of a few milliseconds of 2022 * delay isn't a big problem: the kernel is dying anyway. It 2023 * is more important to save the messages. 2024 */ 2025 while (retries > 0) { 2026 const unsigned long timeo = (HZ / 1000) + 1; 2027 2028 /* send the reset command */ 2029 map_write(map, CMD(0xF0), chip->start); 2030 2031 /* wait for the chip to become ready */ 2032 for (i = 0; i < jiffies_to_usecs(timeo); i++) { 2033 if (chip_ready(map, adr)) 2034 return 0; 2035 2036 udelay(1); 2037 } 2038 2039 retries--; 2040 } 2041 2042 /* the chip never became ready */ 2043 return -EBUSY; 2044 } 2045 2046 /* 2047 * Write out one word of data to a single flash chip during a kernel panic 2048 * 2049 * This is only called during the panic_write() path. When panic_write() 2050 * is called, the kernel is in the process of a panic, and will soon be 2051 * dead. Therefore we don't take any locks, and attempt to get access 2052 * to the chip as soon as possible. 2053 * 2054 * The implementation of this routine is intentionally similar to 2055 * do_write_oneword(), in order to ease code maintenance. 2056 */ 2057 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip, 2058 unsigned long adr, map_word datum) 2059 { 2060 const unsigned long uWriteTimeout = (HZ / 1000) + 1; 2061 struct cfi_private *cfi = map->fldrv_priv; 2062 int retry_cnt = 0; 2063 map_word oldd; 2064 int ret = 0; 2065 int i; 2066 2067 adr += chip->start; 2068 2069 ret = cfi_amdstd_panic_wait(map, chip, adr); 2070 if (ret) 2071 return ret; 2072 2073 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n", 2074 __func__, adr, datum.x[0]); 2075 2076 /* 2077 * Check for a NOP for the case when the datum to write is already 2078 * present - it saves time and works around buggy chips that corrupt 2079 * data at other locations when 0xff is written to a location that 2080 * already contains 0xff. 2081 */ 2082 oldd = map_read(map, adr); 2083 if (map_word_equal(map, oldd, datum)) { 2084 pr_debug("MTD %s(): NOP\n", __func__); 2085 goto op_done; 2086 } 2087 2088 ENABLE_VPP(map); 2089 2090 retry: 2091 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2092 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2093 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2094 map_write(map, datum, adr); 2095 2096 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) { 2097 if (chip_ready(map, adr)) 2098 break; 2099 2100 udelay(1); 2101 } 2102 2103 if (!chip_good(map, adr, datum)) { 2104 /* reset on all failures. */ 2105 map_write(map, CMD(0xF0), chip->start); 2106 /* FIXME - should have reset delay before continuing */ 2107 2108 if (++retry_cnt <= MAX_RETRIES) 2109 goto retry; 2110 2111 ret = -EIO; 2112 } 2113 2114 op_done: 2115 DISABLE_VPP(map); 2116 return ret; 2117 } 2118 2119 /* 2120 * Write out some data during a kernel panic 2121 * 2122 * This is used by the mtdoops driver to save the dying messages from a 2123 * kernel which has panic'd. 2124 * 2125 * This routine ignores all of the locking used throughout the rest of the 2126 * driver, in order to ensure that the data gets written out no matter what 2127 * state this driver (and the flash chip itself) was in when the kernel crashed. 2128 * 2129 * The implementation of this routine is intentionally similar to 2130 * cfi_amdstd_write_words(), in order to ease code maintenance. 2131 */ 2132 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 2133 size_t *retlen, const u_char *buf) 2134 { 2135 struct map_info *map = mtd->priv; 2136 struct cfi_private *cfi = map->fldrv_priv; 2137 unsigned long ofs, chipstart; 2138 int ret = 0; 2139 int chipnum; 2140 2141 chipnum = to >> cfi->chipshift; 2142 ofs = to - (chipnum << cfi->chipshift); 2143 chipstart = cfi->chips[chipnum].start; 2144 2145 /* If it's not bus aligned, do the first byte write */ 2146 if (ofs & (map_bankwidth(map) - 1)) { 2147 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1); 2148 int i = ofs - bus_ofs; 2149 int n = 0; 2150 map_word tmp_buf; 2151 2152 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs); 2153 if (ret) 2154 return ret; 2155 2156 /* Load 'tmp_buf' with old contents of flash */ 2157 tmp_buf = map_read(map, bus_ofs + chipstart); 2158 2159 /* Number of bytes to copy from buffer */ 2160 n = min_t(int, len, map_bankwidth(map) - i); 2161 2162 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 2163 2164 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2165 bus_ofs, tmp_buf); 2166 if (ret) 2167 return ret; 2168 2169 ofs += n; 2170 buf += n; 2171 (*retlen) += n; 2172 len -= n; 2173 2174 if (ofs >> cfi->chipshift) { 2175 chipnum++; 2176 ofs = 0; 2177 if (chipnum == cfi->numchips) 2178 return 0; 2179 } 2180 } 2181 2182 /* We are now aligned, write as much as possible */ 2183 while (len >= map_bankwidth(map)) { 2184 map_word datum; 2185 2186 datum = map_word_load(map, buf); 2187 2188 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2189 ofs, datum); 2190 if (ret) 2191 return ret; 2192 2193 ofs += map_bankwidth(map); 2194 buf += map_bankwidth(map); 2195 (*retlen) += map_bankwidth(map); 2196 len -= map_bankwidth(map); 2197 2198 if (ofs >> cfi->chipshift) { 2199 chipnum++; 2200 ofs = 0; 2201 if (chipnum == cfi->numchips) 2202 return 0; 2203 2204 chipstart = cfi->chips[chipnum].start; 2205 } 2206 } 2207 2208 /* Write the trailing bytes if any */ 2209 if (len & (map_bankwidth(map) - 1)) { 2210 map_word tmp_buf; 2211 2212 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs); 2213 if (ret) 2214 return ret; 2215 2216 tmp_buf = map_read(map, ofs + chipstart); 2217 2218 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 2219 2220 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2221 ofs, tmp_buf); 2222 if (ret) 2223 return ret; 2224 2225 (*retlen) += len; 2226 } 2227 2228 return 0; 2229 } 2230 2231 2232 /* 2233 * Handle devices with one erase region, that only implement 2234 * the chip erase command. 2235 */ 2236 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) 2237 { 2238 struct cfi_private *cfi = map->fldrv_priv; 2239 unsigned long timeo = jiffies + HZ; 2240 unsigned long int adr; 2241 DECLARE_WAITQUEUE(wait, current); 2242 int ret = 0; 2243 int retry_cnt = 0; 2244 2245 adr = cfi->addr_unlock1; 2246 2247 mutex_lock(&chip->mutex); 2248 ret = get_chip(map, chip, adr, FL_WRITING); 2249 if (ret) { 2250 mutex_unlock(&chip->mutex); 2251 return ret; 2252 } 2253 2254 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2255 __func__, chip->start); 2256 2257 XIP_INVAL_CACHED_RANGE(map, adr, map->size); 2258 ENABLE_VPP(map); 2259 xip_disable(map, chip, adr); 2260 2261 retry: 2262 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2263 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2264 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2265 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2266 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2267 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2268 2269 chip->state = FL_ERASING; 2270 chip->erase_suspended = 0; 2271 chip->in_progress_block_addr = adr; 2272 chip->in_progress_block_mask = ~(map->size - 1); 2273 2274 INVALIDATE_CACHE_UDELAY(map, chip, 2275 adr, map->size, 2276 chip->erase_time*500); 2277 2278 timeo = jiffies + (HZ*20); 2279 2280 for (;;) { 2281 if (chip->state != FL_ERASING) { 2282 /* Someone's suspended the erase. Sleep */ 2283 set_current_state(TASK_UNINTERRUPTIBLE); 2284 add_wait_queue(&chip->wq, &wait); 2285 mutex_unlock(&chip->mutex); 2286 schedule(); 2287 remove_wait_queue(&chip->wq, &wait); 2288 mutex_lock(&chip->mutex); 2289 continue; 2290 } 2291 if (chip->erase_suspended) { 2292 /* This erase was suspended and resumed. 2293 Adjust the timeout */ 2294 timeo = jiffies + (HZ*20); /* FIXME */ 2295 chip->erase_suspended = 0; 2296 } 2297 2298 if (chip_good(map, adr, map_word_ff(map))) 2299 break; 2300 2301 if (time_after(jiffies, timeo)) { 2302 printk(KERN_WARNING "MTD %s(): software timeout\n", 2303 __func__); 2304 ret = -EIO; 2305 break; 2306 } 2307 2308 /* Latency issues. Drop the lock, wait a while and retry */ 2309 UDELAY(map, chip, adr, 1000000/HZ); 2310 } 2311 /* Did we succeed? */ 2312 if (ret) { 2313 /* reset on all failures. */ 2314 map_write(map, CMD(0xF0), chip->start); 2315 /* FIXME - should have reset delay before continuing */ 2316 2317 if (++retry_cnt <= MAX_RETRIES) { 2318 ret = 0; 2319 goto retry; 2320 } 2321 } 2322 2323 chip->state = FL_READY; 2324 xip_enable(map, chip, adr); 2325 DISABLE_VPP(map); 2326 put_chip(map, chip, adr); 2327 mutex_unlock(&chip->mutex); 2328 2329 return ret; 2330 } 2331 2332 2333 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) 2334 { 2335 struct cfi_private *cfi = map->fldrv_priv; 2336 unsigned long timeo = jiffies + HZ; 2337 DECLARE_WAITQUEUE(wait, current); 2338 int ret = 0; 2339 int retry_cnt = 0; 2340 2341 adr += chip->start; 2342 2343 mutex_lock(&chip->mutex); 2344 ret = get_chip(map, chip, adr, FL_ERASING); 2345 if (ret) { 2346 mutex_unlock(&chip->mutex); 2347 return ret; 2348 } 2349 2350 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2351 __func__, adr); 2352 2353 XIP_INVAL_CACHED_RANGE(map, adr, len); 2354 ENABLE_VPP(map); 2355 xip_disable(map, chip, adr); 2356 2357 retry: 2358 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2359 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2360 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2361 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2362 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2363 map_write(map, cfi->sector_erase_cmd, adr); 2364 2365 chip->state = FL_ERASING; 2366 chip->erase_suspended = 0; 2367 chip->in_progress_block_addr = adr; 2368 chip->in_progress_block_mask = ~(len - 1); 2369 2370 INVALIDATE_CACHE_UDELAY(map, chip, 2371 adr, len, 2372 chip->erase_time*500); 2373 2374 timeo = jiffies + (HZ*20); 2375 2376 for (;;) { 2377 if (chip->state != FL_ERASING) { 2378 /* Someone's suspended the erase. Sleep */ 2379 set_current_state(TASK_UNINTERRUPTIBLE); 2380 add_wait_queue(&chip->wq, &wait); 2381 mutex_unlock(&chip->mutex); 2382 schedule(); 2383 remove_wait_queue(&chip->wq, &wait); 2384 mutex_lock(&chip->mutex); 2385 continue; 2386 } 2387 if (chip->erase_suspended) { 2388 /* This erase was suspended and resumed. 2389 Adjust the timeout */ 2390 timeo = jiffies + (HZ*20); /* FIXME */ 2391 chip->erase_suspended = 0; 2392 } 2393 2394 if (chip_good(map, adr, map_word_ff(map))) 2395 break; 2396 2397 if (time_after(jiffies, timeo)) { 2398 printk(KERN_WARNING "MTD %s(): software timeout\n", 2399 __func__); 2400 ret = -EIO; 2401 break; 2402 } 2403 2404 /* Latency issues. Drop the lock, wait a while and retry */ 2405 UDELAY(map, chip, adr, 1000000/HZ); 2406 } 2407 /* Did we succeed? */ 2408 if (ret) { 2409 /* reset on all failures. */ 2410 map_write(map, CMD(0xF0), chip->start); 2411 /* FIXME - should have reset delay before continuing */ 2412 2413 if (++retry_cnt <= MAX_RETRIES) { 2414 ret = 0; 2415 goto retry; 2416 } 2417 } 2418 2419 chip->state = FL_READY; 2420 xip_enable(map, chip, adr); 2421 DISABLE_VPP(map); 2422 put_chip(map, chip, adr); 2423 mutex_unlock(&chip->mutex); 2424 return ret; 2425 } 2426 2427 2428 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) 2429 { 2430 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr, 2431 instr->len, NULL); 2432 } 2433 2434 2435 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) 2436 { 2437 struct map_info *map = mtd->priv; 2438 struct cfi_private *cfi = map->fldrv_priv; 2439 2440 if (instr->addr != 0) 2441 return -EINVAL; 2442 2443 if (instr->len != mtd->size) 2444 return -EINVAL; 2445 2446 return do_erase_chip(map, &cfi->chips[0]); 2447 } 2448 2449 static int do_atmel_lock(struct map_info *map, struct flchip *chip, 2450 unsigned long adr, int len, void *thunk) 2451 { 2452 struct cfi_private *cfi = map->fldrv_priv; 2453 int ret; 2454 2455 mutex_lock(&chip->mutex); 2456 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); 2457 if (ret) 2458 goto out_unlock; 2459 chip->state = FL_LOCKING; 2460 2461 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2462 2463 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2464 cfi->device_type, NULL); 2465 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2466 cfi->device_type, NULL); 2467 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, 2468 cfi->device_type, NULL); 2469 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2470 cfi->device_type, NULL); 2471 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2472 cfi->device_type, NULL); 2473 map_write(map, CMD(0x40), chip->start + adr); 2474 2475 chip->state = FL_READY; 2476 put_chip(map, chip, adr + chip->start); 2477 ret = 0; 2478 2479 out_unlock: 2480 mutex_unlock(&chip->mutex); 2481 return ret; 2482 } 2483 2484 static int do_atmel_unlock(struct map_info *map, struct flchip *chip, 2485 unsigned long adr, int len, void *thunk) 2486 { 2487 struct cfi_private *cfi = map->fldrv_priv; 2488 int ret; 2489 2490 mutex_lock(&chip->mutex); 2491 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); 2492 if (ret) 2493 goto out_unlock; 2494 chip->state = FL_UNLOCKING; 2495 2496 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2497 2498 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2499 cfi->device_type, NULL); 2500 map_write(map, CMD(0x70), adr); 2501 2502 chip->state = FL_READY; 2503 put_chip(map, chip, adr + chip->start); 2504 ret = 0; 2505 2506 out_unlock: 2507 mutex_unlock(&chip->mutex); 2508 return ret; 2509 } 2510 2511 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2512 { 2513 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); 2514 } 2515 2516 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2517 { 2518 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); 2519 } 2520 2521 /* 2522 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking 2523 */ 2524 2525 struct ppb_lock { 2526 struct flchip *chip; 2527 unsigned long adr; 2528 int locked; 2529 }; 2530 2531 #define MAX_SECTORS 512 2532 2533 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1) 2534 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2) 2535 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3) 2536 2537 static int __maybe_unused do_ppb_xxlock(struct map_info *map, 2538 struct flchip *chip, 2539 unsigned long adr, int len, void *thunk) 2540 { 2541 struct cfi_private *cfi = map->fldrv_priv; 2542 unsigned long timeo; 2543 int ret; 2544 2545 adr += chip->start; 2546 mutex_lock(&chip->mutex); 2547 ret = get_chip(map, chip, adr, FL_LOCKING); 2548 if (ret) { 2549 mutex_unlock(&chip->mutex); 2550 return ret; 2551 } 2552 2553 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len); 2554 2555 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2556 cfi->device_type, NULL); 2557 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2558 cfi->device_type, NULL); 2559 /* PPB entry command */ 2560 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi, 2561 cfi->device_type, NULL); 2562 2563 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) { 2564 chip->state = FL_LOCKING; 2565 map_write(map, CMD(0xA0), adr); 2566 map_write(map, CMD(0x00), adr); 2567 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) { 2568 /* 2569 * Unlocking of one specific sector is not supported, so we 2570 * have to unlock all sectors of this device instead 2571 */ 2572 chip->state = FL_UNLOCKING; 2573 map_write(map, CMD(0x80), chip->start); 2574 map_write(map, CMD(0x30), chip->start); 2575 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) { 2576 chip->state = FL_JEDEC_QUERY; 2577 /* Return locked status: 0->locked, 1->unlocked */ 2578 ret = !cfi_read_query(map, adr); 2579 } else 2580 BUG(); 2581 2582 /* 2583 * Wait for some time as unlocking of all sectors takes quite long 2584 */ 2585 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */ 2586 for (;;) { 2587 if (chip_ready(map, adr)) 2588 break; 2589 2590 if (time_after(jiffies, timeo)) { 2591 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 2592 ret = -EIO; 2593 break; 2594 } 2595 2596 UDELAY(map, chip, adr, 1); 2597 } 2598 2599 /* Exit BC commands */ 2600 map_write(map, CMD(0x90), chip->start); 2601 map_write(map, CMD(0x00), chip->start); 2602 2603 chip->state = FL_READY; 2604 put_chip(map, chip, adr); 2605 mutex_unlock(&chip->mutex); 2606 2607 return ret; 2608 } 2609 2610 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, 2611 uint64_t len) 2612 { 2613 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2614 DO_XXLOCK_ONEBLOCK_LOCK); 2615 } 2616 2617 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, 2618 uint64_t len) 2619 { 2620 struct mtd_erase_region_info *regions = mtd->eraseregions; 2621 struct map_info *map = mtd->priv; 2622 struct cfi_private *cfi = map->fldrv_priv; 2623 struct ppb_lock *sect; 2624 unsigned long adr; 2625 loff_t offset; 2626 uint64_t length; 2627 int chipnum; 2628 int i; 2629 int sectors; 2630 int ret; 2631 2632 /* 2633 * PPB unlocking always unlocks all sectors of the flash chip. 2634 * We need to re-lock all previously locked sectors. So lets 2635 * first check the locking status of all sectors and save 2636 * it for future use. 2637 */ 2638 sect = kcalloc(MAX_SECTORS, sizeof(struct ppb_lock), GFP_KERNEL); 2639 if (!sect) 2640 return -ENOMEM; 2641 2642 /* 2643 * This code to walk all sectors is a slightly modified version 2644 * of the cfi_varsize_frob() code. 2645 */ 2646 i = 0; 2647 chipnum = 0; 2648 adr = 0; 2649 sectors = 0; 2650 offset = 0; 2651 length = mtd->size; 2652 2653 while (length) { 2654 int size = regions[i].erasesize; 2655 2656 /* 2657 * Only test sectors that shall not be unlocked. The other 2658 * sectors shall be unlocked, so lets keep their locking 2659 * status at "unlocked" (locked=0) for the final re-locking. 2660 */ 2661 if ((offset < ofs) || (offset >= (ofs + len))) { 2662 sect[sectors].chip = &cfi->chips[chipnum]; 2663 sect[sectors].adr = adr; 2664 sect[sectors].locked = do_ppb_xxlock( 2665 map, &cfi->chips[chipnum], adr, 0, 2666 DO_XXLOCK_ONEBLOCK_GETLOCK); 2667 } 2668 2669 adr += size; 2670 offset += size; 2671 length -= size; 2672 2673 if (offset == regions[i].offset + size * regions[i].numblocks) 2674 i++; 2675 2676 if (adr >> cfi->chipshift) { 2677 if (offset >= (ofs + len)) 2678 break; 2679 adr = 0; 2680 chipnum++; 2681 2682 if (chipnum >= cfi->numchips) 2683 break; 2684 } 2685 2686 sectors++; 2687 if (sectors >= MAX_SECTORS) { 2688 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n", 2689 MAX_SECTORS); 2690 kfree(sect); 2691 return -EINVAL; 2692 } 2693 } 2694 2695 /* Now unlock the whole chip */ 2696 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2697 DO_XXLOCK_ONEBLOCK_UNLOCK); 2698 if (ret) { 2699 kfree(sect); 2700 return ret; 2701 } 2702 2703 /* 2704 * PPB unlocking always unlocks all sectors of the flash chip. 2705 * We need to re-lock all previously locked sectors. 2706 */ 2707 for (i = 0; i < sectors; i++) { 2708 if (sect[i].locked) 2709 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0, 2710 DO_XXLOCK_ONEBLOCK_LOCK); 2711 } 2712 2713 kfree(sect); 2714 return ret; 2715 } 2716 2717 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, 2718 uint64_t len) 2719 { 2720 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2721 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0; 2722 } 2723 2724 static void cfi_amdstd_sync (struct mtd_info *mtd) 2725 { 2726 struct map_info *map = mtd->priv; 2727 struct cfi_private *cfi = map->fldrv_priv; 2728 int i; 2729 struct flchip *chip; 2730 int ret = 0; 2731 DECLARE_WAITQUEUE(wait, current); 2732 2733 for (i=0; !ret && i<cfi->numchips; i++) { 2734 chip = &cfi->chips[i]; 2735 2736 retry: 2737 mutex_lock(&chip->mutex); 2738 2739 switch(chip->state) { 2740 case FL_READY: 2741 case FL_STATUS: 2742 case FL_CFI_QUERY: 2743 case FL_JEDEC_QUERY: 2744 chip->oldstate = chip->state; 2745 chip->state = FL_SYNCING; 2746 /* No need to wake_up() on this state change - 2747 * as the whole point is that nobody can do anything 2748 * with the chip now anyway. 2749 */ 2750 case FL_SYNCING: 2751 mutex_unlock(&chip->mutex); 2752 break; 2753 2754 default: 2755 /* Not an idle state */ 2756 set_current_state(TASK_UNINTERRUPTIBLE); 2757 add_wait_queue(&chip->wq, &wait); 2758 2759 mutex_unlock(&chip->mutex); 2760 2761 schedule(); 2762 2763 remove_wait_queue(&chip->wq, &wait); 2764 2765 goto retry; 2766 } 2767 } 2768 2769 /* Unlock the chips again */ 2770 2771 for (i--; i >=0; i--) { 2772 chip = &cfi->chips[i]; 2773 2774 mutex_lock(&chip->mutex); 2775 2776 if (chip->state == FL_SYNCING) { 2777 chip->state = chip->oldstate; 2778 wake_up(&chip->wq); 2779 } 2780 mutex_unlock(&chip->mutex); 2781 } 2782 } 2783 2784 2785 static int cfi_amdstd_suspend(struct mtd_info *mtd) 2786 { 2787 struct map_info *map = mtd->priv; 2788 struct cfi_private *cfi = map->fldrv_priv; 2789 int i; 2790 struct flchip *chip; 2791 int ret = 0; 2792 2793 for (i=0; !ret && i<cfi->numchips; i++) { 2794 chip = &cfi->chips[i]; 2795 2796 mutex_lock(&chip->mutex); 2797 2798 switch(chip->state) { 2799 case FL_READY: 2800 case FL_STATUS: 2801 case FL_CFI_QUERY: 2802 case FL_JEDEC_QUERY: 2803 chip->oldstate = chip->state; 2804 chip->state = FL_PM_SUSPENDED; 2805 /* No need to wake_up() on this state change - 2806 * as the whole point is that nobody can do anything 2807 * with the chip now anyway. 2808 */ 2809 case FL_PM_SUSPENDED: 2810 break; 2811 2812 default: 2813 ret = -EAGAIN; 2814 break; 2815 } 2816 mutex_unlock(&chip->mutex); 2817 } 2818 2819 /* Unlock the chips again */ 2820 2821 if (ret) { 2822 for (i--; i >=0; i--) { 2823 chip = &cfi->chips[i]; 2824 2825 mutex_lock(&chip->mutex); 2826 2827 if (chip->state == FL_PM_SUSPENDED) { 2828 chip->state = chip->oldstate; 2829 wake_up(&chip->wq); 2830 } 2831 mutex_unlock(&chip->mutex); 2832 } 2833 } 2834 2835 return ret; 2836 } 2837 2838 2839 static void cfi_amdstd_resume(struct mtd_info *mtd) 2840 { 2841 struct map_info *map = mtd->priv; 2842 struct cfi_private *cfi = map->fldrv_priv; 2843 int i; 2844 struct flchip *chip; 2845 2846 for (i=0; i<cfi->numchips; i++) { 2847 2848 chip = &cfi->chips[i]; 2849 2850 mutex_lock(&chip->mutex); 2851 2852 if (chip->state == FL_PM_SUSPENDED) { 2853 chip->state = FL_READY; 2854 map_write(map, CMD(0xF0), chip->start); 2855 wake_up(&chip->wq); 2856 } 2857 else 2858 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); 2859 2860 mutex_unlock(&chip->mutex); 2861 } 2862 } 2863 2864 2865 /* 2866 * Ensure that the flash device is put back into read array mode before 2867 * unloading the driver or rebooting. On some systems, rebooting while 2868 * the flash is in query/program/erase mode will prevent the CPU from 2869 * fetching the bootloader code, requiring a hard reset or power cycle. 2870 */ 2871 static int cfi_amdstd_reset(struct mtd_info *mtd) 2872 { 2873 struct map_info *map = mtd->priv; 2874 struct cfi_private *cfi = map->fldrv_priv; 2875 int i, ret; 2876 struct flchip *chip; 2877 2878 for (i = 0; i < cfi->numchips; i++) { 2879 2880 chip = &cfi->chips[i]; 2881 2882 mutex_lock(&chip->mutex); 2883 2884 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN); 2885 if (!ret) { 2886 map_write(map, CMD(0xF0), chip->start); 2887 chip->state = FL_SHUTDOWN; 2888 put_chip(map, chip, chip->start); 2889 } 2890 2891 mutex_unlock(&chip->mutex); 2892 } 2893 2894 return 0; 2895 } 2896 2897 2898 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, 2899 void *v) 2900 { 2901 struct mtd_info *mtd; 2902 2903 mtd = container_of(nb, struct mtd_info, reboot_notifier); 2904 cfi_amdstd_reset(mtd); 2905 return NOTIFY_DONE; 2906 } 2907 2908 2909 static void cfi_amdstd_destroy(struct mtd_info *mtd) 2910 { 2911 struct map_info *map = mtd->priv; 2912 struct cfi_private *cfi = map->fldrv_priv; 2913 2914 cfi_amdstd_reset(mtd); 2915 unregister_reboot_notifier(&mtd->reboot_notifier); 2916 kfree(cfi->cmdset_priv); 2917 kfree(cfi->cfiq); 2918 kfree(cfi); 2919 kfree(mtd->eraseregions); 2920 } 2921 2922 MODULE_LICENSE("GPL"); 2923 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); 2924 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); 2925 MODULE_ALIAS("cfi_cmdset_0006"); 2926 MODULE_ALIAS("cfi_cmdset_0701"); 2927