1 /* 2 * Common Flash Interface support: 3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002) 4 * 5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp> 6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com> 7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com> 8 * 9 * 2_by_8 routines added by Simon Munton 10 * 11 * 4_by_16 work by Carolyn J. Smith 12 * 13 * XIP support hooks by Vitaly Wool (based on code for Intel flash 14 * by Nicolas Pitre) 15 * 16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0 17 * 18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 19 * 20 * This code is GPL 21 */ 22 23 #include <linux/module.h> 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/sched.h> 27 #include <asm/io.h> 28 #include <asm/byteorder.h> 29 30 #include <linux/errno.h> 31 #include <linux/slab.h> 32 #include <linux/delay.h> 33 #include <linux/interrupt.h> 34 #include <linux/reboot.h> 35 #include <linux/of.h> 36 #include <linux/of_platform.h> 37 #include <linux/mtd/map.h> 38 #include <linux/mtd/mtd.h> 39 #include <linux/mtd/cfi.h> 40 #include <linux/mtd/xip.h> 41 42 #define AMD_BOOTLOC_BUG 43 #define FORCE_WORD_WRITE 0 44 45 #define MAX_RETRIES 3 46 47 #define SST49LF004B 0x0060 48 #define SST49LF040B 0x0050 49 #define SST49LF008A 0x005a 50 #define AT49BV6416 0x00d6 51 52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); 55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); 56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); 57 static void cfi_amdstd_sync (struct mtd_info *); 58 static int cfi_amdstd_suspend (struct mtd_info *); 59 static void cfi_amdstd_resume (struct mtd_info *); 60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *); 61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t, 62 size_t *, struct otp_info *); 63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t, 64 size_t *, struct otp_info *); 65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); 66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t, 67 size_t *, u_char *); 68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t, 69 size_t *, u_char *); 70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t, 71 size_t *, u_char *); 72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t); 73 74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 75 size_t *retlen, const u_char *buf); 76 77 static void cfi_amdstd_destroy(struct mtd_info *); 78 79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int); 80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *); 81 82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode); 83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr); 84 #include "fwh_lock.h" 85 86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 88 89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); 91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len); 92 93 static struct mtd_chip_driver cfi_amdstd_chipdrv = { 94 .probe = NULL, /* Not usable directly */ 95 .destroy = cfi_amdstd_destroy, 96 .name = "cfi_cmdset_0002", 97 .module = THIS_MODULE 98 }; 99 100 101 /* #define DEBUG_CFI_FEATURES */ 102 103 104 #ifdef DEBUG_CFI_FEATURES 105 static void cfi_tell_features(struct cfi_pri_amdstd *extp) 106 { 107 const char* erase_suspend[3] = { 108 "Not supported", "Read only", "Read/write" 109 }; 110 const char* top_bottom[6] = { 111 "No WP", "8x8KiB sectors at top & bottom, no WP", 112 "Bottom boot", "Top boot", 113 "Uniform, Bottom WP", "Uniform, Top WP" 114 }; 115 116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1); 117 printk(" Address sensitive unlock: %s\n", 118 (extp->SiliconRevision & 1) ? "Not required" : "Required"); 119 120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend)) 121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]); 122 else 123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend); 124 125 if (extp->BlkProt == 0) 126 printk(" Block protection: Not supported\n"); 127 else 128 printk(" Block protection: %d sectors per group\n", extp->BlkProt); 129 130 131 printk(" Temporary block unprotect: %s\n", 132 extp->TmpBlkUnprotect ? "Supported" : "Not supported"); 133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot); 134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps); 135 printk(" Burst mode: %s\n", 136 extp->BurstMode ? "Supported" : "Not supported"); 137 if (extp->PageMode == 0) 138 printk(" Page mode: Not supported\n"); 139 else 140 printk(" Page mode: %d word page\n", extp->PageMode << 2); 141 142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n", 143 extp->VppMin >> 4, extp->VppMin & 0xf); 144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n", 145 extp->VppMax >> 4, extp->VppMax & 0xf); 146 147 if (extp->TopBottom < ARRAY_SIZE(top_bottom)) 148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]); 149 else 150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom); 151 } 152 #endif 153 154 #ifdef AMD_BOOTLOC_BUG 155 /* Wheee. Bring me the head of someone at AMD. */ 156 static void fixup_amd_bootblock(struct mtd_info *mtd) 157 { 158 struct map_info *map = mtd->priv; 159 struct cfi_private *cfi = map->fldrv_priv; 160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 161 __u8 major = extp->MajorVersion; 162 __u8 minor = extp->MinorVersion; 163 164 if (((major << 8) | minor) < 0x3131) { 165 /* CFI version 1.0 => don't trust bootloc */ 166 167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n", 168 map->name, cfi->mfr, cfi->id); 169 170 /* AFAICS all 29LV400 with a bottom boot block have a device ID 171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode. 172 * These were badly detected as they have the 0x80 bit set 173 * so treat them as a special case. 174 */ 175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) && 176 177 /* Macronix added CFI to their 2nd generation 178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD, 179 * Fujitsu, Spansion, EON, ESI and older Macronix) 180 * has CFI. 181 * 182 * Therefore also check the manufacturer. 183 * This reduces the risk of false detection due to 184 * the 8-bit device ID. 185 */ 186 (cfi->mfr == CFI_MFR_MACRONIX)) { 187 pr_debug("%s: Macronix MX29LV400C with bottom boot block" 188 " detected\n", map->name); 189 extp->TopBottom = 2; /* bottom boot */ 190 } else 191 if (cfi->id & 0x80) { 192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id); 193 extp->TopBottom = 3; /* top boot */ 194 } else { 195 extp->TopBottom = 2; /* bottom boot */ 196 } 197 198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;" 199 " deduced %s from Device ID\n", map->name, major, minor, 200 extp->TopBottom == 2 ? "bottom" : "top"); 201 } 202 } 203 #endif 204 205 static void fixup_use_write_buffers(struct mtd_info *mtd) 206 { 207 struct map_info *map = mtd->priv; 208 struct cfi_private *cfi = map->fldrv_priv; 209 if (cfi->cfiq->BufWriteTimeoutTyp) { 210 pr_debug("Using buffer write method\n"); 211 mtd->_write = cfi_amdstd_write_buffers; 212 } 213 } 214 215 /* Atmel chips don't use the same PRI format as AMD chips */ 216 static void fixup_convert_atmel_pri(struct mtd_info *mtd) 217 { 218 struct map_info *map = mtd->priv; 219 struct cfi_private *cfi = map->fldrv_priv; 220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 221 struct cfi_pri_atmel atmel_pri; 222 223 memcpy(&atmel_pri, extp, sizeof(atmel_pri)); 224 memset((char *)extp + 5, 0, sizeof(*extp) - 5); 225 226 if (atmel_pri.Features & 0x02) 227 extp->EraseSuspend = 2; 228 229 /* Some chips got it backwards... */ 230 if (cfi->id == AT49BV6416) { 231 if (atmel_pri.BottomBoot) 232 extp->TopBottom = 3; 233 else 234 extp->TopBottom = 2; 235 } else { 236 if (atmel_pri.BottomBoot) 237 extp->TopBottom = 2; 238 else 239 extp->TopBottom = 3; 240 } 241 242 /* burst write mode not supported */ 243 cfi->cfiq->BufWriteTimeoutTyp = 0; 244 cfi->cfiq->BufWriteTimeoutMax = 0; 245 } 246 247 static void fixup_use_secsi(struct mtd_info *mtd) 248 { 249 /* Setup for chips with a secsi area */ 250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read; 251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read; 252 } 253 254 static void fixup_use_erase_chip(struct mtd_info *mtd) 255 { 256 struct map_info *map = mtd->priv; 257 struct cfi_private *cfi = map->fldrv_priv; 258 if ((cfi->cfiq->NumEraseRegions == 1) && 259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) { 260 mtd->_erase = cfi_amdstd_erase_chip; 261 } 262 263 } 264 265 /* 266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors 267 * locked by default. 268 */ 269 static void fixup_use_atmel_lock(struct mtd_info *mtd) 270 { 271 mtd->_lock = cfi_atmel_lock; 272 mtd->_unlock = cfi_atmel_unlock; 273 mtd->flags |= MTD_POWERUP_LOCK; 274 } 275 276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd) 277 { 278 struct map_info *map = mtd->priv; 279 struct cfi_private *cfi = map->fldrv_priv; 280 281 /* 282 * These flashes report two separate eraseblock regions based on the 283 * sector_erase-size and block_erase-size, although they both operate on the 284 * same memory. This is not allowed according to CFI, so we just pick the 285 * sector_erase-size. 286 */ 287 cfi->cfiq->NumEraseRegions = 1; 288 } 289 290 static void fixup_sst39vf(struct mtd_info *mtd) 291 { 292 struct map_info *map = mtd->priv; 293 struct cfi_private *cfi = map->fldrv_priv; 294 295 fixup_old_sst_eraseregion(mtd); 296 297 cfi->addr_unlock1 = 0x5555; 298 cfi->addr_unlock2 = 0x2AAA; 299 } 300 301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd) 302 { 303 struct map_info *map = mtd->priv; 304 struct cfi_private *cfi = map->fldrv_priv; 305 306 fixup_old_sst_eraseregion(mtd); 307 308 cfi->addr_unlock1 = 0x555; 309 cfi->addr_unlock2 = 0x2AA; 310 311 cfi->sector_erase_cmd = CMD(0x50); 312 } 313 314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd) 315 { 316 struct map_info *map = mtd->priv; 317 struct cfi_private *cfi = map->fldrv_priv; 318 319 fixup_sst39vf_rev_b(mtd); 320 321 /* 322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where 323 * it should report a size of 8KBytes (0x0020*256). 324 */ 325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff; 326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n", 327 mtd->name); 328 } 329 330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd) 331 { 332 struct map_info *map = mtd->priv; 333 struct cfi_private *cfi = map->fldrv_priv; 334 335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) { 336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040; 337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n", 338 mtd->name); 339 } 340 } 341 342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd) 343 { 344 struct map_info *map = mtd->priv; 345 struct cfi_private *cfi = map->fldrv_priv; 346 347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) { 348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040; 349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n", 350 mtd->name); 351 } 352 } 353 354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd) 355 { 356 struct map_info *map = mtd->priv; 357 struct cfi_private *cfi = map->fldrv_priv; 358 359 /* 360 * S29NS512P flash uses more than 8bits to report number of sectors, 361 * which is not permitted by CFI. 362 */ 363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff; 364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n", 365 mtd->name); 366 } 367 368 /* Used to fix CFI-Tables of chips without Extended Query Tables */ 369 static struct cfi_fixup cfi_nopri_fixup_table[] = { 370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */ 371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */ 372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */ 373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */ 374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */ 375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */ 376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */ 377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */ 378 { 0, 0, NULL } 379 }; 380 381 static struct cfi_fixup cfi_fixup_table[] = { 382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri }, 383 #ifdef AMD_BOOTLOC_BUG 384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock }, 385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock }, 386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock }, 387 #endif 388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi }, 389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi }, 390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi }, 391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi }, 392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi }, 393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi }, 394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors }, 395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors }, 396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors }, 397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors }, 398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors }, 399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */ 400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */ 401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */ 402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */ 403 #if !FORCE_WORD_WRITE 404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers }, 405 #endif 406 { 0, 0, NULL } 407 }; 408 static struct cfi_fixup jedec_fixup_table[] = { 409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock }, 410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock }, 411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock }, 412 { 0, 0, NULL } 413 }; 414 415 static struct cfi_fixup fixup_table[] = { 416 /* The CFI vendor ids and the JEDEC vendor IDs appear 417 * to be common. It is like the devices id's are as 418 * well. This table is to pick all cases where 419 * we know that is the case. 420 */ 421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip }, 422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock }, 423 { 0, 0, NULL } 424 }; 425 426 427 static void cfi_fixup_major_minor(struct cfi_private *cfi, 428 struct cfi_pri_amdstd *extp) 429 { 430 if (cfi->mfr == CFI_MFR_SAMSUNG) { 431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') || 432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) { 433 /* 434 * Samsung K8P2815UQB and K8D6x16UxM chips 435 * report major=0 / minor=0. 436 * K8D3x16UxC chips report major=3 / minor=3. 437 */ 438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu" 439 " Extended Query version to 1.%c\n", 440 extp->MinorVersion); 441 extp->MajorVersion = '1'; 442 } 443 } 444 445 /* 446 * SST 38VF640x chips report major=0xFF / minor=0xFF. 447 */ 448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) { 449 extp->MajorVersion = '1'; 450 extp->MinorVersion = '0'; 451 } 452 } 453 454 static int is_m29ew(struct cfi_private *cfi) 455 { 456 if (cfi->mfr == CFI_MFR_INTEL && 457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) || 458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e))) 459 return 1; 460 return 0; 461 } 462 463 /* 464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20: 465 * Some revisions of the M29EW suffer from erase suspend hang ups. In 466 * particular, it can occur when the sequence 467 * Erase Confirm -> Suspend -> Program -> Resume 468 * causes a lockup due to internal timing issues. The consequence is that the 469 * erase cannot be resumed without inserting a dummy command after programming 470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle 471 * that writes an F0 command code before the RESUME command. 472 */ 473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map, 474 unsigned long adr) 475 { 476 struct cfi_private *cfi = map->fldrv_priv; 477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */ 478 if (is_m29ew(cfi)) 479 map_write(map, CMD(0xF0), adr); 480 } 481 482 /* 483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22: 484 * 485 * Some revisions of the M29EW (for example, A1 and A2 step revisions) 486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND 487 * command is issued after an ERASE RESUME operation without waiting for a 488 * minimum delay. The result is that once the ERASE seems to be completed 489 * (no bits are toggling), the contents of the Flash memory block on which 490 * the erase was ongoing could be inconsistent with the expected values 491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84 492 * values), causing a consequent failure of the ERASE operation. 493 * The occurrence of this issue could be high, especially when file system 494 * operations on the Flash are intensive. As a result, it is recommended 495 * that a patch be applied. Intensive file system operations can cause many 496 * calls to the garbage routine to free Flash space (also by erasing physical 497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME 498 * commands can occur. The problem disappears when a delay is inserted after 499 * the RESUME command by using the udelay() function available in Linux. 500 * The DELAY value must be tuned based on the customer's platform. 501 * The maximum value that fixes the problem in all cases is 500us. 502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient 503 * in most cases. 504 * We have chosen 500µs because this latency is acceptable. 505 */ 506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi) 507 { 508 /* 509 * Resolving the Delay After Resume Issue see Micron TN-13-07 510 * Worst case delay must be 500µs but 30-50µs should be ok as well 511 */ 512 if (is_m29ew(cfi)) 513 cfi_udelay(500); 514 } 515 516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary) 517 { 518 struct cfi_private *cfi = map->fldrv_priv; 519 struct device_node __maybe_unused *np = map->device_node; 520 struct mtd_info *mtd; 521 int i; 522 523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); 524 if (!mtd) 525 return NULL; 526 mtd->priv = map; 527 mtd->type = MTD_NORFLASH; 528 529 /* Fill in the default mtd operations */ 530 mtd->_erase = cfi_amdstd_erase_varsize; 531 mtd->_write = cfi_amdstd_write_words; 532 mtd->_read = cfi_amdstd_read; 533 mtd->_sync = cfi_amdstd_sync; 534 mtd->_suspend = cfi_amdstd_suspend; 535 mtd->_resume = cfi_amdstd_resume; 536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg; 537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg; 538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info; 539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info; 540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg; 541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg; 542 mtd->flags = MTD_CAP_NORFLASH; 543 mtd->name = map->name; 544 mtd->writesize = 1; 545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 546 547 pr_debug("MTD %s(): write buffer size %d\n", __func__, 548 mtd->writebufsize); 549 550 mtd->_panic_write = cfi_amdstd_panic_write; 551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot; 552 553 if (cfi->cfi_mode==CFI_MODE_CFI){ 554 unsigned char bootloc; 555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; 556 struct cfi_pri_amdstd *extp; 557 558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu"); 559 if (extp) { 560 /* 561 * It's a real CFI chip, not one for which the probe 562 * routine faked a CFI structure. 563 */ 564 cfi_fixup_major_minor(cfi, extp); 565 566 /* 567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5 568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19 569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf 570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf 571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf 572 */ 573 if (extp->MajorVersion != '1' || 574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) { 575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query " 576 "version %c.%c (%#02x/%#02x).\n", 577 extp->MajorVersion, extp->MinorVersion, 578 extp->MajorVersion, extp->MinorVersion); 579 kfree(extp); 580 kfree(mtd); 581 return NULL; 582 } 583 584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n", 585 extp->MajorVersion, extp->MinorVersion); 586 587 /* Install our own private info structure */ 588 cfi->cmdset_priv = extp; 589 590 /* Apply cfi device specific fixups */ 591 cfi_fixup(mtd, cfi_fixup_table); 592 593 #ifdef DEBUG_CFI_FEATURES 594 /* Tell the user about it in lots of lovely detail */ 595 cfi_tell_features(extp); 596 #endif 597 598 #ifdef CONFIG_OF 599 if (np && of_property_read_bool( 600 np, "use-advanced-sector-protection") 601 && extp->BlkProtUnprot == 8) { 602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n"); 603 mtd->_lock = cfi_ppb_lock; 604 mtd->_unlock = cfi_ppb_unlock; 605 mtd->_is_locked = cfi_ppb_is_locked; 606 } 607 #endif 608 609 bootloc = extp->TopBottom; 610 if ((bootloc < 2) || (bootloc > 5)) { 611 printk(KERN_WARNING "%s: CFI contains unrecognised boot " 612 "bank location (%d). Assuming bottom.\n", 613 map->name, bootloc); 614 bootloc = 2; 615 } 616 617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { 618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name); 619 620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) { 621 int j = (cfi->cfiq->NumEraseRegions-1)-i; 622 623 swap(cfi->cfiq->EraseRegionInfo[i], 624 cfi->cfiq->EraseRegionInfo[j]); 625 } 626 } 627 /* Set the default CFI lock/unlock addresses */ 628 cfi->addr_unlock1 = 0x555; 629 cfi->addr_unlock2 = 0x2aa; 630 } 631 cfi_fixup(mtd, cfi_nopri_fixup_table); 632 633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) { 634 kfree(mtd); 635 return NULL; 636 } 637 638 } /* CFI mode */ 639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) { 640 /* Apply jedec specific fixups */ 641 cfi_fixup(mtd, jedec_fixup_table); 642 } 643 /* Apply generic fixups */ 644 cfi_fixup(mtd, fixup_table); 645 646 for (i=0; i< cfi->numchips; i++) { 647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp; 648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp; 649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp; 650 /* 651 * First calculate the timeout max according to timeout field 652 * of struct cfi_ident that probed from chip's CFI aera, if 653 * available. Specify a minimum of 2000us, in case the CFI data 654 * is wrong. 655 */ 656 if (cfi->cfiq->BufWriteTimeoutTyp && 657 cfi->cfiq->BufWriteTimeoutMax) 658 cfi->chips[i].buffer_write_time_max = 659 1 << (cfi->cfiq->BufWriteTimeoutTyp + 660 cfi->cfiq->BufWriteTimeoutMax); 661 else 662 cfi->chips[i].buffer_write_time_max = 0; 663 664 cfi->chips[i].buffer_write_time_max = 665 max(cfi->chips[i].buffer_write_time_max, 2000); 666 667 cfi->chips[i].ref_point_counter = 0; 668 init_waitqueue_head(&(cfi->chips[i].wq)); 669 } 670 671 map->fldrv = &cfi_amdstd_chipdrv; 672 673 return cfi_amdstd_setup(mtd); 674 } 675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002"))); 677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002); 678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006); 679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701); 680 681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd) 682 { 683 struct map_info *map = mtd->priv; 684 struct cfi_private *cfi = map->fldrv_priv; 685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave; 686 unsigned long offset = 0; 687 int i,j; 688 689 printk(KERN_NOTICE "number of %s chips: %d\n", 690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips); 691 /* Select the correct geometry setup */ 692 mtd->size = devsize * cfi->numchips; 693 694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips; 695 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info) 696 * mtd->numeraseregions, GFP_KERNEL); 697 if (!mtd->eraseregions) 698 goto setup_err; 699 700 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) { 701 unsigned long ernum, ersize; 702 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave; 703 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1; 704 705 if (mtd->erasesize < ersize) { 706 mtd->erasesize = ersize; 707 } 708 for (j=0; j<cfi->numchips; j++) { 709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset; 710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize; 711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum; 712 } 713 offset += (ersize * ernum); 714 } 715 if (offset != devsize) { 716 /* Argh */ 717 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize); 718 goto setup_err; 719 } 720 721 __module_get(THIS_MODULE); 722 register_reboot_notifier(&mtd->reboot_notifier); 723 return mtd; 724 725 setup_err: 726 kfree(mtd->eraseregions); 727 kfree(mtd); 728 kfree(cfi->cmdset_priv); 729 kfree(cfi->cfiq); 730 return NULL; 731 } 732 733 /* 734 * Return true if the chip is ready. 735 * 736 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 737 * non-suspended sector) and is indicated by no toggle bits toggling. 738 * 739 * Note that anything more complicated than checking if no bits are toggling 740 * (including checking DQ5 for an error status) is tricky to get working 741 * correctly and is therefore not done (particularly with interleaved chips 742 * as each chip must be checked independently of the others). 743 */ 744 static int __xipram chip_ready(struct map_info *map, unsigned long addr) 745 { 746 map_word d, t; 747 748 d = map_read(map, addr); 749 t = map_read(map, addr); 750 751 return map_word_equal(map, d, t); 752 } 753 754 /* 755 * Return true if the chip is ready and has the correct value. 756 * 757 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any 758 * non-suspended sector) and it is indicated by no bits toggling. 759 * 760 * Error are indicated by toggling bits or bits held with the wrong value, 761 * or with bits toggling. 762 * 763 * Note that anything more complicated than checking if no bits are toggling 764 * (including checking DQ5 for an error status) is tricky to get working 765 * correctly and is therefore not done (particularly with interleaved chips 766 * as each chip must be checked independently of the others). 767 * 768 */ 769 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected) 770 { 771 map_word oldd, curd; 772 773 oldd = map_read(map, addr); 774 curd = map_read(map, addr); 775 776 return map_word_equal(map, oldd, curd) && 777 map_word_equal(map, curd, expected); 778 } 779 780 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode) 781 { 782 DECLARE_WAITQUEUE(wait, current); 783 struct cfi_private *cfi = map->fldrv_priv; 784 unsigned long timeo; 785 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv; 786 787 resettime: 788 timeo = jiffies + HZ; 789 retry: 790 switch (chip->state) { 791 792 case FL_STATUS: 793 for (;;) { 794 if (chip_ready(map, adr)) 795 break; 796 797 if (time_after(jiffies, timeo)) { 798 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 799 return -EIO; 800 } 801 mutex_unlock(&chip->mutex); 802 cfi_udelay(1); 803 mutex_lock(&chip->mutex); 804 /* Someone else might have been playing with it. */ 805 goto retry; 806 } 807 808 case FL_READY: 809 case FL_CFI_QUERY: 810 case FL_JEDEC_QUERY: 811 return 0; 812 813 case FL_ERASING: 814 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || 815 !(mode == FL_READY || mode == FL_POINT || 816 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) 817 goto sleep; 818 819 /* Do not allow suspend iff read/write to EB address */ 820 if ((adr & chip->in_progress_block_mask) == 821 chip->in_progress_block_addr) 822 goto sleep; 823 824 /* Erase suspend */ 825 /* It's harmless to issue the Erase-Suspend and Erase-Resume 826 * commands when the erase algorithm isn't in progress. */ 827 map_write(map, CMD(0xB0), chip->in_progress_block_addr); 828 chip->oldstate = FL_ERASING; 829 chip->state = FL_ERASE_SUSPENDING; 830 chip->erase_suspended = 1; 831 for (;;) { 832 if (chip_ready(map, adr)) 833 break; 834 835 if (time_after(jiffies, timeo)) { 836 /* Should have suspended the erase by now. 837 * Send an Erase-Resume command as either 838 * there was an error (so leave the erase 839 * routine to recover from it) or we trying to 840 * use the erase-in-progress sector. */ 841 put_chip(map, chip, adr); 842 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__); 843 return -EIO; 844 } 845 846 mutex_unlock(&chip->mutex); 847 cfi_udelay(1); 848 mutex_lock(&chip->mutex); 849 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING. 850 So we can just loop here. */ 851 } 852 chip->state = FL_READY; 853 return 0; 854 855 case FL_XIP_WHILE_ERASING: 856 if (mode != FL_READY && mode != FL_POINT && 857 (!cfip || !(cfip->EraseSuspend&2))) 858 goto sleep; 859 chip->oldstate = chip->state; 860 chip->state = FL_READY; 861 return 0; 862 863 case FL_SHUTDOWN: 864 /* The machine is rebooting */ 865 return -EIO; 866 867 case FL_POINT: 868 /* Only if there's no operation suspended... */ 869 if (mode == FL_READY && chip->oldstate == FL_READY) 870 return 0; 871 872 default: 873 sleep: 874 set_current_state(TASK_UNINTERRUPTIBLE); 875 add_wait_queue(&chip->wq, &wait); 876 mutex_unlock(&chip->mutex); 877 schedule(); 878 remove_wait_queue(&chip->wq, &wait); 879 mutex_lock(&chip->mutex); 880 goto resettime; 881 } 882 } 883 884 885 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr) 886 { 887 struct cfi_private *cfi = map->fldrv_priv; 888 889 switch(chip->oldstate) { 890 case FL_ERASING: 891 cfi_fixup_m29ew_erase_suspend(map, 892 chip->in_progress_block_addr); 893 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr); 894 cfi_fixup_m29ew_delay_after_resume(cfi); 895 chip->oldstate = FL_READY; 896 chip->state = FL_ERASING; 897 break; 898 899 case FL_XIP_WHILE_ERASING: 900 chip->state = chip->oldstate; 901 chip->oldstate = FL_READY; 902 break; 903 904 case FL_READY: 905 case FL_STATUS: 906 break; 907 default: 908 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate); 909 } 910 wake_up(&chip->wq); 911 } 912 913 #ifdef CONFIG_MTD_XIP 914 915 /* 916 * No interrupt what so ever can be serviced while the flash isn't in array 917 * mode. This is ensured by the xip_disable() and xip_enable() functions 918 * enclosing any code path where the flash is known not to be in array mode. 919 * And within a XIP disabled code path, only functions marked with __xipram 920 * may be called and nothing else (it's a good thing to inspect generated 921 * assembly to make sure inline functions were actually inlined and that gcc 922 * didn't emit calls to its own support functions). Also configuring MTD CFI 923 * support to a single buswidth and a single interleave is also recommended. 924 */ 925 926 static void xip_disable(struct map_info *map, struct flchip *chip, 927 unsigned long adr) 928 { 929 /* TODO: chips with no XIP use should ignore and return */ 930 (void) map_read(map, adr); /* ensure mmu mapping is up to date */ 931 local_irq_disable(); 932 } 933 934 static void __xipram xip_enable(struct map_info *map, struct flchip *chip, 935 unsigned long adr) 936 { 937 struct cfi_private *cfi = map->fldrv_priv; 938 939 if (chip->state != FL_POINT && chip->state != FL_READY) { 940 map_write(map, CMD(0xf0), adr); 941 chip->state = FL_READY; 942 } 943 (void) map_read(map, adr); 944 xip_iprefetch(); 945 local_irq_enable(); 946 } 947 948 /* 949 * When a delay is required for the flash operation to complete, the 950 * xip_udelay() function is polling for both the given timeout and pending 951 * (but still masked) hardware interrupts. Whenever there is an interrupt 952 * pending then the flash erase operation is suspended, array mode restored 953 * and interrupts unmasked. Task scheduling might also happen at that 954 * point. The CPU eventually returns from the interrupt or the call to 955 * schedule() and the suspended flash operation is resumed for the remaining 956 * of the delay period. 957 * 958 * Warning: this function _will_ fool interrupt latency tracing tools. 959 */ 960 961 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip, 962 unsigned long adr, int usec) 963 { 964 struct cfi_private *cfi = map->fldrv_priv; 965 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; 966 map_word status, OK = CMD(0x80); 967 unsigned long suspended, start = xip_currtime(); 968 flstate_t oldstate; 969 970 do { 971 cpu_relax(); 972 if (xip_irqpending() && extp && 973 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) && 974 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) { 975 /* 976 * Let's suspend the erase operation when supported. 977 * Note that we currently don't try to suspend 978 * interleaved chips if there is already another 979 * operation suspended (imagine what happens 980 * when one chip was already done with the current 981 * operation while another chip suspended it, then 982 * we resume the whole thing at once). Yes, it 983 * can happen! 984 */ 985 map_write(map, CMD(0xb0), adr); 986 usec -= xip_elapsed_since(start); 987 suspended = xip_currtime(); 988 do { 989 if (xip_elapsed_since(suspended) > 100000) { 990 /* 991 * The chip doesn't want to suspend 992 * after waiting for 100 msecs. 993 * This is a critical error but there 994 * is not much we can do here. 995 */ 996 return; 997 } 998 status = map_read(map, adr); 999 } while (!map_word_andequal(map, status, OK, OK)); 1000 1001 /* Suspend succeeded */ 1002 oldstate = chip->state; 1003 if (!map_word_bitsset(map, status, CMD(0x40))) 1004 break; 1005 chip->state = FL_XIP_WHILE_ERASING; 1006 chip->erase_suspended = 1; 1007 map_write(map, CMD(0xf0), adr); 1008 (void) map_read(map, adr); 1009 xip_iprefetch(); 1010 local_irq_enable(); 1011 mutex_unlock(&chip->mutex); 1012 xip_iprefetch(); 1013 cond_resched(); 1014 1015 /* 1016 * We're back. However someone else might have 1017 * decided to go write to the chip if we are in 1018 * a suspended erase state. If so let's wait 1019 * until it's done. 1020 */ 1021 mutex_lock(&chip->mutex); 1022 while (chip->state != FL_XIP_WHILE_ERASING) { 1023 DECLARE_WAITQUEUE(wait, current); 1024 set_current_state(TASK_UNINTERRUPTIBLE); 1025 add_wait_queue(&chip->wq, &wait); 1026 mutex_unlock(&chip->mutex); 1027 schedule(); 1028 remove_wait_queue(&chip->wq, &wait); 1029 mutex_lock(&chip->mutex); 1030 } 1031 /* Disallow XIP again */ 1032 local_irq_disable(); 1033 1034 /* Correct Erase Suspend Hangups for M29EW */ 1035 cfi_fixup_m29ew_erase_suspend(map, adr); 1036 /* Resume the write or erase operation */ 1037 map_write(map, cfi->sector_erase_cmd, adr); 1038 chip->state = oldstate; 1039 start = xip_currtime(); 1040 } else if (usec >= 1000000/HZ) { 1041 /* 1042 * Try to save on CPU power when waiting delay 1043 * is at least a system timer tick period. 1044 * No need to be extremely accurate here. 1045 */ 1046 xip_cpu_idle(); 1047 } 1048 status = map_read(map, adr); 1049 } while (!map_word_andequal(map, status, OK, OK) 1050 && xip_elapsed_since(start) < usec); 1051 } 1052 1053 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec) 1054 1055 /* 1056 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while 1057 * the flash is actively programming or erasing since we have to poll for 1058 * the operation to complete anyway. We can't do that in a generic way with 1059 * a XIP setup so do it before the actual flash operation in this case 1060 * and stub it out from INVALIDATE_CACHE_UDELAY. 1061 */ 1062 #define XIP_INVAL_CACHED_RANGE(map, from, size) \ 1063 INVALIDATE_CACHED_RANGE(map, from, size) 1064 1065 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1066 UDELAY(map, chip, adr, usec) 1067 1068 /* 1069 * Extra notes: 1070 * 1071 * Activating this XIP support changes the way the code works a bit. For 1072 * example the code to suspend the current process when concurrent access 1073 * happens is never executed because xip_udelay() will always return with the 1074 * same chip state as it was entered with. This is why there is no care for 1075 * the presence of add_wait_queue() or schedule() calls from within a couple 1076 * xip_disable()'d areas of code, like in do_erase_oneblock for example. 1077 * The queueing and scheduling are always happening within xip_udelay(). 1078 * 1079 * Similarly, get_chip() and put_chip() just happen to always be executed 1080 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state 1081 * is in array mode, therefore never executing many cases therein and not 1082 * causing any problem with XIP. 1083 */ 1084 1085 #else 1086 1087 #define xip_disable(map, chip, adr) 1088 #define xip_enable(map, chip, adr) 1089 #define XIP_INVAL_CACHED_RANGE(x...) 1090 1091 #define UDELAY(map, chip, adr, usec) \ 1092 do { \ 1093 mutex_unlock(&chip->mutex); \ 1094 cfi_udelay(usec); \ 1095 mutex_lock(&chip->mutex); \ 1096 } while (0) 1097 1098 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \ 1099 do { \ 1100 mutex_unlock(&chip->mutex); \ 1101 INVALIDATE_CACHED_RANGE(map, adr, len); \ 1102 cfi_udelay(usec); \ 1103 mutex_lock(&chip->mutex); \ 1104 } while (0) 1105 1106 #endif 1107 1108 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf) 1109 { 1110 unsigned long cmd_addr; 1111 struct cfi_private *cfi = map->fldrv_priv; 1112 int ret; 1113 1114 adr += chip->start; 1115 1116 /* Ensure cmd read/writes are aligned. */ 1117 cmd_addr = adr & ~(map_bankwidth(map)-1); 1118 1119 mutex_lock(&chip->mutex); 1120 ret = get_chip(map, chip, cmd_addr, FL_READY); 1121 if (ret) { 1122 mutex_unlock(&chip->mutex); 1123 return ret; 1124 } 1125 1126 if (chip->state != FL_POINT && chip->state != FL_READY) { 1127 map_write(map, CMD(0xf0), cmd_addr); 1128 chip->state = FL_READY; 1129 } 1130 1131 map_copy_from(map, buf, adr, len); 1132 1133 put_chip(map, chip, cmd_addr); 1134 1135 mutex_unlock(&chip->mutex); 1136 return 0; 1137 } 1138 1139 1140 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1141 { 1142 struct map_info *map = mtd->priv; 1143 struct cfi_private *cfi = map->fldrv_priv; 1144 unsigned long ofs; 1145 int chipnum; 1146 int ret = 0; 1147 1148 /* ofs: offset within the first chip that the first read should start */ 1149 chipnum = (from >> cfi->chipshift); 1150 ofs = from - (chipnum << cfi->chipshift); 1151 1152 while (len) { 1153 unsigned long thislen; 1154 1155 if (chipnum >= cfi->numchips) 1156 break; 1157 1158 if ((len + ofs -1) >> cfi->chipshift) 1159 thislen = (1<<cfi->chipshift) - ofs; 1160 else 1161 thislen = len; 1162 1163 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf); 1164 if (ret) 1165 break; 1166 1167 *retlen += thislen; 1168 len -= thislen; 1169 buf += thislen; 1170 1171 ofs = 0; 1172 chipnum++; 1173 } 1174 return ret; 1175 } 1176 1177 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip, 1178 loff_t adr, size_t len, u_char *buf, size_t grouplen); 1179 1180 static inline void otp_enter(struct map_info *map, struct flchip *chip, 1181 loff_t adr, size_t len) 1182 { 1183 struct cfi_private *cfi = map->fldrv_priv; 1184 1185 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1186 cfi->device_type, NULL); 1187 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1188 cfi->device_type, NULL); 1189 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, 1190 cfi->device_type, NULL); 1191 1192 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1193 } 1194 1195 static inline void otp_exit(struct map_info *map, struct flchip *chip, 1196 loff_t adr, size_t len) 1197 { 1198 struct cfi_private *cfi = map->fldrv_priv; 1199 1200 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1201 cfi->device_type, NULL); 1202 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1203 cfi->device_type, NULL); 1204 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, 1205 cfi->device_type, NULL); 1206 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, 1207 cfi->device_type, NULL); 1208 1209 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len); 1210 } 1211 1212 static inline int do_read_secsi_onechip(struct map_info *map, 1213 struct flchip *chip, loff_t adr, 1214 size_t len, u_char *buf, 1215 size_t grouplen) 1216 { 1217 DECLARE_WAITQUEUE(wait, current); 1218 unsigned long timeo = jiffies + HZ; 1219 1220 retry: 1221 mutex_lock(&chip->mutex); 1222 1223 if (chip->state != FL_READY){ 1224 set_current_state(TASK_UNINTERRUPTIBLE); 1225 add_wait_queue(&chip->wq, &wait); 1226 1227 mutex_unlock(&chip->mutex); 1228 1229 schedule(); 1230 remove_wait_queue(&chip->wq, &wait); 1231 timeo = jiffies + HZ; 1232 1233 goto retry; 1234 } 1235 1236 adr += chip->start; 1237 1238 chip->state = FL_READY; 1239 1240 otp_enter(map, chip, adr, len); 1241 map_copy_from(map, buf, adr, len); 1242 otp_exit(map, chip, adr, len); 1243 1244 wake_up(&chip->wq); 1245 mutex_unlock(&chip->mutex); 1246 1247 return 0; 1248 } 1249 1250 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) 1251 { 1252 struct map_info *map = mtd->priv; 1253 struct cfi_private *cfi = map->fldrv_priv; 1254 unsigned long ofs; 1255 int chipnum; 1256 int ret = 0; 1257 1258 /* ofs: offset within the first chip that the first read should start */ 1259 /* 8 secsi bytes per chip */ 1260 chipnum=from>>3; 1261 ofs=from & 7; 1262 1263 while (len) { 1264 unsigned long thislen; 1265 1266 if (chipnum >= cfi->numchips) 1267 break; 1268 1269 if ((len + ofs -1) >> 3) 1270 thislen = (1<<3) - ofs; 1271 else 1272 thislen = len; 1273 1274 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, 1275 thislen, buf, 0); 1276 if (ret) 1277 break; 1278 1279 *retlen += thislen; 1280 len -= thislen; 1281 buf += thislen; 1282 1283 ofs = 0; 1284 chipnum++; 1285 } 1286 return ret; 1287 } 1288 1289 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1290 unsigned long adr, map_word datum, 1291 int mode); 1292 1293 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr, 1294 size_t len, u_char *buf, size_t grouplen) 1295 { 1296 int ret; 1297 while (len) { 1298 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1); 1299 int gap = adr - bus_ofs; 1300 int n = min_t(int, len, map_bankwidth(map) - gap); 1301 map_word datum = map_word_ff(map); 1302 1303 if (n != map_bankwidth(map)) { 1304 /* partial write of a word, load old contents */ 1305 otp_enter(map, chip, bus_ofs, map_bankwidth(map)); 1306 datum = map_read(map, bus_ofs); 1307 otp_exit(map, chip, bus_ofs, map_bankwidth(map)); 1308 } 1309 1310 datum = map_word_load_partial(map, datum, buf, gap, n); 1311 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE); 1312 if (ret) 1313 return ret; 1314 1315 adr += n; 1316 buf += n; 1317 len -= n; 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr, 1324 size_t len, u_char *buf, size_t grouplen) 1325 { 1326 struct cfi_private *cfi = map->fldrv_priv; 1327 uint8_t lockreg; 1328 unsigned long timeo; 1329 int ret; 1330 1331 /* make sure area matches group boundaries */ 1332 if ((adr != 0) || (len != grouplen)) 1333 return -EINVAL; 1334 1335 mutex_lock(&chip->mutex); 1336 ret = get_chip(map, chip, chip->start, FL_LOCKING); 1337 if (ret) { 1338 mutex_unlock(&chip->mutex); 1339 return ret; 1340 } 1341 chip->state = FL_LOCKING; 1342 1343 /* Enter lock register command */ 1344 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1345 cfi->device_type, NULL); 1346 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1347 cfi->device_type, NULL); 1348 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi, 1349 cfi->device_type, NULL); 1350 1351 /* read lock register */ 1352 lockreg = cfi_read_query(map, 0); 1353 1354 /* set bit 0 to protect extended memory block */ 1355 lockreg &= ~0x01; 1356 1357 /* set bit 0 to protect extended memory block */ 1358 /* write lock register */ 1359 map_write(map, CMD(0xA0), chip->start); 1360 map_write(map, CMD(lockreg), chip->start); 1361 1362 /* wait for chip to become ready */ 1363 timeo = jiffies + msecs_to_jiffies(2); 1364 for (;;) { 1365 if (chip_ready(map, adr)) 1366 break; 1367 1368 if (time_after(jiffies, timeo)) { 1369 pr_err("Waiting for chip to be ready timed out.\n"); 1370 ret = -EIO; 1371 break; 1372 } 1373 UDELAY(map, chip, 0, 1); 1374 } 1375 1376 /* exit protection commands */ 1377 map_write(map, CMD(0x90), chip->start); 1378 map_write(map, CMD(0x00), chip->start); 1379 1380 chip->state = FL_READY; 1381 put_chip(map, chip, chip->start); 1382 mutex_unlock(&chip->mutex); 1383 1384 return ret; 1385 } 1386 1387 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, 1388 size_t *retlen, u_char *buf, 1389 otp_op_t action, int user_regs) 1390 { 1391 struct map_info *map = mtd->priv; 1392 struct cfi_private *cfi = map->fldrv_priv; 1393 int ofs_factor = cfi->interleave * cfi->device_type; 1394 unsigned long base; 1395 int chipnum; 1396 struct flchip *chip; 1397 uint8_t otp, lockreg; 1398 int ret; 1399 1400 size_t user_size, factory_size, otpsize; 1401 loff_t user_offset, factory_offset, otpoffset; 1402 int user_locked = 0, otplocked; 1403 1404 *retlen = 0; 1405 1406 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) { 1407 chip = &cfi->chips[chipnum]; 1408 factory_size = 0; 1409 user_size = 0; 1410 1411 /* Micron M29EW family */ 1412 if (is_m29ew(cfi)) { 1413 base = chip->start; 1414 1415 /* check whether secsi area is factory locked 1416 or user lockable */ 1417 mutex_lock(&chip->mutex); 1418 ret = get_chip(map, chip, base, FL_CFI_QUERY); 1419 if (ret) { 1420 mutex_unlock(&chip->mutex); 1421 return ret; 1422 } 1423 cfi_qry_mode_on(base, map, cfi); 1424 otp = cfi_read_query(map, base + 0x3 * ofs_factor); 1425 cfi_qry_mode_off(base, map, cfi); 1426 put_chip(map, chip, base); 1427 mutex_unlock(&chip->mutex); 1428 1429 if (otp & 0x80) { 1430 /* factory locked */ 1431 factory_offset = 0; 1432 factory_size = 0x100; 1433 } else { 1434 /* customer lockable */ 1435 user_offset = 0; 1436 user_size = 0x100; 1437 1438 mutex_lock(&chip->mutex); 1439 ret = get_chip(map, chip, base, FL_LOCKING); 1440 if (ret) { 1441 mutex_unlock(&chip->mutex); 1442 return ret; 1443 } 1444 1445 /* Enter lock register command */ 1446 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, 1447 chip->start, map, cfi, 1448 cfi->device_type, NULL); 1449 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, 1450 chip->start, map, cfi, 1451 cfi->device_type, NULL); 1452 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, 1453 chip->start, map, cfi, 1454 cfi->device_type, NULL); 1455 /* read lock register */ 1456 lockreg = cfi_read_query(map, 0); 1457 /* exit protection commands */ 1458 map_write(map, CMD(0x90), chip->start); 1459 map_write(map, CMD(0x00), chip->start); 1460 put_chip(map, chip, chip->start); 1461 mutex_unlock(&chip->mutex); 1462 1463 user_locked = ((lockreg & 0x01) == 0x00); 1464 } 1465 } 1466 1467 otpsize = user_regs ? user_size : factory_size; 1468 if (!otpsize) 1469 continue; 1470 otpoffset = user_regs ? user_offset : factory_offset; 1471 otplocked = user_regs ? user_locked : 1; 1472 1473 if (!action) { 1474 /* return otpinfo */ 1475 struct otp_info *otpinfo; 1476 len -= sizeof(*otpinfo); 1477 if (len <= 0) 1478 return -ENOSPC; 1479 otpinfo = (struct otp_info *)buf; 1480 otpinfo->start = from; 1481 otpinfo->length = otpsize; 1482 otpinfo->locked = otplocked; 1483 buf += sizeof(*otpinfo); 1484 *retlen += sizeof(*otpinfo); 1485 from += otpsize; 1486 } else if ((from < otpsize) && (len > 0)) { 1487 size_t size; 1488 size = (len < otpsize - from) ? len : otpsize - from; 1489 ret = action(map, chip, otpoffset + from, size, buf, 1490 otpsize); 1491 if (ret < 0) 1492 return ret; 1493 1494 buf += size; 1495 len -= size; 1496 *retlen += size; 1497 from = 0; 1498 } else { 1499 from -= otpsize; 1500 } 1501 } 1502 return 0; 1503 } 1504 1505 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len, 1506 size_t *retlen, struct otp_info *buf) 1507 { 1508 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1509 NULL, 0); 1510 } 1511 1512 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len, 1513 size_t *retlen, struct otp_info *buf) 1514 { 1515 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf, 1516 NULL, 1); 1517 } 1518 1519 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, 1520 size_t len, size_t *retlen, 1521 u_char *buf) 1522 { 1523 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1524 buf, do_read_secsi_onechip, 0); 1525 } 1526 1527 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, 1528 size_t len, size_t *retlen, 1529 u_char *buf) 1530 { 1531 return cfi_amdstd_otp_walk(mtd, from, len, retlen, 1532 buf, do_read_secsi_onechip, 1); 1533 } 1534 1535 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from, 1536 size_t len, size_t *retlen, 1537 u_char *buf) 1538 { 1539 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf, 1540 do_otp_write, 1); 1541 } 1542 1543 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, 1544 size_t len) 1545 { 1546 size_t retlen; 1547 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL, 1548 do_otp_lock, 1); 1549 } 1550 1551 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, 1552 unsigned long adr, map_word datum, 1553 int mode) 1554 { 1555 struct cfi_private *cfi = map->fldrv_priv; 1556 unsigned long timeo = jiffies + HZ; 1557 /* 1558 * We use a 1ms + 1 jiffies generic timeout for writes (most devices 1559 * have a max write time of a few hundreds usec). However, we should 1560 * use the maximum timeout value given by the chip at probe time 1561 * instead. Unfortunately, struct flchip does have a field for 1562 * maximum timeout, only for typical which can be far too short 1563 * depending of the conditions. The ' + 1' is to avoid having a 1564 * timeout of 0 jiffies if HZ is smaller than 1000. 1565 */ 1566 unsigned long uWriteTimeout = (HZ / 1000) + 1; 1567 int ret = 0; 1568 map_word oldd; 1569 int retry_cnt = 0; 1570 1571 adr += chip->start; 1572 1573 mutex_lock(&chip->mutex); 1574 ret = get_chip(map, chip, adr, mode); 1575 if (ret) { 1576 mutex_unlock(&chip->mutex); 1577 return ret; 1578 } 1579 1580 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1581 __func__, adr, datum.x[0]); 1582 1583 if (mode == FL_OTP_WRITE) 1584 otp_enter(map, chip, adr, map_bankwidth(map)); 1585 1586 /* 1587 * Check for a NOP for the case when the datum to write is already 1588 * present - it saves time and works around buggy chips that corrupt 1589 * data at other locations when 0xff is written to a location that 1590 * already contains 0xff. 1591 */ 1592 oldd = map_read(map, adr); 1593 if (map_word_equal(map, oldd, datum)) { 1594 pr_debug("MTD %s(): NOP\n", 1595 __func__); 1596 goto op_done; 1597 } 1598 1599 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map)); 1600 ENABLE_VPP(map); 1601 xip_disable(map, chip, adr); 1602 1603 retry: 1604 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1605 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1606 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1607 map_write(map, datum, adr); 1608 chip->state = mode; 1609 1610 INVALIDATE_CACHE_UDELAY(map, chip, 1611 adr, map_bankwidth(map), 1612 chip->word_write_time); 1613 1614 /* See comment above for timeout value. */ 1615 timeo = jiffies + uWriteTimeout; 1616 for (;;) { 1617 if (chip->state != mode) { 1618 /* Someone's suspended the write. Sleep */ 1619 DECLARE_WAITQUEUE(wait, current); 1620 1621 set_current_state(TASK_UNINTERRUPTIBLE); 1622 add_wait_queue(&chip->wq, &wait); 1623 mutex_unlock(&chip->mutex); 1624 schedule(); 1625 remove_wait_queue(&chip->wq, &wait); 1626 timeo = jiffies + (HZ / 2); /* FIXME */ 1627 mutex_lock(&chip->mutex); 1628 continue; 1629 } 1630 1631 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){ 1632 xip_enable(map, chip, adr); 1633 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__); 1634 xip_disable(map, chip, adr); 1635 break; 1636 } 1637 1638 if (chip_ready(map, adr)) 1639 break; 1640 1641 /* Latency issues. Drop the lock, wait a while and retry */ 1642 UDELAY(map, chip, adr, 1); 1643 } 1644 /* Did we succeed? */ 1645 if (!chip_good(map, adr, datum)) { 1646 /* reset on all failures. */ 1647 map_write(map, CMD(0xF0), chip->start); 1648 /* FIXME - should have reset delay before continuing */ 1649 1650 if (++retry_cnt <= MAX_RETRIES) 1651 goto retry; 1652 1653 ret = -EIO; 1654 } 1655 xip_enable(map, chip, adr); 1656 op_done: 1657 if (mode == FL_OTP_WRITE) 1658 otp_exit(map, chip, adr, map_bankwidth(map)); 1659 chip->state = FL_READY; 1660 DISABLE_VPP(map); 1661 put_chip(map, chip, adr); 1662 mutex_unlock(&chip->mutex); 1663 1664 return ret; 1665 } 1666 1667 1668 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len, 1669 size_t *retlen, const u_char *buf) 1670 { 1671 struct map_info *map = mtd->priv; 1672 struct cfi_private *cfi = map->fldrv_priv; 1673 int ret = 0; 1674 int chipnum; 1675 unsigned long ofs, chipstart; 1676 DECLARE_WAITQUEUE(wait, current); 1677 1678 chipnum = to >> cfi->chipshift; 1679 ofs = to - (chipnum << cfi->chipshift); 1680 chipstart = cfi->chips[chipnum].start; 1681 1682 /* If it's not bus-aligned, do the first byte write */ 1683 if (ofs & (map_bankwidth(map)-1)) { 1684 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1); 1685 int i = ofs - bus_ofs; 1686 int n = 0; 1687 map_word tmp_buf; 1688 1689 retry: 1690 mutex_lock(&cfi->chips[chipnum].mutex); 1691 1692 if (cfi->chips[chipnum].state != FL_READY) { 1693 set_current_state(TASK_UNINTERRUPTIBLE); 1694 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1695 1696 mutex_unlock(&cfi->chips[chipnum].mutex); 1697 1698 schedule(); 1699 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1700 goto retry; 1701 } 1702 1703 /* Load 'tmp_buf' with old contents of flash */ 1704 tmp_buf = map_read(map, bus_ofs+chipstart); 1705 1706 mutex_unlock(&cfi->chips[chipnum].mutex); 1707 1708 /* Number of bytes to copy from buffer */ 1709 n = min_t(int, len, map_bankwidth(map)-i); 1710 1711 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 1712 1713 ret = do_write_oneword(map, &cfi->chips[chipnum], 1714 bus_ofs, tmp_buf, FL_WRITING); 1715 if (ret) 1716 return ret; 1717 1718 ofs += n; 1719 buf += n; 1720 (*retlen) += n; 1721 len -= n; 1722 1723 if (ofs >> cfi->chipshift) { 1724 chipnum ++; 1725 ofs = 0; 1726 if (chipnum == cfi->numchips) 1727 return 0; 1728 } 1729 } 1730 1731 /* We are now aligned, write as much as possible */ 1732 while(len >= map_bankwidth(map)) { 1733 map_word datum; 1734 1735 datum = map_word_load(map, buf); 1736 1737 ret = do_write_oneword(map, &cfi->chips[chipnum], 1738 ofs, datum, FL_WRITING); 1739 if (ret) 1740 return ret; 1741 1742 ofs += map_bankwidth(map); 1743 buf += map_bankwidth(map); 1744 (*retlen) += map_bankwidth(map); 1745 len -= map_bankwidth(map); 1746 1747 if (ofs >> cfi->chipshift) { 1748 chipnum ++; 1749 ofs = 0; 1750 if (chipnum == cfi->numchips) 1751 return 0; 1752 chipstart = cfi->chips[chipnum].start; 1753 } 1754 } 1755 1756 /* Write the trailing bytes if any */ 1757 if (len & (map_bankwidth(map)-1)) { 1758 map_word tmp_buf; 1759 1760 retry1: 1761 mutex_lock(&cfi->chips[chipnum].mutex); 1762 1763 if (cfi->chips[chipnum].state != FL_READY) { 1764 set_current_state(TASK_UNINTERRUPTIBLE); 1765 add_wait_queue(&cfi->chips[chipnum].wq, &wait); 1766 1767 mutex_unlock(&cfi->chips[chipnum].mutex); 1768 1769 schedule(); 1770 remove_wait_queue(&cfi->chips[chipnum].wq, &wait); 1771 goto retry1; 1772 } 1773 1774 tmp_buf = map_read(map, ofs + chipstart); 1775 1776 mutex_unlock(&cfi->chips[chipnum].mutex); 1777 1778 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 1779 1780 ret = do_write_oneword(map, &cfi->chips[chipnum], 1781 ofs, tmp_buf, FL_WRITING); 1782 if (ret) 1783 return ret; 1784 1785 (*retlen) += len; 1786 } 1787 1788 return 0; 1789 } 1790 1791 1792 /* 1793 * FIXME: interleaved mode not tested, and probably not supported! 1794 */ 1795 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, 1796 unsigned long adr, const u_char *buf, 1797 int len) 1798 { 1799 struct cfi_private *cfi = map->fldrv_priv; 1800 unsigned long timeo = jiffies + HZ; 1801 /* 1802 * Timeout is calculated according to CFI data, if available. 1803 * See more comments in cfi_cmdset_0002(). 1804 */ 1805 unsigned long uWriteTimeout = 1806 usecs_to_jiffies(chip->buffer_write_time_max); 1807 int ret = -EIO; 1808 unsigned long cmd_adr; 1809 int z, words; 1810 map_word datum; 1811 1812 adr += chip->start; 1813 cmd_adr = adr; 1814 1815 mutex_lock(&chip->mutex); 1816 ret = get_chip(map, chip, adr, FL_WRITING); 1817 if (ret) { 1818 mutex_unlock(&chip->mutex); 1819 return ret; 1820 } 1821 1822 datum = map_word_load(map, buf); 1823 1824 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n", 1825 __func__, adr, datum.x[0]); 1826 1827 XIP_INVAL_CACHED_RANGE(map, adr, len); 1828 ENABLE_VPP(map); 1829 xip_disable(map, chip, cmd_adr); 1830 1831 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 1832 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 1833 1834 /* Write Buffer Load */ 1835 map_write(map, CMD(0x25), cmd_adr); 1836 1837 chip->state = FL_WRITING_TO_BUFFER; 1838 1839 /* Write length of data to come */ 1840 words = len / map_bankwidth(map); 1841 map_write(map, CMD(words - 1), cmd_adr); 1842 /* Write data */ 1843 z = 0; 1844 while(z < words * map_bankwidth(map)) { 1845 datum = map_word_load(map, buf); 1846 map_write(map, datum, adr + z); 1847 1848 z += map_bankwidth(map); 1849 buf += map_bankwidth(map); 1850 } 1851 z -= map_bankwidth(map); 1852 1853 adr += z; 1854 1855 /* Write Buffer Program Confirm: GO GO GO */ 1856 map_write(map, CMD(0x29), cmd_adr); 1857 chip->state = FL_WRITING; 1858 1859 INVALIDATE_CACHE_UDELAY(map, chip, 1860 adr, map_bankwidth(map), 1861 chip->word_write_time); 1862 1863 timeo = jiffies + uWriteTimeout; 1864 1865 for (;;) { 1866 if (chip->state != FL_WRITING) { 1867 /* Someone's suspended the write. Sleep */ 1868 DECLARE_WAITQUEUE(wait, current); 1869 1870 set_current_state(TASK_UNINTERRUPTIBLE); 1871 add_wait_queue(&chip->wq, &wait); 1872 mutex_unlock(&chip->mutex); 1873 schedule(); 1874 remove_wait_queue(&chip->wq, &wait); 1875 timeo = jiffies + (HZ / 2); /* FIXME */ 1876 mutex_lock(&chip->mutex); 1877 continue; 1878 } 1879 1880 if (time_after(jiffies, timeo) && !chip_ready(map, adr)) 1881 break; 1882 1883 if (chip_good(map, adr, datum)) { 1884 xip_enable(map, chip, adr); 1885 goto op_done; 1886 } 1887 1888 /* Latency issues. Drop the lock, wait a while and retry */ 1889 UDELAY(map, chip, adr, 1); 1890 } 1891 1892 /* 1893 * Recovery from write-buffer programming failures requires 1894 * the write-to-buffer-reset sequence. Since the last part 1895 * of the sequence also works as a normal reset, we can run 1896 * the same commands regardless of why we are here. 1897 * See e.g. 1898 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf 1899 */ 1900 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 1901 cfi->device_type, NULL); 1902 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 1903 cfi->device_type, NULL); 1904 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi, 1905 cfi->device_type, NULL); 1906 xip_enable(map, chip, adr); 1907 /* FIXME - should have reset delay before continuing */ 1908 1909 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n", 1910 __func__, adr); 1911 1912 ret = -EIO; 1913 op_done: 1914 chip->state = FL_READY; 1915 DISABLE_VPP(map); 1916 put_chip(map, chip, adr); 1917 mutex_unlock(&chip->mutex); 1918 1919 return ret; 1920 } 1921 1922 1923 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, 1924 size_t *retlen, const u_char *buf) 1925 { 1926 struct map_info *map = mtd->priv; 1927 struct cfi_private *cfi = map->fldrv_priv; 1928 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize; 1929 int ret = 0; 1930 int chipnum; 1931 unsigned long ofs; 1932 1933 chipnum = to >> cfi->chipshift; 1934 ofs = to - (chipnum << cfi->chipshift); 1935 1936 /* If it's not bus-aligned, do the first word write */ 1937 if (ofs & (map_bankwidth(map)-1)) { 1938 size_t local_len = (-ofs)&(map_bankwidth(map)-1); 1939 if (local_len > len) 1940 local_len = len; 1941 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1942 local_len, retlen, buf); 1943 if (ret) 1944 return ret; 1945 ofs += local_len; 1946 buf += local_len; 1947 len -= local_len; 1948 1949 if (ofs >> cfi->chipshift) { 1950 chipnum ++; 1951 ofs = 0; 1952 if (chipnum == cfi->numchips) 1953 return 0; 1954 } 1955 } 1956 1957 /* Write buffer is worth it only if more than one word to write... */ 1958 while (len >= map_bankwidth(map) * 2) { 1959 /* We must not cross write block boundaries */ 1960 int size = wbufsize - (ofs & (wbufsize-1)); 1961 1962 if (size > len) 1963 size = len; 1964 if (size % map_bankwidth(map)) 1965 size -= size % map_bankwidth(map); 1966 1967 ret = do_write_buffer(map, &cfi->chips[chipnum], 1968 ofs, buf, size); 1969 if (ret) 1970 return ret; 1971 1972 ofs += size; 1973 buf += size; 1974 (*retlen) += size; 1975 len -= size; 1976 1977 if (ofs >> cfi->chipshift) { 1978 chipnum ++; 1979 ofs = 0; 1980 if (chipnum == cfi->numchips) 1981 return 0; 1982 } 1983 } 1984 1985 if (len) { 1986 size_t retlen_dregs = 0; 1987 1988 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift), 1989 len, &retlen_dregs, buf); 1990 1991 *retlen += retlen_dregs; 1992 return ret; 1993 } 1994 1995 return 0; 1996 } 1997 1998 /* 1999 * Wait for the flash chip to become ready to write data 2000 * 2001 * This is only called during the panic_write() path. When panic_write() 2002 * is called, the kernel is in the process of a panic, and will soon be 2003 * dead. Therefore we don't take any locks, and attempt to get access 2004 * to the chip as soon as possible. 2005 */ 2006 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip, 2007 unsigned long adr) 2008 { 2009 struct cfi_private *cfi = map->fldrv_priv; 2010 int retries = 10; 2011 int i; 2012 2013 /* 2014 * If the driver thinks the chip is idle, and no toggle bits 2015 * are changing, then the chip is actually idle for sure. 2016 */ 2017 if (chip->state == FL_READY && chip_ready(map, adr)) 2018 return 0; 2019 2020 /* 2021 * Try several times to reset the chip and then wait for it 2022 * to become idle. The upper limit of a few milliseconds of 2023 * delay isn't a big problem: the kernel is dying anyway. It 2024 * is more important to save the messages. 2025 */ 2026 while (retries > 0) { 2027 const unsigned long timeo = (HZ / 1000) + 1; 2028 2029 /* send the reset command */ 2030 map_write(map, CMD(0xF0), chip->start); 2031 2032 /* wait for the chip to become ready */ 2033 for (i = 0; i < jiffies_to_usecs(timeo); i++) { 2034 if (chip_ready(map, adr)) 2035 return 0; 2036 2037 udelay(1); 2038 } 2039 2040 retries--; 2041 } 2042 2043 /* the chip never became ready */ 2044 return -EBUSY; 2045 } 2046 2047 /* 2048 * Write out one word of data to a single flash chip during a kernel panic 2049 * 2050 * This is only called during the panic_write() path. When panic_write() 2051 * is called, the kernel is in the process of a panic, and will soon be 2052 * dead. Therefore we don't take any locks, and attempt to get access 2053 * to the chip as soon as possible. 2054 * 2055 * The implementation of this routine is intentionally similar to 2056 * do_write_oneword(), in order to ease code maintenance. 2057 */ 2058 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip, 2059 unsigned long adr, map_word datum) 2060 { 2061 const unsigned long uWriteTimeout = (HZ / 1000) + 1; 2062 struct cfi_private *cfi = map->fldrv_priv; 2063 int retry_cnt = 0; 2064 map_word oldd; 2065 int ret = 0; 2066 int i; 2067 2068 adr += chip->start; 2069 2070 ret = cfi_amdstd_panic_wait(map, chip, adr); 2071 if (ret) 2072 return ret; 2073 2074 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n", 2075 __func__, adr, datum.x[0]); 2076 2077 /* 2078 * Check for a NOP for the case when the datum to write is already 2079 * present - it saves time and works around buggy chips that corrupt 2080 * data at other locations when 0xff is written to a location that 2081 * already contains 0xff. 2082 */ 2083 oldd = map_read(map, adr); 2084 if (map_word_equal(map, oldd, datum)) { 2085 pr_debug("MTD %s(): NOP\n", __func__); 2086 goto op_done; 2087 } 2088 2089 ENABLE_VPP(map); 2090 2091 retry: 2092 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2093 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2094 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2095 map_write(map, datum, adr); 2096 2097 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) { 2098 if (chip_ready(map, adr)) 2099 break; 2100 2101 udelay(1); 2102 } 2103 2104 if (!chip_good(map, adr, datum)) { 2105 /* reset on all failures. */ 2106 map_write(map, CMD(0xF0), chip->start); 2107 /* FIXME - should have reset delay before continuing */ 2108 2109 if (++retry_cnt <= MAX_RETRIES) 2110 goto retry; 2111 2112 ret = -EIO; 2113 } 2114 2115 op_done: 2116 DISABLE_VPP(map); 2117 return ret; 2118 } 2119 2120 /* 2121 * Write out some data during a kernel panic 2122 * 2123 * This is used by the mtdoops driver to save the dying messages from a 2124 * kernel which has panic'd. 2125 * 2126 * This routine ignores all of the locking used throughout the rest of the 2127 * driver, in order to ensure that the data gets written out no matter what 2128 * state this driver (and the flash chip itself) was in when the kernel crashed. 2129 * 2130 * The implementation of this routine is intentionally similar to 2131 * cfi_amdstd_write_words(), in order to ease code maintenance. 2132 */ 2133 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 2134 size_t *retlen, const u_char *buf) 2135 { 2136 struct map_info *map = mtd->priv; 2137 struct cfi_private *cfi = map->fldrv_priv; 2138 unsigned long ofs, chipstart; 2139 int ret = 0; 2140 int chipnum; 2141 2142 chipnum = to >> cfi->chipshift; 2143 ofs = to - (chipnum << cfi->chipshift); 2144 chipstart = cfi->chips[chipnum].start; 2145 2146 /* If it's not bus aligned, do the first byte write */ 2147 if (ofs & (map_bankwidth(map) - 1)) { 2148 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1); 2149 int i = ofs - bus_ofs; 2150 int n = 0; 2151 map_word tmp_buf; 2152 2153 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs); 2154 if (ret) 2155 return ret; 2156 2157 /* Load 'tmp_buf' with old contents of flash */ 2158 tmp_buf = map_read(map, bus_ofs + chipstart); 2159 2160 /* Number of bytes to copy from buffer */ 2161 n = min_t(int, len, map_bankwidth(map) - i); 2162 2163 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n); 2164 2165 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2166 bus_ofs, tmp_buf); 2167 if (ret) 2168 return ret; 2169 2170 ofs += n; 2171 buf += n; 2172 (*retlen) += n; 2173 len -= n; 2174 2175 if (ofs >> cfi->chipshift) { 2176 chipnum++; 2177 ofs = 0; 2178 if (chipnum == cfi->numchips) 2179 return 0; 2180 } 2181 } 2182 2183 /* We are now aligned, write as much as possible */ 2184 while (len >= map_bankwidth(map)) { 2185 map_word datum; 2186 2187 datum = map_word_load(map, buf); 2188 2189 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2190 ofs, datum); 2191 if (ret) 2192 return ret; 2193 2194 ofs += map_bankwidth(map); 2195 buf += map_bankwidth(map); 2196 (*retlen) += map_bankwidth(map); 2197 len -= map_bankwidth(map); 2198 2199 if (ofs >> cfi->chipshift) { 2200 chipnum++; 2201 ofs = 0; 2202 if (chipnum == cfi->numchips) 2203 return 0; 2204 2205 chipstart = cfi->chips[chipnum].start; 2206 } 2207 } 2208 2209 /* Write the trailing bytes if any */ 2210 if (len & (map_bankwidth(map) - 1)) { 2211 map_word tmp_buf; 2212 2213 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs); 2214 if (ret) 2215 return ret; 2216 2217 tmp_buf = map_read(map, ofs + chipstart); 2218 2219 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len); 2220 2221 ret = do_panic_write_oneword(map, &cfi->chips[chipnum], 2222 ofs, tmp_buf); 2223 if (ret) 2224 return ret; 2225 2226 (*retlen) += len; 2227 } 2228 2229 return 0; 2230 } 2231 2232 2233 /* 2234 * Handle devices with one erase region, that only implement 2235 * the chip erase command. 2236 */ 2237 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip) 2238 { 2239 struct cfi_private *cfi = map->fldrv_priv; 2240 unsigned long timeo = jiffies + HZ; 2241 unsigned long int adr; 2242 DECLARE_WAITQUEUE(wait, current); 2243 int ret = 0; 2244 int retry_cnt = 0; 2245 2246 adr = cfi->addr_unlock1; 2247 2248 mutex_lock(&chip->mutex); 2249 ret = get_chip(map, chip, adr, FL_WRITING); 2250 if (ret) { 2251 mutex_unlock(&chip->mutex); 2252 return ret; 2253 } 2254 2255 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2256 __func__, chip->start); 2257 2258 XIP_INVAL_CACHED_RANGE(map, adr, map->size); 2259 ENABLE_VPP(map); 2260 xip_disable(map, chip, adr); 2261 2262 retry: 2263 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2264 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2265 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2266 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2267 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2268 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2269 2270 chip->state = FL_ERASING; 2271 chip->erase_suspended = 0; 2272 chip->in_progress_block_addr = adr; 2273 chip->in_progress_block_mask = ~(map->size - 1); 2274 2275 INVALIDATE_CACHE_UDELAY(map, chip, 2276 adr, map->size, 2277 chip->erase_time*500); 2278 2279 timeo = jiffies + (HZ*20); 2280 2281 for (;;) { 2282 if (chip->state != FL_ERASING) { 2283 /* Someone's suspended the erase. Sleep */ 2284 set_current_state(TASK_UNINTERRUPTIBLE); 2285 add_wait_queue(&chip->wq, &wait); 2286 mutex_unlock(&chip->mutex); 2287 schedule(); 2288 remove_wait_queue(&chip->wq, &wait); 2289 mutex_lock(&chip->mutex); 2290 continue; 2291 } 2292 if (chip->erase_suspended) { 2293 /* This erase was suspended and resumed. 2294 Adjust the timeout */ 2295 timeo = jiffies + (HZ*20); /* FIXME */ 2296 chip->erase_suspended = 0; 2297 } 2298 2299 if (chip_good(map, adr, map_word_ff(map))) 2300 break; 2301 2302 if (time_after(jiffies, timeo)) { 2303 printk(KERN_WARNING "MTD %s(): software timeout\n", 2304 __func__); 2305 ret = -EIO; 2306 break; 2307 } 2308 2309 /* Latency issues. Drop the lock, wait a while and retry */ 2310 UDELAY(map, chip, adr, 1000000/HZ); 2311 } 2312 /* Did we succeed? */ 2313 if (ret) { 2314 /* reset on all failures. */ 2315 map_write(map, CMD(0xF0), chip->start); 2316 /* FIXME - should have reset delay before continuing */ 2317 2318 if (++retry_cnt <= MAX_RETRIES) { 2319 ret = 0; 2320 goto retry; 2321 } 2322 } 2323 2324 chip->state = FL_READY; 2325 xip_enable(map, chip, adr); 2326 DISABLE_VPP(map); 2327 put_chip(map, chip, adr); 2328 mutex_unlock(&chip->mutex); 2329 2330 return ret; 2331 } 2332 2333 2334 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk) 2335 { 2336 struct cfi_private *cfi = map->fldrv_priv; 2337 unsigned long timeo = jiffies + HZ; 2338 DECLARE_WAITQUEUE(wait, current); 2339 int ret = 0; 2340 int retry_cnt = 0; 2341 2342 adr += chip->start; 2343 2344 mutex_lock(&chip->mutex); 2345 ret = get_chip(map, chip, adr, FL_ERASING); 2346 if (ret) { 2347 mutex_unlock(&chip->mutex); 2348 return ret; 2349 } 2350 2351 pr_debug("MTD %s(): ERASE 0x%.8lx\n", 2352 __func__, adr); 2353 2354 XIP_INVAL_CACHED_RANGE(map, adr, len); 2355 ENABLE_VPP(map); 2356 xip_disable(map, chip, adr); 2357 2358 retry: 2359 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2360 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2361 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2362 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); 2363 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); 2364 map_write(map, cfi->sector_erase_cmd, adr); 2365 2366 chip->state = FL_ERASING; 2367 chip->erase_suspended = 0; 2368 chip->in_progress_block_addr = adr; 2369 chip->in_progress_block_mask = ~(len - 1); 2370 2371 INVALIDATE_CACHE_UDELAY(map, chip, 2372 adr, len, 2373 chip->erase_time*500); 2374 2375 timeo = jiffies + (HZ*20); 2376 2377 for (;;) { 2378 if (chip->state != FL_ERASING) { 2379 /* Someone's suspended the erase. Sleep */ 2380 set_current_state(TASK_UNINTERRUPTIBLE); 2381 add_wait_queue(&chip->wq, &wait); 2382 mutex_unlock(&chip->mutex); 2383 schedule(); 2384 remove_wait_queue(&chip->wq, &wait); 2385 mutex_lock(&chip->mutex); 2386 continue; 2387 } 2388 if (chip->erase_suspended) { 2389 /* This erase was suspended and resumed. 2390 Adjust the timeout */ 2391 timeo = jiffies + (HZ*20); /* FIXME */ 2392 chip->erase_suspended = 0; 2393 } 2394 2395 if (chip_good(map, adr, map_word_ff(map))) 2396 break; 2397 2398 if (time_after(jiffies, timeo)) { 2399 printk(KERN_WARNING "MTD %s(): software timeout\n", 2400 __func__); 2401 ret = -EIO; 2402 break; 2403 } 2404 2405 /* Latency issues. Drop the lock, wait a while and retry */ 2406 UDELAY(map, chip, adr, 1000000/HZ); 2407 } 2408 /* Did we succeed? */ 2409 if (ret) { 2410 /* reset on all failures. */ 2411 map_write(map, CMD(0xF0), chip->start); 2412 /* FIXME - should have reset delay before continuing */ 2413 2414 if (++retry_cnt <= MAX_RETRIES) { 2415 ret = 0; 2416 goto retry; 2417 } 2418 } 2419 2420 chip->state = FL_READY; 2421 xip_enable(map, chip, adr); 2422 DISABLE_VPP(map); 2423 put_chip(map, chip, adr); 2424 mutex_unlock(&chip->mutex); 2425 return ret; 2426 } 2427 2428 2429 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr) 2430 { 2431 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr, 2432 instr->len, NULL); 2433 } 2434 2435 2436 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr) 2437 { 2438 struct map_info *map = mtd->priv; 2439 struct cfi_private *cfi = map->fldrv_priv; 2440 2441 if (instr->addr != 0) 2442 return -EINVAL; 2443 2444 if (instr->len != mtd->size) 2445 return -EINVAL; 2446 2447 return do_erase_chip(map, &cfi->chips[0]); 2448 } 2449 2450 static int do_atmel_lock(struct map_info *map, struct flchip *chip, 2451 unsigned long adr, int len, void *thunk) 2452 { 2453 struct cfi_private *cfi = map->fldrv_priv; 2454 int ret; 2455 2456 mutex_lock(&chip->mutex); 2457 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); 2458 if (ret) 2459 goto out_unlock; 2460 chip->state = FL_LOCKING; 2461 2462 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2463 2464 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2465 cfi->device_type, NULL); 2466 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2467 cfi->device_type, NULL); 2468 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, 2469 cfi->device_type, NULL); 2470 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2471 cfi->device_type, NULL); 2472 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2473 cfi->device_type, NULL); 2474 map_write(map, CMD(0x40), chip->start + adr); 2475 2476 chip->state = FL_READY; 2477 put_chip(map, chip, adr + chip->start); 2478 ret = 0; 2479 2480 out_unlock: 2481 mutex_unlock(&chip->mutex); 2482 return ret; 2483 } 2484 2485 static int do_atmel_unlock(struct map_info *map, struct flchip *chip, 2486 unsigned long adr, int len, void *thunk) 2487 { 2488 struct cfi_private *cfi = map->fldrv_priv; 2489 int ret; 2490 2491 mutex_lock(&chip->mutex); 2492 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING); 2493 if (ret) 2494 goto out_unlock; 2495 chip->state = FL_UNLOCKING; 2496 2497 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len); 2498 2499 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2500 cfi->device_type, NULL); 2501 map_write(map, CMD(0x70), adr); 2502 2503 chip->state = FL_READY; 2504 put_chip(map, chip, adr + chip->start); 2505 ret = 0; 2506 2507 out_unlock: 2508 mutex_unlock(&chip->mutex); 2509 return ret; 2510 } 2511 2512 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2513 { 2514 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL); 2515 } 2516 2517 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 2518 { 2519 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL); 2520 } 2521 2522 /* 2523 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking 2524 */ 2525 2526 struct ppb_lock { 2527 struct flchip *chip; 2528 loff_t offset; 2529 int locked; 2530 }; 2531 2532 #define MAX_SECTORS 512 2533 2534 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1) 2535 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2) 2536 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3) 2537 2538 static int __maybe_unused do_ppb_xxlock(struct map_info *map, 2539 struct flchip *chip, 2540 unsigned long adr, int len, void *thunk) 2541 { 2542 struct cfi_private *cfi = map->fldrv_priv; 2543 unsigned long timeo; 2544 int ret; 2545 2546 mutex_lock(&chip->mutex); 2547 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); 2548 if (ret) { 2549 mutex_unlock(&chip->mutex); 2550 return ret; 2551 } 2552 2553 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len); 2554 2555 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, 2556 cfi->device_type, NULL); 2557 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, 2558 cfi->device_type, NULL); 2559 /* PPB entry command */ 2560 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi, 2561 cfi->device_type, NULL); 2562 2563 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) { 2564 chip->state = FL_LOCKING; 2565 map_write(map, CMD(0xA0), chip->start + adr); 2566 map_write(map, CMD(0x00), chip->start + adr); 2567 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) { 2568 /* 2569 * Unlocking of one specific sector is not supported, so we 2570 * have to unlock all sectors of this device instead 2571 */ 2572 chip->state = FL_UNLOCKING; 2573 map_write(map, CMD(0x80), chip->start); 2574 map_write(map, CMD(0x30), chip->start); 2575 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) { 2576 chip->state = FL_JEDEC_QUERY; 2577 /* Return locked status: 0->locked, 1->unlocked */ 2578 ret = !cfi_read_query(map, adr); 2579 } else 2580 BUG(); 2581 2582 /* 2583 * Wait for some time as unlocking of all sectors takes quite long 2584 */ 2585 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */ 2586 for (;;) { 2587 if (chip_ready(map, adr)) 2588 break; 2589 2590 if (time_after(jiffies, timeo)) { 2591 printk(KERN_ERR "Waiting for chip to be ready timed out.\n"); 2592 ret = -EIO; 2593 break; 2594 } 2595 2596 UDELAY(map, chip, adr, 1); 2597 } 2598 2599 /* Exit BC commands */ 2600 map_write(map, CMD(0x90), chip->start); 2601 map_write(map, CMD(0x00), chip->start); 2602 2603 chip->state = FL_READY; 2604 put_chip(map, chip, adr + chip->start); 2605 mutex_unlock(&chip->mutex); 2606 2607 return ret; 2608 } 2609 2610 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, 2611 uint64_t len) 2612 { 2613 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2614 DO_XXLOCK_ONEBLOCK_LOCK); 2615 } 2616 2617 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, 2618 uint64_t len) 2619 { 2620 struct mtd_erase_region_info *regions = mtd->eraseregions; 2621 struct map_info *map = mtd->priv; 2622 struct cfi_private *cfi = map->fldrv_priv; 2623 struct ppb_lock *sect; 2624 unsigned long adr; 2625 loff_t offset; 2626 uint64_t length; 2627 int chipnum; 2628 int i; 2629 int sectors; 2630 int ret; 2631 2632 /* 2633 * PPB unlocking always unlocks all sectors of the flash chip. 2634 * We need to re-lock all previously locked sectors. So lets 2635 * first check the locking status of all sectors and save 2636 * it for future use. 2637 */ 2638 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL); 2639 if (!sect) 2640 return -ENOMEM; 2641 2642 /* 2643 * This code to walk all sectors is a slightly modified version 2644 * of the cfi_varsize_frob() code. 2645 */ 2646 i = 0; 2647 chipnum = 0; 2648 adr = 0; 2649 sectors = 0; 2650 offset = 0; 2651 length = mtd->size; 2652 2653 while (length) { 2654 int size = regions[i].erasesize; 2655 2656 /* 2657 * Only test sectors that shall not be unlocked. The other 2658 * sectors shall be unlocked, so lets keep their locking 2659 * status at "unlocked" (locked=0) for the final re-locking. 2660 */ 2661 if ((adr < ofs) || (adr >= (ofs + len))) { 2662 sect[sectors].chip = &cfi->chips[chipnum]; 2663 sect[sectors].offset = offset; 2664 sect[sectors].locked = do_ppb_xxlock( 2665 map, &cfi->chips[chipnum], adr, 0, 2666 DO_XXLOCK_ONEBLOCK_GETLOCK); 2667 } 2668 2669 adr += size; 2670 offset += size; 2671 length -= size; 2672 2673 if (offset == regions[i].offset + size * regions[i].numblocks) 2674 i++; 2675 2676 if (adr >> cfi->chipshift) { 2677 adr = 0; 2678 chipnum++; 2679 2680 if (chipnum >= cfi->numchips) 2681 break; 2682 } 2683 2684 sectors++; 2685 if (sectors >= MAX_SECTORS) { 2686 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n", 2687 MAX_SECTORS); 2688 kfree(sect); 2689 return -EINVAL; 2690 } 2691 } 2692 2693 /* Now unlock the whole chip */ 2694 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2695 DO_XXLOCK_ONEBLOCK_UNLOCK); 2696 if (ret) { 2697 kfree(sect); 2698 return ret; 2699 } 2700 2701 /* 2702 * PPB unlocking always unlocks all sectors of the flash chip. 2703 * We need to re-lock all previously locked sectors. 2704 */ 2705 for (i = 0; i < sectors; i++) { 2706 if (sect[i].locked) 2707 do_ppb_xxlock(map, sect[i].chip, sect[i].offset, 0, 2708 DO_XXLOCK_ONEBLOCK_LOCK); 2709 } 2710 2711 kfree(sect); 2712 return ret; 2713 } 2714 2715 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, 2716 uint64_t len) 2717 { 2718 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len, 2719 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0; 2720 } 2721 2722 static void cfi_amdstd_sync (struct mtd_info *mtd) 2723 { 2724 struct map_info *map = mtd->priv; 2725 struct cfi_private *cfi = map->fldrv_priv; 2726 int i; 2727 struct flchip *chip; 2728 int ret = 0; 2729 DECLARE_WAITQUEUE(wait, current); 2730 2731 for (i=0; !ret && i<cfi->numchips; i++) { 2732 chip = &cfi->chips[i]; 2733 2734 retry: 2735 mutex_lock(&chip->mutex); 2736 2737 switch(chip->state) { 2738 case FL_READY: 2739 case FL_STATUS: 2740 case FL_CFI_QUERY: 2741 case FL_JEDEC_QUERY: 2742 chip->oldstate = chip->state; 2743 chip->state = FL_SYNCING; 2744 /* No need to wake_up() on this state change - 2745 * as the whole point is that nobody can do anything 2746 * with the chip now anyway. 2747 */ 2748 case FL_SYNCING: 2749 mutex_unlock(&chip->mutex); 2750 break; 2751 2752 default: 2753 /* Not an idle state */ 2754 set_current_state(TASK_UNINTERRUPTIBLE); 2755 add_wait_queue(&chip->wq, &wait); 2756 2757 mutex_unlock(&chip->mutex); 2758 2759 schedule(); 2760 2761 remove_wait_queue(&chip->wq, &wait); 2762 2763 goto retry; 2764 } 2765 } 2766 2767 /* Unlock the chips again */ 2768 2769 for (i--; i >=0; i--) { 2770 chip = &cfi->chips[i]; 2771 2772 mutex_lock(&chip->mutex); 2773 2774 if (chip->state == FL_SYNCING) { 2775 chip->state = chip->oldstate; 2776 wake_up(&chip->wq); 2777 } 2778 mutex_unlock(&chip->mutex); 2779 } 2780 } 2781 2782 2783 static int cfi_amdstd_suspend(struct mtd_info *mtd) 2784 { 2785 struct map_info *map = mtd->priv; 2786 struct cfi_private *cfi = map->fldrv_priv; 2787 int i; 2788 struct flchip *chip; 2789 int ret = 0; 2790 2791 for (i=0; !ret && i<cfi->numchips; i++) { 2792 chip = &cfi->chips[i]; 2793 2794 mutex_lock(&chip->mutex); 2795 2796 switch(chip->state) { 2797 case FL_READY: 2798 case FL_STATUS: 2799 case FL_CFI_QUERY: 2800 case FL_JEDEC_QUERY: 2801 chip->oldstate = chip->state; 2802 chip->state = FL_PM_SUSPENDED; 2803 /* No need to wake_up() on this state change - 2804 * as the whole point is that nobody can do anything 2805 * with the chip now anyway. 2806 */ 2807 case FL_PM_SUSPENDED: 2808 break; 2809 2810 default: 2811 ret = -EAGAIN; 2812 break; 2813 } 2814 mutex_unlock(&chip->mutex); 2815 } 2816 2817 /* Unlock the chips again */ 2818 2819 if (ret) { 2820 for (i--; i >=0; i--) { 2821 chip = &cfi->chips[i]; 2822 2823 mutex_lock(&chip->mutex); 2824 2825 if (chip->state == FL_PM_SUSPENDED) { 2826 chip->state = chip->oldstate; 2827 wake_up(&chip->wq); 2828 } 2829 mutex_unlock(&chip->mutex); 2830 } 2831 } 2832 2833 return ret; 2834 } 2835 2836 2837 static void cfi_amdstd_resume(struct mtd_info *mtd) 2838 { 2839 struct map_info *map = mtd->priv; 2840 struct cfi_private *cfi = map->fldrv_priv; 2841 int i; 2842 struct flchip *chip; 2843 2844 for (i=0; i<cfi->numchips; i++) { 2845 2846 chip = &cfi->chips[i]; 2847 2848 mutex_lock(&chip->mutex); 2849 2850 if (chip->state == FL_PM_SUSPENDED) { 2851 chip->state = FL_READY; 2852 map_write(map, CMD(0xF0), chip->start); 2853 wake_up(&chip->wq); 2854 } 2855 else 2856 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n"); 2857 2858 mutex_unlock(&chip->mutex); 2859 } 2860 } 2861 2862 2863 /* 2864 * Ensure that the flash device is put back into read array mode before 2865 * unloading the driver or rebooting. On some systems, rebooting while 2866 * the flash is in query/program/erase mode will prevent the CPU from 2867 * fetching the bootloader code, requiring a hard reset or power cycle. 2868 */ 2869 static int cfi_amdstd_reset(struct mtd_info *mtd) 2870 { 2871 struct map_info *map = mtd->priv; 2872 struct cfi_private *cfi = map->fldrv_priv; 2873 int i, ret; 2874 struct flchip *chip; 2875 2876 for (i = 0; i < cfi->numchips; i++) { 2877 2878 chip = &cfi->chips[i]; 2879 2880 mutex_lock(&chip->mutex); 2881 2882 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN); 2883 if (!ret) { 2884 map_write(map, CMD(0xF0), chip->start); 2885 chip->state = FL_SHUTDOWN; 2886 put_chip(map, chip, chip->start); 2887 } 2888 2889 mutex_unlock(&chip->mutex); 2890 } 2891 2892 return 0; 2893 } 2894 2895 2896 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val, 2897 void *v) 2898 { 2899 struct mtd_info *mtd; 2900 2901 mtd = container_of(nb, struct mtd_info, reboot_notifier); 2902 cfi_amdstd_reset(mtd); 2903 return NOTIFY_DONE; 2904 } 2905 2906 2907 static void cfi_amdstd_destroy(struct mtd_info *mtd) 2908 { 2909 struct map_info *map = mtd->priv; 2910 struct cfi_private *cfi = map->fldrv_priv; 2911 2912 cfi_amdstd_reset(mtd); 2913 unregister_reboot_notifier(&mtd->reboot_notifier); 2914 kfree(cfi->cmdset_priv); 2915 kfree(cfi->cfiq); 2916 kfree(cfi); 2917 kfree(mtd->eraseregions); 2918 } 2919 2920 MODULE_LICENSE("GPL"); 2921 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al."); 2922 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips"); 2923 MODULE_ALIAS("cfi_cmdset_0006"); 2924 MODULE_ALIAS("cfi_cmdset_0701"); 2925