1# drivers/mtd/chips/Kconfig 2# $Id: Kconfig,v 1.18 2005/11/07 11:14:22 gleixner Exp $ 3 4menu "RAM/ROM/Flash chip drivers" 5 depends on MTD!=n 6 7config MTD_CFI 8 tristate "Detect flash chips by Common Flash Interface (CFI) probe" 9 depends on MTD 10 select MTD_GEN_PROBE 11 help 12 The Common Flash Interface specification was developed by Intel, 13 AMD and other flash manufactures that provides a universal method 14 for probing the capabilities of flash devices. If you wish to 15 support any device that is CFI-compliant, you need to enable this 16 option. Visit <http://www.amd.com/products/nvd/overview/cfi.html> 17 for more information on CFI. 18 19config MTD_JEDECPROBE 20 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips" 21 depends on MTD 22 select MTD_GEN_PROBE 23 help 24 This option enables JEDEC-style probing of flash chips which are not 25 compatible with the Common Flash Interface, but will use the common 26 CFI-targetted flash drivers for any chips which are identified which 27 are in fact compatible in all but the probe method. This actually 28 covers most AMD/Fujitsu-compatible chips and also non-CFI 29 Intel chips. 30 31config MTD_GEN_PROBE 32 tristate 33 select OBSOLETE_INTERMODULE 34 35config MTD_CFI_ADV_OPTIONS 36 bool "Flash chip driver advanced configuration options" 37 depends on MTD_GEN_PROBE 38 help 39 If you need to specify a specific endianness for access to flash 40 chips, or if you wish to reduce the size of the kernel by including 41 support for only specific arrangements of flash chips, say 'Y'. This 42 option does not directly affect the code, but will enable other 43 configuration options which allow you to do so. 44 45 If unsure, say 'N'. 46 47choice 48 prompt "Flash cmd/query data swapping" 49 depends on MTD_CFI_ADV_OPTIONS 50 default MTD_CFI_NOSWAP 51 52config MTD_CFI_NOSWAP 53 bool "NO" 54 ---help--- 55 This option defines the way in which the CPU attempts to arrange 56 data bits when writing the 'magic' commands to the chips. Saying 57 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't 58 enabled, means that the CPU will not do any swapping; the chips 59 are expected to be wired to the CPU in 'host-endian' form. 60 Specific arrangements are possible with the BIG_ENDIAN_BYTE and 61 LITTLE_ENDIAN_BYTE, if the bytes are reversed. 62 63 If you have a LART, on which the data (and address) lines were 64 connected in a fashion which ensured that the nets were as short 65 as possible, resulting in a bit-shuffling which seems utterly 66 random to the untrained eye, you need the LART_ENDIAN_BYTE option. 67 68 Yes, there really exists something sicker than PDP-endian :) 69 70config MTD_CFI_BE_BYTE_SWAP 71 bool "BIG_ENDIAN_BYTE" 72 73config MTD_CFI_LE_BYTE_SWAP 74 bool "LITTLE_ENDIAN_BYTE" 75 76endchoice 77 78config MTD_CFI_GEOMETRY 79 bool "Specific CFI Flash geometry selection" 80 depends on MTD_CFI_ADV_OPTIONS 81 help 82 This option does not affect the code directly, but will enable 83 some other configuration options which would allow you to reduce 84 the size of the kernel by including support for only certain 85 arrangements of CFI chips. If unsure, say 'N' and all options 86 which are supported by the current code will be enabled. 87 88config MTD_MAP_BANK_WIDTH_1 89 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY 90 default y 91 help 92 If you wish to support CFI devices on a physical bus which is 93 8 bits wide, say 'Y'. 94 95config MTD_MAP_BANK_WIDTH_2 96 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY 97 default y 98 help 99 If you wish to support CFI devices on a physical bus which is 100 16 bits wide, say 'Y'. 101 102config MTD_MAP_BANK_WIDTH_4 103 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY 104 default y 105 help 106 If you wish to support CFI devices on a physical bus which is 107 32 bits wide, say 'Y'. 108 109config MTD_MAP_BANK_WIDTH_8 110 bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY 111 default n 112 help 113 If you wish to support CFI devices on a physical bus which is 114 64 bits wide, say 'Y'. 115 116config MTD_MAP_BANK_WIDTH_16 117 bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY 118 default n 119 help 120 If you wish to support CFI devices on a physical bus which is 121 128 bits wide, say 'Y'. 122 123config MTD_MAP_BANK_WIDTH_32 124 bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY 125 default n 126 help 127 If you wish to support CFI devices on a physical bus which is 128 256 bits wide, say 'Y'. 129 130config MTD_CFI_I1 131 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY 132 default y 133 help 134 If your flash chips are not interleaved - i.e. you only have one 135 flash chip addressed by each bus cycle, then say 'Y'. 136 137config MTD_CFI_I2 138 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY 139 default y 140 help 141 If your flash chips are interleaved in pairs - i.e. you have two 142 flash chips addressed by each bus cycle, then say 'Y'. 143 144config MTD_CFI_I4 145 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY 146 default n 147 help 148 If your flash chips are interleaved in fours - i.e. you have four 149 flash chips addressed by each bus cycle, then say 'Y'. 150 151config MTD_CFI_I8 152 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY 153 default n 154 help 155 If your flash chips are interleaved in eights - i.e. you have eight 156 flash chips addressed by each bus cycle, then say 'Y'. 157 158config MTD_OTP 159 bool "Protection Registers aka one-time programmable (OTP) bits" 160 depends on MTD_CFI_ADV_OPTIONS 161 default n 162 help 163 This enables support for reading, writing and locking so called 164 "Protection Registers" present on some flash chips. 165 A subset of them are pre-programmed at the factory with a 166 unique set of values. The rest is user-programmable. 167 168 The user-programmable Protection Registers contain one-time 169 programmable (OTP) bits; when programmed, register bits cannot be 170 erased. Each Protection Register can be accessed multiple times to 171 program individual bits, as long as the register remains unlocked. 172 173 Each Protection Register has an associated Lock Register bit. When a 174 Lock Register bit is programmed, the associated Protection Register 175 can only be read; it can no longer be programmed. Additionally, 176 because the Lock Register bits themselves are OTP, when programmed, 177 Lock Register bits cannot be erased. Therefore, when a Protection 178 Register is locked, it cannot be unlocked. 179 180 This feature should therefore be used with extreme care. Any mistake 181 in the programming of OTP bits will waste them. 182 183config MTD_CFI_INTELEXT 184 tristate "Support for Intel/Sharp flash chips" 185 depends on MTD_GEN_PROBE 186 select MTD_CFI_UTIL 187 help 188 The Common Flash Interface defines a number of different command 189 sets which a CFI-compliant chip may claim to implement. This code 190 provides support for one of those command sets, used on Intel 191 StrataFlash and other parts. 192 193config MTD_CFI_AMDSTD 194 tristate "Support for AMD/Fujitsu flash chips" 195 depends on MTD_GEN_PROBE 196 select MTD_CFI_UTIL 197 help 198 The Common Flash Interface defines a number of different command 199 sets which a CFI-compliant chip may claim to implement. This code 200 provides support for one of those command sets, used on chips 201 including the AMD Am29LV320. 202 203config MTD_CFI_STAA 204 tristate "Support for ST (Advanced Architecture) flash chips" 205 depends on MTD_GEN_PROBE 206 select MTD_CFI_UTIL 207 help 208 The Common Flash Interface defines a number of different command 209 sets which a CFI-compliant chip may claim to implement. This code 210 provides support for one of those command sets. 211 212config MTD_CFI_UTIL 213 tristate 214 215config MTD_RAM 216 tristate "Support for RAM chips in bus mapping" 217 depends on MTD 218 help 219 This option enables basic support for RAM chips accessed through 220 a bus mapping driver. 221 222config MTD_ROM 223 tristate "Support for ROM chips in bus mapping" 224 depends on MTD 225 help 226 This option enables basic support for ROM chips accessed through 227 a bus mapping driver. 228 229config MTD_ABSENT 230 tristate "Support for absent chips in bus mapping" 231 depends on MTD 232 help 233 This option enables support for a dummy probing driver used to 234 allocated placeholder MTD devices on systems that have socketed 235 or removable media. Use of this driver as a fallback chip probe 236 preserves the expected registration order of MTD device nodes on 237 the system regardless of media presence. Device nodes created 238 with this driver will return -ENODEV upon access. 239 240config MTD_OBSOLETE_CHIPS 241 depends on MTD 242 bool "Older (theoretically obsoleted now) drivers for non-CFI chips" 243 help 244 This option does not enable any code directly, but will allow you to 245 select some other chip drivers which are now considered obsolete, 246 because the generic CONFIG_JEDECPROBE code above should now detect 247 the chips which are supported by these drivers, and allow the generic 248 CFI-compatible drivers to drive the chips. Say 'N' here unless you have 249 already tried the CONFIG_JEDECPROBE method and reported its failure 250 to the MTD mailing list at <linux-mtd@lists.infradead.org> 251 252config MTD_AMDSTD 253 tristate "AMD compatible flash chip support (non-CFI)" 254 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN 255 help 256 This option enables support for flash chips using AMD-compatible 257 commands, including some which are not CFI-compatible and hence 258 cannot be used with the CONFIG_MTD_CFI_AMDSTD option. 259 260 It also works on AMD compatible chips that do conform to CFI. 261 262config MTD_SHARP 263 tristate "pre-CFI Sharp chip support" 264 depends on MTD && MTD_OBSOLETE_CHIPS 265 help 266 This option enables support for flash chips using Sharp-compatible 267 commands, including some which are not CFI-compatible and hence 268 cannot be used with the CONFIG_MTD_CFI_INTELxxx options. 269 270config MTD_JEDEC 271 tristate "JEDEC device support" 272 depends on MTD && MTD_OBSOLETE_CHIPS && BROKEN 273 help 274 Enable older older JEDEC flash interface devices for self 275 programming flash. It is commonly used in older AMD chips. It is 276 only called JEDEC because the JEDEC association 277 <http://www.jedec.org/> distributes the identification codes for the 278 chips. 279 280config MTD_XIP 281 bool "XIP aware MTD support" 282 depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && EXPERIMENTAL && ARCH_MTD_XIP 283 default y if XIP_KERNEL 284 help 285 This allows MTD support to work with flash memory which is also 286 used for XIP purposes. If you're not sure what this is all about 287 then say N. 288 289endmenu 290 291