12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver 41c6a0718SPierre Ossman * 51c6a0718SPierre Ossman * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved. 61c6a0718SPierre Ossman */ 71c6a0718SPierre Ossman 81c6a0718SPierre Ossman #define LOCK_CODE 0xAA 91c6a0718SPierre Ossman 101c6a0718SPierre Ossman #define WBSD_CONF_SWRST 0x02 111c6a0718SPierre Ossman #define WBSD_CONF_DEVICE 0x07 121c6a0718SPierre Ossman #define WBSD_CONF_ID_HI 0x20 131c6a0718SPierre Ossman #define WBSD_CONF_ID_LO 0x21 141c6a0718SPierre Ossman #define WBSD_CONF_POWER 0x22 151c6a0718SPierre Ossman #define WBSD_CONF_PME 0x23 161c6a0718SPierre Ossman #define WBSD_CONF_PMES 0x24 171c6a0718SPierre Ossman 181c6a0718SPierre Ossman #define WBSD_CONF_ENABLE 0x30 191c6a0718SPierre Ossman #define WBSD_CONF_PORT_HI 0x60 201c6a0718SPierre Ossman #define WBSD_CONF_PORT_LO 0x61 211c6a0718SPierre Ossman #define WBSD_CONF_IRQ 0x70 221c6a0718SPierre Ossman #define WBSD_CONF_DRQ 0x74 231c6a0718SPierre Ossman 241c6a0718SPierre Ossman #define WBSD_CONF_PINS 0xF0 251c6a0718SPierre Ossman 261c6a0718SPierre Ossman #define DEVICE_SD 0x03 271c6a0718SPierre Ossman 281c6a0718SPierre Ossman #define WBSD_PINS_DAT3_HI 0x20 291c6a0718SPierre Ossman #define WBSD_PINS_DAT3_OUT 0x10 301c6a0718SPierre Ossman #define WBSD_PINS_GP11_HI 0x04 311c6a0718SPierre Ossman #define WBSD_PINS_DETECT_GP11 0x02 321c6a0718SPierre Ossman #define WBSD_PINS_DETECT_DAT3 0x01 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #define WBSD_CMDR 0x00 351c6a0718SPierre Ossman #define WBSD_DFR 0x01 361c6a0718SPierre Ossman #define WBSD_EIR 0x02 371c6a0718SPierre Ossman #define WBSD_ISR 0x03 381c6a0718SPierre Ossman #define WBSD_FSR 0x04 391c6a0718SPierre Ossman #define WBSD_IDXR 0x05 401c6a0718SPierre Ossman #define WBSD_DATAR 0x06 411c6a0718SPierre Ossman #define WBSD_CSR 0x07 421c6a0718SPierre Ossman 431c6a0718SPierre Ossman #define WBSD_EINT_CARD 0x40 441c6a0718SPierre Ossman #define WBSD_EINT_FIFO_THRE 0x20 451c6a0718SPierre Ossman #define WBSD_EINT_CRC 0x10 461c6a0718SPierre Ossman #define WBSD_EINT_TIMEOUT 0x08 471c6a0718SPierre Ossman #define WBSD_EINT_PROGEND 0x04 481c6a0718SPierre Ossman #define WBSD_EINT_BUSYEND 0x02 491c6a0718SPierre Ossman #define WBSD_EINT_TC 0x01 501c6a0718SPierre Ossman 511c6a0718SPierre Ossman #define WBSD_INT_PENDING 0x80 521c6a0718SPierre Ossman #define WBSD_INT_CARD 0x40 531c6a0718SPierre Ossman #define WBSD_INT_FIFO_THRE 0x20 541c6a0718SPierre Ossman #define WBSD_INT_CRC 0x10 551c6a0718SPierre Ossman #define WBSD_INT_TIMEOUT 0x08 561c6a0718SPierre Ossman #define WBSD_INT_PROGEND 0x04 571c6a0718SPierre Ossman #define WBSD_INT_BUSYEND 0x02 581c6a0718SPierre Ossman #define WBSD_INT_TC 0x01 591c6a0718SPierre Ossman 601c6a0718SPierre Ossman #define WBSD_FIFO_EMPTY 0x80 611c6a0718SPierre Ossman #define WBSD_FIFO_FULL 0x40 621c6a0718SPierre Ossman #define WBSD_FIFO_EMTHRE 0x20 631c6a0718SPierre Ossman #define WBSD_FIFO_FUTHRE 0x10 641c6a0718SPierre Ossman #define WBSD_FIFO_SZMASK 0x0F 651c6a0718SPierre Ossman 661c6a0718SPierre Ossman #define WBSD_MSLED 0x20 671c6a0718SPierre Ossman #define WBSD_POWER_N 0x10 681c6a0718SPierre Ossman #define WBSD_WRPT 0x04 691c6a0718SPierre Ossman #define WBSD_CARDPRESENT 0x01 701c6a0718SPierre Ossman 711c6a0718SPierre Ossman #define WBSD_IDX_CLK 0x01 721c6a0718SPierre Ossman #define WBSD_IDX_PBSMSB 0x02 731c6a0718SPierre Ossman #define WBSD_IDX_TAAC 0x03 741c6a0718SPierre Ossman #define WBSD_IDX_NSAC 0x04 751c6a0718SPierre Ossman #define WBSD_IDX_PBSLSB 0x05 761c6a0718SPierre Ossman #define WBSD_IDX_SETUP 0x06 771c6a0718SPierre Ossman #define WBSD_IDX_DMA 0x07 781c6a0718SPierre Ossman #define WBSD_IDX_FIFOEN 0x08 791c6a0718SPierre Ossman #define WBSD_IDX_STATUS 0x10 801c6a0718SPierre Ossman #define WBSD_IDX_RSPLEN 0x1E 811c6a0718SPierre Ossman #define WBSD_IDX_RESP0 0x1F 821c6a0718SPierre Ossman #define WBSD_IDX_RESP1 0x20 831c6a0718SPierre Ossman #define WBSD_IDX_RESP2 0x21 841c6a0718SPierre Ossman #define WBSD_IDX_RESP3 0x22 851c6a0718SPierre Ossman #define WBSD_IDX_RESP4 0x23 861c6a0718SPierre Ossman #define WBSD_IDX_RESP5 0x24 871c6a0718SPierre Ossman #define WBSD_IDX_RESP6 0x25 881c6a0718SPierre Ossman #define WBSD_IDX_RESP7 0x26 891c6a0718SPierre Ossman #define WBSD_IDX_RESP8 0x27 901c6a0718SPierre Ossman #define WBSD_IDX_RESP9 0x28 911c6a0718SPierre Ossman #define WBSD_IDX_RESP10 0x29 921c6a0718SPierre Ossman #define WBSD_IDX_RESP11 0x2A 931c6a0718SPierre Ossman #define WBSD_IDX_RESP12 0x2B 941c6a0718SPierre Ossman #define WBSD_IDX_RESP13 0x2C 951c6a0718SPierre Ossman #define WBSD_IDX_RESP14 0x2D 961c6a0718SPierre Ossman #define WBSD_IDX_RESP15 0x2E 971c6a0718SPierre Ossman #define WBSD_IDX_RESP16 0x2F 981c6a0718SPierre Ossman #define WBSD_IDX_CRCSTATUS 0x30 991c6a0718SPierre Ossman #define WBSD_IDX_ISR 0x3F 1001c6a0718SPierre Ossman 1011c6a0718SPierre Ossman #define WBSD_CLK_375K 0x00 1021c6a0718SPierre Ossman #define WBSD_CLK_12M 0x01 1031c6a0718SPierre Ossman #define WBSD_CLK_16M 0x02 1041c6a0718SPierre Ossman #define WBSD_CLK_24M 0x03 1051c6a0718SPierre Ossman 1061c6a0718SPierre Ossman #define WBSD_DATA_WIDTH 0x01 1071c6a0718SPierre Ossman 1081c6a0718SPierre Ossman #define WBSD_DAT3_H 0x08 1091c6a0718SPierre Ossman #define WBSD_FIFO_RESET 0x04 1101c6a0718SPierre Ossman #define WBSD_SOFT_RESET 0x02 1111c6a0718SPierre Ossman #define WBSD_INC_INDEX 0x01 1121c6a0718SPierre Ossman 1131c6a0718SPierre Ossman #define WBSD_DMA_SINGLE 0x02 1141c6a0718SPierre Ossman #define WBSD_DMA_ENABLE 0x01 1151c6a0718SPierre Ossman 1161c6a0718SPierre Ossman #define WBSD_FIFOEN_EMPTY 0x20 1171c6a0718SPierre Ossman #define WBSD_FIFOEN_FULL 0x10 1181c6a0718SPierre Ossman #define WBSD_FIFO_THREMASK 0x0F 1191c6a0718SPierre Ossman 1201c6a0718SPierre Ossman #define WBSD_BLOCK_READ 0x80 1211c6a0718SPierre Ossman #define WBSD_BLOCK_WRITE 0x40 1221c6a0718SPierre Ossman #define WBSD_BUSY 0x20 1231c6a0718SPierre Ossman #define WBSD_CARDTRAFFIC 0x04 1241c6a0718SPierre Ossman #define WBSD_SENDCMD 0x02 1251c6a0718SPierre Ossman #define WBSD_RECVRES 0x01 1261c6a0718SPierre Ossman 1271c6a0718SPierre Ossman #define WBSD_RSP_SHORT 0x00 1281c6a0718SPierre Ossman #define WBSD_RSP_LONG 0x01 1291c6a0718SPierre Ossman 1301c6a0718SPierre Ossman #define WBSD_CRC_MASK 0x1F 1311c6a0718SPierre Ossman #define WBSD_CRC_OK 0x05 /* S010E (00101) */ 1321c6a0718SPierre Ossman #define WBSD_CRC_FAIL 0x0B /* S101E (01011) */ 1331c6a0718SPierre Ossman 1341c6a0718SPierre Ossman #define WBSD_DMA_SIZE 65536 1351c6a0718SPierre Ossman 1361c6a0718SPierre Ossman struct wbsd_host 1371c6a0718SPierre Ossman { 1381c6a0718SPierre Ossman struct mmc_host* mmc; /* MMC structure */ 1391c6a0718SPierre Ossman 1401c6a0718SPierre Ossman spinlock_t lock; /* Mutex */ 1411c6a0718SPierre Ossman 1421c6a0718SPierre Ossman int flags; /* Driver states */ 1431c6a0718SPierre Ossman 1441c6a0718SPierre Ossman #define WBSD_FCARD_PRESENT (1<<0) /* Card is present */ 1451c6a0718SPierre Ossman #define WBSD_FIGNORE_DETECT (1<<1) /* Ignore card detection */ 1461c6a0718SPierre Ossman 1471c6a0718SPierre Ossman struct mmc_request* mrq; /* Current request */ 1481c6a0718SPierre Ossman 1491c6a0718SPierre Ossman u8 isr; /* Accumulated ISR */ 1501c6a0718SPierre Ossman 1511c6a0718SPierre Ossman struct scatterlist* cur_sg; /* Current SG entry */ 1521c6a0718SPierre Ossman unsigned int num_sg; /* Number of entries left */ 1531c6a0718SPierre Ossman 1541c6a0718SPierre Ossman unsigned int offset; /* Offset into current entry */ 1551c6a0718SPierre Ossman unsigned int remain; /* Data left in curren entry */ 1561c6a0718SPierre Ossman 1571c6a0718SPierre Ossman char* dma_buffer; /* ISA DMA buffer */ 1581c6a0718SPierre Ossman dma_addr_t dma_addr; /* Physical address for same */ 1591c6a0718SPierre Ossman 1601c6a0718SPierre Ossman int firsterr; /* See fifo functions */ 1611c6a0718SPierre Ossman 1621c6a0718SPierre Ossman u8 clk; /* Current clock speed */ 1631c6a0718SPierre Ossman unsigned char bus_width; /* Current bus width */ 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman int config; /* Config port */ 1661c6a0718SPierre Ossman u8 unlock_code; /* Code to unlock config */ 1671c6a0718SPierre Ossman 1681c6a0718SPierre Ossman int chip_id; /* ID of controller */ 1691c6a0718SPierre Ossman 1701c6a0718SPierre Ossman int base; /* I/O port base */ 1711c6a0718SPierre Ossman int irq; /* Interrupt */ 1721c6a0718SPierre Ossman int dma; /* DMA channel */ 1731c6a0718SPierre Ossman 174*921c87baSAllen Pais struct work_struct card_bh_work; /* Work structures */ 175*921c87baSAllen Pais struct work_struct fifo_bh_work; 176*921c87baSAllen Pais struct work_struct crc_bh_work; 177*921c87baSAllen Pais struct work_struct timeout_bh_work; 178*921c87baSAllen Pais struct work_struct finish_bh_work; 1791c6a0718SPierre Ossman 1801c6a0718SPierre Ossman struct timer_list ignore_timer; /* Ignore detection timer */ 1811c6a0718SPierre Ossman }; 182