1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/mmc/host/via-sdmmc.c - VIA SD/MMC Card Reader driver 4 * Copyright (c) 2008, VIA Technologies Inc. All Rights Reserved. 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/module.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 14 #include <linux/mmc/host.h> 15 #include <linux/workqueue.h> 16 17 #define DRV_NAME "via_sdmmc" 18 19 #define PCI_DEVICE_ID_VIA_9530 0x9530 20 21 #define VIA_CRDR_SDC_OFF 0x200 22 #define VIA_CRDR_DDMA_OFF 0x400 23 #define VIA_CRDR_PCICTRL_OFF 0x600 24 25 #define VIA_CRDR_MIN_CLOCK 375000 26 #define VIA_CRDR_MAX_CLOCK 48000000 27 28 /* 29 * PCI registers 30 */ 31 32 #define VIA_CRDR_PCI_WORK_MODE 0x40 33 #define VIA_CRDR_PCI_DBG_MODE 0x41 34 35 /* 36 * SDC MMIO Registers 37 */ 38 39 #define VIA_CRDR_SDCTRL 0x0 40 #define VIA_CRDR_SDCTRL_START 0x01 41 #define VIA_CRDR_SDCTRL_WRITE 0x04 42 #define VIA_CRDR_SDCTRL_SINGLE_WR 0x10 43 #define VIA_CRDR_SDCTRL_SINGLE_RD 0x20 44 #define VIA_CRDR_SDCTRL_MULTI_WR 0x30 45 #define VIA_CRDR_SDCTRL_MULTI_RD 0x40 46 #define VIA_CRDR_SDCTRL_STOP 0x70 47 48 #define VIA_CRDR_SDCTRL_RSP_NONE 0x0 49 #define VIA_CRDR_SDCTRL_RSP_R1 0x10000 50 #define VIA_CRDR_SDCTRL_RSP_R2 0x20000 51 #define VIA_CRDR_SDCTRL_RSP_R3 0x30000 52 #define VIA_CRDR_SDCTRL_RSP_R1B 0x90000 53 54 #define VIA_CRDR_SDCARG 0x4 55 56 #define VIA_CRDR_SDBUSMODE 0x8 57 #define VIA_CRDR_SDMODE_4BIT 0x02 58 #define VIA_CRDR_SDMODE_CLK_ON 0x40 59 60 #define VIA_CRDR_SDBLKLEN 0xc 61 /* 62 * Bit 0 -Bit 10 : Block length. So, the maximum block length should be 2048. 63 * Bit 11 - Bit 13 : Reserved. 64 * GPIDET : Select GPI pin to detect card, GPI means CR_CD# in top design. 65 * INTEN : Enable SD host interrupt. 66 * Bit 16 - Bit 31 : Block count. So, the maximun block count should be 65536. 67 */ 68 #define VIA_CRDR_SDBLKLEN_GPIDET 0x2000 69 #define VIA_CRDR_SDBLKLEN_INTEN 0x8000 70 #define VIA_CRDR_MAX_BLOCK_COUNT 65536 71 #define VIA_CRDR_MAX_BLOCK_LENGTH 2048 72 73 #define VIA_CRDR_SDRESP0 0x10 74 #define VIA_CRDR_SDRESP1 0x14 75 #define VIA_CRDR_SDRESP2 0x18 76 #define VIA_CRDR_SDRESP3 0x1c 77 78 #define VIA_CRDR_SDCURBLKCNT 0x20 79 80 #define VIA_CRDR_SDINTMASK 0x24 81 /* 82 * MBDIE : Multiple Blocks transfer Done Interrupt Enable 83 * BDDIE : Block Data transfer Done Interrupt Enable 84 * CIRIE : Card Insertion or Removal Interrupt Enable 85 * CRDIE : Command-Response transfer Done Interrupt Enable 86 * CRTOIE : Command-Response response TimeOut Interrupt Enable 87 * ASCRDIE : Auto Stop Command-Response transfer Done Interrupt Enable 88 * DTIE : Data access Timeout Interrupt Enable 89 * SCIE : reSponse CRC error Interrupt Enable 90 * RCIE : Read data CRC error Interrupt Enable 91 * WCIE : Write data CRC error Interrupt Enable 92 */ 93 #define VIA_CRDR_SDINTMASK_MBDIE 0x10 94 #define VIA_CRDR_SDINTMASK_BDDIE 0x20 95 #define VIA_CRDR_SDINTMASK_CIRIE 0x80 96 #define VIA_CRDR_SDINTMASK_CRDIE 0x200 97 #define VIA_CRDR_SDINTMASK_CRTOIE 0x400 98 #define VIA_CRDR_SDINTMASK_ASCRDIE 0x800 99 #define VIA_CRDR_SDINTMASK_DTIE 0x1000 100 #define VIA_CRDR_SDINTMASK_SCIE 0x2000 101 #define VIA_CRDR_SDINTMASK_RCIE 0x4000 102 #define VIA_CRDR_SDINTMASK_WCIE 0x8000 103 104 #define VIA_CRDR_SDACTIVE_INTMASK \ 105 (VIA_CRDR_SDINTMASK_MBDIE | VIA_CRDR_SDINTMASK_CIRIE \ 106 | VIA_CRDR_SDINTMASK_CRDIE | VIA_CRDR_SDINTMASK_CRTOIE \ 107 | VIA_CRDR_SDINTMASK_DTIE | VIA_CRDR_SDINTMASK_SCIE \ 108 | VIA_CRDR_SDINTMASK_RCIE | VIA_CRDR_SDINTMASK_WCIE) 109 110 #define VIA_CRDR_SDSTATUS 0x28 111 /* 112 * CECC : Reserved 113 * WP : SD card Write Protect status 114 * SLOTD : Reserved 115 * SLOTG : SD SLOT status(Gpi pin status) 116 * MBD : Multiple Blocks transfer Done interrupt status 117 * BDD : Block Data transfer Done interrupt status 118 * CD : Reserved 119 * CIR : Card Insertion or Removal interrupt detected on GPI pin 120 * IO : Reserved 121 * CRD : Command-Response transfer Done interrupt status 122 * CRTO : Command-Response response TimeOut interrupt status 123 * ASCRDIE : Auto Stop Command-Response transfer Done interrupt status 124 * DT : Data access Timeout interrupt status 125 * SC : reSponse CRC error interrupt status 126 * RC : Read data CRC error interrupt status 127 * WC : Write data CRC error interrupt status 128 */ 129 #define VIA_CRDR_SDSTS_CECC 0x01 130 #define VIA_CRDR_SDSTS_WP 0x02 131 #define VIA_CRDR_SDSTS_SLOTD 0x04 132 #define VIA_CRDR_SDSTS_SLOTG 0x08 133 #define VIA_CRDR_SDSTS_MBD 0x10 134 #define VIA_CRDR_SDSTS_BDD 0x20 135 #define VIA_CRDR_SDSTS_CD 0x40 136 #define VIA_CRDR_SDSTS_CIR 0x80 137 #define VIA_CRDR_SDSTS_IO 0x100 138 #define VIA_CRDR_SDSTS_CRD 0x200 139 #define VIA_CRDR_SDSTS_CRTO 0x400 140 #define VIA_CRDR_SDSTS_ASCRDIE 0x800 141 #define VIA_CRDR_SDSTS_DT 0x1000 142 #define VIA_CRDR_SDSTS_SC 0x2000 143 #define VIA_CRDR_SDSTS_RC 0x4000 144 #define VIA_CRDR_SDSTS_WC 0x8000 145 146 #define VIA_CRDR_SDSTS_IGN_MASK\ 147 (VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_IO) 148 #define VIA_CRDR_SDSTS_INT_MASK \ 149 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD | VIA_CRDR_SDSTS_CD \ 150 | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_IO | VIA_CRDR_SDSTS_CRD \ 151 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 152 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 153 #define VIA_CRDR_SDSTS_W1C_MASK \ 154 (VIA_CRDR_SDSTS_CECC | VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_BDD \ 155 | VIA_CRDR_SDSTS_CD | VIA_CRDR_SDSTS_CIR | VIA_CRDR_SDSTS_CRD \ 156 | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_ASCRDIE | VIA_CRDR_SDSTS_DT \ 157 | VIA_CRDR_SDSTS_SC | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 158 #define VIA_CRDR_SDSTS_CMD_MASK \ 159 (VIA_CRDR_SDSTS_CRD | VIA_CRDR_SDSTS_CRTO | VIA_CRDR_SDSTS_SC) 160 #define VIA_CRDR_SDSTS_DATA_MASK\ 161 (VIA_CRDR_SDSTS_MBD | VIA_CRDR_SDSTS_DT \ 162 | VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC) 163 164 #define VIA_CRDR_SDSTATUS2 0x2a 165 /* 166 * CFE : Enable SD host automatic Clock FReezing 167 */ 168 #define VIA_CRDR_SDSTS_CFE 0x80 169 170 #define VIA_CRDR_SDRSPTMO 0x2C 171 172 #define VIA_CRDR_SDCLKSEL 0x30 173 174 #define VIA_CRDR_SDEXTCTRL 0x34 175 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD 0x01 176 #define VIS_CRDR_SDEXTCTRL_SHIFT_9 0x02 177 #define VIS_CRDR_SDEXTCTRL_MMC_8BIT 0x04 178 #define VIS_CRDR_SDEXTCTRL_RELD_BLK 0x08 179 #define VIS_CRDR_SDEXTCTRL_BAD_CMDA 0x10 180 #define VIS_CRDR_SDEXTCTRL_BAD_DATA 0x20 181 #define VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI 0x40 182 #define VIA_CRDR_SDEXTCTRL_HISPD 0x80 183 /* 0x38-0xFF reserved */ 184 185 /* 186 * Data DMA Control Registers 187 */ 188 189 #define VIA_CRDR_DMABASEADD 0x0 190 #define VIA_CRDR_DMACOUNTER 0x4 191 192 #define VIA_CRDR_DMACTRL 0x8 193 /* 194 * DIR :Transaction Direction 195 * 0 : From card to memory 196 * 1 : From memory to card 197 */ 198 #define VIA_CRDR_DMACTRL_DIR 0x100 199 #define VIA_CRDR_DMACTRL_ENIRQ 0x10000 200 #define VIA_CRDR_DMACTRL_SFTRST 0x1000000 201 202 #define VIA_CRDR_DMASTS 0xc 203 204 #define VIA_CRDR_DMASTART 0x10 205 /*0x14-0xFF reserved*/ 206 207 /* 208 * PCI Control Registers 209 */ 210 211 /*0x0 - 0x1 reserved*/ 212 #define VIA_CRDR_PCICLKGATT 0x2 213 /* 214 * SFTRST : 215 * 0 : Soft reset all the controller and it will be de-asserted automatically 216 * 1 : Soft reset is de-asserted 217 */ 218 #define VIA_CRDR_PCICLKGATT_SFTRST 0x01 219 /* 220 * 3V3 : Pad power select 221 * 0 : 1.8V 222 * 1 : 3.3V 223 * NOTE : No mater what the actual value should be, this bit always 224 * read as 0. This is a hardware bug. 225 */ 226 #define VIA_CRDR_PCICLKGATT_3V3 0x10 227 /* 228 * PAD_PWRON : Pad Power on/off select 229 * 0 : Power off 230 * 1 : Power on 231 * NOTE : No mater what the actual value should be, this bit always 232 * read as 0. This is a hardware bug. 233 */ 234 #define VIA_CRDR_PCICLKGATT_PAD_PWRON 0x20 235 236 #define VIA_CRDR_PCISDCCLK 0x5 237 238 #define VIA_CRDR_PCIDMACLK 0x7 239 #define VIA_CRDR_PCIDMACLK_SDC 0x2 240 241 #define VIA_CRDR_PCIINTCTRL 0x8 242 #define VIA_CRDR_PCIINTCTRL_SDCIRQEN 0x04 243 244 #define VIA_CRDR_PCIINTSTATUS 0x9 245 #define VIA_CRDR_PCIINTSTATUS_SDC 0x04 246 247 #define VIA_CRDR_PCITMOCTRL 0xa 248 #define VIA_CRDR_PCITMOCTRL_NO 0x0 249 #define VIA_CRDR_PCITMOCTRL_32US 0x1 250 #define VIA_CRDR_PCITMOCTRL_256US 0x2 251 #define VIA_CRDR_PCITMOCTRL_1024US 0x3 252 #define VIA_CRDR_PCITMOCTRL_256MS 0x4 253 #define VIA_CRDR_PCITMOCTRL_512MS 0x5 254 #define VIA_CRDR_PCITMOCTRL_1024MS 0x6 255 256 /*0xB-0xFF reserved*/ 257 258 enum PCI_HOST_CLK_CONTROL { 259 PCI_CLK_375K = 0x03, 260 PCI_CLK_8M = 0x04, 261 PCI_CLK_12M = 0x00, 262 PCI_CLK_16M = 0x05, 263 PCI_CLK_24M = 0x01, 264 PCI_CLK_33M = 0x06, 265 PCI_CLK_48M = 0x02 266 }; 267 268 struct sdhcreg { 269 u32 sdcontrol_reg; 270 u32 sdcmdarg_reg; 271 u32 sdbusmode_reg; 272 u32 sdblklen_reg; 273 u32 sdresp_reg[4]; 274 u32 sdcurblkcnt_reg; 275 u32 sdintmask_reg; 276 u32 sdstatus_reg; 277 u32 sdrsptmo_reg; 278 u32 sdclksel_reg; 279 u32 sdextctrl_reg; 280 }; 281 282 struct pcictrlreg { 283 u8 reserve[2]; 284 u8 pciclkgat_reg; 285 u8 pcinfcclk_reg; 286 u8 pcimscclk_reg; 287 u8 pcisdclk_reg; 288 u8 pcicaclk_reg; 289 u8 pcidmaclk_reg; 290 u8 pciintctrl_reg; 291 u8 pciintstatus_reg; 292 u8 pcitmoctrl_reg; 293 u8 Resv; 294 }; 295 296 struct via_crdr_mmc_host { 297 struct mmc_host *mmc; 298 struct mmc_request *mrq; 299 struct mmc_command *cmd; 300 struct mmc_data *data; 301 302 void __iomem *mmiobase; 303 void __iomem *sdhc_mmiobase; 304 void __iomem *ddma_mmiobase; 305 void __iomem *pcictrl_mmiobase; 306 307 struct pcictrlreg pm_pcictrl_reg; 308 struct sdhcreg pm_sdhc_reg; 309 310 struct work_struct carddet_work; 311 struct work_struct finish_bh_work; 312 313 struct timer_list timer; 314 spinlock_t lock; 315 u8 power; 316 int reject; 317 unsigned int quirks; 318 }; 319 320 /* some devices need a very long delay for power to stabilize */ 321 #define VIA_CRDR_QUIRK_300MS_PWRDELAY 0x0001 322 323 #define VIA_CMD_TIMEOUT_MS 1000 324 325 static const struct pci_device_id via_ids[] = { 326 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_9530) }, 327 { } 328 }; 329 330 MODULE_DEVICE_TABLE(pci, via_ids); 331 332 static void via_print_sdchc(struct via_crdr_mmc_host *host) 333 { 334 void __iomem *addrbase = host->sdhc_mmiobase; 335 336 pr_debug("SDC MMIO Registers:\n"); 337 pr_debug("SDCONTROL=%08x, SDCMDARG=%08x, SDBUSMODE=%08x\n", 338 readl(addrbase + VIA_CRDR_SDCTRL), 339 readl(addrbase + VIA_CRDR_SDCARG), 340 readl(addrbase + VIA_CRDR_SDBUSMODE)); 341 pr_debug("SDBLKLEN=%08x, SDCURBLKCNT=%08x, SDINTMASK=%08x\n", 342 readl(addrbase + VIA_CRDR_SDBLKLEN), 343 readl(addrbase + VIA_CRDR_SDCURBLKCNT), 344 readl(addrbase + VIA_CRDR_SDINTMASK)); 345 pr_debug("SDSTATUS=%08x, SDCLKSEL=%08x, SDEXTCTRL=%08x\n", 346 readl(addrbase + VIA_CRDR_SDSTATUS), 347 readl(addrbase + VIA_CRDR_SDCLKSEL), 348 readl(addrbase + VIA_CRDR_SDEXTCTRL)); 349 } 350 351 static void via_print_pcictrl(struct via_crdr_mmc_host *host) 352 { 353 void __iomem *addrbase = host->pcictrl_mmiobase; 354 355 pr_debug("PCI Control Registers:\n"); 356 pr_debug("PCICLKGATT=%02x, PCISDCCLK=%02x, PCIDMACLK=%02x\n", 357 readb(addrbase + VIA_CRDR_PCICLKGATT), 358 readb(addrbase + VIA_CRDR_PCISDCCLK), 359 readb(addrbase + VIA_CRDR_PCIDMACLK)); 360 pr_debug("PCIINTCTRL=%02x, PCIINTSTATUS=%02x\n", 361 readb(addrbase + VIA_CRDR_PCIINTCTRL), 362 readb(addrbase + VIA_CRDR_PCIINTSTATUS)); 363 } 364 365 static void via_save_pcictrlreg(struct via_crdr_mmc_host *host) 366 { 367 struct pcictrlreg *pm_pcictrl_reg; 368 void __iomem *addrbase; 369 370 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 371 addrbase = host->pcictrl_mmiobase; 372 373 pm_pcictrl_reg->pciclkgat_reg = readb(addrbase + VIA_CRDR_PCICLKGATT); 374 pm_pcictrl_reg->pciclkgat_reg |= 375 VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 376 pm_pcictrl_reg->pcisdclk_reg = readb(addrbase + VIA_CRDR_PCISDCCLK); 377 pm_pcictrl_reg->pcidmaclk_reg = readb(addrbase + VIA_CRDR_PCIDMACLK); 378 pm_pcictrl_reg->pciintctrl_reg = readb(addrbase + VIA_CRDR_PCIINTCTRL); 379 pm_pcictrl_reg->pciintstatus_reg = 380 readb(addrbase + VIA_CRDR_PCIINTSTATUS); 381 pm_pcictrl_reg->pcitmoctrl_reg = readb(addrbase + VIA_CRDR_PCITMOCTRL); 382 } 383 384 static void via_restore_pcictrlreg(struct via_crdr_mmc_host *host) 385 { 386 struct pcictrlreg *pm_pcictrl_reg; 387 void __iomem *addrbase; 388 389 pm_pcictrl_reg = &(host->pm_pcictrl_reg); 390 addrbase = host->pcictrl_mmiobase; 391 392 writeb(pm_pcictrl_reg->pciclkgat_reg, addrbase + VIA_CRDR_PCICLKGATT); 393 writeb(pm_pcictrl_reg->pcisdclk_reg, addrbase + VIA_CRDR_PCISDCCLK); 394 writeb(pm_pcictrl_reg->pcidmaclk_reg, addrbase + VIA_CRDR_PCIDMACLK); 395 writeb(pm_pcictrl_reg->pciintctrl_reg, addrbase + VIA_CRDR_PCIINTCTRL); 396 writeb(pm_pcictrl_reg->pciintstatus_reg, 397 addrbase + VIA_CRDR_PCIINTSTATUS); 398 writeb(pm_pcictrl_reg->pcitmoctrl_reg, addrbase + VIA_CRDR_PCITMOCTRL); 399 } 400 401 static void via_save_sdcreg(struct via_crdr_mmc_host *host) 402 { 403 struct sdhcreg *pm_sdhc_reg; 404 void __iomem *addrbase; 405 406 pm_sdhc_reg = &(host->pm_sdhc_reg); 407 addrbase = host->sdhc_mmiobase; 408 409 pm_sdhc_reg->sdcontrol_reg = readl(addrbase + VIA_CRDR_SDCTRL); 410 pm_sdhc_reg->sdcmdarg_reg = readl(addrbase + VIA_CRDR_SDCARG); 411 pm_sdhc_reg->sdbusmode_reg = readl(addrbase + VIA_CRDR_SDBUSMODE); 412 pm_sdhc_reg->sdblklen_reg = readl(addrbase + VIA_CRDR_SDBLKLEN); 413 pm_sdhc_reg->sdcurblkcnt_reg = readl(addrbase + VIA_CRDR_SDCURBLKCNT); 414 pm_sdhc_reg->sdintmask_reg = readl(addrbase + VIA_CRDR_SDINTMASK); 415 pm_sdhc_reg->sdstatus_reg = readl(addrbase + VIA_CRDR_SDSTATUS); 416 pm_sdhc_reg->sdrsptmo_reg = readl(addrbase + VIA_CRDR_SDRSPTMO); 417 pm_sdhc_reg->sdclksel_reg = readl(addrbase + VIA_CRDR_SDCLKSEL); 418 pm_sdhc_reg->sdextctrl_reg = readl(addrbase + VIA_CRDR_SDEXTCTRL); 419 } 420 421 static void via_restore_sdcreg(struct via_crdr_mmc_host *host) 422 { 423 struct sdhcreg *pm_sdhc_reg; 424 void __iomem *addrbase; 425 426 pm_sdhc_reg = &(host->pm_sdhc_reg); 427 addrbase = host->sdhc_mmiobase; 428 429 writel(pm_sdhc_reg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 430 writel(pm_sdhc_reg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 431 writel(pm_sdhc_reg->sdbusmode_reg, addrbase + VIA_CRDR_SDBUSMODE); 432 writel(pm_sdhc_reg->sdblklen_reg, addrbase + VIA_CRDR_SDBLKLEN); 433 writel(pm_sdhc_reg->sdcurblkcnt_reg, addrbase + VIA_CRDR_SDCURBLKCNT); 434 writel(pm_sdhc_reg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 435 writel(pm_sdhc_reg->sdstatus_reg, addrbase + VIA_CRDR_SDSTATUS); 436 writel(pm_sdhc_reg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 437 writel(pm_sdhc_reg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 438 writel(pm_sdhc_reg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 439 } 440 441 static void via_pwron_sleep(struct via_crdr_mmc_host *sdhost) 442 { 443 if (sdhost->quirks & VIA_CRDR_QUIRK_300MS_PWRDELAY) 444 msleep(300); 445 else 446 msleep(3); 447 } 448 449 static void via_set_ddma(struct via_crdr_mmc_host *host, 450 dma_addr_t dmaaddr, u32 count, int dir, int enirq) 451 { 452 void __iomem *addrbase; 453 u32 ctrl_data = 0; 454 455 if (enirq) 456 ctrl_data |= VIA_CRDR_DMACTRL_ENIRQ; 457 458 if (dir) 459 ctrl_data |= VIA_CRDR_DMACTRL_DIR; 460 461 addrbase = host->ddma_mmiobase; 462 463 writel(dmaaddr, addrbase + VIA_CRDR_DMABASEADD); 464 writel(count, addrbase + VIA_CRDR_DMACOUNTER); 465 writel(ctrl_data, addrbase + VIA_CRDR_DMACTRL); 466 writel(0x01, addrbase + VIA_CRDR_DMASTART); 467 468 /* It seems that our DMA can not work normally with 375kHz clock */ 469 /* FIXME: don't brute-force 8MHz but use PIO at 375kHz !! */ 470 addrbase = host->pcictrl_mmiobase; 471 if (readb(addrbase + VIA_CRDR_PCISDCCLK) == PCI_CLK_375K) { 472 dev_info(host->mmc->parent, "forcing card speed to 8MHz\n"); 473 writeb(PCI_CLK_8M, addrbase + VIA_CRDR_PCISDCCLK); 474 } 475 } 476 477 static void via_sdc_preparedata(struct via_crdr_mmc_host *host, 478 struct mmc_data *data) 479 { 480 void __iomem *addrbase; 481 u32 blk_reg; 482 int count; 483 484 WARN_ON(host->data); 485 486 /* Sanity checks */ 487 BUG_ON(data->blksz > host->mmc->max_blk_size); 488 BUG_ON(data->blocks > host->mmc->max_blk_count); 489 490 host->data = data; 491 492 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 493 ((data->flags & MMC_DATA_READ) ? 494 DMA_FROM_DEVICE : DMA_TO_DEVICE)); 495 BUG_ON(count != 1); 496 497 via_set_ddma(host, sg_dma_address(data->sg), sg_dma_len(data->sg), 498 (data->flags & MMC_DATA_WRITE) ? 1 : 0, 1); 499 500 addrbase = host->sdhc_mmiobase; 501 502 blk_reg = data->blksz - 1; 503 blk_reg |= VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 504 blk_reg |= (data->blocks) << 16; 505 506 writel(blk_reg, addrbase + VIA_CRDR_SDBLKLEN); 507 } 508 509 static void via_sdc_get_response(struct via_crdr_mmc_host *host, 510 struct mmc_command *cmd) 511 { 512 void __iomem *addrbase = host->sdhc_mmiobase; 513 u32 dwdata0 = readl(addrbase + VIA_CRDR_SDRESP0); 514 u32 dwdata1 = readl(addrbase + VIA_CRDR_SDRESP1); 515 u32 dwdata2 = readl(addrbase + VIA_CRDR_SDRESP2); 516 u32 dwdata3 = readl(addrbase + VIA_CRDR_SDRESP3); 517 518 if (cmd->flags & MMC_RSP_136) { 519 cmd->resp[0] = ((u8) (dwdata1)) | 520 (((u8) (dwdata0 >> 24)) << 8) | 521 (((u8) (dwdata0 >> 16)) << 16) | 522 (((u8) (dwdata0 >> 8)) << 24); 523 524 cmd->resp[1] = ((u8) (dwdata2)) | 525 (((u8) (dwdata1 >> 24)) << 8) | 526 (((u8) (dwdata1 >> 16)) << 16) | 527 (((u8) (dwdata1 >> 8)) << 24); 528 529 cmd->resp[2] = ((u8) (dwdata3)) | 530 (((u8) (dwdata2 >> 24)) << 8) | 531 (((u8) (dwdata2 >> 16)) << 16) | 532 (((u8) (dwdata2 >> 8)) << 24); 533 534 cmd->resp[3] = 0xff | 535 ((((u8) (dwdata3 >> 24))) << 8) | 536 (((u8) (dwdata3 >> 16)) << 16) | 537 (((u8) (dwdata3 >> 8)) << 24); 538 } else { 539 dwdata0 >>= 8; 540 cmd->resp[0] = ((dwdata0 & 0xff) << 24) | 541 (((dwdata0 >> 8) & 0xff) << 16) | 542 (((dwdata0 >> 16) & 0xff) << 8) | (dwdata1 & 0xff); 543 544 dwdata1 >>= 8; 545 cmd->resp[1] = ((dwdata1 & 0xff) << 24) | 546 (((dwdata1 >> 8) & 0xff) << 16) | 547 (((dwdata1 >> 16) & 0xff) << 8); 548 } 549 } 550 551 static void via_sdc_send_command(struct via_crdr_mmc_host *host, 552 struct mmc_command *cmd) 553 { 554 void __iomem *addrbase; 555 struct mmc_data *data; 556 unsigned int timeout_ms; 557 u32 cmdctrl = 0; 558 559 WARN_ON(host->cmd); 560 561 data = cmd->data; 562 host->cmd = cmd; 563 564 timeout_ms = cmd->busy_timeout ? cmd->busy_timeout : VIA_CMD_TIMEOUT_MS; 565 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms)); 566 567 /*Command index*/ 568 cmdctrl = cmd->opcode << 8; 569 570 /*Response type*/ 571 switch (mmc_resp_type(cmd)) { 572 case MMC_RSP_NONE: 573 cmdctrl |= VIA_CRDR_SDCTRL_RSP_NONE; 574 break; 575 case MMC_RSP_R1: 576 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1; 577 break; 578 case MMC_RSP_R1B: 579 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R1B; 580 break; 581 case MMC_RSP_R2: 582 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R2; 583 break; 584 case MMC_RSP_R3: 585 cmdctrl |= VIA_CRDR_SDCTRL_RSP_R3; 586 break; 587 default: 588 pr_err("%s: cmd->flag is not valid\n", mmc_hostname(host->mmc)); 589 break; 590 } 591 592 if (!(cmd->data)) 593 goto nodata; 594 595 via_sdc_preparedata(host, data); 596 597 /*Command control*/ 598 if (data->blocks > 1) { 599 if (data->flags & MMC_DATA_WRITE) { 600 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 601 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_WR; 602 } else { 603 cmdctrl |= VIA_CRDR_SDCTRL_MULTI_RD; 604 } 605 } else { 606 if (data->flags & MMC_DATA_WRITE) { 607 cmdctrl |= VIA_CRDR_SDCTRL_WRITE; 608 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_WR; 609 } else { 610 cmdctrl |= VIA_CRDR_SDCTRL_SINGLE_RD; 611 } 612 } 613 614 nodata: 615 if (cmd == host->mrq->stop) 616 cmdctrl |= VIA_CRDR_SDCTRL_STOP; 617 618 cmdctrl |= VIA_CRDR_SDCTRL_START; 619 620 addrbase = host->sdhc_mmiobase; 621 writel(cmd->arg, addrbase + VIA_CRDR_SDCARG); 622 writel(cmdctrl, addrbase + VIA_CRDR_SDCTRL); 623 } 624 625 static void via_sdc_finish_data(struct via_crdr_mmc_host *host) 626 { 627 struct mmc_data *data; 628 629 BUG_ON(!host->data); 630 631 data = host->data; 632 host->data = NULL; 633 634 if (data->error) 635 data->bytes_xfered = 0; 636 else 637 data->bytes_xfered = data->blocks * data->blksz; 638 639 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 640 ((data->flags & MMC_DATA_READ) ? 641 DMA_FROM_DEVICE : DMA_TO_DEVICE)); 642 643 if (data->stop) 644 via_sdc_send_command(host, data->stop); 645 else 646 queue_work(system_bh_wq, &host->finish_bh_work); 647 } 648 649 static void via_sdc_finish_command(struct via_crdr_mmc_host *host) 650 { 651 via_sdc_get_response(host, host->cmd); 652 653 host->cmd->error = 0; 654 655 if (!host->cmd->data) 656 queue_work(system_bh_wq, &host->finish_bh_work); 657 658 host->cmd = NULL; 659 } 660 661 static void via_sdc_request(struct mmc_host *mmc, struct mmc_request *mrq) 662 { 663 void __iomem *addrbase; 664 struct via_crdr_mmc_host *host; 665 unsigned long flags; 666 u16 status; 667 668 host = mmc_priv(mmc); 669 670 spin_lock_irqsave(&host->lock, flags); 671 672 addrbase = host->pcictrl_mmiobase; 673 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 674 675 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 676 status &= VIA_CRDR_SDSTS_W1C_MASK; 677 writew(status, host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 678 679 WARN_ON(host->mrq != NULL); 680 host->mrq = mrq; 681 682 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 683 if (!(status & VIA_CRDR_SDSTS_SLOTG) || host->reject) { 684 host->mrq->cmd->error = -ENOMEDIUM; 685 queue_work(system_bh_wq, &host->finish_bh_work); 686 } else { 687 via_sdc_send_command(host, mrq->cmd); 688 } 689 690 spin_unlock_irqrestore(&host->lock, flags); 691 } 692 693 static void via_sdc_set_power(struct via_crdr_mmc_host *host, 694 unsigned short power, unsigned int on) 695 { 696 unsigned long flags; 697 u8 gatt; 698 699 spin_lock_irqsave(&host->lock, flags); 700 701 host->power = (1 << power); 702 703 gatt = readb(host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 704 if (host->power == MMC_VDD_165_195) 705 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 706 else 707 gatt |= VIA_CRDR_PCICLKGATT_3V3; 708 if (on) 709 gatt |= VIA_CRDR_PCICLKGATT_PAD_PWRON; 710 else 711 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 712 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 713 714 spin_unlock_irqrestore(&host->lock, flags); 715 716 via_pwron_sleep(host); 717 } 718 719 static void via_sdc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 720 { 721 struct via_crdr_mmc_host *host; 722 unsigned long flags; 723 void __iomem *addrbase; 724 u32 org_data, sdextctrl; 725 u8 clock; 726 727 host = mmc_priv(mmc); 728 729 spin_lock_irqsave(&host->lock, flags); 730 731 addrbase = host->sdhc_mmiobase; 732 org_data = readl(addrbase + VIA_CRDR_SDBUSMODE); 733 sdextctrl = readl(addrbase + VIA_CRDR_SDEXTCTRL); 734 735 if (ios->bus_width == MMC_BUS_WIDTH_1) 736 org_data &= ~VIA_CRDR_SDMODE_4BIT; 737 else 738 org_data |= VIA_CRDR_SDMODE_4BIT; 739 740 if (ios->power_mode == MMC_POWER_OFF) 741 org_data &= ~VIA_CRDR_SDMODE_CLK_ON; 742 else 743 org_data |= VIA_CRDR_SDMODE_CLK_ON; 744 745 if (ios->timing == MMC_TIMING_SD_HS) 746 sdextctrl |= VIA_CRDR_SDEXTCTRL_HISPD; 747 else 748 sdextctrl &= ~VIA_CRDR_SDEXTCTRL_HISPD; 749 750 writel(org_data, addrbase + VIA_CRDR_SDBUSMODE); 751 writel(sdextctrl, addrbase + VIA_CRDR_SDEXTCTRL); 752 753 if (ios->clock >= 48000000) 754 clock = PCI_CLK_48M; 755 else if (ios->clock >= 33000000) 756 clock = PCI_CLK_33M; 757 else if (ios->clock >= 24000000) 758 clock = PCI_CLK_24M; 759 else if (ios->clock >= 16000000) 760 clock = PCI_CLK_16M; 761 else if (ios->clock >= 12000000) 762 clock = PCI_CLK_12M; 763 else if (ios->clock >= 8000000) 764 clock = PCI_CLK_8M; 765 else 766 clock = PCI_CLK_375K; 767 768 addrbase = host->pcictrl_mmiobase; 769 if (readb(addrbase + VIA_CRDR_PCISDCCLK) != clock) 770 writeb(clock, addrbase + VIA_CRDR_PCISDCCLK); 771 772 spin_unlock_irqrestore(&host->lock, flags); 773 774 if (ios->power_mode != MMC_POWER_OFF) 775 via_sdc_set_power(host, ios->vdd, 1); 776 else 777 via_sdc_set_power(host, ios->vdd, 0); 778 } 779 780 static int via_sdc_get_ro(struct mmc_host *mmc) 781 { 782 struct via_crdr_mmc_host *host; 783 unsigned long flags; 784 u16 status; 785 786 host = mmc_priv(mmc); 787 788 spin_lock_irqsave(&host->lock, flags); 789 790 status = readw(host->sdhc_mmiobase + VIA_CRDR_SDSTATUS); 791 792 spin_unlock_irqrestore(&host->lock, flags); 793 794 return !(status & VIA_CRDR_SDSTS_WP); 795 } 796 797 static const struct mmc_host_ops via_sdc_ops = { 798 .request = via_sdc_request, 799 .set_ios = via_sdc_set_ios, 800 .get_ro = via_sdc_get_ro, 801 }; 802 803 static void via_reset_pcictrl(struct via_crdr_mmc_host *host) 804 { 805 unsigned long flags; 806 u8 gatt; 807 808 spin_lock_irqsave(&host->lock, flags); 809 810 via_save_pcictrlreg(host); 811 via_save_sdcreg(host); 812 813 spin_unlock_irqrestore(&host->lock, flags); 814 815 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 816 if (host->power == MMC_VDD_165_195) 817 gatt &= VIA_CRDR_PCICLKGATT_3V3; 818 else 819 gatt |= VIA_CRDR_PCICLKGATT_3V3; 820 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 821 via_pwron_sleep(host); 822 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 823 writeb(gatt, host->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 824 msleep(3); 825 826 spin_lock_irqsave(&host->lock, flags); 827 828 via_restore_pcictrlreg(host); 829 via_restore_sdcreg(host); 830 831 spin_unlock_irqrestore(&host->lock, flags); 832 } 833 834 static void via_sdc_cmd_isr(struct via_crdr_mmc_host *host, u16 intmask) 835 { 836 BUG_ON(intmask == 0); 837 838 if (!host->cmd) { 839 pr_err("%s: Got command interrupt 0x%x even " 840 "though no command operation was in progress.\n", 841 mmc_hostname(host->mmc), intmask); 842 return; 843 } 844 845 if (intmask & VIA_CRDR_SDSTS_CRTO) 846 host->cmd->error = -ETIMEDOUT; 847 else if (intmask & VIA_CRDR_SDSTS_SC) 848 host->cmd->error = -EILSEQ; 849 850 if (host->cmd->error) 851 queue_work(system_bh_wq, &host->finish_bh_work); 852 else if (intmask & VIA_CRDR_SDSTS_CRD) 853 via_sdc_finish_command(host); 854 } 855 856 static void via_sdc_data_isr(struct via_crdr_mmc_host *host, u16 intmask) 857 { 858 BUG_ON(intmask == 0); 859 860 if (!host->data) 861 return; 862 863 if (intmask & VIA_CRDR_SDSTS_DT) 864 host->data->error = -ETIMEDOUT; 865 else if (intmask & (VIA_CRDR_SDSTS_RC | VIA_CRDR_SDSTS_WC)) 866 host->data->error = -EILSEQ; 867 868 via_sdc_finish_data(host); 869 } 870 871 static irqreturn_t via_sdc_isr(int irq, void *dev_id) 872 { 873 struct via_crdr_mmc_host *sdhost = dev_id; 874 void __iomem *addrbase; 875 u8 pci_status; 876 u16 sd_status; 877 irqreturn_t result; 878 879 if (!sdhost) 880 return IRQ_NONE; 881 882 spin_lock(&sdhost->lock); 883 884 addrbase = sdhost->pcictrl_mmiobase; 885 pci_status = readb(addrbase + VIA_CRDR_PCIINTSTATUS); 886 if (!(pci_status & VIA_CRDR_PCIINTSTATUS_SDC)) { 887 result = IRQ_NONE; 888 goto out; 889 } 890 891 addrbase = sdhost->sdhc_mmiobase; 892 sd_status = readw(addrbase + VIA_CRDR_SDSTATUS); 893 sd_status &= VIA_CRDR_SDSTS_INT_MASK; 894 sd_status &= ~VIA_CRDR_SDSTS_IGN_MASK; 895 if (!sd_status) { 896 result = IRQ_NONE; 897 goto out; 898 } 899 900 if (sd_status & VIA_CRDR_SDSTS_CIR) { 901 writew(sd_status & VIA_CRDR_SDSTS_CIR, 902 addrbase + VIA_CRDR_SDSTATUS); 903 904 schedule_work(&sdhost->carddet_work); 905 } 906 907 sd_status &= ~VIA_CRDR_SDSTS_CIR; 908 if (sd_status & VIA_CRDR_SDSTS_CMD_MASK) { 909 writew(sd_status & VIA_CRDR_SDSTS_CMD_MASK, 910 addrbase + VIA_CRDR_SDSTATUS); 911 via_sdc_cmd_isr(sdhost, sd_status & VIA_CRDR_SDSTS_CMD_MASK); 912 } 913 if (sd_status & VIA_CRDR_SDSTS_DATA_MASK) { 914 writew(sd_status & VIA_CRDR_SDSTS_DATA_MASK, 915 addrbase + VIA_CRDR_SDSTATUS); 916 via_sdc_data_isr(sdhost, sd_status & VIA_CRDR_SDSTS_DATA_MASK); 917 } 918 919 sd_status &= ~(VIA_CRDR_SDSTS_CMD_MASK | VIA_CRDR_SDSTS_DATA_MASK); 920 if (sd_status) { 921 pr_err("%s: Unexpected interrupt 0x%x\n", 922 mmc_hostname(sdhost->mmc), sd_status); 923 writew(sd_status, addrbase + VIA_CRDR_SDSTATUS); 924 } 925 926 result = IRQ_HANDLED; 927 928 out: 929 spin_unlock(&sdhost->lock); 930 931 return result; 932 } 933 934 static void via_sdc_timeout(struct timer_list *t) 935 { 936 struct via_crdr_mmc_host *sdhost; 937 unsigned long flags; 938 939 sdhost = timer_container_of(sdhost, t, timer); 940 941 spin_lock_irqsave(&sdhost->lock, flags); 942 943 if (sdhost->mrq) { 944 pr_err("%s: Timeout waiting for hardware interrupt." 945 "cmd:0x%x\n", mmc_hostname(sdhost->mmc), 946 sdhost->mrq->cmd->opcode); 947 948 if (sdhost->data) { 949 writel(VIA_CRDR_DMACTRL_SFTRST, 950 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 951 sdhost->data->error = -ETIMEDOUT; 952 via_sdc_finish_data(sdhost); 953 } else { 954 if (sdhost->cmd) 955 sdhost->cmd->error = -ETIMEDOUT; 956 else 957 sdhost->mrq->cmd->error = -ETIMEDOUT; 958 queue_work(system_bh_wq, &sdhost->finish_bh_work); 959 } 960 } 961 962 spin_unlock_irqrestore(&sdhost->lock, flags); 963 } 964 965 static void via_sdc_finish_bh_work(struct work_struct *t) 966 { 967 struct via_crdr_mmc_host *host = from_work(host, t, finish_bh_work); 968 unsigned long flags; 969 struct mmc_request *mrq; 970 971 spin_lock_irqsave(&host->lock, flags); 972 973 timer_delete(&host->timer); 974 mrq = host->mrq; 975 host->mrq = NULL; 976 host->cmd = NULL; 977 host->data = NULL; 978 979 spin_unlock_irqrestore(&host->lock, flags); 980 981 mmc_request_done(host->mmc, mrq); 982 } 983 984 static void via_sdc_card_detect(struct work_struct *work) 985 { 986 struct via_crdr_mmc_host *host; 987 void __iomem *addrbase; 988 unsigned long flags; 989 u16 status; 990 991 host = container_of(work, struct via_crdr_mmc_host, carddet_work); 992 993 addrbase = host->ddma_mmiobase; 994 writel(VIA_CRDR_DMACTRL_SFTRST, addrbase + VIA_CRDR_DMACTRL); 995 996 spin_lock_irqsave(&host->lock, flags); 997 998 addrbase = host->pcictrl_mmiobase; 999 writeb(VIA_CRDR_PCIDMACLK_SDC, addrbase + VIA_CRDR_PCIDMACLK); 1000 1001 addrbase = host->sdhc_mmiobase; 1002 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1003 if (!(status & VIA_CRDR_SDSTS_SLOTG)) { 1004 if (host->mrq) { 1005 pr_err("%s: Card removed during transfer!\n", 1006 mmc_hostname(host->mmc)); 1007 host->mrq->cmd->error = -ENOMEDIUM; 1008 queue_work(system_bh_wq, &host->finish_bh_work); 1009 } 1010 1011 spin_unlock_irqrestore(&host->lock, flags); 1012 1013 via_reset_pcictrl(host); 1014 1015 spin_lock_irqsave(&host->lock, flags); 1016 } 1017 1018 spin_unlock_irqrestore(&host->lock, flags); 1019 1020 via_print_pcictrl(host); 1021 via_print_sdchc(host); 1022 1023 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1024 } 1025 1026 static void via_init_mmc_host(struct via_crdr_mmc_host *host) 1027 { 1028 struct mmc_host *mmc = host->mmc; 1029 void __iomem *addrbase; 1030 u32 lenreg; 1031 u32 status; 1032 1033 timer_setup(&host->timer, via_sdc_timeout, 0); 1034 1035 spin_lock_init(&host->lock); 1036 1037 mmc->f_min = VIA_CRDR_MIN_CLOCK; 1038 mmc->f_max = VIA_CRDR_MAX_CLOCK; 1039 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1040 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED; 1041 mmc->ops = &via_sdc_ops; 1042 1043 /*Hardware cannot do scatter lists*/ 1044 mmc->max_segs = 1; 1045 1046 mmc->max_blk_size = VIA_CRDR_MAX_BLOCK_LENGTH; 1047 mmc->max_blk_count = VIA_CRDR_MAX_BLOCK_COUNT; 1048 1049 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 1050 mmc->max_req_size = mmc->max_seg_size; 1051 1052 INIT_WORK(&host->carddet_work, via_sdc_card_detect); 1053 1054 INIT_WORK(&host->finish_bh_work, via_sdc_finish_bh_work); 1055 1056 addrbase = host->sdhc_mmiobase; 1057 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1058 msleep(1); 1059 1060 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1061 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1062 1063 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1064 status &= VIA_CRDR_SDSTS_W1C_MASK; 1065 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1066 1067 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1068 status |= VIA_CRDR_SDSTS_CFE; 1069 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1070 1071 writeb(0x0, addrbase + VIA_CRDR_SDEXTCTRL); 1072 1073 writel(VIA_CRDR_SDACTIVE_INTMASK, addrbase + VIA_CRDR_SDINTMASK); 1074 msleep(1); 1075 } 1076 1077 static int via_sd_probe(struct pci_dev *pcidev, 1078 const struct pci_device_id *id) 1079 { 1080 struct mmc_host *mmc; 1081 struct via_crdr_mmc_host *sdhost; 1082 u32 base, len; 1083 u8 gatt; 1084 int ret; 1085 1086 pr_info(DRV_NAME 1087 ": VIA SDMMC controller found at %s [%04x:%04x] (rev %x)\n", 1088 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, 1089 (int)pcidev->revision); 1090 1091 ret = pci_enable_device(pcidev); 1092 if (ret) 1093 return ret; 1094 1095 ret = pci_request_regions(pcidev, DRV_NAME); 1096 if (ret) 1097 goto disable; 1098 1099 pci_write_config_byte(pcidev, VIA_CRDR_PCI_WORK_MODE, 0); 1100 pci_write_config_byte(pcidev, VIA_CRDR_PCI_DBG_MODE, 0); 1101 1102 mmc = devm_mmc_alloc_host(&pcidev->dev, sizeof(*sdhost)); 1103 if (!mmc) { 1104 ret = -ENOMEM; 1105 goto release; 1106 } 1107 1108 sdhost = mmc_priv(mmc); 1109 sdhost->mmc = mmc; 1110 dev_set_drvdata(&pcidev->dev, sdhost); 1111 1112 len = pci_resource_len(pcidev, 0); 1113 base = pci_resource_start(pcidev, 0); 1114 sdhost->mmiobase = ioremap(base, len); 1115 if (!sdhost->mmiobase) { 1116 ret = -ENOMEM; 1117 goto release; 1118 } 1119 1120 sdhost->sdhc_mmiobase = 1121 sdhost->mmiobase + VIA_CRDR_SDC_OFF; 1122 sdhost->ddma_mmiobase = 1123 sdhost->mmiobase + VIA_CRDR_DDMA_OFF; 1124 sdhost->pcictrl_mmiobase = 1125 sdhost->mmiobase + VIA_CRDR_PCICTRL_OFF; 1126 1127 sdhost->power = MMC_VDD_165_195; 1128 1129 gatt = VIA_CRDR_PCICLKGATT_3V3 | VIA_CRDR_PCICLKGATT_PAD_PWRON; 1130 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1131 via_pwron_sleep(sdhost); 1132 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1133 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1134 msleep(3); 1135 1136 via_init_mmc_host(sdhost); 1137 1138 ret = 1139 request_irq(pcidev->irq, via_sdc_isr, IRQF_SHARED, DRV_NAME, 1140 sdhost); 1141 if (ret) 1142 goto unmap; 1143 1144 writeb(VIA_CRDR_PCIINTCTRL_SDCIRQEN, 1145 sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1146 writeb(VIA_CRDR_PCITMOCTRL_1024MS, 1147 sdhost->pcictrl_mmiobase + VIA_CRDR_PCITMOCTRL); 1148 1149 /* device-specific quirks */ 1150 if (pcidev->subsystem_vendor == PCI_VENDOR_ID_LENOVO && 1151 pcidev->subsystem_device == 0x3891) 1152 sdhost->quirks = VIA_CRDR_QUIRK_300MS_PWRDELAY; 1153 1154 ret = mmc_add_host(mmc); 1155 if (ret) 1156 goto free_irq; 1157 1158 return 0; 1159 1160 free_irq: 1161 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1162 free_irq(pcidev->irq, sdhost); 1163 cancel_work_sync(&sdhost->carddet_work); 1164 /* carddet_work may re-enable the interrupt via via_reset_pcictrl(). */ 1165 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1166 unmap: 1167 iounmap(sdhost->mmiobase); 1168 release: 1169 pci_release_regions(pcidev); 1170 disable: 1171 pci_disable_device(pcidev); 1172 1173 return ret; 1174 } 1175 1176 static void via_sd_remove(struct pci_dev *pcidev) 1177 { 1178 struct via_crdr_mmc_host *sdhost = pci_get_drvdata(pcidev); 1179 unsigned long flags; 1180 u8 gatt; 1181 1182 spin_lock_irqsave(&sdhost->lock, flags); 1183 1184 /* Ensure we don't accept more commands from mmc layer */ 1185 sdhost->reject = 1; 1186 1187 /* Disable generating further interrupts */ 1188 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1189 1190 if (sdhost->mrq) { 1191 pr_err("%s: Controller removed during " 1192 "transfer\n", mmc_hostname(sdhost->mmc)); 1193 1194 /* make sure all DMA is stopped */ 1195 writel(VIA_CRDR_DMACTRL_SFTRST, 1196 sdhost->ddma_mmiobase + VIA_CRDR_DMACTRL); 1197 sdhost->mrq->cmd->error = -ENOMEDIUM; 1198 if (sdhost->mrq->stop) 1199 sdhost->mrq->stop->error = -ENOMEDIUM; 1200 queue_work(system_bh_wq, &sdhost->finish_bh_work); 1201 } 1202 spin_unlock_irqrestore(&sdhost->lock, flags); 1203 1204 mmc_remove_host(sdhost->mmc); 1205 1206 free_irq(pcidev->irq, sdhost); 1207 1208 cancel_work_sync(&sdhost->carddet_work); 1209 /* carddet_work may re-enable the interrupt via via_reset_pcictrl(). */ 1210 writeb(0x0, sdhost->pcictrl_mmiobase + VIA_CRDR_PCIINTCTRL); 1211 1212 timer_delete_sync(&sdhost->timer); 1213 1214 cancel_work_sync(&sdhost->finish_bh_work); 1215 1216 /* switch off power */ 1217 gatt = readb(sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1218 gatt &= ~VIA_CRDR_PCICLKGATT_PAD_PWRON; 1219 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1220 1221 iounmap(sdhost->mmiobase); 1222 pci_release_regions(pcidev); 1223 pci_disable_device(pcidev); 1224 1225 pr_info(DRV_NAME 1226 ": VIA SDMMC controller at %s [%04x:%04x] has been removed\n", 1227 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); 1228 } 1229 1230 static void via_init_sdc_pm(struct via_crdr_mmc_host *host) 1231 { 1232 struct sdhcreg *pm_sdhcreg; 1233 void __iomem *addrbase; 1234 u32 lenreg; 1235 u16 status; 1236 1237 pm_sdhcreg = &(host->pm_sdhc_reg); 1238 addrbase = host->sdhc_mmiobase; 1239 1240 writel(0x0, addrbase + VIA_CRDR_SDINTMASK); 1241 1242 lenreg = VIA_CRDR_SDBLKLEN_GPIDET | VIA_CRDR_SDBLKLEN_INTEN; 1243 writel(lenreg, addrbase + VIA_CRDR_SDBLKLEN); 1244 1245 status = readw(addrbase + VIA_CRDR_SDSTATUS); 1246 status &= VIA_CRDR_SDSTS_W1C_MASK; 1247 writew(status, addrbase + VIA_CRDR_SDSTATUS); 1248 1249 status = readw(addrbase + VIA_CRDR_SDSTATUS2); 1250 status |= VIA_CRDR_SDSTS_CFE; 1251 writew(status, addrbase + VIA_CRDR_SDSTATUS2); 1252 1253 writel(pm_sdhcreg->sdcontrol_reg, addrbase + VIA_CRDR_SDCTRL); 1254 writel(pm_sdhcreg->sdcmdarg_reg, addrbase + VIA_CRDR_SDCARG); 1255 writel(pm_sdhcreg->sdintmask_reg, addrbase + VIA_CRDR_SDINTMASK); 1256 writel(pm_sdhcreg->sdrsptmo_reg, addrbase + VIA_CRDR_SDRSPTMO); 1257 writel(pm_sdhcreg->sdclksel_reg, addrbase + VIA_CRDR_SDCLKSEL); 1258 writel(pm_sdhcreg->sdextctrl_reg, addrbase + VIA_CRDR_SDEXTCTRL); 1259 1260 via_print_pcictrl(host); 1261 via_print_sdchc(host); 1262 } 1263 1264 static int via_sd_suspend(struct device *dev) 1265 { 1266 struct via_crdr_mmc_host *host; 1267 unsigned long flags; 1268 1269 host = dev_get_drvdata(dev); 1270 1271 spin_lock_irqsave(&host->lock, flags); 1272 via_save_pcictrlreg(host); 1273 via_save_sdcreg(host); 1274 spin_unlock_irqrestore(&host->lock, flags); 1275 1276 device_wakeup_enable(dev); 1277 1278 return 0; 1279 } 1280 1281 static int via_sd_resume(struct device *dev) 1282 { 1283 struct via_crdr_mmc_host *sdhost; 1284 u8 gatt; 1285 1286 sdhost = dev_get_drvdata(dev); 1287 1288 gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; 1289 if (sdhost->power == MMC_VDD_165_195) 1290 gatt &= ~VIA_CRDR_PCICLKGATT_3V3; 1291 else 1292 gatt |= VIA_CRDR_PCICLKGATT_3V3; 1293 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1294 via_pwron_sleep(sdhost); 1295 gatt |= VIA_CRDR_PCICLKGATT_SFTRST; 1296 writeb(gatt, sdhost->pcictrl_mmiobase + VIA_CRDR_PCICLKGATT); 1297 msleep(3); 1298 1299 msleep(100); 1300 1301 via_restore_pcictrlreg(sdhost); 1302 via_init_sdc_pm(sdhost); 1303 1304 return 0; 1305 } 1306 1307 static DEFINE_SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume); 1308 1309 static struct pci_driver via_sd_driver = { 1310 .name = DRV_NAME, 1311 .id_table = via_ids, 1312 .probe = via_sd_probe, 1313 .remove = via_sd_remove, 1314 .driver.pm = pm_sleep_ptr(&via_sd_pm_ops), 1315 }; 1316 1317 module_pci_driver(via_sd_driver); 1318 1319 MODULE_LICENSE("GPL"); 1320 MODULE_AUTHOR("VIA Technologies Inc."); 1321 MODULE_DESCRIPTION("VIA SD/MMC Card Interface driver"); 1322