1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2017-2018 Socionext Inc. 4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mmc/host.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_data/tmio.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 21 #include "tmio_mmc.h" 22 23 #define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16) 24 #define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10) 25 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop 26 #define UNIPHIER_SD_CC_EXT_MODE 0x1b0 27 #define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1) 28 #define UNIPHIER_SD_HOST_MODE 0x1c8 29 #define UNIPHIER_SD_VOLT 0x1e4 30 #define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0) 31 #define UNIPHIER_SD_VOLT_OFF 0 32 #define UNIPHIER_SD_VOLT_330 1 // 3.3V signal 33 #define UNIPHIER_SD_VOLT_180 2 // 1.8V signal 34 #define UNIPHIER_SD_DMA_MODE 0x410 35 #define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16) 36 #define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0 37 #define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1 38 #define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4) 39 #define UNIPHIER_SD_DMA_MODE_WIDTH_8 0 40 #define UNIPHIER_SD_DMA_MODE_WIDTH_16 1 41 #define UNIPHIER_SD_DMA_MODE_WIDTH_32 2 42 #define UNIPHIER_SD_DMA_MODE_WIDTH_64 3 43 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed 44 #define UNIPHIER_SD_DMA_CTL 0x414 45 #define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared) 46 #define UNIPHIER_SD_DMA_RST 0x418 47 #define UNIPHIER_SD_DMA_RST_CH1 BIT(9) 48 #define UNIPHIER_SD_DMA_RST_CH0 BIT(8) 49 #define UNIPHIER_SD_DMA_ADDR_L 0x440 50 #define UNIPHIER_SD_DMA_ADDR_H 0x444 51 52 /* SD control */ 53 #define UNIPHIER_SDCTRL_CHOFFSET 0x200 54 #define UNIPHIER_SDCTRL_MODE 0x30 55 #define UNIPHIER_SDCTRL_MODE_UHS1MOD BIT(15) 56 #define UNIPHIER_SDCTRL_MODE_SDRSEL BIT(14) 57 58 /* 59 * IP is extended to support various features: built-in DMA engine, 60 * 1/1024 divisor, etc. 61 */ 62 #define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0) 63 /* RX channel of the built-in DMA controller is broken (Pro5) */ 64 #define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1) 65 66 struct uniphier_sd_priv { 67 struct tmio_mmc_data tmio_data; 68 struct pinctrl *pinctrl; 69 struct pinctrl_state *pinstate_uhs; 70 struct clk *clk; 71 struct reset_control *rst; 72 struct reset_control *rst_br; 73 struct reset_control *rst_hw; 74 struct dma_chan *chan; 75 enum dma_data_direction dma_dir; 76 struct regmap *sdctrl_regmap; 77 u32 sdctrl_ch; 78 unsigned long clk_rate; 79 unsigned long caps; 80 }; 81 82 static void *uniphier_sd_priv(struct tmio_mmc_host *host) 83 { 84 return container_of(host->pdata, struct uniphier_sd_priv, tmio_data); 85 } 86 87 static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable) 88 { 89 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 90 } 91 92 /* external DMA engine */ 93 static void uniphier_sd_external_dma_issue(struct work_struct *t) 94 { 95 struct tmio_mmc_host *host = from_work(host, t, dma_issue); 96 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 97 98 uniphier_sd_dma_endisable(host, 1); 99 dma_async_issue_pending(priv->chan); 100 } 101 102 static void uniphier_sd_external_dma_callback(void *param, 103 const struct dmaengine_result *result) 104 { 105 struct tmio_mmc_host *host = param; 106 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 107 unsigned long flags; 108 109 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 110 priv->dma_dir); 111 112 spin_lock_irqsave(&host->lock, flags); 113 114 if (result->result == DMA_TRANS_NOERROR) { 115 /* 116 * When the external DMA engine is enabled, strangely enough, 117 * the DATAEND flag can be asserted even if the DMA engine has 118 * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only 119 * after we make sure the DMA engine finishes the transfer, 120 * hence, in this callback. 121 */ 122 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 123 } else { 124 host->data->error = -ETIMEDOUT; 125 tmio_mmc_do_data_irq(host); 126 } 127 128 spin_unlock_irqrestore(&host->lock, flags); 129 } 130 131 static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host, 132 struct mmc_data *data) 133 { 134 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 135 enum dma_transfer_direction dma_tx_dir; 136 struct dma_async_tx_descriptor *desc; 137 dma_cookie_t cookie; 138 int sg_len; 139 140 if (!priv->chan) 141 goto force_pio; 142 143 if (data->flags & MMC_DATA_READ) { 144 priv->dma_dir = DMA_FROM_DEVICE; 145 dma_tx_dir = DMA_DEV_TO_MEM; 146 } else { 147 priv->dma_dir = DMA_TO_DEVICE; 148 dma_tx_dir = DMA_MEM_TO_DEV; 149 } 150 151 sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 152 priv->dma_dir); 153 if (sg_len == 0) 154 goto force_pio; 155 156 desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len, 157 dma_tx_dir, DMA_CTRL_ACK); 158 if (!desc) 159 goto unmap_sg; 160 161 desc->callback_result = uniphier_sd_external_dma_callback; 162 desc->callback_param = host; 163 164 cookie = dmaengine_submit(desc); 165 if (cookie < 0) 166 goto unmap_sg; 167 168 host->dma_on = true; 169 170 return; 171 172 unmap_sg: 173 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len, 174 priv->dma_dir); 175 force_pio: 176 uniphier_sd_dma_endisable(host, 0); 177 } 178 179 static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host, 180 bool enable) 181 { 182 } 183 184 static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host, 185 struct tmio_mmc_data *pdata) 186 { 187 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 188 struct dma_chan *chan; 189 190 chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx"); 191 if (IS_ERR(chan)) { 192 dev_warn(mmc_dev(host->mmc), 193 "failed to request DMA channel. falling back to PIO\n"); 194 return; /* just use PIO even for -EPROBE_DEFER */ 195 } 196 197 /* this driver uses a single channel for both RX an TX */ 198 priv->chan = chan; 199 host->chan_rx = chan; 200 host->chan_tx = chan; 201 202 INIT_WORK(&host->dma_issue, uniphier_sd_external_dma_issue); 203 } 204 205 static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host) 206 { 207 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 208 209 if (priv->chan) 210 dma_release_channel(priv->chan); 211 } 212 213 static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host) 214 { 215 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 216 217 uniphier_sd_dma_endisable(host, 0); 218 219 if (priv->chan) 220 dmaengine_terminate_sync(priv->chan); 221 } 222 223 static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host) 224 { 225 uniphier_sd_dma_endisable(host, 0); 226 227 tmio_mmc_do_data_irq(host); 228 } 229 230 static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = { 231 .start = uniphier_sd_external_dma_start, 232 .enable = uniphier_sd_external_dma_enable, 233 .request = uniphier_sd_external_dma_request, 234 .release = uniphier_sd_external_dma_release, 235 .abort = uniphier_sd_external_dma_abort, 236 .dataend = uniphier_sd_external_dma_dataend, 237 }; 238 239 static void uniphier_sd_internal_dma_issue(struct work_struct *t) 240 { 241 struct tmio_mmc_host *host = from_work(host, t, dma_issue); 242 unsigned long flags; 243 244 spin_lock_irqsave(&host->lock, flags); 245 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 246 spin_unlock_irqrestore(&host->lock, flags); 247 248 uniphier_sd_dma_endisable(host, 1); 249 writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL); 250 } 251 252 static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host, 253 struct mmc_data *data) 254 { 255 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 256 struct scatterlist *sg = host->sg_ptr; 257 dma_addr_t dma_addr; 258 unsigned int dma_mode_dir; 259 u32 dma_mode; 260 int sg_len; 261 262 if ((data->flags & MMC_DATA_READ) && !host->chan_rx) 263 goto force_pio; 264 265 if (WARN_ON(host->sg_len != 1)) 266 goto force_pio; 267 268 if (!IS_ALIGNED(sg->offset, 8)) 269 goto force_pio; 270 271 if (data->flags & MMC_DATA_READ) { 272 priv->dma_dir = DMA_FROM_DEVICE; 273 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV; 274 } else { 275 priv->dma_dir = DMA_TO_DEVICE; 276 dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV; 277 } 278 279 sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir); 280 if (sg_len == 0) 281 goto force_pio; 282 283 dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir); 284 dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK, 285 UNIPHIER_SD_DMA_MODE_WIDTH_64); 286 dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 287 288 writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE); 289 290 dma_addr = sg_dma_address(data->sg); 291 writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L); 292 writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H); 293 294 host->dma_on = true; 295 296 return; 297 force_pio: 298 uniphier_sd_dma_endisable(host, 0); 299 } 300 301 static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host, 302 bool enable) 303 { 304 } 305 306 static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host, 307 struct tmio_mmc_data *pdata) 308 { 309 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 310 311 /* 312 * Due to a hardware bug, Pro5 cannot use DMA for RX. 313 * We can still use DMA for TX, but PIO for RX. 314 */ 315 if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX)) 316 host->chan_rx = (void *)0xdeadbeaf; 317 318 host->chan_tx = (void *)0xdeadbeaf; 319 320 INIT_WORK(&host->dma_issue, uniphier_sd_internal_dma_issue); 321 } 322 323 static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host) 324 { 325 /* Each value is set to zero to assume "disabling" each DMA */ 326 host->chan_rx = NULL; 327 host->chan_tx = NULL; 328 } 329 330 static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host) 331 { 332 u32 tmp; 333 334 uniphier_sd_dma_endisable(host, 0); 335 336 tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST); 337 tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0); 338 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 339 340 tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0; 341 writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST); 342 } 343 344 static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host) 345 { 346 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 347 348 uniphier_sd_dma_endisable(host, 0); 349 dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir); 350 351 tmio_mmc_do_data_irq(host); 352 } 353 354 static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = { 355 .start = uniphier_sd_internal_dma_start, 356 .enable = uniphier_sd_internal_dma_enable, 357 .request = uniphier_sd_internal_dma_request, 358 .release = uniphier_sd_internal_dma_release, 359 .abort = uniphier_sd_internal_dma_abort, 360 .dataend = uniphier_sd_internal_dma_dataend, 361 }; 362 363 static int uniphier_sd_clk_enable(struct tmio_mmc_host *host) 364 { 365 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 366 struct mmc_host *mmc = host->mmc; 367 int ret; 368 369 ret = clk_prepare_enable(priv->clk); 370 if (ret) 371 return ret; 372 373 ret = clk_set_rate(priv->clk, ULONG_MAX); 374 if (ret) 375 goto disable_clk; 376 377 priv->clk_rate = clk_get_rate(priv->clk); 378 379 /* If max-frequency property is set, use it. */ 380 if (!mmc->f_max) 381 mmc->f_max = priv->clk_rate; 382 383 /* 384 * 1/512 is the finest divisor in the original IP. Newer versions 385 * also supports 1/1024 divisor. (UniPhier-specific extension) 386 */ 387 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 388 mmc->f_min = priv->clk_rate / 1024; 389 else 390 mmc->f_min = priv->clk_rate / 512; 391 392 ret = reset_control_deassert(priv->rst); 393 if (ret) 394 goto disable_clk; 395 396 ret = reset_control_deassert(priv->rst_br); 397 if (ret) 398 goto assert_rst; 399 400 return 0; 401 402 assert_rst: 403 reset_control_assert(priv->rst); 404 disable_clk: 405 clk_disable_unprepare(priv->clk); 406 407 return ret; 408 } 409 410 static void uniphier_sd_clk_disable(struct tmio_mmc_host *host) 411 { 412 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 413 414 reset_control_assert(priv->rst_br); 415 reset_control_assert(priv->rst); 416 clk_disable_unprepare(priv->clk); 417 } 418 419 static void uniphier_sd_hw_reset(struct mmc_host *mmc) 420 { 421 struct tmio_mmc_host *host = mmc_priv(mmc); 422 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 423 424 reset_control_assert(priv->rst_hw); 425 /* For eMMC, minimum is 1us but give it 9us for good measure */ 426 udelay(9); 427 reset_control_deassert(priv->rst_hw); 428 /* For eMMC, minimum is 200us but give it 300us for good measure */ 429 usleep_range(300, 1000); 430 } 431 432 static void uniphier_sd_speed_switch(struct tmio_mmc_host *host) 433 { 434 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 435 unsigned int offset; 436 u32 val = 0; 437 438 if (!(host->mmc->caps & MMC_CAP_UHS)) 439 return; 440 441 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR50 || 442 host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) 443 val = UNIPHIER_SDCTRL_MODE_SDRSEL; 444 445 offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch 446 + UNIPHIER_SDCTRL_MODE; 447 regmap_write_bits(priv->sdctrl_regmap, offset, 448 UNIPHIER_SDCTRL_MODE_SDRSEL, val); 449 } 450 451 static void uniphier_sd_uhs_enable(struct tmio_mmc_host *host, bool uhs_en) 452 { 453 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 454 unsigned int offset; 455 u32 val; 456 457 if (!(host->mmc->caps & MMC_CAP_UHS)) 458 return; 459 460 val = (uhs_en) ? UNIPHIER_SDCTRL_MODE_UHS1MOD : 0; 461 462 offset = UNIPHIER_SDCTRL_CHOFFSET * priv->sdctrl_ch 463 + UNIPHIER_SDCTRL_MODE; 464 regmap_write_bits(priv->sdctrl_regmap, offset, 465 UNIPHIER_SDCTRL_MODE_UHS1MOD, val); 466 } 467 468 static void uniphier_sd_set_clock(struct tmio_mmc_host *host, 469 unsigned int clock) 470 { 471 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 472 unsigned long divisor; 473 u32 tmp; 474 475 tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 476 477 /* stop the clock before changing its rate to avoid a glitch signal */ 478 tmp &= ~CLK_CTL_SCLKEN; 479 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 480 481 uniphier_sd_speed_switch(host); 482 483 if (clock == 0) 484 return; 485 486 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024; 487 tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1; 488 tmp &= ~CLK_CTL_DIV_MASK; 489 490 divisor = priv->clk_rate / clock; 491 492 /* 493 * In the original IP, bit[7:0] represents the divisor. 494 * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 495 * 496 * The IP does not define a way to achieve 1/1. For UniPhier variants, 497 * bit10 is used for 1/1. Newer versions of UniPhier variants use 498 * bit16 for 1/1024. 499 */ 500 if (divisor <= 1) 501 tmp |= UNIPHIER_SD_CLK_CTL_DIV1; 502 else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512) 503 tmp |= UNIPHIER_SD_CLK_CTL_DIV1024; 504 else 505 tmp |= roundup_pow_of_two(divisor) >> 2; 506 507 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 508 509 tmp |= CLK_CTL_SCLKEN; 510 writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 511 } 512 513 static void uniphier_sd_host_init(struct tmio_mmc_host *host) 514 { 515 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 516 u32 val; 517 518 /* 519 * Connected to 32bit AXI. 520 * This register holds settings for SoC-specific internal bus 521 * connection. What is worse, the register spec was changed, 522 * breaking the backward compatibility. Write an appropriate 523 * value depending on a flag associated with a compatible string. 524 */ 525 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 526 val = 0x00000101; 527 else 528 val = 0x00000000; 529 530 writel(val, host->ctl + UNIPHIER_SD_HOST_MODE); 531 532 val = 0; 533 /* 534 * If supported, the controller can automatically 535 * enable/disable the clock line to the card. 536 */ 537 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 538 val |= UNIPHIER_SD_CLKCTL_OFFEN; 539 540 writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1)); 541 } 542 543 static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc, 544 struct mmc_ios *ios) 545 { 546 struct tmio_mmc_host *host = mmc_priv(mmc); 547 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 548 struct pinctrl_state *pinstate = NULL; 549 u32 val, tmp; 550 bool uhs_en; 551 552 switch (ios->signal_voltage) { 553 case MMC_SIGNAL_VOLTAGE_330: 554 val = UNIPHIER_SD_VOLT_330; 555 uhs_en = false; 556 break; 557 case MMC_SIGNAL_VOLTAGE_180: 558 val = UNIPHIER_SD_VOLT_180; 559 pinstate = priv->pinstate_uhs; 560 uhs_en = true; 561 break; 562 default: 563 return -ENOTSUPP; 564 } 565 566 tmp = readl(host->ctl + UNIPHIER_SD_VOLT); 567 tmp &= ~UNIPHIER_SD_VOLT_MASK; 568 tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val); 569 writel(tmp, host->ctl + UNIPHIER_SD_VOLT); 570 571 if (pinstate) 572 pinctrl_select_state(priv->pinctrl, pinstate); 573 else 574 pinctrl_select_default_state(mmc_dev(mmc)); 575 576 uniphier_sd_uhs_enable(host, uhs_en); 577 578 return 0; 579 } 580 581 static int uniphier_sd_uhs_init(struct tmio_mmc_host *host) 582 { 583 struct uniphier_sd_priv *priv = uniphier_sd_priv(host); 584 struct device *dev = &host->pdev->dev; 585 struct device_node *np = dev->of_node; 586 struct of_phandle_args args; 587 int ret; 588 589 priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc)); 590 if (IS_ERR(priv->pinctrl)) 591 return PTR_ERR(priv->pinctrl); 592 593 priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs"); 594 if (IS_ERR(priv->pinstate_uhs)) 595 return PTR_ERR(priv->pinstate_uhs); 596 597 ret = of_parse_phandle_with_fixed_args(np, 598 "socionext,syscon-uhs-mode", 599 1, 0, &args); 600 if (ret) { 601 dev_err(dev, "Can't get syscon-uhs-mode property\n"); 602 return ret; 603 } 604 priv->sdctrl_regmap = syscon_node_to_regmap(args.np); 605 of_node_put(args.np); 606 if (IS_ERR(priv->sdctrl_regmap)) { 607 dev_err(dev, "Can't map syscon-uhs-mode\n"); 608 return PTR_ERR(priv->sdctrl_regmap); 609 } 610 priv->sdctrl_ch = args.args[0]; 611 612 return 0; 613 } 614 615 static int uniphier_sd_probe(struct platform_device *pdev) 616 { 617 struct device *dev = &pdev->dev; 618 struct uniphier_sd_priv *priv; 619 struct tmio_mmc_data *tmio_data; 620 struct tmio_mmc_host *host; 621 int irq, ret; 622 623 irq = platform_get_irq(pdev, 0); 624 if (irq < 0) 625 return irq; 626 627 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 628 if (!priv) 629 return -ENOMEM; 630 631 priv->caps = (unsigned long)of_device_get_match_data(dev); 632 633 priv->clk = devm_clk_get(dev, NULL); 634 if (IS_ERR(priv->clk)) { 635 dev_err(dev, "failed to get clock\n"); 636 return PTR_ERR(priv->clk); 637 } 638 639 priv->rst = devm_reset_control_get_shared(dev, "host"); 640 if (IS_ERR(priv->rst)) { 641 dev_err(dev, "failed to get host reset\n"); 642 return PTR_ERR(priv->rst); 643 } 644 645 /* old version has one more reset */ 646 if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) { 647 priv->rst_br = devm_reset_control_get_shared(dev, "bridge"); 648 if (IS_ERR(priv->rst_br)) { 649 dev_err(dev, "failed to get bridge reset\n"); 650 return PTR_ERR(priv->rst_br); 651 } 652 } 653 654 tmio_data = &priv->tmio_data; 655 tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT; 656 tmio_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 657 658 host = tmio_mmc_host_alloc(pdev, tmio_data); 659 if (IS_ERR(host)) 660 return PTR_ERR(host); 661 662 if (host->mmc->caps & MMC_CAP_HW_RESET) { 663 priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw"); 664 if (IS_ERR(priv->rst_hw)) { 665 dev_err(dev, "failed to get hw reset\n"); 666 ret = PTR_ERR(priv->rst_hw); 667 goto free_host; 668 } 669 host->ops.card_hw_reset = uniphier_sd_hw_reset; 670 } 671 672 if (host->mmc->caps & MMC_CAP_UHS) { 673 ret = uniphier_sd_uhs_init(host); 674 if (ret) { 675 dev_warn(dev, 676 "failed to setup UHS (error %d). Disabling UHS.", 677 ret); 678 host->mmc->caps &= ~MMC_CAP_UHS; 679 } else { 680 host->ops.start_signal_voltage_switch = 681 uniphier_sd_start_signal_voltage_switch; 682 } 683 } 684 685 if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP) 686 host->dma_ops = &uniphier_sd_internal_dma_ops; 687 else 688 host->dma_ops = &uniphier_sd_external_dma_ops; 689 690 host->bus_shift = 1; 691 host->clk_enable = uniphier_sd_clk_enable; 692 host->clk_disable = uniphier_sd_clk_disable; 693 host->set_clock = uniphier_sd_set_clock; 694 695 ret = uniphier_sd_clk_enable(host); 696 if (ret) 697 goto free_host; 698 699 uniphier_sd_host_init(host); 700 701 tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; 702 if (host->mmc->caps & MMC_CAP_UHS) 703 tmio_data->ocr_mask |= MMC_VDD_165_195; 704 705 tmio_data->max_segs = 1; 706 tmio_data->max_blk_count = U16_MAX; 707 708 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL); 709 710 ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED, 711 dev_name(dev), host); 712 if (ret) 713 goto disable_clk; 714 715 ret = tmio_mmc_host_probe(host); 716 if (ret) 717 goto disable_clk; 718 719 return 0; 720 721 disable_clk: 722 uniphier_sd_clk_disable(host); 723 free_host: 724 tmio_mmc_host_free(host); 725 726 return ret; 727 } 728 729 static void uniphier_sd_remove(struct platform_device *pdev) 730 { 731 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 732 733 tmio_mmc_host_remove(host); 734 uniphier_sd_clk_disable(host); 735 tmio_mmc_host_free(host); 736 } 737 738 static const struct of_device_id uniphier_sd_match[] = { 739 { 740 .compatible = "socionext,uniphier-sd-v2.91", 741 }, 742 { 743 .compatible = "socionext,uniphier-sd-v3.1", 744 .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP | 745 UNIPHIER_SD_CAP_BROKEN_DMA_RX), 746 }, 747 { 748 .compatible = "socionext,uniphier-sd-v3.1.1", 749 .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP, 750 }, 751 { /* sentinel */ } 752 }; 753 MODULE_DEVICE_TABLE(of, uniphier_sd_match); 754 755 static struct platform_driver uniphier_sd_driver = { 756 .probe = uniphier_sd_probe, 757 .remove = uniphier_sd_remove, 758 .driver = { 759 .name = "uniphier-sd", 760 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 761 .of_match_table = uniphier_sd_match, 762 }, 763 }; 764 module_platform_driver(uniphier_sd_driver); 765 766 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 767 MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver"); 768 MODULE_LICENSE("GPL v2"); 769