1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Sunplus Inc. 4 * Author: Tony Huang <tonyhuang.sunplus@gmail.com> 5 * Author: Li-hao Kuo <lhjeff911@gmail.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/mmc/core.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mmc/mmc.h> 17 #include <linux/mmc/sdio.h> 18 #include <linux/mmc/slot-gpio.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/reset.h> 25 26 #define SPMMC_MIN_CLK 400000 27 #define SPMMC_MAX_CLK 52000000 28 #define SPMMC_MAX_BLK_COUNT 65536 29 #define SPMMC_MAX_TUNABLE_DLY 7 30 #define SPMMC_TIMEOUT_US 500000 31 #define SPMMC_POLL_DELAY_US 10 32 33 #define SPMMC_CARD_MEDIATYPE_SRCDST_REG 0x0000 34 #define SPMMC_MEDIA_TYPE GENMASK(2, 0) 35 #define SPMMC_DMA_SOURCE GENMASK(6, 4) 36 #define SPMMC_DMA_DESTINATION GENMASK(10, 8) 37 #define SPMMC_MEDIA_NONE 0 38 #define SPMMC_MEDIA_SD 6 39 #define SPMMC_MEDIA_MS 7 40 41 #define SPMMC_SDRAM_SECTOR_0_SIZE_REG 0x0008 42 #define SPMMC_DMA_BASE_ADDR_REG 0x000C 43 #define SPMMC_HW_DMA_CTRL_REG 0x0010 44 #define SPMMC_HW_DMA_RST BIT(9) 45 #define SPMMC_DMAIDLE BIT(10) 46 47 #define SPMMC_MAX_DMA_MEMORY_SECTORS 8 48 49 #define SPMMC_SDRAM_SECTOR_1_ADDR_REG 0x0018 50 #define SPMMC_SDRAM_SECTOR_1_LENG_REG 0x001C 51 #define SPMMC_SDRAM_SECTOR_2_ADDR_REG 0x0020 52 #define SPMMC_SDRAM_SECTOR_2_LENG_REG 0x0024 53 #define SPMMC_SDRAM_SECTOR_3_ADDR_REG 0x0028 54 #define SPMMC_SDRAM_SECTOR_3_LENG_REG 0x002C 55 #define SPMMC_SDRAM_SECTOR_4_ADDR_REG 0x0030 56 #define SPMMC_SDRAM_SECTOR_4_LENG_REG 0x0034 57 #define SPMMC_SDRAM_SECTOR_5_ADDR_REG 0x0038 58 #define SPMMC_SDRAM_SECTOR_5_LENG_REG 0x003C 59 #define SPMMC_SDRAM_SECTOR_6_ADDR_REG 0x0040 60 #define SPMMC_SDRAM_SECTOR_6_LENG_REG 0x0044 61 #define SPMMC_SDRAM_SECTOR_7_ADDR_REG 0x0048 62 #define SPMMC_SDRAM_SECTOR_7_LENG_REG 0x004C 63 64 #define SPMMC_SD_INT_REG 0x0088 65 #define SPMMC_SDINT_SDCMPEN BIT(0) 66 #define SPMMC_SDINT_SDCMP BIT(1) 67 #define SPMMC_SDINT_SDCMPCLR BIT(2) 68 #define SPMMC_SDINT_SDIOEN BIT(3) 69 #define SPMMC_SDINT_SDIO BIT(4) 70 #define SPMMC_SDINT_SDIOCLR BIT(5) 71 72 #define SPMMC_SD_PAGE_NUM_REG 0x008C 73 74 #define SPMMC_SD_CONFIG0_REG 0x0090 75 #define SPMMC_SD_PIO_MODE BIT(0) 76 #define SPMMC_SD_DDR_MODE BIT(1) 77 #define SPMMC_SD_LEN_MODE BIT(2) 78 #define SPMMC_SD_TRANS_MODE GENMASK(5, 4) 79 #define SPMMC_SD_AUTO_RESPONSE BIT(6) 80 #define SPMMC_SD_CMD_DUMMY BIT(7) 81 #define SPMMC_SD_RSP_CHK_EN BIT(8) 82 #define SPMMC_SDIO_MODE BIT(9) 83 #define SPMMC_SD_MMC_MODE BIT(10) 84 #define SPMMC_SD_DATA_WD BIT(11) 85 #define SPMMC_RX4_EN BIT(14) 86 #define SPMMC_SD_RSP_TYPE BIT(15) 87 #define SPMMC_MMC8_EN BIT(18) 88 #define SPMMC_CLOCK_DIVISION GENMASK(31, 20) 89 90 #define SPMMC_SDIO_CTRL_REG 0x0094 91 #define SPMMC_INT_MULTI_TRIG BIT(6) 92 93 #define SPMMC_SD_RST_REG 0x0098 94 #define SPMMC_SD_CTRL_REG 0x009C 95 #define SPMMC_NEW_COMMAND_TRIGGER BIT(0) 96 #define SPMMC_DUMMY_CLOCK_TRIGGER BIT(1) 97 98 #define SPMMC_SD_STATUS_REG 0x00A0 99 #define SPMMC_SDSTATUS_DUMMY_READY BIT(0) 100 #define SPMMC_SDSTATUS_RSP_BUF_FULL BIT(1) 101 #define SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY BIT(2) 102 #define SPMMC_SDSTATUS_RX_DATA_BUF_FULL BIT(3) 103 #define SPMMC_SDSTATUS_CMD_PIN_STATUS BIT(4) 104 #define SPMMC_SDSTATUS_DAT0_PIN_STATUS BIT(5) 105 #define SPMMC_SDSTATUS_RSP_TIMEOUT BIT(6) 106 #define SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT BIT(7) 107 #define SPMMC_SDSTATUS_STB_TIMEOUT BIT(8) 108 #define SPMMC_SDSTATUS_RSP_CRC7_ERROR BIT(9) 109 #define SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR BIT(10) 110 #define SPMMC_SDSTATUS_RDATA_CRC16_ERROR BIT(11) 111 #define SPMMC_SDSTATUS_SUSPEND_STATE_READY BIT(12) 112 #define SPMMC_SDSTATUS_BUSY_CYCLE BIT(13) 113 #define SPMMC_SDSTATUS_DAT1_PIN_STATUS BIT(14) 114 #define SPMMC_SDSTATUS_SD_SENSE_STATUS BIT(15) 115 #define SPMMC_SDSTATUS_BOOT_ACK_TIMEOUT BIT(16) 116 #define SPMMC_SDSTATUS_BOOT_DATA_TIMEOUT BIT(17) 117 #define SPMMC_SDSTATUS_BOOT_ACK_ERROR BIT(18) 118 119 #define SPMMC_SD_STATE_REG 0x00A4 120 #define SPMMC_CRCTOKEN_CHECK_RESULT GENMASK(6, 4) 121 #define SPMMC_SDSTATE_ERROR BIT(13) 122 #define SPMMC_SDSTATE_FINISH BIT(14) 123 124 #define SPMMC_SD_HW_STATE_REG 0x00A8 125 #define SPMMC_SD_BLOCKSIZE_REG 0x00AC 126 127 #define SPMMC_SD_CONFIG1_REG 0x00B0 128 #define SPMMC_TX_DUMMY_NUM GENMASK(8, 0) 129 #define SPMMC_SD_HIGH_SPEED_EN BIT(31) 130 131 #define SPMMC_SD_TIMING_CONFIG0_REG 0x00B4 132 #define SPMMC_SD_CLOCK_DELAY GENMASK(2, 0) 133 #define SPMMC_SD_WRITE_DATA_DELAY GENMASK(6, 4) 134 #define SPMMC_SD_WRITE_COMMAND_DELAY GENMASK(10, 8) 135 #define SPMMC_SD_READ_RESPONSE_DELAY GENMASK(14, 12) 136 #define SPMMC_SD_READ_DATA_DELAY GENMASK(18, 16) 137 #define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20) 138 139 #define SPMMC_SD_PIODATATX_REG 0x00BC 140 #define SPMMC_SD_PIODATARX_REG 0x00C0 141 #define SPMMC_SD_CMDBUF0_3_REG 0x00C4 142 #define SPMMC_SD_CMDBUF4_REG 0x00C8 143 #define SPMMC_SD_RSPBUF0_3_REG 0x00CC 144 #define SPMMC_SD_RSPBUF4_5_REG 0x00D0 145 146 #define SPMMC_MAX_RETRIES (8 * 8) 147 148 struct spmmc_tuning_info { 149 int enable_tuning; 150 int need_tuning; 151 int retried; /* how many times has been retried */ 152 u32 rd_crc_dly:3; 153 u32 rd_dat_dly:3; 154 u32 rd_rsp_dly:3; 155 u32 wr_cmd_dly:3; 156 u32 wr_dat_dly:3; 157 u32 clk_dly:3; 158 }; 159 160 #define SPMMC_DMA_MODE 0 161 #define SPMMC_PIO_MODE 1 162 163 struct spmmc_host { 164 void __iomem *base; 165 struct clk *clk; 166 struct reset_control *rstc; 167 struct mmc_host *mmc; 168 struct mmc_request *mrq; /* current mrq */ 169 int irq; 170 int dmapio_mode; 171 struct spmmc_tuning_info tuning_info; 172 int dma_int_threshold; 173 int dma_use_int; 174 }; 175 176 static inline int spmmc_wait_finish(struct spmmc_host *host) 177 { 178 u32 state; 179 180 return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state, 181 (state & SPMMC_SDSTATE_FINISH), 182 SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US); 183 } 184 185 static inline int spmmc_wait_sdstatus(struct spmmc_host *host, unsigned int status_bit) 186 { 187 u32 status; 188 189 return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status, 190 (status & status_bit), 191 SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US); 192 } 193 194 #define spmmc_wait_rspbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RSP_BUF_FULL) 195 #define spmmc_wait_rxbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RX_DATA_BUF_FULL) 196 #define spmmc_wait_txbuf_empty(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY) 197 198 static void spmmc_get_rsp(struct spmmc_host *host, struct mmc_command *cmd) 199 { 200 u32 value0_3, value4_5; 201 202 if (!(cmd->flags & MMC_RSP_PRESENT)) 203 return; 204 if (cmd->flags & MMC_RSP_136) { 205 if (spmmc_wait_rspbuf_full(host)) 206 return; 207 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 208 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 209 cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8); 210 cmd->resp[1] = value4_5 << 24; 211 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 212 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 213 cmd->resp[1] |= value0_3 >> 8; 214 cmd->resp[2] = value0_3 << 24; 215 cmd->resp[2] |= value4_5 << 8; 216 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 217 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 218 cmd->resp[2] |= value0_3 >> 24; 219 cmd->resp[3] = value0_3 << 8; 220 cmd->resp[3] |= value4_5 >> 8; 221 } else { 222 if (spmmc_wait_rspbuf_full(host)) 223 return; 224 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); 225 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; 226 cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8); 227 cmd->resp[1] = value4_5 << 24; 228 } 229 } 230 231 static void spmmc_set_bus_clk(struct spmmc_host *host, int clk) 232 { 233 unsigned int clkdiv; 234 int f_min = host->mmc->f_min; 235 int f_max = host->mmc->f_max; 236 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 237 238 if (clk < f_min) 239 clk = f_min; 240 if (clk > f_max) 241 clk = f_max; 242 243 clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1; 244 if (clkdiv > 0xfff) 245 clkdiv = 0xfff; 246 value &= ~SPMMC_CLOCK_DIVISION; 247 value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv); 248 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 249 } 250 251 static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing) 252 { 253 u32 value = readl(host->base + SPMMC_SD_CONFIG1_REG); 254 int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG)); 255 int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7; 256 int hs_en = 1, ddr_enabled = 0; 257 258 switch (timing) { 259 case MMC_TIMING_LEGACY: 260 hs_en = 0; 261 break; 262 case MMC_TIMING_MMC_HS: 263 case MMC_TIMING_SD_HS: 264 case MMC_TIMING_UHS_SDR50: 265 case MMC_TIMING_UHS_SDR104: 266 case MMC_TIMING_MMC_HS200: 267 hs_en = 1; 268 break; 269 case MMC_TIMING_UHS_DDR50: 270 ddr_enabled = 1; 271 break; 272 case MMC_TIMING_MMC_DDR52: 273 ddr_enabled = 1; 274 break; 275 default: 276 hs_en = 0; 277 break; 278 } 279 280 if (hs_en) { 281 value |= SPMMC_SD_HIGH_SPEED_EN; 282 writel(value, host->base + SPMMC_SD_CONFIG1_REG); 283 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 284 value &= ~SPMMC_SD_WRITE_DATA_DELAY; 285 value |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, delay); 286 value &= ~SPMMC_SD_WRITE_COMMAND_DELAY; 287 value |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, delay); 288 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 289 } else { 290 value &= ~SPMMC_SD_HIGH_SPEED_EN; 291 writel(value, host->base + SPMMC_SD_CONFIG1_REG); 292 } 293 if (ddr_enabled) { 294 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 295 value |= SPMMC_SD_DDR_MODE; 296 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 297 /* DDR mode needs rd_crc_dly=1 */ 298 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 299 value &= ~SPMMC_SD_READ_CRC_DELAY; 300 value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, 1); 301 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 302 } else { 303 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 304 value &= ~SPMMC_SD_DDR_MODE; 305 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 306 } 307 } 308 309 static void spmmc_set_bus_width(struct spmmc_host *host, int width) 310 { 311 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 312 313 switch (width) { 314 case MMC_BUS_WIDTH_8: 315 value &= ~SPMMC_SD_DATA_WD; 316 value |= SPMMC_MMC8_EN; 317 break; 318 case MMC_BUS_WIDTH_4: 319 value |= SPMMC_SD_DATA_WD; 320 value &= ~SPMMC_MMC8_EN; 321 break; 322 default: 323 value &= ~SPMMC_SD_DATA_WD; 324 value &= ~SPMMC_MMC8_EN; 325 break; 326 } 327 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 328 } 329 330 /* 331 * select the working mode of controller: sd/sdio/emmc 332 */ 333 static void spmmc_set_sdmmc_mode(struct spmmc_host *host) 334 { 335 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 336 337 value |= SPMMC_SD_MMC_MODE; 338 value &= ~SPMMC_SDIO_MODE; 339 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 340 } 341 342 static void spmmc_sw_reset(struct spmmc_host *host) 343 { 344 u32 value; 345 346 /* 347 * Must reset dma operation first, or it will 348 * be stuck on sd_state == 0x1c00 because of 349 * a controller software reset bug 350 */ 351 value = readl(host->base + SPMMC_HW_DMA_CTRL_REG); 352 value |= SPMMC_DMAIDLE; 353 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 354 value &= ~SPMMC_DMAIDLE; 355 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 356 value = readl(host->base + SPMMC_HW_DMA_CTRL_REG); 357 value |= SPMMC_HW_DMA_RST; 358 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); 359 writel(0x7, host->base + SPMMC_SD_RST_REG); 360 readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value, 361 !(value & BIT(6)), 1, SPMMC_TIMEOUT_US); 362 } 363 364 static void spmmc_prepare_cmd(struct spmmc_host *host, struct mmc_command *cmd) 365 { 366 u32 value; 367 368 /* add start bit, according to spec, command format */ 369 value = ((cmd->opcode | 0x40) << 24) | (cmd->arg >> 8); 370 writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG); 371 writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG); 372 373 /* disable interrupt if needed */ 374 value = readl(host->base + SPMMC_SD_INT_REG); 375 value |= SPMMC_SDINT_SDCMPCLR; 376 value &= ~SPMMC_SDINT_SDCMPEN; 377 writel(value, host->base + SPMMC_SD_INT_REG); 378 379 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 380 value &= ~SPMMC_SD_TRANS_MODE; 381 value |= SPMMC_SD_CMD_DUMMY; 382 if (cmd->flags & MMC_RSP_PRESENT) { 383 value |= SPMMC_SD_AUTO_RESPONSE; 384 } else { 385 value &= ~SPMMC_SD_AUTO_RESPONSE; 386 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 387 388 return; 389 } 390 /* 391 * Currently, host is not capable of checking R2's CRC7, 392 * thus, enable crc7 check only for 48 bit response commands 393 */ 394 if (cmd->flags & MMC_RSP_CRC && !(cmd->flags & MMC_RSP_136)) 395 value |= SPMMC_SD_RSP_CHK_EN; 396 else 397 value &= ~SPMMC_SD_RSP_CHK_EN; 398 399 if (cmd->flags & MMC_RSP_136) 400 value |= SPMMC_SD_RSP_TYPE; 401 else 402 value &= ~SPMMC_SD_RSP_TYPE; 403 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 404 } 405 406 static void spmmc_prepare_data(struct spmmc_host *host, struct mmc_data *data) 407 { 408 u32 value, srcdst; 409 410 writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG); 411 writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG); 412 value = readl(host->base + SPMMC_SD_CONFIG0_REG); 413 if (data->flags & MMC_DATA_READ) { 414 value &= ~SPMMC_SD_TRANS_MODE; 415 value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 2); 416 value &= ~SPMMC_SD_AUTO_RESPONSE; 417 value &= ~SPMMC_SD_CMD_DUMMY; 418 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 419 srcdst &= ~SPMMC_DMA_SOURCE; 420 srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x2); 421 srcdst &= ~SPMMC_DMA_DESTINATION; 422 srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x1); 423 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 424 } else { 425 value &= ~SPMMC_SD_TRANS_MODE; 426 value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 1); 427 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 428 srcdst &= ~SPMMC_DMA_SOURCE; 429 srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x1); 430 srcdst &= ~SPMMC_DMA_DESTINATION; 431 srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x2); 432 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 433 } 434 435 value |= SPMMC_SD_LEN_MODE; 436 if (host->dmapio_mode == SPMMC_DMA_MODE) { 437 struct scatterlist *sg; 438 dma_addr_t dma_addr; 439 unsigned int dma_size; 440 int i, count = 1; 441 442 count = dma_map_sg(host->mmc->parent, data->sg, data->sg_len, 443 mmc_get_dma_dir(data)); 444 if (!count || count > SPMMC_MAX_DMA_MEMORY_SECTORS) { 445 data->error = -EINVAL; 446 447 return; 448 } 449 for_each_sg(data->sg, sg, count, i) { 450 dma_addr = sg_dma_address(sg); 451 dma_size = sg_dma_len(sg) / data->blksz - 1; 452 if (i == 0) { 453 writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG); 454 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG); 455 } else if (i == 1) { 456 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG); 457 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG); 458 } else if (i == 2) { 459 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG); 460 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG); 461 } else if (i == 3) { 462 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG); 463 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG); 464 } else if (i == 4) { 465 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG); 466 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG); 467 } else if (i == 5) { 468 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG); 469 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG); 470 } else if (i == 6) { 471 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG); 472 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG); 473 } else if (i == 7) { 474 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG); 475 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG); 476 } 477 } 478 value &= ~SPMMC_SD_PIO_MODE; 479 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 480 /* enable interrupt if needed */ 481 if (data->blksz * data->blocks > host->dma_int_threshold) { 482 host->dma_use_int = 1; 483 value = readl(host->base + SPMMC_SD_INT_REG); 484 value &= ~SPMMC_SDINT_SDCMPEN; 485 value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 1); /* sdcmpen */ 486 writel(value, host->base + SPMMC_SD_INT_REG); 487 } 488 } else { 489 value |= SPMMC_SD_PIO_MODE; 490 value |= SPMMC_RX4_EN; 491 writel(value, host->base + SPMMC_SD_CONFIG0_REG); 492 } 493 } 494 495 static inline void spmmc_trigger_transaction(struct spmmc_host *host) 496 { 497 u32 value = readl(host->base + SPMMC_SD_CTRL_REG); 498 499 value |= SPMMC_NEW_COMMAND_TRIGGER; 500 writel(value, host->base + SPMMC_SD_CTRL_REG); 501 } 502 503 static void spmmc_send_stop_cmd(struct spmmc_host *host) 504 { 505 struct mmc_command stop = {}; 506 u32 value; 507 508 stop.opcode = MMC_STOP_TRANSMISSION; 509 stop.arg = 0; 510 stop.flags = MMC_RSP_R1B; 511 spmmc_prepare_cmd(host, &stop); 512 value = readl(host->base + SPMMC_SD_INT_REG); 513 value &= ~SPMMC_SDINT_SDCMPEN; 514 value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 0); 515 writel(value, host->base + SPMMC_SD_INT_REG); 516 spmmc_trigger_transaction(host); 517 readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, value, 518 (value & SPMMC_SDSTATE_FINISH), 1, SPMMC_TIMEOUT_US); 519 } 520 521 static int spmmc_check_error(struct spmmc_host *host, struct mmc_request *mrq) 522 { 523 int ret = 0; 524 struct mmc_command *cmd = mrq->cmd; 525 struct mmc_data *data = mrq->data; 526 527 u32 value = readl(host->base + SPMMC_SD_STATE_REG); 528 u32 crc_token = FIELD_GET(SPMMC_CRCTOKEN_CHECK_RESULT, value); 529 530 if (value & SPMMC_SDSTATE_ERROR) { 531 u32 timing_cfg0 = 0; 532 533 value = readl(host->base + SPMMC_SD_STATUS_REG); 534 535 if (host->tuning_info.enable_tuning) { 536 timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 537 host->tuning_info.rd_crc_dly = FIELD_GET(SPMMC_SD_READ_CRC_DELAY, 538 timing_cfg0); 539 host->tuning_info.rd_dat_dly = FIELD_GET(SPMMC_SD_READ_DATA_DELAY, 540 timing_cfg0); 541 host->tuning_info.rd_rsp_dly = FIELD_GET(SPMMC_SD_READ_RESPONSE_DELAY, 542 timing_cfg0); 543 host->tuning_info.wr_cmd_dly = FIELD_GET(SPMMC_SD_WRITE_COMMAND_DELAY, 544 timing_cfg0); 545 host->tuning_info.wr_dat_dly = FIELD_GET(SPMMC_SD_WRITE_DATA_DELAY, 546 timing_cfg0); 547 } 548 549 if (value & SPMMC_SDSTATUS_RSP_TIMEOUT) { 550 ret = -ETIMEDOUT; 551 host->tuning_info.wr_cmd_dly++; 552 } else if (value & SPMMC_SDSTATUS_RSP_CRC7_ERROR) { 553 ret = -EILSEQ; 554 host->tuning_info.rd_rsp_dly++; 555 } else if (data) { 556 if ((value & SPMMC_SDSTATUS_STB_TIMEOUT)) { 557 ret = -ETIMEDOUT; 558 host->tuning_info.rd_dat_dly++; 559 } else if (value & SPMMC_SDSTATUS_RDATA_CRC16_ERROR) { 560 ret = -EILSEQ; 561 host->tuning_info.rd_dat_dly++; 562 } else if (value & SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT) { 563 ret = -ETIMEDOUT; 564 host->tuning_info.rd_crc_dly++; 565 } else if (value & SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR) { 566 ret = -EILSEQ; 567 if (crc_token == 0x5) 568 host->tuning_info.wr_dat_dly++; 569 else 570 host->tuning_info.rd_crc_dly++; 571 } 572 } 573 cmd->error = ret; 574 if (data) { 575 data->error = ret; 576 data->bytes_xfered = 0; 577 } 578 if (!host->tuning_info.need_tuning && host->tuning_info.enable_tuning) 579 cmd->retries = SPMMC_MAX_RETRIES; 580 spmmc_sw_reset(host); 581 582 if (host->tuning_info.enable_tuning) { 583 timing_cfg0 &= ~SPMMC_SD_READ_CRC_DELAY; 584 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, 585 host->tuning_info.rd_crc_dly); 586 timing_cfg0 &= ~SPMMC_SD_READ_DATA_DELAY; 587 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, 588 host->tuning_info.rd_dat_dly); 589 timing_cfg0 &= ~SPMMC_SD_READ_RESPONSE_DELAY; 590 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, 591 host->tuning_info.rd_rsp_dly); 592 timing_cfg0 &= ~SPMMC_SD_WRITE_COMMAND_DELAY; 593 timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, 594 host->tuning_info.wr_cmd_dly); 595 timing_cfg0 &= ~SPMMC_SD_WRITE_DATA_DELAY; 596 timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, 597 host->tuning_info.wr_dat_dly); 598 writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 599 } 600 } else if (data) { 601 data->error = 0; 602 data->bytes_xfered = data->blocks * data->blksz; 603 } 604 host->tuning_info.need_tuning = ret; 605 606 return ret; 607 } 608 609 /* 610 * the strategy is: 611 * 1. if several continuous delays are acceptable, we choose a middle one; 612 * 2. otherwise, we choose the first one. 613 */ 614 static inline int spmmc_find_best_delay(u8 candidate_dly) 615 { 616 int f, w, value; 617 618 if (!candidate_dly) 619 return 0; 620 f = ffs(candidate_dly) - 1; 621 w = hweight8(candidate_dly); 622 value = ((1 << w) - 1) << f; 623 if (0xff == (value & ~candidate_dly)) 624 return (f + w / 2); 625 else 626 return (f); 627 } 628 629 static void spmmc_xfer_data_pio(struct spmmc_host *host, struct mmc_data *data) 630 { 631 u32 *buf; 632 int data_left = data->blocks * data->blksz; 633 int consumed, remain; 634 635 struct sg_mapping_iter sg_miter; 636 unsigned int flags = 0; 637 638 if (data->flags & MMC_DATA_WRITE) 639 flags |= SG_MITER_FROM_SG; 640 else 641 flags |= SG_MITER_TO_SG; 642 sg_miter_start(&sg_miter, data->sg, data->sg_len, flags); 643 while (data_left > 0) { 644 consumed = 0; 645 if (!sg_miter_next(&sg_miter)) 646 break; 647 buf = sg_miter.addr; 648 remain = sg_miter.length; 649 do { 650 if (data->flags & MMC_DATA_WRITE) { 651 if (spmmc_wait_txbuf_empty(host)) 652 goto done; 653 writel(*buf, host->base + SPMMC_SD_PIODATATX_REG); 654 } else { 655 if (spmmc_wait_rxbuf_full(host)) 656 goto done; 657 *buf = readl(host->base + SPMMC_SD_PIODATARX_REG); 658 } 659 buf++; 660 /* tx/rx 4 bytes one time in pio mode */ 661 consumed += 4; 662 remain -= 4; 663 } while (remain); 664 sg_miter.consumed = consumed; 665 data_left -= consumed; 666 } 667 done: 668 sg_miter_stop(&sg_miter); 669 } 670 671 static void spmmc_controller_init(struct spmmc_host *host) 672 { 673 u32 value; 674 int ret = reset_control_assert(host->rstc); 675 676 if (!ret) { 677 usleep_range(1000, 1250); 678 ret = reset_control_deassert(host->rstc); 679 } 680 681 value = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 682 value &= ~SPMMC_MEDIA_TYPE; 683 value |= FIELD_PREP(SPMMC_MEDIA_TYPE, SPMMC_MEDIA_SD); 684 writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); 685 } 686 687 /* 688 * 1. unmap scatterlist if needed; 689 * 2. get response & check error conditions; 690 * 3. notify mmc layer the request is done 691 */ 692 static void spmmc_finish_request(struct spmmc_host *host, struct mmc_request *mrq) 693 { 694 struct mmc_command *cmd; 695 struct mmc_data *data; 696 697 if (!mrq) 698 return; 699 700 cmd = mrq->cmd; 701 data = mrq->data; 702 703 if (data && SPMMC_DMA_MODE == host->dmapio_mode) { 704 dma_unmap_sg(host->mmc->parent, data->sg, data->sg_len, mmc_get_dma_dir(data)); 705 host->dma_use_int = 0; 706 } 707 708 spmmc_get_rsp(host, cmd); 709 spmmc_check_error(host, mrq); 710 if (mrq->stop) 711 spmmc_send_stop_cmd(host); 712 713 host->mrq = NULL; 714 mmc_request_done(host->mmc, mrq); 715 } 716 717 /* Interrupt Service Routine */ 718 static irqreturn_t spmmc_irq(int irq, void *dev_id) 719 { 720 struct spmmc_host *host = dev_id; 721 u32 value = readl(host->base + SPMMC_SD_INT_REG); 722 723 if ((value & SPMMC_SDINT_SDCMP) && (value & SPMMC_SDINT_SDCMPEN)) { 724 value &= ~SPMMC_SDINT_SDCMPEN; 725 value |= SPMMC_SDINT_SDCMPCLR; 726 writel(value, host->base + SPMMC_SD_INT_REG); 727 return IRQ_WAKE_THREAD; 728 } 729 return IRQ_HANDLED; 730 } 731 732 static void spmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 733 { 734 struct spmmc_host *host = mmc_priv(mmc); 735 struct mmc_data *data; 736 struct mmc_command *cmd; 737 738 host->mrq = mrq; 739 data = mrq->data; 740 cmd = mrq->cmd; 741 742 spmmc_prepare_cmd(host, cmd); 743 /* we need manually read response R2. */ 744 if (cmd->flags & MMC_RSP_136) { 745 spmmc_trigger_transaction(host); 746 spmmc_get_rsp(host, cmd); 747 spmmc_wait_finish(host); 748 spmmc_check_error(host, mrq); 749 host->mrq = NULL; 750 mmc_request_done(host->mmc, mrq); 751 } else { 752 if (data) 753 spmmc_prepare_data(host, data); 754 755 if (host->dmapio_mode == SPMMC_PIO_MODE && data) { 756 u32 value; 757 /* pio data transfer do not use interrupt */ 758 value = readl(host->base + SPMMC_SD_INT_REG); 759 value &= ~SPMMC_SDINT_SDCMPEN; 760 writel(value, host->base + SPMMC_SD_INT_REG); 761 spmmc_trigger_transaction(host); 762 spmmc_xfer_data_pio(host, data); 763 spmmc_wait_finish(host); 764 spmmc_finish_request(host, mrq); 765 } else { 766 if (host->dma_use_int) { 767 spmmc_trigger_transaction(host); 768 } else { 769 spmmc_trigger_transaction(host); 770 spmmc_wait_finish(host); 771 spmmc_finish_request(host, mrq); 772 } 773 } 774 } 775 } 776 777 static void spmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 778 { 779 struct spmmc_host *host = (struct spmmc_host *)mmc_priv(mmc); 780 781 spmmc_set_bus_clk(host, ios->clock); 782 spmmc_set_bus_timing(host, ios->timing); 783 spmmc_set_bus_width(host, ios->bus_width); 784 /* ensure mode is correct, because we might have hw reset the controller */ 785 spmmc_set_sdmmc_mode(host); 786 } 787 788 /* 789 * Return values for the get_cd callback should be: 790 * 0 for a absent card 791 * 1 for a present card 792 * -ENOSYS when not supported (equal to NULL callback) 793 * or a negative errno value when something bad happened 794 */ 795 static int spmmc_get_cd(struct mmc_host *mmc) 796 { 797 int ret = 0; 798 799 if (mmc_host_can_gpio_cd(mmc)) 800 ret = mmc_gpio_get_cd(mmc); 801 802 if (ret < 0) 803 ret = 0; 804 805 return ret; 806 } 807 808 static int spmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 809 { 810 struct spmmc_host *host = mmc_priv(mmc); 811 u8 smpl_dly = 0, candidate_dly = 0; 812 u32 value; 813 814 host->tuning_info.enable_tuning = 0; 815 do { 816 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 817 value &= ~SPMMC_SD_READ_RESPONSE_DELAY; 818 value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); 819 value &= ~SPMMC_SD_READ_DATA_DELAY; 820 value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); 821 value &= ~SPMMC_SD_READ_CRC_DELAY; 822 value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); 823 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 824 825 if (!mmc_send_tuning(mmc, opcode, NULL)) { 826 candidate_dly |= (1 << smpl_dly); 827 break; 828 } 829 } while (smpl_dly++ <= SPMMC_MAX_TUNABLE_DLY); 830 host->tuning_info.enable_tuning = 1; 831 832 if (candidate_dly) { 833 smpl_dly = spmmc_find_best_delay(candidate_dly); 834 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); 835 value &= ~SPMMC_SD_READ_RESPONSE_DELAY; 836 value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); 837 value &= ~SPMMC_SD_READ_DATA_DELAY; 838 value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); 839 value &= ~SPMMC_SD_READ_CRC_DELAY; 840 value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); 841 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); 842 return 0; 843 } 844 845 return -EIO; 846 } 847 848 static const struct mmc_host_ops spmmc_ops = { 849 .request = spmmc_request, 850 .set_ios = spmmc_set_ios, 851 .get_cd = spmmc_get_cd, 852 .execute_tuning = spmmc_execute_tuning, 853 }; 854 855 static irqreturn_t spmmc_func_finish_req(int irq, void *dev_id) 856 { 857 struct spmmc_host *host = dev_id; 858 859 spmmc_finish_request(host, host->mrq); 860 861 return IRQ_HANDLED; 862 } 863 864 static int spmmc_drv_probe(struct platform_device *pdev) 865 { 866 struct mmc_host *mmc; 867 struct resource *res; 868 struct spmmc_host *host; 869 int ret = 0; 870 871 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct spmmc_host)); 872 if (!mmc) 873 return -ENOMEM; 874 875 host = mmc_priv(mmc); 876 host->mmc = mmc; 877 host->dmapio_mode = SPMMC_DMA_MODE; 878 host->dma_int_threshold = 1024; 879 880 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 881 if (IS_ERR(host->base)) 882 return PTR_ERR(host->base); 883 884 host->clk = devm_clk_get(&pdev->dev, NULL); 885 if (IS_ERR(host->clk)) 886 return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "clk get fail\n"); 887 888 host->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 889 if (IS_ERR(host->rstc)) 890 return dev_err_probe(&pdev->dev, PTR_ERR(host->rstc), "rst get fail\n"); 891 892 host->irq = platform_get_irq(pdev, 0); 893 if (host->irq < 0) 894 return host->irq; 895 896 ret = devm_request_threaded_irq(&pdev->dev, host->irq, 897 spmmc_irq, spmmc_func_finish_req, IRQF_SHARED, 898 NULL, host); 899 if (ret) 900 return ret; 901 902 ret = clk_prepare_enable(host->clk); 903 if (ret) 904 return dev_err_probe(&pdev->dev, ret, "failed to enable clk\n"); 905 906 ret = mmc_of_parse(mmc); 907 if (ret) 908 goto clk_disable; 909 910 mmc->ops = &spmmc_ops; 911 mmc->f_min = SPMMC_MIN_CLK; 912 if (mmc->f_max > SPMMC_MAX_CLK) 913 mmc->f_max = SPMMC_MAX_CLK; 914 915 ret = mmc_regulator_get_supply(mmc); 916 if (ret) 917 goto clk_disable; 918 919 if (!mmc->ocr_avail) 920 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 921 mmc->max_seg_size = SPMMC_MAX_BLK_COUNT * 512; 922 mmc->max_segs = SPMMC_MAX_DMA_MEMORY_SECTORS; 923 mmc->max_req_size = SPMMC_MAX_BLK_COUNT * 512; 924 mmc->max_blk_size = 512; 925 mmc->max_blk_count = SPMMC_MAX_BLK_COUNT; 926 927 dev_set_drvdata(&pdev->dev, host); 928 spmmc_controller_init(host); 929 spmmc_set_sdmmc_mode(host); 930 host->tuning_info.enable_tuning = 1; 931 pm_runtime_set_active(&pdev->dev); 932 pm_runtime_enable(&pdev->dev); 933 ret = mmc_add_host(mmc); 934 if (ret) 935 goto pm_disable; 936 937 return 0; 938 939 pm_disable: 940 pm_runtime_disable(&pdev->dev); 941 942 clk_disable: 943 clk_disable_unprepare(host->clk); 944 return ret; 945 } 946 947 static void spmmc_drv_remove(struct platform_device *dev) 948 { 949 struct spmmc_host *host = platform_get_drvdata(dev); 950 951 mmc_remove_host(host->mmc); 952 pm_runtime_get_sync(&dev->dev); 953 clk_disable_unprepare(host->clk); 954 pm_runtime_put_noidle(&dev->dev); 955 pm_runtime_disable(&dev->dev); 956 } 957 958 static int spmmc_pm_runtime_suspend(struct device *dev) 959 { 960 struct spmmc_host *host; 961 962 host = dev_get_drvdata(dev); 963 clk_disable_unprepare(host->clk); 964 965 return 0; 966 } 967 968 static int spmmc_pm_runtime_resume(struct device *dev) 969 { 970 struct spmmc_host *host; 971 972 host = dev_get_drvdata(dev); 973 974 return clk_prepare_enable(host->clk); 975 } 976 977 static DEFINE_RUNTIME_DEV_PM_OPS(spmmc_pm_ops, spmmc_pm_runtime_suspend, 978 spmmc_pm_runtime_resume, NULL); 979 980 static const struct of_device_id spmmc_of_table[] = { 981 { 982 .compatible = "sunplus,sp7021-mmc", 983 }, 984 {/* sentinel */} 985 }; 986 MODULE_DEVICE_TABLE(of, spmmc_of_table); 987 988 static struct platform_driver spmmc_driver = { 989 .probe = spmmc_drv_probe, 990 .remove = spmmc_drv_remove, 991 .driver = { 992 .name = "spmmc", 993 .pm = pm_ptr(&spmmc_pm_ops), 994 .of_match_table = spmmc_of_table, 995 }, 996 }; 997 module_platform_driver(spmmc_driver); 998 999 MODULE_AUTHOR("Tony Huang <tonyhuang.sunplus@gmail.com>"); 1000 MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>"); 1001 MODULE_DESCRIPTION("Sunplus MMC controller driver"); 1002 MODULE_LICENSE("GPL"); 1003