1 /* 2 * MMCIF eMMC driver. 3 * 4 * Copyright (C) 2010 Renesas Solutions Corp. 5 * Yusuke Goda <yusuke.goda.sx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 * 11 * 12 * TODO 13 * 1. DMA 14 * 2. Power management 15 * 3. Handle MMC errors better 16 * 17 */ 18 19 #include <linux/dma-mapping.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/card.h> 22 #include <linux/mmc/core.h> 23 #include <linux/mmc/mmc.h> 24 #include <linux/mmc/sdio.h> 25 #include <linux/delay.h> 26 #include <linux/platform_device.h> 27 #include <linux/clk.h> 28 #include <linux/mmc/sh_mmcif.h> 29 30 #define DRIVER_NAME "sh_mmcif" 31 #define DRIVER_VERSION "2010-04-28" 32 33 /* CE_CMD_SET */ 34 #define CMD_MASK 0x3f000000 35 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 36 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 37 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 38 #define CMD_SET_RBSY (1 << 21) /* R1b */ 39 #define CMD_SET_CCSEN (1 << 20) 40 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 41 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 42 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 43 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 44 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 45 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 46 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 47 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 48 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 49 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 50 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 51 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 52 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 53 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 54 #define CMD_SET_CCSH (1 << 5) 55 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 56 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 57 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 58 59 /* CE_CMD_CTRL */ 60 #define CMD_CTRL_BREAK (1 << 0) 61 62 /* CE_BLOCK_SET */ 63 #define BLOCK_SIZE_MASK 0x0000ffff 64 65 /* CE_CLK_CTRL */ 66 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */ 67 #define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) 68 #define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16)) 69 #define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */ 70 #define SRBSYTO_29 ((1 << 11) | (1 << 10) | \ 71 (1 << 9) | (1 << 8)) /* resp busy timeout */ 72 #define SRWDTO_29 ((1 << 7) | (1 << 6) | \ 73 (1 << 5) | (1 << 4)) /* read/write timeout */ 74 #define SCCSTO_29 ((1 << 3) | (1 << 2) | \ 75 (1 << 1) | (1 << 0)) /* ccs timeout */ 76 77 /* CE_BUF_ACC */ 78 #define BUF_ACC_DMAWEN (1 << 25) 79 #define BUF_ACC_DMAREN (1 << 24) 80 #define BUF_ACC_BUSW_32 (0 << 17) 81 #define BUF_ACC_BUSW_16 (1 << 17) 82 #define BUF_ACC_ATYP (1 << 16) 83 84 /* CE_INT */ 85 #define INT_CCSDE (1 << 29) 86 #define INT_CMD12DRE (1 << 26) 87 #define INT_CMD12RBE (1 << 25) 88 #define INT_CMD12CRE (1 << 24) 89 #define INT_DTRANE (1 << 23) 90 #define INT_BUFRE (1 << 22) 91 #define INT_BUFWEN (1 << 21) 92 #define INT_BUFREN (1 << 20) 93 #define INT_CCSRCV (1 << 19) 94 #define INT_RBSYE (1 << 17) 95 #define INT_CRSPE (1 << 16) 96 #define INT_CMDVIO (1 << 15) 97 #define INT_BUFVIO (1 << 14) 98 #define INT_WDATERR (1 << 11) 99 #define INT_RDATERR (1 << 10) 100 #define INT_RIDXERR (1 << 9) 101 #define INT_RSPERR (1 << 8) 102 #define INT_CCSTO (1 << 5) 103 #define INT_CRCSTO (1 << 4) 104 #define INT_WDATTO (1 << 3) 105 #define INT_RDATTO (1 << 2) 106 #define INT_RBSYTO (1 << 1) 107 #define INT_RSPTO (1 << 0) 108 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 109 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 110 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 111 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 112 113 /* CE_INT_MASK */ 114 #define MASK_ALL 0x00000000 115 #define MASK_MCCSDE (1 << 29) 116 #define MASK_MCMD12DRE (1 << 26) 117 #define MASK_MCMD12RBE (1 << 25) 118 #define MASK_MCMD12CRE (1 << 24) 119 #define MASK_MDTRANE (1 << 23) 120 #define MASK_MBUFRE (1 << 22) 121 #define MASK_MBUFWEN (1 << 21) 122 #define MASK_MBUFREN (1 << 20) 123 #define MASK_MCCSRCV (1 << 19) 124 #define MASK_MRBSYE (1 << 17) 125 #define MASK_MCRSPE (1 << 16) 126 #define MASK_MCMDVIO (1 << 15) 127 #define MASK_MBUFVIO (1 << 14) 128 #define MASK_MWDATERR (1 << 11) 129 #define MASK_MRDATERR (1 << 10) 130 #define MASK_MRIDXERR (1 << 9) 131 #define MASK_MRSPERR (1 << 8) 132 #define MASK_MCCSTO (1 << 5) 133 #define MASK_MCRCSTO (1 << 4) 134 #define MASK_MWDATTO (1 << 3) 135 #define MASK_MRDATTO (1 << 2) 136 #define MASK_MRBSYTO (1 << 1) 137 #define MASK_MRSPTO (1 << 0) 138 139 /* CE_HOST_STS1 */ 140 #define STS1_CMDSEQ (1 << 31) 141 142 /* CE_HOST_STS2 */ 143 #define STS2_CRCSTE (1 << 31) 144 #define STS2_CRC16E (1 << 30) 145 #define STS2_AC12CRCE (1 << 29) 146 #define STS2_RSPCRC7E (1 << 28) 147 #define STS2_CRCSTEBE (1 << 27) 148 #define STS2_RDATEBE (1 << 26) 149 #define STS2_AC12REBE (1 << 25) 150 #define STS2_RSPEBE (1 << 24) 151 #define STS2_AC12IDXE (1 << 23) 152 #define STS2_RSPIDXE (1 << 22) 153 #define STS2_CCSTO (1 << 15) 154 #define STS2_RDATTO (1 << 14) 155 #define STS2_DATBSYTO (1 << 13) 156 #define STS2_CRCSTTO (1 << 12) 157 #define STS2_AC12BSYTO (1 << 11) 158 #define STS2_RSPBSYTO (1 << 10) 159 #define STS2_AC12RSPTO (1 << 9) 160 #define STS2_RSPTO (1 << 8) 161 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 162 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 163 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 164 STS2_DATBSYTO | STS2_CRCSTTO | \ 165 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 166 STS2_AC12RSPTO | STS2_RSPTO) 167 168 /* CE_VERSION */ 169 #define SOFT_RST_ON (1 << 31) 170 #define SOFT_RST_OFF (0 << 31) 171 172 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 173 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 174 #define CLKDEV_INIT 400000 /* 400 KHz */ 175 176 struct sh_mmcif_host { 177 struct mmc_host *mmc; 178 struct mmc_data *data; 179 struct mmc_command *cmd; 180 struct platform_device *pd; 181 struct clk *hclk; 182 unsigned int clk; 183 int bus_width; 184 u16 wait_int; 185 u16 sd_error; 186 long timeout; 187 void __iomem *addr; 188 wait_queue_head_t intr_wait; 189 }; 190 191 192 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 193 unsigned int reg, u32 val) 194 { 195 writel(val | readl(host->addr + reg), host->addr + reg); 196 } 197 198 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 199 unsigned int reg, u32 val) 200 { 201 writel(~val & readl(host->addr + reg), host->addr + reg); 202 } 203 204 205 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 206 { 207 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 208 209 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 210 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 211 212 if (!clk) 213 return; 214 if (p->sup_pclk && clk == host->clk) 215 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 216 else 217 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 218 (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16)); 219 220 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 221 } 222 223 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 224 { 225 u32 tmp; 226 227 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 228 229 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 230 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 231 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 232 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 233 /* byte swap on */ 234 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 235 } 236 237 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 238 { 239 u32 state1, state2; 240 int ret, timeout = 10000000; 241 242 host->sd_error = 0; 243 host->wait_int = 0; 244 245 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 246 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 247 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1); 248 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2); 249 250 if (state1 & STS1_CMDSEQ) { 251 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 252 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 253 while (1) { 254 timeout--; 255 if (timeout < 0) { 256 pr_err(DRIVER_NAME": Forceed end of " \ 257 "command sequence timeout err\n"); 258 return -EIO; 259 } 260 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 261 & STS1_CMDSEQ)) 262 break; 263 mdelay(1); 264 } 265 sh_mmcif_sync_reset(host); 266 pr_debug(DRIVER_NAME": Forced end of command sequence\n"); 267 return -EIO; 268 } 269 270 if (state2 & STS2_CRC_ERR) { 271 pr_debug(DRIVER_NAME": Happened CRC error\n"); 272 ret = -EIO; 273 } else if (state2 & STS2_TIMEOUT_ERR) { 274 pr_debug(DRIVER_NAME": Happened Timeout error\n"); 275 ret = -ETIMEDOUT; 276 } else { 277 pr_debug(DRIVER_NAME": Happened End/Index error\n"); 278 ret = -EIO; 279 } 280 return ret; 281 } 282 283 static int sh_mmcif_single_read(struct sh_mmcif_host *host, 284 struct mmc_request *mrq) 285 { 286 struct mmc_data *data = mrq->data; 287 long time; 288 u32 blocksize, i, *p = sg_virt(data->sg); 289 290 host->wait_int = 0; 291 292 /* buf read enable */ 293 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 294 time = wait_event_interruptible_timeout(host->intr_wait, 295 host->wait_int == 1 || 296 host->sd_error == 1, host->timeout); 297 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) 298 return sh_mmcif_error_manage(host); 299 300 host->wait_int = 0; 301 blocksize = (BLOCK_SIZE_MASK & 302 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 303 for (i = 0; i < blocksize / 4; i++) 304 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 305 306 /* buffer read end */ 307 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 308 time = wait_event_interruptible_timeout(host->intr_wait, 309 host->wait_int == 1 || 310 host->sd_error == 1, host->timeout); 311 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) 312 return sh_mmcif_error_manage(host); 313 314 host->wait_int = 0; 315 return 0; 316 } 317 318 static int sh_mmcif_multi_read(struct sh_mmcif_host *host, 319 struct mmc_request *mrq) 320 { 321 struct mmc_data *data = mrq->data; 322 long time; 323 u32 blocksize, i, j, sec, *p; 324 325 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 326 MMCIF_CE_BLOCK_SET); 327 for (j = 0; j < data->sg_len; j++) { 328 p = sg_virt(data->sg); 329 host->wait_int = 0; 330 for (sec = 0; sec < data->sg->length / blocksize; sec++) { 331 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 332 /* buf read enable */ 333 time = wait_event_interruptible_timeout(host->intr_wait, 334 host->wait_int == 1 || 335 host->sd_error == 1, host->timeout); 336 337 if (host->wait_int != 1 && 338 (time == 0 || host->sd_error != 0)) 339 return sh_mmcif_error_manage(host); 340 341 host->wait_int = 0; 342 for (i = 0; i < blocksize / 4; i++) 343 *p++ = sh_mmcif_readl(host->addr, 344 MMCIF_CE_DATA); 345 } 346 if (j < data->sg_len - 1) 347 data->sg++; 348 } 349 return 0; 350 } 351 352 static int sh_mmcif_single_write(struct sh_mmcif_host *host, 353 struct mmc_request *mrq) 354 { 355 struct mmc_data *data = mrq->data; 356 long time; 357 u32 blocksize, i, *p = sg_virt(data->sg); 358 359 host->wait_int = 0; 360 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 361 362 /* buf write enable */ 363 time = wait_event_interruptible_timeout(host->intr_wait, 364 host->wait_int == 1 || 365 host->sd_error == 1, host->timeout); 366 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) 367 return sh_mmcif_error_manage(host); 368 369 host->wait_int = 0; 370 blocksize = (BLOCK_SIZE_MASK & 371 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 372 for (i = 0; i < blocksize / 4; i++) 373 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 374 375 /* buffer write end */ 376 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 377 378 time = wait_event_interruptible_timeout(host->intr_wait, 379 host->wait_int == 1 || 380 host->sd_error == 1, host->timeout); 381 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) 382 return sh_mmcif_error_manage(host); 383 384 host->wait_int = 0; 385 return 0; 386 } 387 388 static int sh_mmcif_multi_write(struct sh_mmcif_host *host, 389 struct mmc_request *mrq) 390 { 391 struct mmc_data *data = mrq->data; 392 long time; 393 u32 i, sec, j, blocksize, *p; 394 395 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 396 MMCIF_CE_BLOCK_SET); 397 398 for (j = 0; j < data->sg_len; j++) { 399 p = sg_virt(data->sg); 400 host->wait_int = 0; 401 for (sec = 0; sec < data->sg->length / blocksize; sec++) { 402 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 403 /* buf write enable*/ 404 time = wait_event_interruptible_timeout(host->intr_wait, 405 host->wait_int == 1 || 406 host->sd_error == 1, host->timeout); 407 408 if (host->wait_int != 1 && 409 (time == 0 || host->sd_error != 0)) 410 return sh_mmcif_error_manage(host); 411 412 host->wait_int = 0; 413 for (i = 0; i < blocksize / 4; i++) 414 sh_mmcif_writel(host->addr, 415 MMCIF_CE_DATA, *p++); 416 } 417 if (j < data->sg_len - 1) 418 data->sg++; 419 } 420 return 0; 421 } 422 423 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 424 struct mmc_command *cmd) 425 { 426 if (cmd->flags & MMC_RSP_136) { 427 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 428 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 429 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 430 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 431 } else 432 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 433 } 434 435 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 436 struct mmc_command *cmd) 437 { 438 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 439 } 440 441 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 442 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc) 443 { 444 u32 tmp = 0; 445 446 /* Response Type check */ 447 switch (mmc_resp_type(cmd)) { 448 case MMC_RSP_NONE: 449 tmp |= CMD_SET_RTYP_NO; 450 break; 451 case MMC_RSP_R1: 452 case MMC_RSP_R1B: 453 case MMC_RSP_R3: 454 tmp |= CMD_SET_RTYP_6B; 455 break; 456 case MMC_RSP_R2: 457 tmp |= CMD_SET_RTYP_17B; 458 break; 459 default: 460 pr_err(DRIVER_NAME": Not support type response.\n"); 461 break; 462 } 463 switch (opc) { 464 /* RBSY */ 465 case MMC_SWITCH: 466 case MMC_STOP_TRANSMISSION: 467 case MMC_SET_WRITE_PROT: 468 case MMC_CLR_WRITE_PROT: 469 case MMC_ERASE: 470 case MMC_GEN_CMD: 471 tmp |= CMD_SET_RBSY; 472 break; 473 } 474 /* WDAT / DATW */ 475 if (host->data) { 476 tmp |= CMD_SET_WDAT; 477 switch (host->bus_width) { 478 case MMC_BUS_WIDTH_1: 479 tmp |= CMD_SET_DATW_1; 480 break; 481 case MMC_BUS_WIDTH_4: 482 tmp |= CMD_SET_DATW_4; 483 break; 484 case MMC_BUS_WIDTH_8: 485 tmp |= CMD_SET_DATW_8; 486 break; 487 default: 488 pr_err(DRIVER_NAME": Not support bus width.\n"); 489 break; 490 } 491 } 492 /* DWEN */ 493 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 494 tmp |= CMD_SET_DWEN; 495 /* CMLTE/CMD12EN */ 496 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 497 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 498 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 499 mrq->data->blocks << 16); 500 } 501 /* RIDXC[1:0] check bits */ 502 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 503 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 504 tmp |= CMD_SET_RIDXC_BITS; 505 /* RCRC7C[1:0] check bits */ 506 if (opc == MMC_SEND_OP_COND) 507 tmp |= CMD_SET_CRC7C_BITS; 508 /* RCRC7C[1:0] internal CRC7 */ 509 if (opc == MMC_ALL_SEND_CID || 510 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 511 tmp |= CMD_SET_CRC7C_INTERNAL; 512 513 return opc = ((opc << 24) | tmp); 514 } 515 516 static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host, 517 struct mmc_request *mrq, u32 opc) 518 { 519 u32 ret; 520 521 switch (opc) { 522 case MMC_READ_MULTIPLE_BLOCK: 523 ret = sh_mmcif_multi_read(host, mrq); 524 break; 525 case MMC_WRITE_MULTIPLE_BLOCK: 526 ret = sh_mmcif_multi_write(host, mrq); 527 break; 528 case MMC_WRITE_BLOCK: 529 ret = sh_mmcif_single_write(host, mrq); 530 break; 531 case MMC_READ_SINGLE_BLOCK: 532 case MMC_SEND_EXT_CSD: 533 ret = sh_mmcif_single_read(host, mrq); 534 break; 535 default: 536 pr_err(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc); 537 ret = -EINVAL; 538 break; 539 } 540 return ret; 541 } 542 543 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 544 struct mmc_request *mrq, struct mmc_command *cmd) 545 { 546 long time; 547 int ret = 0, mask = 0; 548 u32 opc = cmd->opcode; 549 550 host->cmd = cmd; 551 552 switch (opc) { 553 /* respons busy check */ 554 case MMC_SWITCH: 555 case MMC_STOP_TRANSMISSION: 556 case MMC_SET_WRITE_PROT: 557 case MMC_CLR_WRITE_PROT: 558 case MMC_ERASE: 559 case MMC_GEN_CMD: 560 mask = MASK_MRBSYE; 561 break; 562 default: 563 mask = MASK_MCRSPE; 564 break; 565 } 566 mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | 567 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | 568 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | 569 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 570 571 if (host->data) { 572 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 573 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 574 mrq->data->blksz); 575 } 576 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 577 578 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 579 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 580 /* set arg */ 581 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 582 host->wait_int = 0; 583 /* set cmd */ 584 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 585 586 time = wait_event_interruptible_timeout(host->intr_wait, 587 host->wait_int == 1 || host->sd_error == 1, host->timeout); 588 if (host->wait_int != 1 && time == 0) { 589 cmd->error = sh_mmcif_error_manage(host); 590 return; 591 } 592 if (host->sd_error) { 593 switch (cmd->opcode) { 594 case MMC_ALL_SEND_CID: 595 case MMC_SELECT_CARD: 596 case MMC_APP_CMD: 597 cmd->error = -ETIMEDOUT; 598 break; 599 default: 600 pr_debug("%s: Cmd(d'%d) err\n", 601 DRIVER_NAME, cmd->opcode); 602 cmd->error = sh_mmcif_error_manage(host); 603 break; 604 } 605 host->sd_error = 0; 606 host->wait_int = 0; 607 return; 608 } 609 if (!(cmd->flags & MMC_RSP_PRESENT)) { 610 cmd->error = ret; 611 host->wait_int = 0; 612 return; 613 } 614 if (host->wait_int == 1) { 615 sh_mmcif_get_response(host, cmd); 616 host->wait_int = 0; 617 } 618 if (host->data) { 619 ret = sh_mmcif_data_trans(host, mrq, cmd->opcode); 620 if (ret < 0) 621 mrq->data->bytes_xfered = 0; 622 else 623 mrq->data->bytes_xfered = 624 mrq->data->blocks * mrq->data->blksz; 625 } 626 cmd->error = ret; 627 } 628 629 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 630 struct mmc_request *mrq, struct mmc_command *cmd) 631 { 632 long time; 633 634 if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 635 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 636 else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 637 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 638 else { 639 pr_err(DRIVER_NAME": not support stop cmd\n"); 640 cmd->error = sh_mmcif_error_manage(host); 641 return; 642 } 643 644 time = wait_event_interruptible_timeout(host->intr_wait, 645 host->wait_int == 1 || 646 host->sd_error == 1, host->timeout); 647 if (host->wait_int != 1 && (time == 0 || host->sd_error != 0)) { 648 cmd->error = sh_mmcif_error_manage(host); 649 return; 650 } 651 sh_mmcif_get_cmd12response(host, cmd); 652 host->wait_int = 0; 653 cmd->error = 0; 654 } 655 656 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 657 { 658 struct sh_mmcif_host *host = mmc_priv(mmc); 659 660 switch (mrq->cmd->opcode) { 661 /* MMCIF does not support SD/SDIO command */ 662 case SD_IO_SEND_OP_COND: 663 case MMC_APP_CMD: 664 mrq->cmd->error = -ETIMEDOUT; 665 mmc_request_done(mmc, mrq); 666 return; 667 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 668 if (!mrq->data) { 669 /* send_if_cond cmd (not support) */ 670 mrq->cmd->error = -ETIMEDOUT; 671 mmc_request_done(mmc, mrq); 672 return; 673 } 674 break; 675 default: 676 break; 677 } 678 host->data = mrq->data; 679 sh_mmcif_start_cmd(host, mrq, mrq->cmd); 680 host->data = NULL; 681 682 if (mrq->cmd->error != 0) { 683 mmc_request_done(mmc, mrq); 684 return; 685 } 686 if (mrq->stop) 687 sh_mmcif_stop_cmd(host, mrq, mrq->stop); 688 mmc_request_done(mmc, mrq); 689 } 690 691 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 692 { 693 struct sh_mmcif_host *host = mmc_priv(mmc); 694 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 695 696 if (ios->power_mode == MMC_POWER_OFF) { 697 /* clock stop */ 698 sh_mmcif_clock_control(host, 0); 699 if (p->down_pwr) 700 p->down_pwr(host->pd); 701 return; 702 } else if (ios->power_mode == MMC_POWER_UP) { 703 if (p->set_pwr) 704 p->set_pwr(host->pd, ios->power_mode); 705 } 706 707 if (ios->clock) 708 sh_mmcif_clock_control(host, ios->clock); 709 710 host->bus_width = ios->bus_width; 711 } 712 713 static struct mmc_host_ops sh_mmcif_ops = { 714 .request = sh_mmcif_request, 715 .set_ios = sh_mmcif_set_ios, 716 }; 717 718 static void sh_mmcif_detect(struct mmc_host *mmc) 719 { 720 mmc_detect_change(mmc, 0); 721 } 722 723 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 724 { 725 struct sh_mmcif_host *host = dev_id; 726 u32 state = 0; 727 int err = 0; 728 729 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 730 731 if (state & INT_RBSYE) { 732 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 733 ~(INT_RBSYE | INT_CRSPE)); 734 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 735 } else if (state & INT_CRSPE) { 736 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 737 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 738 } else if (state & INT_BUFREN) { 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 740 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 741 } else if (state & INT_BUFWEN) { 742 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 743 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 744 } else if (state & INT_CMD12DRE) { 745 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 746 ~(INT_CMD12DRE | INT_CMD12RBE | 747 INT_CMD12CRE | INT_BUFRE)); 748 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 749 } else if (state & INT_BUFRE) { 750 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 751 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 752 } else if (state & INT_DTRANE) { 753 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 754 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 755 } else if (state & INT_CMD12RBE) { 756 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 757 ~(INT_CMD12RBE | INT_CMD12CRE)); 758 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 759 } else if (state & INT_ERR_STS) { 760 /* err interrupts */ 761 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 763 err = 1; 764 } else { 765 pr_debug("%s: Not support int\n", DRIVER_NAME); 766 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 767 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 768 err = 1; 769 } 770 if (err) { 771 host->sd_error = 1; 772 pr_debug("%s: int err state = %08x\n", DRIVER_NAME, state); 773 } 774 host->wait_int = 1; 775 wake_up(&host->intr_wait); 776 777 return IRQ_HANDLED; 778 } 779 780 static int __devinit sh_mmcif_probe(struct platform_device *pdev) 781 { 782 int ret = 0, irq[2]; 783 struct mmc_host *mmc; 784 struct sh_mmcif_host *host = NULL; 785 struct sh_mmcif_plat_data *pd = NULL; 786 struct resource *res; 787 void __iomem *reg; 788 char clk_name[8]; 789 790 irq[0] = platform_get_irq(pdev, 0); 791 irq[1] = platform_get_irq(pdev, 1); 792 if (irq[0] < 0 || irq[1] < 0) { 793 pr_err(DRIVER_NAME": Get irq error\n"); 794 return -ENXIO; 795 } 796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 797 if (!res) { 798 dev_err(&pdev->dev, "platform_get_resource error.\n"); 799 return -ENXIO; 800 } 801 reg = ioremap(res->start, resource_size(res)); 802 if (!reg) { 803 dev_err(&pdev->dev, "ioremap error.\n"); 804 return -ENOMEM; 805 } 806 pd = (struct sh_mmcif_plat_data *)(pdev->dev.platform_data); 807 if (!pd) { 808 dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 809 ret = -ENXIO; 810 goto clean_up; 811 } 812 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 813 if (!mmc) { 814 ret = -ENOMEM; 815 goto clean_up; 816 } 817 host = mmc_priv(mmc); 818 host->mmc = mmc; 819 host->addr = reg; 820 host->timeout = 1000; 821 822 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 823 host->hclk = clk_get(&pdev->dev, clk_name); 824 if (IS_ERR(host->hclk)) { 825 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 826 ret = PTR_ERR(host->hclk); 827 goto clean_up1; 828 } 829 clk_enable(host->hclk); 830 host->clk = clk_get_rate(host->hclk); 831 host->pd = pdev; 832 833 init_waitqueue_head(&host->intr_wait); 834 835 mmc->ops = &sh_mmcif_ops; 836 mmc->f_max = host->clk; 837 /* close to 400KHz */ 838 if (mmc->f_max < 51200000) 839 mmc->f_min = mmc->f_max / 128; 840 else if (mmc->f_max < 102400000) 841 mmc->f_min = mmc->f_max / 256; 842 else 843 mmc->f_min = mmc->f_max / 512; 844 if (pd->ocr) 845 mmc->ocr_avail = pd->ocr; 846 mmc->caps = MMC_CAP_MMC_HIGHSPEED; 847 if (pd->caps) 848 mmc->caps |= pd->caps; 849 mmc->max_phys_segs = 128; 850 mmc->max_hw_segs = 128; 851 mmc->max_blk_size = 512; 852 mmc->max_blk_count = 65535; 853 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 854 mmc->max_seg_size = mmc->max_req_size; 855 856 sh_mmcif_sync_reset(host); 857 platform_set_drvdata(pdev, host); 858 mmc_add_host(mmc); 859 860 ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host); 861 if (ret) { 862 pr_err(DRIVER_NAME": request_irq error (sh_mmc:error)\n"); 863 goto clean_up2; 864 } 865 ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host); 866 if (ret) { 867 free_irq(irq[0], host); 868 pr_err(DRIVER_NAME": request_irq error (sh_mmc:int)\n"); 869 goto clean_up2; 870 } 871 872 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 873 sh_mmcif_detect(host->mmc); 874 875 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION); 876 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME, 877 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 878 return ret; 879 880 clean_up2: 881 clk_disable(host->hclk); 882 clean_up1: 883 mmc_free_host(mmc); 884 clean_up: 885 if (reg) 886 iounmap(reg); 887 return ret; 888 } 889 890 static int __devexit sh_mmcif_remove(struct platform_device *pdev) 891 { 892 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 893 int irq[2]; 894 895 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 896 897 irq[0] = platform_get_irq(pdev, 0); 898 irq[1] = platform_get_irq(pdev, 1); 899 900 if (host->addr) 901 iounmap(host->addr); 902 903 platform_set_drvdata(pdev, NULL); 904 mmc_remove_host(host->mmc); 905 906 free_irq(irq[0], host); 907 free_irq(irq[1], host); 908 909 clk_disable(host->hclk); 910 mmc_free_host(host->mmc); 911 912 return 0; 913 } 914 915 static struct platform_driver sh_mmcif_driver = { 916 .probe = sh_mmcif_probe, 917 .remove = sh_mmcif_remove, 918 .driver = { 919 .name = DRIVER_NAME, 920 }, 921 }; 922 923 static int __init sh_mmcif_init(void) 924 { 925 return platform_driver_register(&sh_mmcif_driver); 926 } 927 928 static void __exit sh_mmcif_exit(void) 929 { 930 platform_driver_unregister(&sh_mmcif_driver); 931 } 932 933 module_init(sh_mmcif_init); 934 module_exit(sh_mmcif_exit); 935 936 937 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 938 MODULE_LICENSE("GPL"); 939 MODULE_ALIAS(DRIVER_NAME); 940 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 941