1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MMCIF eMMC driver. 4 * 5 * Copyright (C) 2010 Renesas Solutions Corp. 6 * Yusuke Goda <yusuke.goda.sx@renesas.com> 7 */ 8 9 /* 10 * The MMCIF driver is now processing MMC requests asynchronously, according 11 * to the Linux MMC API requirement. 12 * 13 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 14 * data, and optional stop. To achieve asynchronous processing each of these 15 * stages is split into two halves: a top and a bottom half. The top half 16 * initialises the hardware, installs a timeout handler to handle completion 17 * timeouts, and returns. In case of the command stage this immediately returns 18 * control to the caller, leaving all further processing to run asynchronously. 19 * All further request processing is performed by the bottom halves. 20 * 21 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 22 * thread, a DMA completion callback, if DMA is used, a timeout work, and 23 * request- and stage-specific handler methods. 24 * 25 * Each bottom half run begins with either a hardware interrupt, a DMA callback 26 * invocation, or a timeout work run. In case of an error or a successful 27 * processing completion, the MMC core is informed and the request processing is 28 * finished. In case processing has to continue, i.e., if data has to be read 29 * from or written to the card, or if a stop command has to be sent, the next 30 * top half is called, which performs the necessary hardware handling and 31 * reschedules the timeout work. This returns the driver state machine into the 32 * bottom half waiting state. 33 */ 34 35 #include <linux/bitops.h> 36 #include <linux/clk.h> 37 #include <linux/completion.h> 38 #include <linux/delay.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/mmc/card.h> 42 #include <linux/mmc/core.h> 43 #include <linux/mmc/host.h> 44 #include <linux/mmc/mmc.h> 45 #include <linux/mmc/sdio.h> 46 #include <linux/mmc/sh_mmcif.h> 47 #include <linux/mmc/slot-gpio.h> 48 #include <linux/mod_devicetable.h> 49 #include <linux/mutex.h> 50 #include <linux/of_device.h> 51 #include <linux/pagemap.h> 52 #include <linux/platform_device.h> 53 #include <linux/pm_qos.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/sh_dma.h> 56 #include <linux/spinlock.h> 57 #include <linux/module.h> 58 59 #define DRIVER_NAME "sh_mmcif" 60 61 /* CE_CMD_SET */ 62 #define CMD_MASK 0x3f000000 63 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 64 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 65 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 66 #define CMD_SET_RBSY (1 << 21) /* R1b */ 67 #define CMD_SET_CCSEN (1 << 20) 68 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 69 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 70 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 71 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 72 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 73 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 74 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 75 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 76 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 77 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 78 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 79 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 80 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 81 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 82 #define CMD_SET_CCSH (1 << 5) 83 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 84 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 85 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 86 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 87 88 /* CE_CMD_CTRL */ 89 #define CMD_CTRL_BREAK (1 << 0) 90 91 /* CE_BLOCK_SET */ 92 #define BLOCK_SIZE_MASK 0x0000ffff 93 94 /* CE_INT */ 95 #define INT_CCSDE (1 << 29) 96 #define INT_CMD12DRE (1 << 26) 97 #define INT_CMD12RBE (1 << 25) 98 #define INT_CMD12CRE (1 << 24) 99 #define INT_DTRANE (1 << 23) 100 #define INT_BUFRE (1 << 22) 101 #define INT_BUFWEN (1 << 21) 102 #define INT_BUFREN (1 << 20) 103 #define INT_CCSRCV (1 << 19) 104 #define INT_RBSYE (1 << 17) 105 #define INT_CRSPE (1 << 16) 106 #define INT_CMDVIO (1 << 15) 107 #define INT_BUFVIO (1 << 14) 108 #define INT_WDATERR (1 << 11) 109 #define INT_RDATERR (1 << 10) 110 #define INT_RIDXERR (1 << 9) 111 #define INT_RSPERR (1 << 8) 112 #define INT_CCSTO (1 << 5) 113 #define INT_CRCSTO (1 << 4) 114 #define INT_WDATTO (1 << 3) 115 #define INT_RDATTO (1 << 2) 116 #define INT_RBSYTO (1 << 1) 117 #define INT_RSPTO (1 << 0) 118 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 119 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 120 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 121 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 122 123 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 124 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 125 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 126 127 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 128 129 /* CE_INT_MASK */ 130 #define MASK_ALL 0x00000000 131 #define MASK_MCCSDE (1 << 29) 132 #define MASK_MCMD12DRE (1 << 26) 133 #define MASK_MCMD12RBE (1 << 25) 134 #define MASK_MCMD12CRE (1 << 24) 135 #define MASK_MDTRANE (1 << 23) 136 #define MASK_MBUFRE (1 << 22) 137 #define MASK_MBUFWEN (1 << 21) 138 #define MASK_MBUFREN (1 << 20) 139 #define MASK_MCCSRCV (1 << 19) 140 #define MASK_MRBSYE (1 << 17) 141 #define MASK_MCRSPE (1 << 16) 142 #define MASK_MCMDVIO (1 << 15) 143 #define MASK_MBUFVIO (1 << 14) 144 #define MASK_MWDATERR (1 << 11) 145 #define MASK_MRDATERR (1 << 10) 146 #define MASK_MRIDXERR (1 << 9) 147 #define MASK_MRSPERR (1 << 8) 148 #define MASK_MCCSTO (1 << 5) 149 #define MASK_MCRCSTO (1 << 4) 150 #define MASK_MWDATTO (1 << 3) 151 #define MASK_MRDATTO (1 << 2) 152 #define MASK_MRBSYTO (1 << 1) 153 #define MASK_MRSPTO (1 << 0) 154 155 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 156 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 157 MASK_MCRCSTO | MASK_MWDATTO | \ 158 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 159 160 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 161 MASK_MBUFREN | MASK_MBUFWEN | \ 162 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 163 MASK_MCMD12RBE | MASK_MCMD12CRE) 164 165 /* CE_HOST_STS1 */ 166 #define STS1_CMDSEQ (1 << 31) 167 168 /* CE_HOST_STS2 */ 169 #define STS2_CRCSTE (1 << 31) 170 #define STS2_CRC16E (1 << 30) 171 #define STS2_AC12CRCE (1 << 29) 172 #define STS2_RSPCRC7E (1 << 28) 173 #define STS2_CRCSTEBE (1 << 27) 174 #define STS2_RDATEBE (1 << 26) 175 #define STS2_AC12REBE (1 << 25) 176 #define STS2_RSPEBE (1 << 24) 177 #define STS2_AC12IDXE (1 << 23) 178 #define STS2_RSPIDXE (1 << 22) 179 #define STS2_CCSTO (1 << 15) 180 #define STS2_RDATTO (1 << 14) 181 #define STS2_DATBSYTO (1 << 13) 182 #define STS2_CRCSTTO (1 << 12) 183 #define STS2_AC12BSYTO (1 << 11) 184 #define STS2_RSPBSYTO (1 << 10) 185 #define STS2_AC12RSPTO (1 << 9) 186 #define STS2_RSPTO (1 << 8) 187 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 188 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 189 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 190 STS2_DATBSYTO | STS2_CRCSTTO | \ 191 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 192 STS2_AC12RSPTO | STS2_RSPTO) 193 194 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 195 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 196 #define CLKDEV_INIT 400000 /* 400 KHz */ 197 198 enum sh_mmcif_state { 199 STATE_IDLE, 200 STATE_REQUEST, 201 STATE_IOS, 202 STATE_TIMEOUT, 203 }; 204 205 enum sh_mmcif_wait_for { 206 MMCIF_WAIT_FOR_REQUEST, 207 MMCIF_WAIT_FOR_CMD, 208 MMCIF_WAIT_FOR_MREAD, 209 MMCIF_WAIT_FOR_MWRITE, 210 MMCIF_WAIT_FOR_READ, 211 MMCIF_WAIT_FOR_WRITE, 212 MMCIF_WAIT_FOR_READ_END, 213 MMCIF_WAIT_FOR_WRITE_END, 214 MMCIF_WAIT_FOR_STOP, 215 }; 216 217 /* 218 * difference for each SoC 219 */ 220 struct sh_mmcif_host { 221 struct mmc_host *mmc; 222 struct mmc_request *mrq; 223 struct platform_device *pd; 224 struct clk *clk; 225 int bus_width; 226 unsigned char timing; 227 bool sd_error; 228 bool dying; 229 long timeout; 230 void __iomem *addr; 231 u32 *pio_ptr; 232 spinlock_t lock; /* protect sh_mmcif_host::state */ 233 enum sh_mmcif_state state; 234 enum sh_mmcif_wait_for wait_for; 235 struct delayed_work timeout_work; 236 size_t blocksize; 237 int sg_idx; 238 int sg_blkidx; 239 bool power; 240 bool ccs_enable; /* Command Completion Signal support */ 241 bool clk_ctrl2_enable; 242 struct mutex thread_lock; 243 u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ 244 245 /* DMA support */ 246 struct dma_chan *chan_rx; 247 struct dma_chan *chan_tx; 248 struct completion dma_complete; 249 bool dma_active; 250 }; 251 252 static const struct of_device_id sh_mmcif_of_match[] = { 253 { .compatible = "renesas,sh-mmcif" }, 254 { } 255 }; 256 MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); 257 258 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 259 260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261 unsigned int reg, u32 val) 262 { 263 writel(val | readl(host->addr + reg), host->addr + reg); 264 } 265 266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267 unsigned int reg, u32 val) 268 { 269 writel(~val & readl(host->addr + reg), host->addr + reg); 270 } 271 272 static void sh_mmcif_dma_complete(void *arg) 273 { 274 struct sh_mmcif_host *host = arg; 275 struct mmc_request *mrq = host->mrq; 276 struct device *dev = sh_mmcif_host_to_dev(host); 277 278 dev_dbg(dev, "Command completed\n"); 279 280 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 281 dev_name(dev))) 282 return; 283 284 complete(&host->dma_complete); 285 } 286 287 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 288 { 289 struct mmc_data *data = host->mrq->data; 290 struct scatterlist *sg = data->sg; 291 struct dma_async_tx_descriptor *desc = NULL; 292 struct dma_chan *chan = host->chan_rx; 293 struct device *dev = sh_mmcif_host_to_dev(host); 294 dma_cookie_t cookie = -EINVAL; 295 int ret; 296 297 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 298 DMA_FROM_DEVICE); 299 if (ret > 0) { 300 host->dma_active = true; 301 desc = dmaengine_prep_slave_sg(chan, sg, ret, 302 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 303 } 304 305 if (desc) { 306 desc->callback = sh_mmcif_dma_complete; 307 desc->callback_param = host; 308 cookie = dmaengine_submit(desc); 309 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 310 dma_async_issue_pending(chan); 311 } 312 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 313 __func__, data->sg_len, ret, cookie); 314 315 if (!desc) { 316 /* DMA failed, fall back to PIO */ 317 if (ret >= 0) 318 ret = -EIO; 319 host->chan_rx = NULL; 320 host->dma_active = false; 321 dma_release_channel(chan); 322 /* Free the Tx channel too */ 323 chan = host->chan_tx; 324 if (chan) { 325 host->chan_tx = NULL; 326 dma_release_channel(chan); 327 } 328 dev_warn(dev, 329 "DMA failed: %d, falling back to PIO\n", ret); 330 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 331 } 332 333 dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 334 desc, cookie, data->sg_len); 335 } 336 337 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 338 { 339 struct mmc_data *data = host->mrq->data; 340 struct scatterlist *sg = data->sg; 341 struct dma_async_tx_descriptor *desc = NULL; 342 struct dma_chan *chan = host->chan_tx; 343 struct device *dev = sh_mmcif_host_to_dev(host); 344 dma_cookie_t cookie = -EINVAL; 345 int ret; 346 347 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 348 DMA_TO_DEVICE); 349 if (ret > 0) { 350 host->dma_active = true; 351 desc = dmaengine_prep_slave_sg(chan, sg, ret, 352 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 353 } 354 355 if (desc) { 356 desc->callback = sh_mmcif_dma_complete; 357 desc->callback_param = host; 358 cookie = dmaengine_submit(desc); 359 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 360 dma_async_issue_pending(chan); 361 } 362 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 363 __func__, data->sg_len, ret, cookie); 364 365 if (!desc) { 366 /* DMA failed, fall back to PIO */ 367 if (ret >= 0) 368 ret = -EIO; 369 host->chan_tx = NULL; 370 host->dma_active = false; 371 dma_release_channel(chan); 372 /* Free the Rx channel too */ 373 chan = host->chan_rx; 374 if (chan) { 375 host->chan_rx = NULL; 376 dma_release_channel(chan); 377 } 378 dev_warn(dev, 379 "DMA failed: %d, falling back to PIO\n", ret); 380 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 381 } 382 383 dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 384 desc, cookie); 385 } 386 387 static struct dma_chan * 388 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) 389 { 390 dma_cap_mask_t mask; 391 392 dma_cap_zero(mask); 393 dma_cap_set(DMA_SLAVE, mask); 394 if (slave_id <= 0) 395 return NULL; 396 397 return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); 398 } 399 400 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, 401 struct dma_chan *chan, 402 enum dma_transfer_direction direction) 403 { 404 struct resource *res; 405 struct dma_slave_config cfg = { 0, }; 406 407 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 408 cfg.direction = direction; 409 410 if (direction == DMA_DEV_TO_MEM) { 411 cfg.src_addr = res->start + MMCIF_CE_DATA; 412 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 413 } else { 414 cfg.dst_addr = res->start + MMCIF_CE_DATA; 415 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 416 } 417 418 return dmaengine_slave_config(chan, &cfg); 419 } 420 421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) 422 { 423 struct device *dev = sh_mmcif_host_to_dev(host); 424 host->dma_active = false; 425 426 /* We can only either use DMA for both Tx and Rx or not use it at all */ 427 if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { 428 struct sh_mmcif_plat_data *pdata = dev->platform_data; 429 430 host->chan_tx = sh_mmcif_request_dma_pdata(host, 431 pdata->slave_id_tx); 432 host->chan_rx = sh_mmcif_request_dma_pdata(host, 433 pdata->slave_id_rx); 434 } else { 435 host->chan_tx = dma_request_chan(dev, "tx"); 436 if (IS_ERR(host->chan_tx)) 437 host->chan_tx = NULL; 438 host->chan_rx = dma_request_chan(dev, "rx"); 439 if (IS_ERR(host->chan_rx)) 440 host->chan_rx = NULL; 441 } 442 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, 443 host->chan_rx); 444 445 if (!host->chan_tx || !host->chan_rx || 446 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || 447 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) 448 goto error; 449 450 return; 451 452 error: 453 if (host->chan_tx) 454 dma_release_channel(host->chan_tx); 455 if (host->chan_rx) 456 dma_release_channel(host->chan_rx); 457 host->chan_tx = host->chan_rx = NULL; 458 } 459 460 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 461 { 462 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 463 /* Descriptors are freed automatically */ 464 if (host->chan_tx) { 465 struct dma_chan *chan = host->chan_tx; 466 host->chan_tx = NULL; 467 dma_release_channel(chan); 468 } 469 if (host->chan_rx) { 470 struct dma_chan *chan = host->chan_rx; 471 host->chan_rx = NULL; 472 dma_release_channel(chan); 473 } 474 475 host->dma_active = false; 476 } 477 478 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 479 { 480 struct device *dev = sh_mmcif_host_to_dev(host); 481 struct sh_mmcif_plat_data *p = dev->platform_data; 482 bool sup_pclk = p ? p->sup_pclk : false; 483 unsigned int current_clk = clk_get_rate(host->clk); 484 unsigned int clkdiv; 485 486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 488 489 if (!clk) 490 return; 491 492 if (host->clkdiv_map) { 493 unsigned int freq, best_freq, myclk, div, diff_min, diff; 494 int i; 495 496 clkdiv = 0; 497 diff_min = ~0; 498 best_freq = 0; 499 for (i = 31; i >= 0; i--) { 500 if (!((1 << i) & host->clkdiv_map)) 501 continue; 502 503 /* 504 * clk = parent_freq / div 505 * -> parent_freq = clk x div 506 */ 507 508 div = 1 << (i + 1); 509 freq = clk_round_rate(host->clk, clk * div); 510 myclk = freq / div; 511 diff = (myclk > clk) ? myclk - clk : clk - myclk; 512 513 if (diff <= diff_min) { 514 best_freq = freq; 515 clkdiv = i; 516 diff_min = diff; 517 } 518 } 519 520 dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", 521 (best_freq / (1 << (clkdiv + 1))), clk, 522 best_freq, clkdiv); 523 524 clk_set_rate(host->clk, best_freq); 525 clkdiv = clkdiv << 16; 526 } else if (sup_pclk && clk == current_clk) { 527 clkdiv = CLK_SUP_PCLK; 528 } else { 529 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; 530 } 531 532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); 533 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 534 } 535 536 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 537 { 538 u32 tmp; 539 540 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 541 542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 543 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 544 if (host->ccs_enable) 545 tmp |= SCCSTO_29; 546 if (host->clk_ctrl2_enable) 547 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 548 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 549 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 550 /* byte swap on */ 551 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 552 } 553 554 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 555 { 556 struct device *dev = sh_mmcif_host_to_dev(host); 557 u32 state1, state2; 558 int ret, timeout; 559 560 host->sd_error = false; 561 562 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 563 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 564 dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 565 dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 566 567 if (state1 & STS1_CMDSEQ) { 568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 569 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 570 for (timeout = 10000; timeout; timeout--) { 571 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 572 & STS1_CMDSEQ)) 573 break; 574 mdelay(1); 575 } 576 if (!timeout) { 577 dev_err(dev, 578 "Forced end of command sequence timeout err\n"); 579 return -EIO; 580 } 581 sh_mmcif_sync_reset(host); 582 dev_dbg(dev, "Forced end of command sequence\n"); 583 return -EIO; 584 } 585 586 if (state2 & STS2_CRC_ERR) { 587 dev_err(dev, " CRC error: state %u, wait %u\n", 588 host->state, host->wait_for); 589 ret = -EIO; 590 } else if (state2 & STS2_TIMEOUT_ERR) { 591 dev_err(dev, " Timeout: state %u, wait %u\n", 592 host->state, host->wait_for); 593 ret = -ETIMEDOUT; 594 } else { 595 dev_dbg(dev, " End/Index error: state %u, wait %u\n", 596 host->state, host->wait_for); 597 ret = -EIO; 598 } 599 return ret; 600 } 601 602 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 603 { 604 struct mmc_data *data = host->mrq->data; 605 606 host->sg_blkidx += host->blocksize; 607 608 /* data->sg->length must be a multiple of host->blocksize? */ 609 BUG_ON(host->sg_blkidx > data->sg->length); 610 611 if (host->sg_blkidx == data->sg->length) { 612 host->sg_blkidx = 0; 613 if (++host->sg_idx < data->sg_len) 614 host->pio_ptr = sg_virt(++data->sg); 615 } else { 616 host->pio_ptr = p; 617 } 618 619 return host->sg_idx != data->sg_len; 620 } 621 622 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 623 struct mmc_request *mrq) 624 { 625 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 626 BLOCK_SIZE_MASK) + 3; 627 628 host->wait_for = MMCIF_WAIT_FOR_READ; 629 630 /* buf read enable */ 631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 632 } 633 634 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 635 { 636 struct device *dev = sh_mmcif_host_to_dev(host); 637 struct mmc_data *data = host->mrq->data; 638 u32 *p = sg_virt(data->sg); 639 int i; 640 641 if (host->sd_error) { 642 data->error = sh_mmcif_error_manage(host); 643 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 644 return false; 645 } 646 647 for (i = 0; i < host->blocksize / 4; i++) 648 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 649 650 /* buffer read end */ 651 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 652 host->wait_for = MMCIF_WAIT_FOR_READ_END; 653 654 return true; 655 } 656 657 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 658 struct mmc_request *mrq) 659 { 660 struct mmc_data *data = mrq->data; 661 662 if (!data->sg_len || !data->sg->length) 663 return; 664 665 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 666 BLOCK_SIZE_MASK; 667 668 host->wait_for = MMCIF_WAIT_FOR_MREAD; 669 host->sg_idx = 0; 670 host->sg_blkidx = 0; 671 host->pio_ptr = sg_virt(data->sg); 672 673 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 674 } 675 676 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 677 { 678 struct device *dev = sh_mmcif_host_to_dev(host); 679 struct mmc_data *data = host->mrq->data; 680 u32 *p = host->pio_ptr; 681 int i; 682 683 if (host->sd_error) { 684 data->error = sh_mmcif_error_manage(host); 685 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 686 return false; 687 } 688 689 BUG_ON(!data->sg->length); 690 691 for (i = 0; i < host->blocksize / 4; i++) 692 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 693 694 if (!sh_mmcif_next_block(host, p)) 695 return false; 696 697 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 698 699 return true; 700 } 701 702 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 703 struct mmc_request *mrq) 704 { 705 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 706 BLOCK_SIZE_MASK) + 3; 707 708 host->wait_for = MMCIF_WAIT_FOR_WRITE; 709 710 /* buf write enable */ 711 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 712 } 713 714 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 715 { 716 struct device *dev = sh_mmcif_host_to_dev(host); 717 struct mmc_data *data = host->mrq->data; 718 u32 *p = sg_virt(data->sg); 719 int i; 720 721 if (host->sd_error) { 722 data->error = sh_mmcif_error_manage(host); 723 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 724 return false; 725 } 726 727 for (i = 0; i < host->blocksize / 4; i++) 728 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 729 730 /* buffer write end */ 731 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 732 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 733 734 return true; 735 } 736 737 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 738 struct mmc_request *mrq) 739 { 740 struct mmc_data *data = mrq->data; 741 742 if (!data->sg_len || !data->sg->length) 743 return; 744 745 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 746 BLOCK_SIZE_MASK; 747 748 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 749 host->sg_idx = 0; 750 host->sg_blkidx = 0; 751 host->pio_ptr = sg_virt(data->sg); 752 753 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 754 } 755 756 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 757 { 758 struct device *dev = sh_mmcif_host_to_dev(host); 759 struct mmc_data *data = host->mrq->data; 760 u32 *p = host->pio_ptr; 761 int i; 762 763 if (host->sd_error) { 764 data->error = sh_mmcif_error_manage(host); 765 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 766 return false; 767 } 768 769 BUG_ON(!data->sg->length); 770 771 for (i = 0; i < host->blocksize / 4; i++) 772 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 773 774 if (!sh_mmcif_next_block(host, p)) 775 return false; 776 777 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 778 779 return true; 780 } 781 782 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 783 struct mmc_command *cmd) 784 { 785 if (cmd->flags & MMC_RSP_136) { 786 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 787 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 788 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 789 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 790 } else 791 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 792 } 793 794 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 795 struct mmc_command *cmd) 796 { 797 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 798 } 799 800 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 801 struct mmc_request *mrq) 802 { 803 struct device *dev = sh_mmcif_host_to_dev(host); 804 struct mmc_data *data = mrq->data; 805 struct mmc_command *cmd = mrq->cmd; 806 u32 opc = cmd->opcode; 807 u32 tmp = 0; 808 809 /* Response Type check */ 810 switch (mmc_resp_type(cmd)) { 811 case MMC_RSP_NONE: 812 tmp |= CMD_SET_RTYP_NO; 813 break; 814 case MMC_RSP_R1: 815 case MMC_RSP_R3: 816 tmp |= CMD_SET_RTYP_6B; 817 break; 818 case MMC_RSP_R1B: 819 tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B; 820 break; 821 case MMC_RSP_R2: 822 tmp |= CMD_SET_RTYP_17B; 823 break; 824 default: 825 dev_err(dev, "Unsupported response type.\n"); 826 break; 827 } 828 829 /* WDAT / DATW */ 830 if (data) { 831 tmp |= CMD_SET_WDAT; 832 switch (host->bus_width) { 833 case MMC_BUS_WIDTH_1: 834 tmp |= CMD_SET_DATW_1; 835 break; 836 case MMC_BUS_WIDTH_4: 837 tmp |= CMD_SET_DATW_4; 838 break; 839 case MMC_BUS_WIDTH_8: 840 tmp |= CMD_SET_DATW_8; 841 break; 842 default: 843 dev_err(dev, "Unsupported bus width.\n"); 844 break; 845 } 846 switch (host->timing) { 847 case MMC_TIMING_MMC_DDR52: 848 /* 849 * MMC core will only set this timing, if the host 850 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 851 * capability. MMCIF implementations with this 852 * capability, e.g. sh73a0, will have to set it 853 * in their platform data. 854 */ 855 tmp |= CMD_SET_DARS; 856 break; 857 } 858 } 859 /* DWEN */ 860 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 861 tmp |= CMD_SET_DWEN; 862 /* CMLTE/CMD12EN */ 863 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 864 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 865 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 866 data->blocks << 16); 867 } 868 /* RIDXC[1:0] check bits */ 869 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 870 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 871 tmp |= CMD_SET_RIDXC_BITS; 872 /* RCRC7C[1:0] check bits */ 873 if (opc == MMC_SEND_OP_COND) 874 tmp |= CMD_SET_CRC7C_BITS; 875 /* RCRC7C[1:0] internal CRC7 */ 876 if (opc == MMC_ALL_SEND_CID || 877 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 878 tmp |= CMD_SET_CRC7C_INTERNAL; 879 880 return (opc << 24) | tmp; 881 } 882 883 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 884 struct mmc_request *mrq, u32 opc) 885 { 886 struct device *dev = sh_mmcif_host_to_dev(host); 887 888 switch (opc) { 889 case MMC_READ_MULTIPLE_BLOCK: 890 sh_mmcif_multi_read(host, mrq); 891 return 0; 892 case MMC_WRITE_MULTIPLE_BLOCK: 893 sh_mmcif_multi_write(host, mrq); 894 return 0; 895 case MMC_WRITE_BLOCK: 896 sh_mmcif_single_write(host, mrq); 897 return 0; 898 case MMC_READ_SINGLE_BLOCK: 899 case MMC_SEND_EXT_CSD: 900 sh_mmcif_single_read(host, mrq); 901 return 0; 902 default: 903 dev_err(dev, "Unsupported CMD%d\n", opc); 904 return -EINVAL; 905 } 906 } 907 908 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 909 struct mmc_request *mrq) 910 { 911 struct mmc_command *cmd = mrq->cmd; 912 u32 opc; 913 u32 mask = 0; 914 unsigned long flags; 915 916 if (cmd->flags & MMC_RSP_BUSY) 917 mask = MASK_START_CMD | MASK_MRBSYE; 918 else 919 mask = MASK_START_CMD | MASK_MCRSPE; 920 921 if (host->ccs_enable) 922 mask |= MASK_MCCSTO; 923 924 if (mrq->data) { 925 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 926 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 927 mrq->data->blksz); 928 } 929 opc = sh_mmcif_set_cmd(host, mrq); 930 931 if (host->ccs_enable) 932 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 933 else 934 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 935 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 936 /* set arg */ 937 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 938 /* set cmd */ 939 spin_lock_irqsave(&host->lock, flags); 940 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 941 942 host->wait_for = MMCIF_WAIT_FOR_CMD; 943 schedule_delayed_work(&host->timeout_work, host->timeout); 944 spin_unlock_irqrestore(&host->lock, flags); 945 } 946 947 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 948 struct mmc_request *mrq) 949 { 950 struct device *dev = sh_mmcif_host_to_dev(host); 951 952 switch (mrq->cmd->opcode) { 953 case MMC_READ_MULTIPLE_BLOCK: 954 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 955 break; 956 case MMC_WRITE_MULTIPLE_BLOCK: 957 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 958 break; 959 default: 960 dev_err(dev, "unsupported stop cmd\n"); 961 mrq->stop->error = sh_mmcif_error_manage(host); 962 return; 963 } 964 965 host->wait_for = MMCIF_WAIT_FOR_STOP; 966 } 967 968 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 969 { 970 struct sh_mmcif_host *host = mmc_priv(mmc); 971 struct device *dev = sh_mmcif_host_to_dev(host); 972 unsigned long flags; 973 974 spin_lock_irqsave(&host->lock, flags); 975 if (host->state != STATE_IDLE) { 976 dev_dbg(dev, "%s() rejected, state %u\n", 977 __func__, host->state); 978 spin_unlock_irqrestore(&host->lock, flags); 979 mrq->cmd->error = -EAGAIN; 980 mmc_request_done(mmc, mrq); 981 return; 982 } 983 984 host->state = STATE_REQUEST; 985 spin_unlock_irqrestore(&host->lock, flags); 986 987 host->mrq = mrq; 988 989 sh_mmcif_start_cmd(host, mrq); 990 } 991 992 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 993 { 994 struct device *dev = sh_mmcif_host_to_dev(host); 995 996 if (host->mmc->f_max) { 997 unsigned int f_max, f_min = 0, f_min_old; 998 999 f_max = host->mmc->f_max; 1000 for (f_min_old = f_max; f_min_old > 2;) { 1001 f_min = clk_round_rate(host->clk, f_min_old / 2); 1002 if (f_min == f_min_old) 1003 break; 1004 f_min_old = f_min; 1005 } 1006 1007 /* 1008 * This driver assumes this SoC is R-Car Gen2 or later 1009 */ 1010 host->clkdiv_map = 0x3ff; 1011 1012 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); 1013 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); 1014 } else { 1015 unsigned int clk = clk_get_rate(host->clk); 1016 1017 host->mmc->f_max = clk / 2; 1018 host->mmc->f_min = clk / 512; 1019 } 1020 1021 dev_dbg(dev, "clk max/min = %d/%d\n", 1022 host->mmc->f_max, host->mmc->f_min); 1023 } 1024 1025 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1026 { 1027 struct sh_mmcif_host *host = mmc_priv(mmc); 1028 struct device *dev = sh_mmcif_host_to_dev(host); 1029 unsigned long flags; 1030 1031 spin_lock_irqsave(&host->lock, flags); 1032 if (host->state != STATE_IDLE) { 1033 dev_dbg(dev, "%s() rejected, state %u\n", 1034 __func__, host->state); 1035 spin_unlock_irqrestore(&host->lock, flags); 1036 return; 1037 } 1038 1039 host->state = STATE_IOS; 1040 spin_unlock_irqrestore(&host->lock, flags); 1041 1042 switch (ios->power_mode) { 1043 case MMC_POWER_UP: 1044 if (!IS_ERR(mmc->supply.vmmc)) 1045 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1046 if (!host->power) { 1047 clk_prepare_enable(host->clk); 1048 pm_runtime_get_sync(dev); 1049 sh_mmcif_sync_reset(host); 1050 sh_mmcif_request_dma(host); 1051 host->power = true; 1052 } 1053 break; 1054 case MMC_POWER_OFF: 1055 if (!IS_ERR(mmc->supply.vmmc)) 1056 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1057 if (host->power) { 1058 sh_mmcif_clock_control(host, 0); 1059 sh_mmcif_release_dma(host); 1060 pm_runtime_put(dev); 1061 clk_disable_unprepare(host->clk); 1062 host->power = false; 1063 } 1064 break; 1065 case MMC_POWER_ON: 1066 sh_mmcif_clock_control(host, ios->clock); 1067 break; 1068 } 1069 1070 host->timing = ios->timing; 1071 host->bus_width = ios->bus_width; 1072 host->state = STATE_IDLE; 1073 } 1074 1075 static const struct mmc_host_ops sh_mmcif_ops = { 1076 .request = sh_mmcif_request, 1077 .set_ios = sh_mmcif_set_ios, 1078 .get_cd = mmc_gpio_get_cd, 1079 }; 1080 1081 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1082 { 1083 struct mmc_command *cmd = host->mrq->cmd; 1084 struct mmc_data *data = host->mrq->data; 1085 struct device *dev = sh_mmcif_host_to_dev(host); 1086 long time; 1087 1088 if (host->sd_error) { 1089 switch (cmd->opcode) { 1090 case MMC_ALL_SEND_CID: 1091 case MMC_SELECT_CARD: 1092 case MMC_APP_CMD: 1093 cmd->error = -ETIMEDOUT; 1094 break; 1095 default: 1096 cmd->error = sh_mmcif_error_manage(host); 1097 break; 1098 } 1099 dev_dbg(dev, "CMD%d error %d\n", 1100 cmd->opcode, cmd->error); 1101 host->sd_error = false; 1102 return false; 1103 } 1104 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1105 cmd->error = 0; 1106 return false; 1107 } 1108 1109 sh_mmcif_get_response(host, cmd); 1110 1111 if (!data) 1112 return false; 1113 1114 /* 1115 * Completion can be signalled from DMA callback and error, so, have to 1116 * reset here, before setting .dma_active 1117 */ 1118 init_completion(&host->dma_complete); 1119 1120 if (data->flags & MMC_DATA_READ) { 1121 if (host->chan_rx) 1122 sh_mmcif_start_dma_rx(host); 1123 } else { 1124 if (host->chan_tx) 1125 sh_mmcif_start_dma_tx(host); 1126 } 1127 1128 if (!host->dma_active) { 1129 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1130 return !data->error; 1131 } 1132 1133 /* Running in the IRQ thread, can sleep */ 1134 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1135 host->timeout); 1136 1137 if (data->flags & MMC_DATA_READ) 1138 dma_unmap_sg(host->chan_rx->device->dev, 1139 data->sg, data->sg_len, 1140 DMA_FROM_DEVICE); 1141 else 1142 dma_unmap_sg(host->chan_tx->device->dev, 1143 data->sg, data->sg_len, 1144 DMA_TO_DEVICE); 1145 1146 if (host->sd_error) { 1147 dev_err(host->mmc->parent, 1148 "Error IRQ while waiting for DMA completion!\n"); 1149 /* Woken up by an error IRQ: abort DMA */ 1150 data->error = sh_mmcif_error_manage(host); 1151 } else if (!time) { 1152 dev_err(host->mmc->parent, "DMA timeout!\n"); 1153 data->error = -ETIMEDOUT; 1154 } else if (time < 0) { 1155 dev_err(host->mmc->parent, 1156 "wait_for_completion_...() error %ld!\n", time); 1157 data->error = time; 1158 } 1159 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1160 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1161 host->dma_active = false; 1162 1163 if (data->error) { 1164 data->bytes_xfered = 0; 1165 /* Abort DMA */ 1166 if (data->flags & MMC_DATA_READ) 1167 dmaengine_terminate_all(host->chan_rx); 1168 else 1169 dmaengine_terminate_all(host->chan_tx); 1170 } 1171 1172 return false; 1173 } 1174 1175 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1176 { 1177 struct sh_mmcif_host *host = dev_id; 1178 struct mmc_request *mrq; 1179 struct device *dev = sh_mmcif_host_to_dev(host); 1180 bool wait = false; 1181 unsigned long flags; 1182 int wait_work; 1183 1184 spin_lock_irqsave(&host->lock, flags); 1185 wait_work = host->wait_for; 1186 spin_unlock_irqrestore(&host->lock, flags); 1187 1188 cancel_delayed_work_sync(&host->timeout_work); 1189 1190 mutex_lock(&host->thread_lock); 1191 1192 mrq = host->mrq; 1193 if (!mrq) { 1194 dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 1195 host->state, host->wait_for); 1196 mutex_unlock(&host->thread_lock); 1197 return IRQ_HANDLED; 1198 } 1199 1200 /* 1201 * All handlers return true, if processing continues, and false, if the 1202 * request has to be completed - successfully or not 1203 */ 1204 switch (wait_work) { 1205 case MMCIF_WAIT_FOR_REQUEST: 1206 /* We're too late, the timeout has already kicked in */ 1207 mutex_unlock(&host->thread_lock); 1208 return IRQ_HANDLED; 1209 case MMCIF_WAIT_FOR_CMD: 1210 /* Wait for data? */ 1211 wait = sh_mmcif_end_cmd(host); 1212 break; 1213 case MMCIF_WAIT_FOR_MREAD: 1214 /* Wait for more data? */ 1215 wait = sh_mmcif_mread_block(host); 1216 break; 1217 case MMCIF_WAIT_FOR_READ: 1218 /* Wait for data end? */ 1219 wait = sh_mmcif_read_block(host); 1220 break; 1221 case MMCIF_WAIT_FOR_MWRITE: 1222 /* Wait data to write? */ 1223 wait = sh_mmcif_mwrite_block(host); 1224 break; 1225 case MMCIF_WAIT_FOR_WRITE: 1226 /* Wait for data end? */ 1227 wait = sh_mmcif_write_block(host); 1228 break; 1229 case MMCIF_WAIT_FOR_STOP: 1230 if (host->sd_error) { 1231 mrq->stop->error = sh_mmcif_error_manage(host); 1232 dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1233 break; 1234 } 1235 sh_mmcif_get_cmd12response(host, mrq->stop); 1236 mrq->stop->error = 0; 1237 break; 1238 case MMCIF_WAIT_FOR_READ_END: 1239 case MMCIF_WAIT_FOR_WRITE_END: 1240 if (host->sd_error) { 1241 mrq->data->error = sh_mmcif_error_manage(host); 1242 dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1243 } 1244 break; 1245 default: 1246 BUG(); 1247 } 1248 1249 if (wait) { 1250 schedule_delayed_work(&host->timeout_work, host->timeout); 1251 /* Wait for more data */ 1252 mutex_unlock(&host->thread_lock); 1253 return IRQ_HANDLED; 1254 } 1255 1256 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1257 struct mmc_data *data = mrq->data; 1258 if (!mrq->cmd->error && data && !data->error) 1259 data->bytes_xfered = 1260 data->blocks * data->blksz; 1261 1262 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1263 sh_mmcif_stop_cmd(host, mrq); 1264 if (!mrq->stop->error) { 1265 schedule_delayed_work(&host->timeout_work, host->timeout); 1266 mutex_unlock(&host->thread_lock); 1267 return IRQ_HANDLED; 1268 } 1269 } 1270 } 1271 1272 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1273 host->state = STATE_IDLE; 1274 host->mrq = NULL; 1275 mmc_request_done(host->mmc, mrq); 1276 1277 mutex_unlock(&host->thread_lock); 1278 1279 return IRQ_HANDLED; 1280 } 1281 1282 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1283 { 1284 struct sh_mmcif_host *host = dev_id; 1285 struct device *dev = sh_mmcif_host_to_dev(host); 1286 u32 state, mask; 1287 1288 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1289 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1290 if (host->ccs_enable) 1291 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1292 else 1293 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 1294 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1295 1296 if (state & ~MASK_CLEAN) 1297 dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 1298 state); 1299 1300 if (state & INT_ERR_STS || state & ~INT_ALL) { 1301 host->sd_error = true; 1302 dev_dbg(dev, "int err state = 0x%08x\n", state); 1303 } 1304 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1305 if (!host->mrq) 1306 dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1307 if (!host->dma_active) 1308 return IRQ_WAKE_THREAD; 1309 else if (host->sd_error) 1310 sh_mmcif_dma_complete(host); 1311 } else { 1312 dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1313 } 1314 1315 return IRQ_HANDLED; 1316 } 1317 1318 static void sh_mmcif_timeout_work(struct work_struct *work) 1319 { 1320 struct delayed_work *d = to_delayed_work(work); 1321 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1322 struct mmc_request *mrq = host->mrq; 1323 struct device *dev = sh_mmcif_host_to_dev(host); 1324 unsigned long flags; 1325 1326 if (host->dying) 1327 /* Don't run after mmc_remove_host() */ 1328 return; 1329 1330 spin_lock_irqsave(&host->lock, flags); 1331 if (host->state == STATE_IDLE) { 1332 spin_unlock_irqrestore(&host->lock, flags); 1333 return; 1334 } 1335 1336 dev_err(dev, "Timeout waiting for %u on CMD%u\n", 1337 host->wait_for, mrq->cmd->opcode); 1338 1339 host->state = STATE_TIMEOUT; 1340 spin_unlock_irqrestore(&host->lock, flags); 1341 1342 /* 1343 * Handle races with cancel_delayed_work(), unless 1344 * cancel_delayed_work_sync() is used 1345 */ 1346 switch (host->wait_for) { 1347 case MMCIF_WAIT_FOR_CMD: 1348 mrq->cmd->error = sh_mmcif_error_manage(host); 1349 break; 1350 case MMCIF_WAIT_FOR_STOP: 1351 mrq->stop->error = sh_mmcif_error_manage(host); 1352 break; 1353 case MMCIF_WAIT_FOR_MREAD: 1354 case MMCIF_WAIT_FOR_MWRITE: 1355 case MMCIF_WAIT_FOR_READ: 1356 case MMCIF_WAIT_FOR_WRITE: 1357 case MMCIF_WAIT_FOR_READ_END: 1358 case MMCIF_WAIT_FOR_WRITE_END: 1359 mrq->data->error = sh_mmcif_error_manage(host); 1360 break; 1361 default: 1362 BUG(); 1363 } 1364 1365 host->state = STATE_IDLE; 1366 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1367 host->mrq = NULL; 1368 mmc_request_done(host->mmc, mrq); 1369 } 1370 1371 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 1372 { 1373 struct device *dev = sh_mmcif_host_to_dev(host); 1374 struct sh_mmcif_plat_data *pd = dev->platform_data; 1375 struct mmc_host *mmc = host->mmc; 1376 1377 mmc_regulator_get_supply(mmc); 1378 1379 if (!pd) 1380 return; 1381 1382 if (!mmc->ocr_avail) 1383 mmc->ocr_avail = pd->ocr; 1384 else if (pd->ocr) 1385 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1386 } 1387 1388 static int sh_mmcif_probe(struct platform_device *pdev) 1389 { 1390 int ret = 0, irq[2]; 1391 struct mmc_host *mmc; 1392 struct sh_mmcif_host *host; 1393 struct device *dev = &pdev->dev; 1394 struct sh_mmcif_plat_data *pd = dev->platform_data; 1395 void __iomem *reg; 1396 const char *name; 1397 1398 irq[0] = platform_get_irq(pdev, 0); 1399 irq[1] = platform_get_irq_optional(pdev, 1); 1400 if (irq[0] < 0) 1401 return -ENXIO; 1402 1403 reg = devm_platform_ioremap_resource(pdev, 0); 1404 if (IS_ERR(reg)) 1405 return PTR_ERR(reg); 1406 1407 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 1408 if (!mmc) 1409 return -ENOMEM; 1410 1411 ret = mmc_of_parse(mmc); 1412 if (ret < 0) 1413 goto err_host; 1414 1415 host = mmc_priv(mmc); 1416 host->mmc = mmc; 1417 host->addr = reg; 1418 host->timeout = msecs_to_jiffies(10000); 1419 host->ccs_enable = true; 1420 host->clk_ctrl2_enable = false; 1421 1422 host->pd = pdev; 1423 1424 spin_lock_init(&host->lock); 1425 1426 mmc->ops = &sh_mmcif_ops; 1427 sh_mmcif_init_ocr(host); 1428 1429 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1430 mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1431 mmc->max_busy_timeout = 10000; 1432 1433 if (pd && pd->caps) 1434 mmc->caps |= pd->caps; 1435 mmc->max_segs = 32; 1436 mmc->max_blk_size = 512; 1437 mmc->max_req_size = PAGE_SIZE * mmc->max_segs; 1438 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1439 mmc->max_seg_size = mmc->max_req_size; 1440 1441 platform_set_drvdata(pdev, host); 1442 1443 host->clk = devm_clk_get(dev, NULL); 1444 if (IS_ERR(host->clk)) { 1445 ret = PTR_ERR(host->clk); 1446 dev_err(dev, "cannot get clock: %d\n", ret); 1447 goto err_host; 1448 } 1449 1450 ret = clk_prepare_enable(host->clk); 1451 if (ret < 0) 1452 goto err_host; 1453 1454 sh_mmcif_clk_setup(host); 1455 1456 pm_runtime_enable(dev); 1457 host->power = false; 1458 1459 ret = pm_runtime_get_sync(dev); 1460 if (ret < 0) 1461 goto err_clk; 1462 1463 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); 1464 1465 sh_mmcif_sync_reset(host); 1466 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1467 1468 name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 1469 ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 1470 sh_mmcif_irqt, 0, name, host); 1471 if (ret) { 1472 dev_err(dev, "request_irq error (%s)\n", name); 1473 goto err_clk; 1474 } 1475 if (irq[1] >= 0) { 1476 ret = devm_request_threaded_irq(dev, irq[1], 1477 sh_mmcif_intr, sh_mmcif_irqt, 1478 0, "sh_mmc:int", host); 1479 if (ret) { 1480 dev_err(dev, "request_irq error (sh_mmc:int)\n"); 1481 goto err_clk; 1482 } 1483 } 1484 1485 mutex_init(&host->thread_lock); 1486 1487 ret = mmc_add_host(mmc); 1488 if (ret < 0) 1489 goto err_clk; 1490 1491 dev_pm_qos_expose_latency_limit(dev, 100); 1492 1493 dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1494 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 1495 clk_get_rate(host->clk) / 1000000UL); 1496 1497 pm_runtime_put(dev); 1498 clk_disable_unprepare(host->clk); 1499 return ret; 1500 1501 err_clk: 1502 clk_disable_unprepare(host->clk); 1503 pm_runtime_put_sync(dev); 1504 pm_runtime_disable(dev); 1505 err_host: 1506 mmc_free_host(mmc); 1507 return ret; 1508 } 1509 1510 static int sh_mmcif_remove(struct platform_device *pdev) 1511 { 1512 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1513 1514 host->dying = true; 1515 clk_prepare_enable(host->clk); 1516 pm_runtime_get_sync(&pdev->dev); 1517 1518 dev_pm_qos_hide_latency_limit(&pdev->dev); 1519 1520 mmc_remove_host(host->mmc); 1521 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1522 1523 /* 1524 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1525 * mmc_remove_host() call above. But swapping order doesn't help either 1526 * (a query on the linux-mmc mailing list didn't bring any replies). 1527 */ 1528 cancel_delayed_work_sync(&host->timeout_work); 1529 1530 clk_disable_unprepare(host->clk); 1531 mmc_free_host(host->mmc); 1532 pm_runtime_put_sync(&pdev->dev); 1533 pm_runtime_disable(&pdev->dev); 1534 1535 return 0; 1536 } 1537 1538 #ifdef CONFIG_PM_SLEEP 1539 static int sh_mmcif_suspend(struct device *dev) 1540 { 1541 struct sh_mmcif_host *host = dev_get_drvdata(dev); 1542 1543 pm_runtime_get_sync(dev); 1544 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1545 pm_runtime_put(dev); 1546 1547 return 0; 1548 } 1549 1550 static int sh_mmcif_resume(struct device *dev) 1551 { 1552 return 0; 1553 } 1554 #endif 1555 1556 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1557 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1558 }; 1559 1560 static struct platform_driver sh_mmcif_driver = { 1561 .probe = sh_mmcif_probe, 1562 .remove = sh_mmcif_remove, 1563 .driver = { 1564 .name = DRIVER_NAME, 1565 .pm = &sh_mmcif_dev_pm_ops, 1566 .of_match_table = sh_mmcif_of_match, 1567 }, 1568 }; 1569 1570 module_platform_driver(sh_mmcif_driver); 1571 1572 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1573 MODULE_LICENSE("GPL v2"); 1574 MODULE_ALIAS("platform:" DRIVER_NAME); 1575 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1576