1dd79b7e3STakao Orito /* SPDX-License-Identifier: GPL-2.0 */ 2dd79b7e3STakao Orito /* 3dd79b7e3STakao Orito * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd 4dd79b7e3STakao Orito * Vincent Yang <vincent.yang@tw.fujitsu.com> 5dd79b7e3STakao Orito * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org> 6dd79b7e3STakao Orito * Copyright (C) 2019 Socionext Inc. 7dd79b7e3STakao Orito * 8dd79b7e3STakao Orito */ 9dd79b7e3STakao Orito 10dd79b7e3STakao Orito /* F_SDH30 extended Controller registers */ 11dd79b7e3STakao Orito #define F_SDH30_AHB_CONFIG 0x100 12dd79b7e3STakao Orito #define F_SDH30_AHB_BIGED BIT(6) 13dd79b7e3STakao Orito #define F_SDH30_BUSLOCK_DMA BIT(5) 14dd79b7e3STakao Orito #define F_SDH30_BUSLOCK_EN BIT(4) 15dd79b7e3STakao Orito #define F_SDH30_SIN BIT(3) 16dd79b7e3STakao Orito #define F_SDH30_AHB_INCR_16 BIT(2) 17dd79b7e3STakao Orito #define F_SDH30_AHB_INCR_8 BIT(1) 18dd79b7e3STakao Orito #define F_SDH30_AHB_INCR_4 BIT(0) 19dd79b7e3STakao Orito 20dd79b7e3STakao Orito #define F_SDH30_TUNING_SETTING 0x108 21dd79b7e3STakao Orito #define F_SDH30_CMD_CHK_DIS BIT(16) 22dd79b7e3STakao Orito 23dd79b7e3STakao Orito #define F_SDH30_IO_CONTROL2 0x114 24dd79b7e3STakao Orito #define F_SDH30_CRES_O_DN BIT(19) 25dd79b7e3STakao Orito #define F_SDH30_MSEL_O_1_8 BIT(18) 26dd79b7e3STakao Orito 27dd79b7e3STakao Orito #define F_SDH30_ESD_CONTROL 0x124 28dd79b7e3STakao Orito #define F_SDH30_EMMC_RST BIT(1) 29dd79b7e3STakao Orito #define F_SDH30_CMD_DAT_DELAY BIT(9) 30dd79b7e3STakao Orito #define F_SDH30_EMMC_HS200 BIT(24) 31dd79b7e3STakao Orito 32*e2d2dcc8SKunihiko Hayashi #define F_SDH30_TEST 0x158 33*e2d2dcc8SKunihiko Hayashi #define F_SDH30_FORCE_CARD_INSERT BIT(6) 34*e2d2dcc8SKunihiko Hayashi 35dd79b7e3STakao Orito #define F_SDH30_MIN_CLOCK 400000 36