1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 4 * 5 * Header file for Host Controller registers and I/O accessors. 6 * 7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 8 */ 9 #ifndef __SDHCI_HW_H 10 #define __SDHCI_HW_H 11 12 #include <linux/bits.h> 13 #include <linux/scatterlist.h> 14 #include <linux/compiler.h> 15 #include <linux/types.h> 16 #include <linux/io.h> 17 #include <linux/leds.h> 18 #include <linux/interrupt.h> 19 20 #include <linux/mmc/host.h> 21 22 /* 23 * Controller registers 24 */ 25 26 #define SDHCI_DMA_ADDRESS 0x00 27 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS 28 #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS 29 30 #define SDHCI_BLOCK_SIZE 0x04 31 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 32 33 #define SDHCI_BLOCK_COUNT 0x06 34 35 #define SDHCI_ARGUMENT 0x08 36 37 #define SDHCI_TRANSFER_MODE 0x0C 38 #define SDHCI_TRNS_DMA 0x01 39 #define SDHCI_TRNS_BLK_CNT_EN 0x02 40 #define SDHCI_TRNS_AUTO_CMD12 0x04 41 #define SDHCI_TRNS_AUTO_CMD23 0x08 42 #define SDHCI_TRNS_AUTO_SEL 0x0C 43 #define SDHCI_TRNS_READ 0x10 44 #define SDHCI_TRNS_MULTI 0x20 45 46 /* 47 * Defined in Host Version 4.0. 48 */ 49 #define SDHCI_TRNS_RES_TYPE 0x40 50 #define SDHCI_TRNS_RES_ERR_CHECK 0x80 51 #define SDHCI_TRNS_RES_INT_DIS 0x0100 52 53 #define SDHCI_COMMAND 0x0E 54 #define SDHCI_CMD_RESP_MASK 0x03 55 56 /* 57 * Host Version 4.10 adds this bit to distinguish a main command or 58 * sub command. 59 * For example with SDIO, CMD52 (sub command) issued during CMD53 (main command). 60 */ 61 #define SDHCI_CMD_SUB_CMD 0x04 62 63 #define SDHCI_CMD_CRC 0x08 64 #define SDHCI_CMD_INDEX 0x10 65 #define SDHCI_CMD_DATA 0x20 66 #define SDHCI_CMD_ABORTCMD 0xC0 67 68 #define SDHCI_CMD_RESP_NONE 0x00 69 #define SDHCI_CMD_RESP_LONG 0x01 70 #define SDHCI_CMD_RESP_SHORT 0x02 71 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 72 73 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 74 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) 75 76 #define SDHCI_RESPONSE 0x10 77 78 #define SDHCI_BUFFER 0x20 79 80 #define SDHCI_PRESENT_STATE 0x24 81 #define SDHCI_CMD_INHIBIT 0x00000001 82 #define SDHCI_DATA_INHIBIT 0x00000002 83 84 #define SDHCI_DAT_4_TO_7_LVL_MASK 0x000000F0 85 86 #define SDHCI_DOING_WRITE 0x00000100 87 #define SDHCI_DOING_READ 0x00000200 88 #define SDHCI_SPACE_AVAILABLE 0x00000400 89 #define SDHCI_DATA_AVAILABLE 0x00000800 90 #define SDHCI_CARD_PRESENT 0x00010000 91 #define SDHCI_CARD_PRES_SHIFT 16 92 #define SDHCI_CD_STABLE 0x00020000 93 #define SDHCI_CD_LVL 0x00040000 94 #define SDHCI_CD_LVL_SHIFT 18 95 #define SDHCI_WRITE_PROTECT 0x00080000 96 #define SDHCI_DATA_LVL_MASK 0x00F00000 97 #define SDHCI_DATA_LVL_SHIFT 20 98 #define SDHCI_DATA_0_LVL_MASK 0x00100000 99 #define SDHCI_CMD_LVL 0x01000000 100 101 /* Host Version 4.10 */ 102 103 #define SDHCI_HOST_REGULATOR_STABLE 0x02000000 104 #define SDHCI_CMD_NOT_ISSUED_ERR 0x08000000 105 #define SDHCI_SUB_CMD_STATUS 0x10000000 106 #define SDHCI_UHS2_IN_DORMANT_STATE 0x20000000 107 #define SDHCI_UHS2_LANE_SYNC 0x40000000 108 #define SDHCI_UHS2_IF_DETECT 0x80000000 109 110 #define SDHCI_HOST_CONTROL 0x28 111 #define SDHCI_CTRL_LED 0x01 112 #define SDHCI_CTRL_4BITBUS 0x02 113 #define SDHCI_CTRL_HISPD 0x04 114 #define SDHCI_CTRL_DMA_MASK 0x18 115 #define SDHCI_CTRL_SDMA 0x00 116 #define SDHCI_CTRL_ADMA1 0x08 117 #define SDHCI_CTRL_ADMA32 0x10 118 #define SDHCI_CTRL_ADMA64 0x18 119 #define SDHCI_CTRL_ADMA3 0x18 120 #define SDHCI_CTRL_8BITBUS 0x20 121 #define SDHCI_CTRL_CDTEST_INS 0x40 122 #define SDHCI_CTRL_CDTEST_EN 0x80 123 124 #define SDHCI_POWER_CONTROL 0x29 125 #define SDHCI_POWER_ON 0x01 126 #define SDHCI_POWER_180 0x0A 127 #define SDHCI_POWER_300 0x0C 128 #define SDHCI_POWER_330 0x0E 129 /* 130 * VDD2 - UHS2 or PCIe/NVMe 131 * VDD2 power on/off and voltage select 132 */ 133 #define SDHCI_VDD2_POWER_ON 0x10 134 #define SDHCI_VDD2_POWER_120 0x80 135 #define SDHCI_VDD2_POWER_180 0xA0 136 137 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 138 139 #define SDHCI_WAKE_UP_CONTROL 0x2B 140 #define SDHCI_WAKE_ON_INT 0x01 141 #define SDHCI_WAKE_ON_INSERT 0x02 142 #define SDHCI_WAKE_ON_REMOVE 0x04 143 144 #define SDHCI_CLOCK_CONTROL 0x2C 145 #define SDHCI_DIVIDER_SHIFT 8 146 #define SDHCI_DIVIDER_HI_SHIFT 6 147 #define SDHCI_DIV_MASK 0xFF 148 #define SDHCI_DIV_MASK_LEN 8 149 #define SDHCI_DIV_HI_MASK 0x300 150 #define SDHCI_PROG_CLOCK_MODE 0x0020 151 #define SDHCI_CLOCK_CARD_EN 0x0004 152 #define SDHCI_CLOCK_PLL_EN 0x0008 153 #define SDHCI_CLOCK_INT_STABLE 0x0002 154 #define SDHCI_CLOCK_INT_EN 0x0001 155 156 #define SDHCI_TIMEOUT_CONTROL 0x2E 157 158 #define SDHCI_SOFTWARE_RESET 0x2F 159 #define SDHCI_RESET_ALL 0x01 160 #define SDHCI_RESET_CMD 0x02 161 #define SDHCI_RESET_DATA 0x04 162 163 #define SDHCI_INT_STATUS 0x30 164 #define SDHCI_INT_ENABLE 0x34 165 #define SDHCI_SIGNAL_ENABLE 0x38 166 #define SDHCI_INT_RESPONSE 0x00000001 167 #define SDHCI_INT_DATA_END 0x00000002 168 #define SDHCI_INT_BLK_GAP 0x00000004 169 #define SDHCI_INT_DMA_END 0x00000008 170 #define SDHCI_INT_SPACE_AVAIL 0x00000010 171 #define SDHCI_INT_DATA_AVAIL 0x00000020 172 #define SDHCI_INT_CARD_INSERT 0x00000040 173 #define SDHCI_INT_CARD_REMOVE 0x00000080 174 #define SDHCI_INT_CARD_INT 0x00000100 175 #define SDHCI_INT_RETUNE 0x00001000 176 177 /* Host Version 4.10 */ 178 #define SDHCI_INT_FX_EVENT 0x00002000 179 180 #define SDHCI_INT_CQE 0x00004000 181 #define SDHCI_INT_ERROR 0x00008000 182 #define SDHCI_INT_TIMEOUT 0x00010000 183 #define SDHCI_INT_CRC 0x00020000 184 #define SDHCI_INT_END_BIT 0x00040000 185 #define SDHCI_INT_INDEX 0x00080000 186 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 187 #define SDHCI_INT_DATA_CRC 0x00200000 188 #define SDHCI_INT_DATA_END_BIT 0x00400000 189 #define SDHCI_INT_BUS_POWER 0x00800000 190 #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 191 #define SDHCI_INT_ADMA_ERROR 0x02000000 192 #define SDHCI_INT_TUNING_ERROR 0x04000000 193 194 /* Host Version 4.0 */ 195 #define SDHCI_INT_RESP_ERR 0x08000000 196 197 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 198 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 199 200 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 201 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ 202 SDHCI_INT_AUTO_CMD_ERR) 203 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 204 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 205 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 206 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ 207 SDHCI_INT_BLK_GAP | SDHCI_INT_TUNING_ERROR) 208 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 209 210 #define SDHCI_CQE_INT_ERR_MASK ( \ 211 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ 212 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ 213 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) 214 215 #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) 216 217 #define SDHCI_AUTO_CMD_STATUS 0x3C 218 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 219 #define SDHCI_AUTO_CMD_CRC 0x00000004 220 #define SDHCI_AUTO_CMD_END_BIT 0x00000008 221 #define SDHCI_AUTO_CMD_INDEX 0x00000010 222 223 /* Host Version 4.10 */ 224 #define SDHCI_AUTO_CMD_RESP_ERR 0x0020 225 226 #define SDHCI_HOST_CONTROL2 0x3E 227 #define SDHCI_CTRL_UHS_MASK 0x0007 228 #define SDHCI_CTRL_UHS_SDR12 0x0000 229 #define SDHCI_CTRL_UHS_SDR25 0x0001 230 #define SDHCI_CTRL_UHS_SDR50 0x0002 231 #define SDHCI_CTRL_UHS_SDR104 0x0003 232 #define SDHCI_CTRL_UHS_DDR50 0x0004 233 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ 234 #define SDHCI_CTRL_UHS2 0x0007 235 #define SDHCI_CTRL_VDD_180 0x0008 236 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 237 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 238 #define SDHCI_CTRL_DRV_TYPE_A 0x0010 239 #define SDHCI_CTRL_DRV_TYPE_C 0x0020 240 #define SDHCI_CTRL_DRV_TYPE_D 0x0030 241 #define SDHCI_CTRL_EXEC_TUNING 0x0040 242 #define SDHCI_CTRL_TUNED_CLK 0x0080 243 #define SDHCI_CTRL_UHS2_ENABLE 0x0100 244 #define SDHCI_CTRL_ADMA2_LEN_MODE 0x0400 245 #define SDHCI_CMD23_ENABLE 0x0800 246 #define SDHCI_CTRL_V4_MODE 0x1000 247 #define SDHCI_CTRL_64BIT_ADDR 0x2000 248 #define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 249 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 250 251 #define SDHCI_CAPABILITIES 0x40 252 #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) 253 #define SDHCI_TIMEOUT_CLK_SHIFT 0 254 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 255 #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) 256 #define SDHCI_CLOCK_BASE_SHIFT 8 257 #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) 258 #define SDHCI_MAX_BLOCK_MASK 0x00030000 259 #define SDHCI_MAX_BLOCK_SHIFT 16 260 #define SDHCI_CAN_DO_8BIT 0x00040000 261 #define SDHCI_CAN_DO_ADMA2 0x00080000 262 #define SDHCI_CAN_DO_ADMA1 0x00100000 263 #define SDHCI_CAN_DO_HISPD 0x00200000 264 #define SDHCI_CAN_DO_SDMA 0x00400000 265 #define SDHCI_CAN_DO_SUSPEND 0x00800000 266 #define SDHCI_CAN_VDD_330 0x01000000 267 #define SDHCI_CAN_VDD_300 0x02000000 268 #define SDHCI_CAN_VDD_180 0x04000000 269 #define SDHCI_CAN_64BIT_V4 0x08000000 270 #define SDHCI_CAN_64BIT 0x10000000 271 #define SDHCI_CAN_ASYNC_INT 0x20000000 272 273 #define SDHCI_CAPABILITIES_1 0x44 274 #define SDHCI_SUPPORT_SDR50 0x00000001 275 #define SDHCI_SUPPORT_SDR104 0x00000002 276 #define SDHCI_SUPPORT_DDR50 0x00000004 277 #define SDHCI_SUPPORT_UHS2 0x00000008 278 #define SDHCI_DRIVER_TYPE_A 0x00000010 279 #define SDHCI_DRIVER_TYPE_C 0x00000020 280 #define SDHCI_DRIVER_TYPE_D 0x00000040 281 #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) 282 #define SDHCI_USE_SDR50_TUNING 0x00002000 283 #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) 284 #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) 285 #define SDHCI_CAN_DO_ADMA3 0x08000000 286 #define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */ 287 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ 288 289 #define SDHCI_MAX_CURRENT 0x48 290 #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) 291 #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) 292 #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) 293 #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) 294 #define SDHCI_MAX_CURRENT_1 0x4C 295 #define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */ 296 #define SDHCI_MAX_CURRENT_MULTIPLIER 4 297 298 /* 4C-4F reserved for more max current */ 299 300 #define SDHCI_SET_ACMD12_ERROR 0x50 301 /* Host Version 4.10 */ 302 #define SDHCI_SET_INT_ERROR 0x52 303 304 #define SDHCI_ADMA_ERROR 0x54 305 306 /* 55-57 reserved */ 307 308 #define SDHCI_ADMA_ADDRESS 0x58 309 #define SDHCI_ADMA_ADDRESS_HI 0x5C 310 311 /* 60-FB reserved */ 312 313 #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 314 #define SDHCI_PRESET_FOR_SDR12 0x66 315 #define SDHCI_PRESET_FOR_SDR25 0x68 316 #define SDHCI_PRESET_FOR_SDR50 0x6A 317 #define SDHCI_PRESET_FOR_SDR104 0x6C 318 #define SDHCI_PRESET_FOR_DDR50 0x6E 319 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ 320 321 /* UHS2 */ 322 #define SDHCI_PRESET_FOR_UHS2 0x74 323 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) 324 #define SDHCI_PRESET_CLKGEN_SEL BIT(10) 325 #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) 326 327 #define SDHCI_ADMA3_ADDRESS 0x78 328 329 #define SDHCI_SLOT_INT_STATUS 0xFC 330 331 #define SDHCI_HOST_VERSION 0xFE 332 #define SDHCI_VENDOR_VER_MASK 0xFF00 333 #define SDHCI_VENDOR_VER_SHIFT 8 334 #define SDHCI_SPEC_VER_MASK 0x00FF 335 #define SDHCI_SPEC_VER_SHIFT 0 336 #define SDHCI_SPEC_100 0 337 #define SDHCI_SPEC_200 1 338 #define SDHCI_SPEC_300 2 339 #define SDHCI_SPEC_400 3 340 #define SDHCI_SPEC_410 4 341 #define SDHCI_SPEC_420 5 342 343 /* 344 * End of controller registers. 345 */ 346 347 #define SDHCI_MAX_DIV_SPEC_200 256 348 #define SDHCI_MAX_DIV_SPEC_300 2046 349 350 /* 351 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. 352 */ 353 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) 354 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) 355 356 /* ADMA2 32-bit DMA descriptor size */ 357 #define SDHCI_ADMA2_32_DESC_SZ 8 358 359 /* ADMA2 32-bit descriptor */ 360 struct sdhci_adma2_32_desc { 361 __le16 cmd; 362 __le16 len; 363 __le32 addr; 364 } __packed __aligned(4); 365 366 /* ADMA2 data alignment */ 367 #define SDHCI_ADMA2_ALIGN 4 368 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) 369 370 /* 371 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte 372 * alignment for the descriptor table even in 32-bit DMA mode. Memory 373 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. 374 */ 375 #define SDHCI_ADMA2_DESC_ALIGN 8 376 377 /* 378 * ADMA2 64-bit DMA descriptor size 379 * According to SD Host Controller spec v4.10, there are two kinds of 380 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit 381 * Descriptor, if Host Version 4 Enable is set in the Host Control 2 382 * register, 128-bit Descriptor will be selected. 383 */ 384 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) 385 386 /* 387 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte 388 * aligned. 389 */ 390 struct sdhci_adma2_64_desc { 391 __le16 cmd; 392 __le16 len; 393 __le32 addr_lo; 394 __le32 addr_hi; 395 } __packed __aligned(4); 396 397 #define ADMA2_TRAN_VALID 0x21 398 #define ADMA2_NOP_END_VALID 0x3 399 #define ADMA2_END 0x2 400 401 /* 402 * Maximum segments assuming a 512KiB maximum requisition size and a minimum 403 * 4KiB page size. Note this also allows enough for multiple descriptors in 404 * case of PAGE_SIZE >= 64KiB. 405 */ 406 #define SDHCI_MAX_SEGS 128 407 408 /* Allow for a command request and a data request at the same time */ 409 #define SDHCI_MAX_MRQS 2 410 411 /* 412 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. 413 * However since the start time of the command, the time between 414 * command and response, and the time between response and start of data is 415 * not known, set the command transfer time to 10ms. 416 */ 417 #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ 418 419 #define sdhci_err_stats_inc(host, err_name) \ 420 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name) 421 422 enum sdhci_cookie { 423 COOKIE_UNMAPPED, 424 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ 425 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ 426 }; 427 428 struct sdhci_host { 429 /* Data set by hardware interface driver */ 430 const char *hw_name; /* Hardware bus name */ 431 432 unsigned int quirks; /* Deviations from spec. */ 433 434 /* Controller doesn't honor resets unless we touch the clock register */ 435 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 436 /* Controller has bad caps bits, but really supports DMA */ 437 #define SDHCI_QUIRK_FORCE_DMA (1<<1) 438 /* Controller doesn't like to be reset when there is no card inserted. */ 439 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 440 /* Controller doesn't like clearing the power reg before a change */ 441 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 442 /* Controller has an unusable DMA engine */ 443 #define SDHCI_QUIRK_BROKEN_DMA (1<<5) 444 /* Controller has an unusable ADMA engine */ 445 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 446 /* Controller can only DMA from 32-bit aligned addresses */ 447 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 448 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 449 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 450 /* Controller can only ADMA chunks that are a multiple of 32 bits */ 451 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 452 /* Controller needs to be reset after each request to stay stable */ 453 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 454 /* Controller needs voltage and power writes to happen separately */ 455 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 456 /* Controller provides an incorrect timeout value for transfers */ 457 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 458 /* Controller has an issue with buffer bits for small transfers */ 459 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 460 /* Controller does not provide transfer-complete interrupt when not busy */ 461 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 462 /* Controller has unreliable card detection */ 463 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 464 /* Controller reports inverted write-protect state */ 465 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 466 /* Controller has unusable command queue engine */ 467 #define SDHCI_QUIRK_BROKEN_CQE (1<<17) 468 /* Controller does not like fast PIO transfers */ 469 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 470 /* Controller does not have a LED */ 471 #define SDHCI_QUIRK_NO_LED (1<<19) 472 /* Controller has to be forced to use block size of 2048 bytes */ 473 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 474 /* Controller cannot do multi-block transfers */ 475 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 476 /* Controller can only handle 1-bit data transfers */ 477 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 478 /* Controller needs 10ms delay between applying power and clock */ 479 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 480 /* Controller uses SDCLK instead of TMCLK for data timeouts */ 481 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 482 /* Controller reports wrong base clock capability */ 483 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 484 /* Controller cannot support End Attribute in NOP ADMA descriptor */ 485 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 486 /* Controller uses Auto CMD12 command to stop the transfer */ 487 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 488 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 489 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 490 /* Controller treats ADMA descriptors with length 0000h incorrectly */ 491 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 492 493 unsigned int quirks2; /* More deviations from spec. */ 494 495 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 496 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 497 /* The system physically doesn't support 1.8v, even if the host does */ 498 #define SDHCI_QUIRK2_NO_1_8_V (1<<2) 499 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 500 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 501 /* Controller has a non-standard host control register */ 502 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 503 /* Controller does not support HS200 */ 504 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 505 /* Controller does not support DDR50 */ 506 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 507 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 508 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 509 /* Controller does not support 64-bit DMA */ 510 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 511 /* need clear transfer mode register before send cmd */ 512 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 513 /* Capability register bit-63 indicates HS400 support */ 514 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 515 /* forced tuned clock */ 516 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) 517 /* disable the block count for single block transactions */ 518 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) 519 /* Controller broken with using ACMD23 */ 520 #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) 521 /* Broken Clock divider zero in controller */ 522 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) 523 /* Controller has CRC in 136 bit Command Response */ 524 #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) 525 /* 526 * Disable HW timeout if the requested timeout is more than the maximum 527 * obtainable timeout. 528 */ 529 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) 530 /* 531 * 32-bit block count may not support eMMC where upper bits of CMD23 are used 532 * for other purposes. Consequently we support 16-bit block count by default. 533 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit 534 * block count. 535 */ 536 #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) 537 /* Issue CMD and DATA reset together */ 538 #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) 539 540 int irq; /* Device IRQ */ 541 void __iomem *ioaddr; /* Mapped address */ 542 phys_addr_t mapbase; /* physical address base */ 543 char *bounce_buffer; /* For packing SDMA reads/writes */ 544 dma_addr_t bounce_addr; 545 unsigned int bounce_buffer_size; 546 547 const struct sdhci_ops *ops; /* Low level hw interface */ 548 549 /* Internal data */ 550 struct mmc_host *mmc; /* MMC structure */ 551 struct mmc_host_ops mmc_host_ops; /* MMC host ops */ 552 u64 dma_mask; /* custom DMA mask */ 553 554 #if IS_ENABLED(CONFIG_LEDS_CLASS) 555 struct led_classdev led; /* LED control */ 556 char led_name[32]; 557 #endif 558 559 spinlock_t lock; /* Mutex */ 560 561 int flags; /* Host attributes */ 562 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 563 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 564 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 565 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 566 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 567 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 568 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 569 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 570 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 571 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 572 #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ 573 #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ 574 #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ 575 576 unsigned int version; /* SDHCI spec. version */ 577 578 unsigned int max_clk; /* Max possible freq (MHz) */ 579 unsigned int timeout_clk; /* Timeout freq (KHz) */ 580 u8 max_timeout_count; /* Vendor specific max timeout count */ 581 unsigned int clk_mul; /* Clock Muliplier value */ 582 583 unsigned int clock; /* Current clock (MHz) */ 584 u8 pwr; /* Current voltage */ 585 u8 drv_type; /* Current UHS-I driver type */ 586 bool reinit_uhs; /* Force UHS-related re-initialization */ 587 588 bool runtime_suspended; /* Host is runtime suspended */ 589 bool bus_on; /* Bus power prevents runtime suspend */ 590 bool preset_enabled; /* Preset is enabled */ 591 bool pending_reset; /* Cmd/data reset is pending */ 592 bool irq_wake_enabled; /* IRQ wakeup is enabled */ 593 bool v4_mode; /* Host Version 4 Enable */ 594 bool use_external_dma; /* Host selects to use external DMA */ 595 bool always_defer_done; /* Always defer to complete requests */ 596 597 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ 598 struct mmc_command *cmd; /* Current command */ 599 struct mmc_command *data_cmd; /* Current data command */ 600 struct mmc_command *deferred_cmd; /* Deferred command */ 601 struct mmc_data *data; /* Current data request */ 602 unsigned int data_early:1; /* Data finished before cmd */ 603 604 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 605 unsigned int blocks; /* remaining PIO blocks */ 606 607 int sg_count; /* Mapped sg entries */ 608 int max_adma; /* Max. length in ADMA descriptor */ 609 610 void *adma_table; /* ADMA descriptor table */ 611 void *align_buffer; /* Bounce buffer */ 612 613 size_t adma_table_sz; /* ADMA descriptor table size */ 614 size_t align_buffer_sz; /* Bounce buffer size */ 615 616 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 617 dma_addr_t align_addr; /* Mapped bounce buffer */ 618 619 unsigned int desc_sz; /* ADMA current descriptor size */ 620 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ 621 622 struct workqueue_struct *complete_wq; /* Request completion wq */ 623 struct work_struct complete_work; /* Request completion work */ 624 625 struct timer_list timer; /* Timer for timeouts */ 626 struct timer_list data_timer; /* Timer for data timeouts */ 627 628 void (*complete_work_fn)(struct work_struct *work); 629 irqreturn_t (*thread_irq_fn)(int irq, void *dev_id); 630 631 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) 632 struct dma_chan *rx_chan; 633 struct dma_chan *tx_chan; 634 #endif 635 636 u32 caps; /* CAPABILITY_0 */ 637 u32 caps1; /* CAPABILITY_1 */ 638 bool read_caps; /* Capability flags have been read */ 639 640 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ 641 unsigned int ocr_avail_sdio; /* OCR bit masks */ 642 unsigned int ocr_avail_sd; 643 unsigned int ocr_avail_mmc; 644 u32 ocr_mask; /* available voltages */ 645 646 unsigned timing; /* Current timing */ 647 648 u32 thread_isr; 649 650 /* cached registers */ 651 u32 ier; 652 653 bool cqe_on; /* CQE is operating */ 654 u32 cqe_ier; /* CQE interrupt mask */ 655 u32 cqe_err_ier; /* CQE error interrupt mask */ 656 657 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 658 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 659 660 unsigned int tuning_count; /* Timer count for re-tuning */ 661 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 662 unsigned int tuning_err; /* Error code for re-tuning */ 663 #define SDHCI_TUNING_MODE_1 0 664 #define SDHCI_TUNING_MODE_2 1 665 #define SDHCI_TUNING_MODE_3 2 666 /* Delay (ms) between tuning commands */ 667 int tuning_delay; 668 int tuning_loop_count; 669 670 /* Host SDMA buffer boundary. */ 671 u32 sdma_boundary; 672 673 /* Host ADMA table count */ 674 u32 adma_table_cnt; 675 676 u64 data_timeout; 677 678 unsigned long private[] ____cacheline_aligned; 679 }; 680 681 struct sdhci_ops { 682 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 683 u32 (*read_l)(struct sdhci_host *host, int reg); 684 u16 (*read_w)(struct sdhci_host *host, int reg); 685 u8 (*read_b)(struct sdhci_host *host, int reg); 686 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 687 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 688 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 689 #endif 690 691 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 692 void (*set_power)(struct sdhci_host *host, unsigned char mode, 693 unsigned short vdd); 694 695 u32 (*irq)(struct sdhci_host *host, u32 intmask); 696 697 int (*set_dma_mask)(struct sdhci_host *host); 698 int (*enable_dma)(struct sdhci_host *host); 699 unsigned int (*get_max_clock)(struct sdhci_host *host); 700 unsigned int (*get_min_clock)(struct sdhci_host *host); 701 /* get_timeout_clock should return clk rate in unit of Hz */ 702 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 703 unsigned int (*get_max_timeout_count)(struct sdhci_host *host); 704 void (*set_timeout)(struct sdhci_host *host, 705 struct mmc_command *cmd); 706 void (*set_bus_width)(struct sdhci_host *host, int width); 707 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 708 u8 power_mode); 709 unsigned int (*get_ro)(struct sdhci_host *host); 710 void (*reset)(struct sdhci_host *host, u8 mask); 711 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); 712 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); 713 void (*hw_reset)(struct sdhci_host *host); 714 void (*adma_workaround)(struct sdhci_host *host, u32 intmask); 715 void (*card_event)(struct sdhci_host *host); 716 void (*voltage_switch)(struct sdhci_host *host); 717 void (*adma_write_desc)(struct sdhci_host *host, void **desc, 718 dma_addr_t addr, int len, unsigned int cmd); 719 void (*copy_to_bounce_buffer)(struct sdhci_host *host, 720 struct mmc_data *data, 721 unsigned int length); 722 void (*request_done)(struct sdhci_host *host, 723 struct mmc_request *mrq); 724 void (*dump_vendor_regs)(struct sdhci_host *host); 725 void (*dump_uhs2_regs)(struct sdhci_host *host); 726 void (*uhs2_pre_detect_init)(struct sdhci_host *host); 727 }; 728 729 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 730 731 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 732 { 733 if (unlikely(host->ops->write_l)) 734 host->ops->write_l(host, val, reg); 735 else 736 writel(val, host->ioaddr + reg); 737 } 738 739 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 740 { 741 if (unlikely(host->ops->write_w)) 742 host->ops->write_w(host, val, reg); 743 else 744 writew(val, host->ioaddr + reg); 745 } 746 747 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 748 { 749 if (unlikely(host->ops->write_b)) 750 host->ops->write_b(host, val, reg); 751 else 752 writeb(val, host->ioaddr + reg); 753 } 754 755 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 756 { 757 if (unlikely(host->ops->read_l)) 758 return host->ops->read_l(host, reg); 759 else 760 return readl(host->ioaddr + reg); 761 } 762 763 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 764 { 765 if (unlikely(host->ops->read_w)) 766 return host->ops->read_w(host, reg); 767 else 768 return readw(host->ioaddr + reg); 769 } 770 771 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 772 { 773 if (unlikely(host->ops->read_b)) 774 return host->ops->read_b(host, reg); 775 else 776 return readb(host->ioaddr + reg); 777 } 778 779 #else 780 781 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 782 { 783 writel(val, host->ioaddr + reg); 784 } 785 786 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 787 { 788 writew(val, host->ioaddr + reg); 789 } 790 791 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 792 { 793 writeb(val, host->ioaddr + reg); 794 } 795 796 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 797 { 798 return readl(host->ioaddr + reg); 799 } 800 801 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 802 { 803 return readw(host->ioaddr + reg); 804 } 805 806 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 807 { 808 return readb(host->ioaddr + reg); 809 } 810 811 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 812 813 struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); 814 void sdhci_free_host(struct sdhci_host *host); 815 816 static inline void *sdhci_priv(struct sdhci_host *host) 817 { 818 return host->private; 819 } 820 821 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, 822 const u32 *caps, const u32 *caps1); 823 int sdhci_setup_host(struct sdhci_host *host); 824 void sdhci_cleanup_host(struct sdhci_host *host); 825 int __sdhci_add_host(struct sdhci_host *host); 826 int sdhci_add_host(struct sdhci_host *host); 827 void sdhci_remove_host(struct sdhci_host *host, int dead); 828 829 static inline void sdhci_read_caps(struct sdhci_host *host) 830 { 831 __sdhci_read_caps(host, NULL, NULL, NULL); 832 } 833 834 bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq); 835 bool sdhci_data_line_cmd(struct mmc_command *cmd); 836 void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout); 837 void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); 838 void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); 839 void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); 840 void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); 841 void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset); 842 bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present); 843 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 844 unsigned int *actual_clock); 845 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); 846 void sdhci_enable_clk(struct sdhci_host *host, u16 clk); 847 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 848 unsigned short vdd); 849 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, 850 unsigned char mode, 851 unsigned short vdd); 852 unsigned short sdhci_get_vdd_value(unsigned short vdd); 853 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 854 unsigned short vdd); 855 int sdhci_get_cd_nogpio(struct mmc_host *mmc); 856 int sdhci_get_ro(struct mmc_host *mmc); 857 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); 858 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); 859 void sdhci_set_bus_width(struct sdhci_host *host, int width); 860 void sdhci_reset(struct sdhci_host *host, u8 mask); 861 bool sdhci_do_reset(struct sdhci_host *host, u8 mask); 862 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); 863 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 864 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); 865 void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 866 void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios); 867 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 868 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 869 struct mmc_ios *ios); 870 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); 871 void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq); 872 void sdhci_complete_work(struct work_struct *work); 873 irqreturn_t sdhci_thread_irq(int irq, void *dev_id); 874 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 875 dma_addr_t addr, int len, unsigned int cmd); 876 877 #ifdef CONFIG_PM 878 int sdhci_suspend_host(struct sdhci_host *host); 879 int sdhci_resume_host(struct sdhci_host *host); 880 int sdhci_runtime_suspend_host(struct sdhci_host *host); 881 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); 882 #endif 883 884 void sdhci_cqe_enable(struct mmc_host *mmc); 885 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); 886 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 887 int *data_error); 888 889 void sdhci_dumpregs(struct sdhci_host *host); 890 void sdhci_enable_v4_mode(struct sdhci_host *host); 891 892 void sdhci_start_tuning(struct sdhci_host *host); 893 void sdhci_end_tuning(struct sdhci_host *host); 894 void sdhci_reset_tuning(struct sdhci_host *host); 895 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); 896 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); 897 void sdhci_switch_external_dma(struct sdhci_host *host, bool en); 898 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); 899 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); 900 901 #endif /* __SDHCI_HW_H */ 902