1 /* 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver 3 * 4 * Header file for Host Controller registers and I/O accessors. 5 * 6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or (at 11 * your option) any later version. 12 */ 13 #ifndef __SDHCI_HW_H 14 #define __SDHCI_HW_H 15 16 #include <linux/scatterlist.h> 17 #include <linux/compiler.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 21 #include <linux/mmc/sdhci.h> 22 23 /* 24 * Controller registers 25 */ 26 27 #define SDHCI_DMA_ADDRESS 0x00 28 29 #define SDHCI_BLOCK_SIZE 0x04 30 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) 31 32 #define SDHCI_BLOCK_COUNT 0x06 33 34 #define SDHCI_ARGUMENT 0x08 35 36 #define SDHCI_TRANSFER_MODE 0x0C 37 #define SDHCI_TRNS_DMA 0x01 38 #define SDHCI_TRNS_BLK_CNT_EN 0x02 39 #define SDHCI_TRNS_ACMD12 0x04 40 #define SDHCI_TRNS_READ 0x10 41 #define SDHCI_TRNS_MULTI 0x20 42 43 #define SDHCI_COMMAND 0x0E 44 #define SDHCI_CMD_RESP_MASK 0x03 45 #define SDHCI_CMD_CRC 0x08 46 #define SDHCI_CMD_INDEX 0x10 47 #define SDHCI_CMD_DATA 0x20 48 49 #define SDHCI_CMD_RESP_NONE 0x00 50 #define SDHCI_CMD_RESP_LONG 0x01 51 #define SDHCI_CMD_RESP_SHORT 0x02 52 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 53 54 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) 55 56 #define SDHCI_RESPONSE 0x10 57 58 #define SDHCI_BUFFER 0x20 59 60 #define SDHCI_PRESENT_STATE 0x24 61 #define SDHCI_CMD_INHIBIT 0x00000001 62 #define SDHCI_DATA_INHIBIT 0x00000002 63 #define SDHCI_DOING_WRITE 0x00000100 64 #define SDHCI_DOING_READ 0x00000200 65 #define SDHCI_SPACE_AVAILABLE 0x00000400 66 #define SDHCI_DATA_AVAILABLE 0x00000800 67 #define SDHCI_CARD_PRESENT 0x00010000 68 #define SDHCI_WRITE_PROTECT 0x00080000 69 70 #define SDHCI_HOST_CONTROL 0x28 71 #define SDHCI_CTRL_LED 0x01 72 #define SDHCI_CTRL_4BITBUS 0x02 73 #define SDHCI_CTRL_HISPD 0x04 74 #define SDHCI_CTRL_DMA_MASK 0x18 75 #define SDHCI_CTRL_SDMA 0x00 76 #define SDHCI_CTRL_ADMA1 0x08 77 #define SDHCI_CTRL_ADMA32 0x10 78 #define SDHCI_CTRL_ADMA64 0x18 79 #define SDHCI_CTRL_8BITBUS 0x20 80 81 #define SDHCI_POWER_CONTROL 0x29 82 #define SDHCI_POWER_ON 0x01 83 #define SDHCI_POWER_180 0x0A 84 #define SDHCI_POWER_300 0x0C 85 #define SDHCI_POWER_330 0x0E 86 87 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 88 89 #define SDHCI_WAKE_UP_CONTROL 0x2B 90 #define SDHCI_WAKE_ON_INT 0x01 91 #define SDHCI_WAKE_ON_INSERT 0x02 92 #define SDHCI_WAKE_ON_REMOVE 0x04 93 94 #define SDHCI_CLOCK_CONTROL 0x2C 95 #define SDHCI_DIVIDER_SHIFT 8 96 #define SDHCI_DIVIDER_HI_SHIFT 6 97 #define SDHCI_DIV_MASK 0xFF 98 #define SDHCI_DIV_MASK_LEN 8 99 #define SDHCI_DIV_HI_MASK 0x300 100 #define SDHCI_CLOCK_CARD_EN 0x0004 101 #define SDHCI_CLOCK_INT_STABLE 0x0002 102 #define SDHCI_CLOCK_INT_EN 0x0001 103 104 #define SDHCI_TIMEOUT_CONTROL 0x2E 105 106 #define SDHCI_SOFTWARE_RESET 0x2F 107 #define SDHCI_RESET_ALL 0x01 108 #define SDHCI_RESET_CMD 0x02 109 #define SDHCI_RESET_DATA 0x04 110 111 #define SDHCI_INT_STATUS 0x30 112 #define SDHCI_INT_ENABLE 0x34 113 #define SDHCI_SIGNAL_ENABLE 0x38 114 #define SDHCI_INT_RESPONSE 0x00000001 115 #define SDHCI_INT_DATA_END 0x00000002 116 #define SDHCI_INT_DMA_END 0x00000008 117 #define SDHCI_INT_SPACE_AVAIL 0x00000010 118 #define SDHCI_INT_DATA_AVAIL 0x00000020 119 #define SDHCI_INT_CARD_INSERT 0x00000040 120 #define SDHCI_INT_CARD_REMOVE 0x00000080 121 #define SDHCI_INT_CARD_INT 0x00000100 122 #define SDHCI_INT_ERROR 0x00008000 123 #define SDHCI_INT_TIMEOUT 0x00010000 124 #define SDHCI_INT_CRC 0x00020000 125 #define SDHCI_INT_END_BIT 0x00040000 126 #define SDHCI_INT_INDEX 0x00080000 127 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 128 #define SDHCI_INT_DATA_CRC 0x00200000 129 #define SDHCI_INT_DATA_END_BIT 0x00400000 130 #define SDHCI_INT_BUS_POWER 0x00800000 131 #define SDHCI_INT_ACMD12ERR 0x01000000 132 #define SDHCI_INT_ADMA_ERROR 0x02000000 133 134 #define SDHCI_INT_NORMAL_MASK 0x00007FFF 135 #define SDHCI_INT_ERROR_MASK 0xFFFF8000 136 137 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ 138 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) 139 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ 140 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ 141 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ 142 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) 143 #define SDHCI_INT_ALL_MASK ((unsigned int)-1) 144 145 #define SDHCI_ACMD12_ERR 0x3C 146 147 /* 3E-3F reserved */ 148 149 #define SDHCI_CAPABILITIES 0x40 150 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F 151 #define SDHCI_TIMEOUT_CLK_SHIFT 0 152 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 153 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 154 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 155 #define SDHCI_CLOCK_BASE_SHIFT 8 156 #define SDHCI_MAX_BLOCK_MASK 0x00030000 157 #define SDHCI_MAX_BLOCK_SHIFT 16 158 #define SDHCI_CAN_DO_8BIT 0x00040000 159 #define SDHCI_CAN_DO_ADMA2 0x00080000 160 #define SDHCI_CAN_DO_ADMA1 0x00100000 161 #define SDHCI_CAN_DO_HISPD 0x00200000 162 #define SDHCI_CAN_DO_SDMA 0x00400000 163 #define SDHCI_CAN_VDD_330 0x01000000 164 #define SDHCI_CAN_VDD_300 0x02000000 165 #define SDHCI_CAN_VDD_180 0x04000000 166 #define SDHCI_CAN_64BIT 0x10000000 167 168 /* 44-47 reserved for more caps */ 169 170 #define SDHCI_MAX_CURRENT 0x48 171 172 /* 4C-4F reserved for more max current */ 173 174 #define SDHCI_SET_ACMD12_ERROR 0x50 175 #define SDHCI_SET_INT_ERROR 0x52 176 177 #define SDHCI_ADMA_ERROR 0x54 178 179 /* 55-57 reserved */ 180 181 #define SDHCI_ADMA_ADDRESS 0x58 182 183 /* 60-FB reserved */ 184 185 #define SDHCI_SLOT_INT_STATUS 0xFC 186 187 #define SDHCI_HOST_VERSION 0xFE 188 #define SDHCI_VENDOR_VER_MASK 0xFF00 189 #define SDHCI_VENDOR_VER_SHIFT 8 190 #define SDHCI_SPEC_VER_MASK 0x00FF 191 #define SDHCI_SPEC_VER_SHIFT 0 192 #define SDHCI_SPEC_100 0 193 #define SDHCI_SPEC_200 1 194 #define SDHCI_SPEC_300 2 195 196 /* 197 * End of controller registers. 198 */ 199 200 #define SDHCI_MAX_DIV_SPEC_200 256 201 #define SDHCI_MAX_DIV_SPEC_300 2046 202 203 struct sdhci_ops { 204 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 205 u32 (*read_l)(struct sdhci_host *host, int reg); 206 u16 (*read_w)(struct sdhci_host *host, int reg); 207 u8 (*read_b)(struct sdhci_host *host, int reg); 208 void (*write_l)(struct sdhci_host *host, u32 val, int reg); 209 void (*write_w)(struct sdhci_host *host, u16 val, int reg); 210 void (*write_b)(struct sdhci_host *host, u8 val, int reg); 211 #endif 212 213 void (*set_clock)(struct sdhci_host *host, unsigned int clock); 214 215 int (*enable_dma)(struct sdhci_host *host); 216 unsigned int (*get_max_clock)(struct sdhci_host *host); 217 unsigned int (*get_min_clock)(struct sdhci_host *host); 218 unsigned int (*get_timeout_clock)(struct sdhci_host *host); 219 int (*platform_8bit_width)(struct sdhci_host *host, 220 int width); 221 void (*platform_send_init_74_clocks)(struct sdhci_host *host, 222 u8 power_mode); 223 unsigned int (*get_ro)(struct sdhci_host *host); 224 }; 225 226 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 227 228 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 229 { 230 if (unlikely(host->ops->write_l)) 231 host->ops->write_l(host, val, reg); 232 else 233 writel(val, host->ioaddr + reg); 234 } 235 236 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 237 { 238 if (unlikely(host->ops->write_w)) 239 host->ops->write_w(host, val, reg); 240 else 241 writew(val, host->ioaddr + reg); 242 } 243 244 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 245 { 246 if (unlikely(host->ops->write_b)) 247 host->ops->write_b(host, val, reg); 248 else 249 writeb(val, host->ioaddr + reg); 250 } 251 252 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 253 { 254 if (unlikely(host->ops->read_l)) 255 return host->ops->read_l(host, reg); 256 else 257 return readl(host->ioaddr + reg); 258 } 259 260 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 261 { 262 if (unlikely(host->ops->read_w)) 263 return host->ops->read_w(host, reg); 264 else 265 return readw(host->ioaddr + reg); 266 } 267 268 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 269 { 270 if (unlikely(host->ops->read_b)) 271 return host->ops->read_b(host, reg); 272 else 273 return readb(host->ioaddr + reg); 274 } 275 276 #else 277 278 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) 279 { 280 writel(val, host->ioaddr + reg); 281 } 282 283 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) 284 { 285 writew(val, host->ioaddr + reg); 286 } 287 288 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 289 { 290 writeb(val, host->ioaddr + reg); 291 } 292 293 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) 294 { 295 return readl(host->ioaddr + reg); 296 } 297 298 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) 299 { 300 return readw(host->ioaddr + reg); 301 } 302 303 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) 304 { 305 return readb(host->ioaddr + reg); 306 } 307 308 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ 309 310 extern struct sdhci_host *sdhci_alloc_host(struct device *dev, 311 size_t priv_size); 312 extern void sdhci_free_host(struct sdhci_host *host); 313 314 static inline void *sdhci_priv(struct sdhci_host *host) 315 { 316 return (void *)host->private; 317 } 318 319 extern void sdhci_card_detect(struct sdhci_host *host); 320 extern int sdhci_add_host(struct sdhci_host *host); 321 extern void sdhci_remove_host(struct sdhci_host *host, int dead); 322 323 #ifdef CONFIG_PM 324 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state); 325 extern int sdhci_resume_host(struct sdhci_host *host); 326 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); 327 #endif 328 329 #endif /* __SDHCI_HW_H */ 330