1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #include "sdhci.h" 35 36 #define DRIVER_NAME "sdhci" 37 38 #define DBG(f, x...) \ 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 40 41 #define MAX_TUNING_LOOP 40 42 43 static unsigned int debug_quirks = 0; 44 static unsigned int debug_quirks2; 45 46 static void sdhci_finish_data(struct sdhci_host *); 47 48 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 49 50 static void sdhci_dumpregs(struct sdhci_host *host) 51 { 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 53 mmc_hostname(host->mmc)); 54 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 56 sdhci_readl(host, SDHCI_DMA_ADDRESS), 57 sdhci_readw(host, SDHCI_HOST_VERSION)); 58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 59 sdhci_readw(host, SDHCI_BLOCK_SIZE), 60 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 62 sdhci_readl(host, SDHCI_ARGUMENT), 63 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 65 sdhci_readl(host, SDHCI_PRESENT_STATE), 66 sdhci_readb(host, SDHCI_HOST_CONTROL)); 67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 68 sdhci_readb(host, SDHCI_POWER_CONTROL), 69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 72 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 75 sdhci_readl(host, SDHCI_INT_STATUS)); 76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 77 sdhci_readl(host, SDHCI_INT_ENABLE), 78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 80 sdhci_readw(host, SDHCI_ACMD12_ERR), 81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 83 sdhci_readl(host, SDHCI_CAPABILITIES), 84 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 86 sdhci_readw(host, SDHCI_COMMAND), 87 sdhci_readl(host, SDHCI_MAX_CURRENT)); 88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", 89 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 90 91 if (host->flags & SDHCI_USE_ADMA) { 92 if (host->flags & SDHCI_USE_64_BIT_DMA) 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 94 readl(host->ioaddr + SDHCI_ADMA_ERROR), 95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 97 else 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 99 readl(host->ioaddr + SDHCI_ADMA_ERROR), 100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 101 } 102 103 pr_err(DRIVER_NAME ": ===========================================\n"); 104 } 105 106 /*****************************************************************************\ 107 * * 108 * Low level functions * 109 * * 110 \*****************************************************************************/ 111 112 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 113 { 114 return cmd->data || cmd->flags & MMC_RSP_BUSY; 115 } 116 117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 118 { 119 u32 present; 120 121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 122 !mmc_card_is_removable(host->mmc)) 123 return; 124 125 if (enable) { 126 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 127 SDHCI_CARD_PRESENT; 128 129 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 130 SDHCI_INT_CARD_INSERT; 131 } else { 132 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 133 } 134 135 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 136 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 137 } 138 139 static void sdhci_enable_card_detection(struct sdhci_host *host) 140 { 141 sdhci_set_card_detection(host, true); 142 } 143 144 static void sdhci_disable_card_detection(struct sdhci_host *host) 145 { 146 sdhci_set_card_detection(host, false); 147 } 148 149 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 150 { 151 if (host->bus_on) 152 return; 153 host->bus_on = true; 154 pm_runtime_get_noresume(host->mmc->parent); 155 } 156 157 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 158 { 159 if (!host->bus_on) 160 return; 161 host->bus_on = false; 162 pm_runtime_put_noidle(host->mmc->parent); 163 } 164 165 void sdhci_reset(struct sdhci_host *host, u8 mask) 166 { 167 unsigned long timeout; 168 169 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 170 171 if (mask & SDHCI_RESET_ALL) { 172 host->clock = 0; 173 /* Reset-all turns off SD Bus Power */ 174 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 175 sdhci_runtime_pm_bus_off(host); 176 } 177 178 /* Wait max 100 ms */ 179 timeout = 100; 180 181 /* hw clears the bit when it's done */ 182 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 183 if (timeout == 0) { 184 pr_err("%s: Reset 0x%x never completed.\n", 185 mmc_hostname(host->mmc), (int)mask); 186 sdhci_dumpregs(host); 187 return; 188 } 189 timeout--; 190 mdelay(1); 191 } 192 } 193 EXPORT_SYMBOL_GPL(sdhci_reset); 194 195 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 196 { 197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 198 struct mmc_host *mmc = host->mmc; 199 200 if (!mmc->ops->get_cd(mmc)) 201 return; 202 } 203 204 host->ops->reset(host, mask); 205 206 if (mask & SDHCI_RESET_ALL) { 207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 208 if (host->ops->enable_dma) 209 host->ops->enable_dma(host); 210 } 211 212 /* Resetting the controller clears many */ 213 host->preset_enabled = false; 214 } 215 } 216 217 static void sdhci_init(struct sdhci_host *host, int soft) 218 { 219 struct mmc_host *mmc = host->mmc; 220 221 if (soft) 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 223 else 224 sdhci_do_reset(host, SDHCI_RESET_ALL); 225 226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 230 SDHCI_INT_RESPONSE; 231 232 if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 233 host->tuning_mode == SDHCI_TUNING_MODE_3) 234 host->ier |= SDHCI_INT_RETUNE; 235 236 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 237 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 238 239 if (soft) { 240 /* force clock reconfiguration */ 241 host->clock = 0; 242 mmc->ops->set_ios(mmc, &mmc->ios); 243 } 244 } 245 246 static void sdhci_reinit(struct sdhci_host *host) 247 { 248 sdhci_init(host, 0); 249 sdhci_enable_card_detection(host); 250 } 251 252 static void __sdhci_led_activate(struct sdhci_host *host) 253 { 254 u8 ctrl; 255 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 257 ctrl |= SDHCI_CTRL_LED; 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 259 } 260 261 static void __sdhci_led_deactivate(struct sdhci_host *host) 262 { 263 u8 ctrl; 264 265 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 266 ctrl &= ~SDHCI_CTRL_LED; 267 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 268 } 269 270 #if IS_REACHABLE(CONFIG_LEDS_CLASS) 271 static void sdhci_led_control(struct led_classdev *led, 272 enum led_brightness brightness) 273 { 274 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 275 unsigned long flags; 276 277 spin_lock_irqsave(&host->lock, flags); 278 279 if (host->runtime_suspended) 280 goto out; 281 282 if (brightness == LED_OFF) 283 __sdhci_led_deactivate(host); 284 else 285 __sdhci_led_activate(host); 286 out: 287 spin_unlock_irqrestore(&host->lock, flags); 288 } 289 290 static int sdhci_led_register(struct sdhci_host *host) 291 { 292 struct mmc_host *mmc = host->mmc; 293 294 snprintf(host->led_name, sizeof(host->led_name), 295 "%s::", mmc_hostname(mmc)); 296 297 host->led.name = host->led_name; 298 host->led.brightness = LED_OFF; 299 host->led.default_trigger = mmc_hostname(mmc); 300 host->led.brightness_set = sdhci_led_control; 301 302 return led_classdev_register(mmc_dev(mmc), &host->led); 303 } 304 305 static void sdhci_led_unregister(struct sdhci_host *host) 306 { 307 led_classdev_unregister(&host->led); 308 } 309 310 static inline void sdhci_led_activate(struct sdhci_host *host) 311 { 312 } 313 314 static inline void sdhci_led_deactivate(struct sdhci_host *host) 315 { 316 } 317 318 #else 319 320 static inline int sdhci_led_register(struct sdhci_host *host) 321 { 322 return 0; 323 } 324 325 static inline void sdhci_led_unregister(struct sdhci_host *host) 326 { 327 } 328 329 static inline void sdhci_led_activate(struct sdhci_host *host) 330 { 331 __sdhci_led_activate(host); 332 } 333 334 static inline void sdhci_led_deactivate(struct sdhci_host *host) 335 { 336 __sdhci_led_deactivate(host); 337 } 338 339 #endif 340 341 /*****************************************************************************\ 342 * * 343 * Core functions * 344 * * 345 \*****************************************************************************/ 346 347 static void sdhci_read_block_pio(struct sdhci_host *host) 348 { 349 unsigned long flags; 350 size_t blksize, len, chunk; 351 u32 uninitialized_var(scratch); 352 u8 *buf; 353 354 DBG("PIO reading\n"); 355 356 blksize = host->data->blksz; 357 chunk = 0; 358 359 local_irq_save(flags); 360 361 while (blksize) { 362 BUG_ON(!sg_miter_next(&host->sg_miter)); 363 364 len = min(host->sg_miter.length, blksize); 365 366 blksize -= len; 367 host->sg_miter.consumed = len; 368 369 buf = host->sg_miter.addr; 370 371 while (len) { 372 if (chunk == 0) { 373 scratch = sdhci_readl(host, SDHCI_BUFFER); 374 chunk = 4; 375 } 376 377 *buf = scratch & 0xFF; 378 379 buf++; 380 scratch >>= 8; 381 chunk--; 382 len--; 383 } 384 } 385 386 sg_miter_stop(&host->sg_miter); 387 388 local_irq_restore(flags); 389 } 390 391 static void sdhci_write_block_pio(struct sdhci_host *host) 392 { 393 unsigned long flags; 394 size_t blksize, len, chunk; 395 u32 scratch; 396 u8 *buf; 397 398 DBG("PIO writing\n"); 399 400 blksize = host->data->blksz; 401 chunk = 0; 402 scratch = 0; 403 404 local_irq_save(flags); 405 406 while (blksize) { 407 BUG_ON(!sg_miter_next(&host->sg_miter)); 408 409 len = min(host->sg_miter.length, blksize); 410 411 blksize -= len; 412 host->sg_miter.consumed = len; 413 414 buf = host->sg_miter.addr; 415 416 while (len) { 417 scratch |= (u32)*buf << (chunk * 8); 418 419 buf++; 420 chunk++; 421 len--; 422 423 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 424 sdhci_writel(host, scratch, SDHCI_BUFFER); 425 chunk = 0; 426 scratch = 0; 427 } 428 } 429 } 430 431 sg_miter_stop(&host->sg_miter); 432 433 local_irq_restore(flags); 434 } 435 436 static void sdhci_transfer_pio(struct sdhci_host *host) 437 { 438 u32 mask; 439 440 if (host->blocks == 0) 441 return; 442 443 if (host->data->flags & MMC_DATA_READ) 444 mask = SDHCI_DATA_AVAILABLE; 445 else 446 mask = SDHCI_SPACE_AVAILABLE; 447 448 /* 449 * Some controllers (JMicron JMB38x) mess up the buffer bits 450 * for transfers < 4 bytes. As long as it is just one block, 451 * we can ignore the bits. 452 */ 453 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 454 (host->data->blocks == 1)) 455 mask = ~0; 456 457 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 458 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 459 udelay(100); 460 461 if (host->data->flags & MMC_DATA_READ) 462 sdhci_read_block_pio(host); 463 else 464 sdhci_write_block_pio(host); 465 466 host->blocks--; 467 if (host->blocks == 0) 468 break; 469 } 470 471 DBG("PIO transfer complete.\n"); 472 } 473 474 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 475 struct mmc_data *data, int cookie) 476 { 477 int sg_count; 478 479 /* 480 * If the data buffers are already mapped, return the previous 481 * dma_map_sg() result. 482 */ 483 if (data->host_cookie == COOKIE_PRE_MAPPED) 484 return data->sg_count; 485 486 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 487 data->flags & MMC_DATA_WRITE ? 488 DMA_TO_DEVICE : DMA_FROM_DEVICE); 489 490 if (sg_count == 0) 491 return -ENOSPC; 492 493 data->sg_count = sg_count; 494 data->host_cookie = cookie; 495 496 return sg_count; 497 } 498 499 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 500 { 501 local_irq_save(*flags); 502 return kmap_atomic(sg_page(sg)) + sg->offset; 503 } 504 505 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 506 { 507 kunmap_atomic(buffer); 508 local_irq_restore(*flags); 509 } 510 511 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 512 dma_addr_t addr, int len, unsigned cmd) 513 { 514 struct sdhci_adma2_64_desc *dma_desc = desc; 515 516 /* 32-bit and 64-bit descriptors have these members in same position */ 517 dma_desc->cmd = cpu_to_le16(cmd); 518 dma_desc->len = cpu_to_le16(len); 519 dma_desc->addr_lo = cpu_to_le32((u32)addr); 520 521 if (host->flags & SDHCI_USE_64_BIT_DMA) 522 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 523 } 524 525 static void sdhci_adma_mark_end(void *desc) 526 { 527 struct sdhci_adma2_64_desc *dma_desc = desc; 528 529 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 530 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 531 } 532 533 static void sdhci_adma_table_pre(struct sdhci_host *host, 534 struct mmc_data *data, int sg_count) 535 { 536 struct scatterlist *sg; 537 unsigned long flags; 538 dma_addr_t addr, align_addr; 539 void *desc, *align; 540 char *buffer; 541 int len, offset, i; 542 543 /* 544 * The spec does not specify endianness of descriptor table. 545 * We currently guess that it is LE. 546 */ 547 548 host->sg_count = sg_count; 549 550 desc = host->adma_table; 551 align = host->align_buffer; 552 553 align_addr = host->align_addr; 554 555 for_each_sg(data->sg, sg, host->sg_count, i) { 556 addr = sg_dma_address(sg); 557 len = sg_dma_len(sg); 558 559 /* 560 * The SDHCI specification states that ADMA addresses must 561 * be 32-bit aligned. If they aren't, then we use a bounce 562 * buffer for the (up to three) bytes that screw up the 563 * alignment. 564 */ 565 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 566 SDHCI_ADMA2_MASK; 567 if (offset) { 568 if (data->flags & MMC_DATA_WRITE) { 569 buffer = sdhci_kmap_atomic(sg, &flags); 570 memcpy(align, buffer, offset); 571 sdhci_kunmap_atomic(buffer, &flags); 572 } 573 574 /* tran, valid */ 575 sdhci_adma_write_desc(host, desc, align_addr, offset, 576 ADMA2_TRAN_VALID); 577 578 BUG_ON(offset > 65536); 579 580 align += SDHCI_ADMA2_ALIGN; 581 align_addr += SDHCI_ADMA2_ALIGN; 582 583 desc += host->desc_sz; 584 585 addr += offset; 586 len -= offset; 587 } 588 589 BUG_ON(len > 65536); 590 591 if (len) { 592 /* tran, valid */ 593 sdhci_adma_write_desc(host, desc, addr, len, 594 ADMA2_TRAN_VALID); 595 desc += host->desc_sz; 596 } 597 598 /* 599 * If this triggers then we have a calculation bug 600 * somewhere. :/ 601 */ 602 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 603 } 604 605 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 606 /* Mark the last descriptor as the terminating descriptor */ 607 if (desc != host->adma_table) { 608 desc -= host->desc_sz; 609 sdhci_adma_mark_end(desc); 610 } 611 } else { 612 /* Add a terminating entry - nop, end, valid */ 613 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 614 } 615 } 616 617 static void sdhci_adma_table_post(struct sdhci_host *host, 618 struct mmc_data *data) 619 { 620 struct scatterlist *sg; 621 int i, size; 622 void *align; 623 char *buffer; 624 unsigned long flags; 625 626 if (data->flags & MMC_DATA_READ) { 627 bool has_unaligned = false; 628 629 /* Do a quick scan of the SG list for any unaligned mappings */ 630 for_each_sg(data->sg, sg, host->sg_count, i) 631 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 632 has_unaligned = true; 633 break; 634 } 635 636 if (has_unaligned) { 637 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 638 data->sg_len, DMA_FROM_DEVICE); 639 640 align = host->align_buffer; 641 642 for_each_sg(data->sg, sg, host->sg_count, i) { 643 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 644 size = SDHCI_ADMA2_ALIGN - 645 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 646 647 buffer = sdhci_kmap_atomic(sg, &flags); 648 memcpy(buffer, align, size); 649 sdhci_kunmap_atomic(buffer, &flags); 650 651 align += SDHCI_ADMA2_ALIGN; 652 } 653 } 654 } 655 } 656 } 657 658 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 659 { 660 u8 count; 661 struct mmc_data *data = cmd->data; 662 unsigned target_timeout, current_timeout; 663 664 /* 665 * If the host controller provides us with an incorrect timeout 666 * value, just skip the check and use 0xE. The hardware may take 667 * longer to time out, but that's much better than having a too-short 668 * timeout value. 669 */ 670 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 671 return 0xE; 672 673 /* Unspecified timeout, assume max */ 674 if (!data && !cmd->busy_timeout) 675 return 0xE; 676 677 /* timeout in us */ 678 if (!data) 679 target_timeout = cmd->busy_timeout * 1000; 680 else { 681 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 682 if (host->clock && data->timeout_clks) { 683 unsigned long long val; 684 685 /* 686 * data->timeout_clks is in units of clock cycles. 687 * host->clock is in Hz. target_timeout is in us. 688 * Hence, us = 1000000 * cycles / Hz. Round up. 689 */ 690 val = 1000000ULL * data->timeout_clks; 691 if (do_div(val, host->clock)) 692 target_timeout++; 693 target_timeout += val; 694 } 695 } 696 697 /* 698 * Figure out needed cycles. 699 * We do this in steps in order to fit inside a 32 bit int. 700 * The first step is the minimum timeout, which will have a 701 * minimum resolution of 6 bits: 702 * (1) 2^13*1000 > 2^22, 703 * (2) host->timeout_clk < 2^16 704 * => 705 * (1) / (2) > 2^6 706 */ 707 count = 0; 708 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 709 while (current_timeout < target_timeout) { 710 count++; 711 current_timeout <<= 1; 712 if (count >= 0xF) 713 break; 714 } 715 716 if (count >= 0xF) { 717 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 718 mmc_hostname(host->mmc), count, cmd->opcode); 719 count = 0xE; 720 } 721 722 return count; 723 } 724 725 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 726 { 727 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 728 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 729 730 if (host->flags & SDHCI_REQ_USE_DMA) 731 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 732 else 733 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 734 735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 737 } 738 739 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 740 { 741 u8 count; 742 743 if (host->ops->set_timeout) { 744 host->ops->set_timeout(host, cmd); 745 } else { 746 count = sdhci_calc_timeout(host, cmd); 747 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 748 } 749 } 750 751 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 752 { 753 u8 ctrl; 754 struct mmc_data *data = cmd->data; 755 756 if (sdhci_data_line_cmd(cmd)) 757 sdhci_set_timeout(host, cmd); 758 759 if (!data) 760 return; 761 762 WARN_ON(host->data); 763 764 /* Sanity checks */ 765 BUG_ON(data->blksz * data->blocks > 524288); 766 BUG_ON(data->blksz > host->mmc->max_blk_size); 767 BUG_ON(data->blocks > 65535); 768 769 host->data = data; 770 host->data_early = 0; 771 host->data->bytes_xfered = 0; 772 773 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 774 struct scatterlist *sg; 775 unsigned int length_mask, offset_mask; 776 int i; 777 778 host->flags |= SDHCI_REQ_USE_DMA; 779 780 /* 781 * FIXME: This doesn't account for merging when mapping the 782 * scatterlist. 783 * 784 * The assumption here being that alignment and lengths are 785 * the same after DMA mapping to device address space. 786 */ 787 length_mask = 0; 788 offset_mask = 0; 789 if (host->flags & SDHCI_USE_ADMA) { 790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 791 length_mask = 3; 792 /* 793 * As we use up to 3 byte chunks to work 794 * around alignment problems, we need to 795 * check the offset as well. 796 */ 797 offset_mask = 3; 798 } 799 } else { 800 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 801 length_mask = 3; 802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 803 offset_mask = 3; 804 } 805 806 if (unlikely(length_mask | offset_mask)) { 807 for_each_sg(data->sg, sg, data->sg_len, i) { 808 if (sg->length & length_mask) { 809 DBG("Reverting to PIO because of transfer size (%d)\n", 810 sg->length); 811 host->flags &= ~SDHCI_REQ_USE_DMA; 812 break; 813 } 814 if (sg->offset & offset_mask) { 815 DBG("Reverting to PIO because of bad alignment\n"); 816 host->flags &= ~SDHCI_REQ_USE_DMA; 817 break; 818 } 819 } 820 } 821 } 822 823 if (host->flags & SDHCI_REQ_USE_DMA) { 824 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 825 826 if (sg_cnt <= 0) { 827 /* 828 * This only happens when someone fed 829 * us an invalid request. 830 */ 831 WARN_ON(1); 832 host->flags &= ~SDHCI_REQ_USE_DMA; 833 } else if (host->flags & SDHCI_USE_ADMA) { 834 sdhci_adma_table_pre(host, data, sg_cnt); 835 836 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 837 if (host->flags & SDHCI_USE_64_BIT_DMA) 838 sdhci_writel(host, 839 (u64)host->adma_addr >> 32, 840 SDHCI_ADMA_ADDRESS_HI); 841 } else { 842 WARN_ON(sg_cnt != 1); 843 sdhci_writel(host, sg_dma_address(data->sg), 844 SDHCI_DMA_ADDRESS); 845 } 846 } 847 848 /* 849 * Always adjust the DMA selection as some controllers 850 * (e.g. JMicron) can't do PIO properly when the selection 851 * is ADMA. 852 */ 853 if (host->version >= SDHCI_SPEC_200) { 854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 855 ctrl &= ~SDHCI_CTRL_DMA_MASK; 856 if ((host->flags & SDHCI_REQ_USE_DMA) && 857 (host->flags & SDHCI_USE_ADMA)) { 858 if (host->flags & SDHCI_USE_64_BIT_DMA) 859 ctrl |= SDHCI_CTRL_ADMA64; 860 else 861 ctrl |= SDHCI_CTRL_ADMA32; 862 } else { 863 ctrl |= SDHCI_CTRL_SDMA; 864 } 865 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 866 } 867 868 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 869 int flags; 870 871 flags = SG_MITER_ATOMIC; 872 if (host->data->flags & MMC_DATA_READ) 873 flags |= SG_MITER_TO_SG; 874 else 875 flags |= SG_MITER_FROM_SG; 876 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 877 host->blocks = data->blocks; 878 } 879 880 sdhci_set_transfer_irqs(host); 881 882 /* Set the DMA boundary value and block size */ 883 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 884 data->blksz), SDHCI_BLOCK_SIZE); 885 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 886 } 887 888 static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 889 struct mmc_request *mrq) 890 { 891 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 892 !mrq->cap_cmd_during_tfr; 893 } 894 895 static void sdhci_set_transfer_mode(struct sdhci_host *host, 896 struct mmc_command *cmd) 897 { 898 u16 mode = 0; 899 struct mmc_data *data = cmd->data; 900 901 if (data == NULL) { 902 if (host->quirks2 & 903 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 904 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 905 } else { 906 /* clear Auto CMD settings for no data CMDs */ 907 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 908 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 909 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 910 } 911 return; 912 } 913 914 WARN_ON(!host->data); 915 916 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 917 mode = SDHCI_TRNS_BLK_CNT_EN; 918 919 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 920 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 921 /* 922 * If we are sending CMD23, CMD12 never gets sent 923 * on successful completion (so no Auto-CMD12). 924 */ 925 if (sdhci_auto_cmd12(host, cmd->mrq) && 926 (cmd->opcode != SD_IO_RW_EXTENDED)) 927 mode |= SDHCI_TRNS_AUTO_CMD12; 928 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 929 mode |= SDHCI_TRNS_AUTO_CMD23; 930 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 931 } 932 } 933 934 if (data->flags & MMC_DATA_READ) 935 mode |= SDHCI_TRNS_READ; 936 if (host->flags & SDHCI_REQ_USE_DMA) 937 mode |= SDHCI_TRNS_DMA; 938 939 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 940 } 941 942 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 943 { 944 return (!(host->flags & SDHCI_DEVICE_DEAD) && 945 ((mrq->cmd && mrq->cmd->error) || 946 (mrq->sbc && mrq->sbc->error) || 947 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 948 (mrq->data->stop && mrq->data->stop->error))) || 949 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 950 } 951 952 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 953 { 954 int i; 955 956 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 957 if (host->mrqs_done[i] == mrq) { 958 WARN_ON(1); 959 return; 960 } 961 } 962 963 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 964 if (!host->mrqs_done[i]) { 965 host->mrqs_done[i] = mrq; 966 break; 967 } 968 } 969 970 WARN_ON(i >= SDHCI_MAX_MRQS); 971 972 tasklet_schedule(&host->finish_tasklet); 973 } 974 975 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 976 { 977 if (host->cmd && host->cmd->mrq == mrq) 978 host->cmd = NULL; 979 980 if (host->data_cmd && host->data_cmd->mrq == mrq) 981 host->data_cmd = NULL; 982 983 if (host->data && host->data->mrq == mrq) 984 host->data = NULL; 985 986 if (sdhci_needs_reset(host, mrq)) 987 host->pending_reset = true; 988 989 __sdhci_finish_mrq(host, mrq); 990 } 991 992 static void sdhci_finish_data(struct sdhci_host *host) 993 { 994 struct mmc_command *data_cmd = host->data_cmd; 995 struct mmc_data *data = host->data; 996 997 host->data = NULL; 998 host->data_cmd = NULL; 999 1000 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1001 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1002 sdhci_adma_table_post(host, data); 1003 1004 /* 1005 * The specification states that the block count register must 1006 * be updated, but it does not specify at what point in the 1007 * data flow. That makes the register entirely useless to read 1008 * back so we have to assume that nothing made it to the card 1009 * in the event of an error. 1010 */ 1011 if (data->error) 1012 data->bytes_xfered = 0; 1013 else 1014 data->bytes_xfered = data->blksz * data->blocks; 1015 1016 /* 1017 * Need to send CMD12 if - 1018 * a) open-ended multiblock transfer (no CMD23) 1019 * b) error in multiblock transfer 1020 */ 1021 if (data->stop && 1022 (data->error || 1023 !data->mrq->sbc)) { 1024 1025 /* 1026 * The controller needs a reset of internal state machines 1027 * upon error conditions. 1028 */ 1029 if (data->error) { 1030 if (!host->cmd || host->cmd == data_cmd) 1031 sdhci_do_reset(host, SDHCI_RESET_CMD); 1032 sdhci_do_reset(host, SDHCI_RESET_DATA); 1033 } 1034 1035 /* 1036 * 'cap_cmd_during_tfr' request must not use the command line 1037 * after mmc_command_done() has been called. It is upper layer's 1038 * responsibility to send the stop command if required. 1039 */ 1040 if (data->mrq->cap_cmd_during_tfr) { 1041 sdhci_finish_mrq(host, data->mrq); 1042 } else { 1043 /* Avoid triggering warning in sdhci_send_command() */ 1044 host->cmd = NULL; 1045 sdhci_send_command(host, data->stop); 1046 } 1047 } else { 1048 sdhci_finish_mrq(host, data->mrq); 1049 } 1050 } 1051 1052 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 1053 unsigned long timeout) 1054 { 1055 if (sdhci_data_line_cmd(mrq->cmd)) 1056 mod_timer(&host->data_timer, timeout); 1057 else 1058 mod_timer(&host->timer, timeout); 1059 } 1060 1061 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 1062 { 1063 if (sdhci_data_line_cmd(mrq->cmd)) 1064 del_timer(&host->data_timer); 1065 else 1066 del_timer(&host->timer); 1067 } 1068 1069 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1070 { 1071 int flags; 1072 u32 mask; 1073 unsigned long timeout; 1074 1075 WARN_ON(host->cmd); 1076 1077 /* Initially, a command has no error */ 1078 cmd->error = 0; 1079 1080 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1081 cmd->opcode == MMC_STOP_TRANSMISSION) 1082 cmd->flags |= MMC_RSP_BUSY; 1083 1084 /* Wait max 10 ms */ 1085 timeout = 10; 1086 1087 mask = SDHCI_CMD_INHIBIT; 1088 if (sdhci_data_line_cmd(cmd)) 1089 mask |= SDHCI_DATA_INHIBIT; 1090 1091 /* We shouldn't wait for data inihibit for stop commands, even 1092 though they might use busy signaling */ 1093 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 1094 mask &= ~SDHCI_DATA_INHIBIT; 1095 1096 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1097 if (timeout == 0) { 1098 pr_err("%s: Controller never released inhibit bit(s).\n", 1099 mmc_hostname(host->mmc)); 1100 sdhci_dumpregs(host); 1101 cmd->error = -EIO; 1102 sdhci_finish_mrq(host, cmd->mrq); 1103 return; 1104 } 1105 timeout--; 1106 mdelay(1); 1107 } 1108 1109 timeout = jiffies; 1110 if (!cmd->data && cmd->busy_timeout > 9000) 1111 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1112 else 1113 timeout += 10 * HZ; 1114 sdhci_mod_timer(host, cmd->mrq, timeout); 1115 1116 host->cmd = cmd; 1117 if (sdhci_data_line_cmd(cmd)) { 1118 WARN_ON(host->data_cmd); 1119 host->data_cmd = cmd; 1120 } 1121 1122 sdhci_prepare_data(host, cmd); 1123 1124 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1125 1126 sdhci_set_transfer_mode(host, cmd); 1127 1128 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1129 pr_err("%s: Unsupported response type!\n", 1130 mmc_hostname(host->mmc)); 1131 cmd->error = -EINVAL; 1132 sdhci_finish_mrq(host, cmd->mrq); 1133 return; 1134 } 1135 1136 if (!(cmd->flags & MMC_RSP_PRESENT)) 1137 flags = SDHCI_CMD_RESP_NONE; 1138 else if (cmd->flags & MMC_RSP_136) 1139 flags = SDHCI_CMD_RESP_LONG; 1140 else if (cmd->flags & MMC_RSP_BUSY) 1141 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1142 else 1143 flags = SDHCI_CMD_RESP_SHORT; 1144 1145 if (cmd->flags & MMC_RSP_CRC) 1146 flags |= SDHCI_CMD_CRC; 1147 if (cmd->flags & MMC_RSP_OPCODE) 1148 flags |= SDHCI_CMD_INDEX; 1149 1150 /* CMD19 is special in that the Data Present Select should be set */ 1151 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1152 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1153 flags |= SDHCI_CMD_DATA; 1154 1155 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1156 } 1157 EXPORT_SYMBOL_GPL(sdhci_send_command); 1158 1159 static void sdhci_finish_command(struct sdhci_host *host) 1160 { 1161 struct mmc_command *cmd = host->cmd; 1162 int i; 1163 1164 host->cmd = NULL; 1165 1166 if (cmd->flags & MMC_RSP_PRESENT) { 1167 if (cmd->flags & MMC_RSP_136) { 1168 /* CRC is stripped so we need to do some shifting. */ 1169 for (i = 0;i < 4;i++) { 1170 cmd->resp[i] = sdhci_readl(host, 1171 SDHCI_RESPONSE + (3-i)*4) << 8; 1172 if (i != 3) 1173 cmd->resp[i] |= 1174 sdhci_readb(host, 1175 SDHCI_RESPONSE + (3-i)*4-1); 1176 } 1177 } else { 1178 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1179 } 1180 } 1181 1182 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 1183 mmc_command_done(host->mmc, cmd->mrq); 1184 1185 /* 1186 * The host can send and interrupt when the busy state has 1187 * ended, allowing us to wait without wasting CPU cycles. 1188 * The busy signal uses DAT0 so this is similar to waiting 1189 * for data to complete. 1190 * 1191 * Note: The 1.0 specification is a bit ambiguous about this 1192 * feature so there might be some problems with older 1193 * controllers. 1194 */ 1195 if (cmd->flags & MMC_RSP_BUSY) { 1196 if (cmd->data) { 1197 DBG("Cannot wait for busy signal when also doing a data transfer"); 1198 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1199 cmd == host->data_cmd) { 1200 /* Command complete before busy is ended */ 1201 return; 1202 } 1203 } 1204 1205 /* Finished CMD23, now send actual command. */ 1206 if (cmd == cmd->mrq->sbc) { 1207 sdhci_send_command(host, cmd->mrq->cmd); 1208 } else { 1209 1210 /* Processed actual command. */ 1211 if (host->data && host->data_early) 1212 sdhci_finish_data(host); 1213 1214 if (!cmd->data) 1215 sdhci_finish_mrq(host, cmd->mrq); 1216 } 1217 } 1218 1219 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1220 { 1221 u16 preset = 0; 1222 1223 switch (host->timing) { 1224 case MMC_TIMING_UHS_SDR12: 1225 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1226 break; 1227 case MMC_TIMING_UHS_SDR25: 1228 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1229 break; 1230 case MMC_TIMING_UHS_SDR50: 1231 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1232 break; 1233 case MMC_TIMING_UHS_SDR104: 1234 case MMC_TIMING_MMC_HS200: 1235 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1236 break; 1237 case MMC_TIMING_UHS_DDR50: 1238 case MMC_TIMING_MMC_DDR52: 1239 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1240 break; 1241 case MMC_TIMING_MMC_HS400: 1242 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1243 break; 1244 default: 1245 pr_warn("%s: Invalid UHS-I mode selected\n", 1246 mmc_hostname(host->mmc)); 1247 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1248 break; 1249 } 1250 return preset; 1251 } 1252 1253 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1254 unsigned int *actual_clock) 1255 { 1256 int div = 0; /* Initialized for compiler warning */ 1257 int real_div = div, clk_mul = 1; 1258 u16 clk = 0; 1259 bool switch_base_clk = false; 1260 1261 if (host->version >= SDHCI_SPEC_300) { 1262 if (host->preset_enabled) { 1263 u16 pre_val; 1264 1265 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1266 pre_val = sdhci_get_preset_value(host); 1267 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1268 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1269 if (host->clk_mul && 1270 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1271 clk = SDHCI_PROG_CLOCK_MODE; 1272 real_div = div + 1; 1273 clk_mul = host->clk_mul; 1274 } else { 1275 real_div = max_t(int, 1, div << 1); 1276 } 1277 goto clock_set; 1278 } 1279 1280 /* 1281 * Check if the Host Controller supports Programmable Clock 1282 * Mode. 1283 */ 1284 if (host->clk_mul) { 1285 for (div = 1; div <= 1024; div++) { 1286 if ((host->max_clk * host->clk_mul / div) 1287 <= clock) 1288 break; 1289 } 1290 if ((host->max_clk * host->clk_mul / div) <= clock) { 1291 /* 1292 * Set Programmable Clock Mode in the Clock 1293 * Control register. 1294 */ 1295 clk = SDHCI_PROG_CLOCK_MODE; 1296 real_div = div; 1297 clk_mul = host->clk_mul; 1298 div--; 1299 } else { 1300 /* 1301 * Divisor can be too small to reach clock 1302 * speed requirement. Then use the base clock. 1303 */ 1304 switch_base_clk = true; 1305 } 1306 } 1307 1308 if (!host->clk_mul || switch_base_clk) { 1309 /* Version 3.00 divisors must be a multiple of 2. */ 1310 if (host->max_clk <= clock) 1311 div = 1; 1312 else { 1313 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1314 div += 2) { 1315 if ((host->max_clk / div) <= clock) 1316 break; 1317 } 1318 } 1319 real_div = div; 1320 div >>= 1; 1321 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1322 && !div && host->max_clk <= 25000000) 1323 div = 1; 1324 } 1325 } else { 1326 /* Version 2.00 divisors must be a power of 2. */ 1327 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1328 if ((host->max_clk / div) <= clock) 1329 break; 1330 } 1331 real_div = div; 1332 div >>= 1; 1333 } 1334 1335 clock_set: 1336 if (real_div) 1337 *actual_clock = (host->max_clk * clk_mul) / real_div; 1338 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1339 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1340 << SDHCI_DIVIDER_HI_SHIFT; 1341 1342 return clk; 1343 } 1344 EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1345 1346 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1347 { 1348 u16 clk; 1349 unsigned long timeout; 1350 1351 host->mmc->actual_clock = 0; 1352 1353 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1354 1355 if (clock == 0) 1356 return; 1357 1358 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1359 1360 clk |= SDHCI_CLOCK_INT_EN; 1361 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1362 1363 /* Wait max 20 ms */ 1364 timeout = 20; 1365 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1366 & SDHCI_CLOCK_INT_STABLE)) { 1367 if (timeout == 0) { 1368 pr_err("%s: Internal clock never stabilised.\n", 1369 mmc_hostname(host->mmc)); 1370 sdhci_dumpregs(host); 1371 return; 1372 } 1373 timeout--; 1374 mdelay(1); 1375 } 1376 1377 clk |= SDHCI_CLOCK_CARD_EN; 1378 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1379 } 1380 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1381 1382 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 1383 unsigned short vdd) 1384 { 1385 struct mmc_host *mmc = host->mmc; 1386 1387 spin_unlock_irq(&host->lock); 1388 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1389 spin_lock_irq(&host->lock); 1390 1391 if (mode != MMC_POWER_OFF) 1392 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1393 else 1394 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1395 } 1396 1397 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 1398 unsigned short vdd) 1399 { 1400 u8 pwr = 0; 1401 1402 if (mode != MMC_POWER_OFF) { 1403 switch (1 << vdd) { 1404 case MMC_VDD_165_195: 1405 pwr = SDHCI_POWER_180; 1406 break; 1407 case MMC_VDD_29_30: 1408 case MMC_VDD_30_31: 1409 pwr = SDHCI_POWER_300; 1410 break; 1411 case MMC_VDD_32_33: 1412 case MMC_VDD_33_34: 1413 pwr = SDHCI_POWER_330; 1414 break; 1415 default: 1416 WARN(1, "%s: Invalid vdd %#x\n", 1417 mmc_hostname(host->mmc), vdd); 1418 break; 1419 } 1420 } 1421 1422 if (host->pwr == pwr) 1423 return; 1424 1425 host->pwr = pwr; 1426 1427 if (pwr == 0) { 1428 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1429 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1430 sdhci_runtime_pm_bus_off(host); 1431 } else { 1432 /* 1433 * Spec says that we should clear the power reg before setting 1434 * a new value. Some controllers don't seem to like this though. 1435 */ 1436 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1437 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1438 1439 /* 1440 * At least the Marvell CaFe chip gets confused if we set the 1441 * voltage and set turn on power at the same time, so set the 1442 * voltage first. 1443 */ 1444 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1445 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1446 1447 pwr |= SDHCI_POWER_ON; 1448 1449 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1450 1451 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1452 sdhci_runtime_pm_bus_on(host); 1453 1454 /* 1455 * Some controllers need an extra 10ms delay of 10ms before 1456 * they can apply clock after applying power 1457 */ 1458 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1459 mdelay(10); 1460 } 1461 } 1462 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 1463 1464 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1465 unsigned short vdd) 1466 { 1467 if (IS_ERR(host->mmc->supply.vmmc)) 1468 sdhci_set_power_noreg(host, mode, vdd); 1469 else 1470 sdhci_set_power_reg(host, mode, vdd); 1471 } 1472 EXPORT_SYMBOL_GPL(sdhci_set_power); 1473 1474 /*****************************************************************************\ 1475 * * 1476 * MMC callbacks * 1477 * * 1478 \*****************************************************************************/ 1479 1480 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1481 { 1482 struct sdhci_host *host; 1483 int present; 1484 unsigned long flags; 1485 1486 host = mmc_priv(mmc); 1487 1488 /* Firstly check card presence */ 1489 present = mmc->ops->get_cd(mmc); 1490 1491 spin_lock_irqsave(&host->lock, flags); 1492 1493 sdhci_led_activate(host); 1494 1495 /* 1496 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1497 * requests if Auto-CMD12 is enabled. 1498 */ 1499 if (sdhci_auto_cmd12(host, mrq)) { 1500 if (mrq->stop) { 1501 mrq->data->stop = NULL; 1502 mrq->stop = NULL; 1503 } 1504 } 1505 1506 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1507 mrq->cmd->error = -ENOMEDIUM; 1508 sdhci_finish_mrq(host, mrq); 1509 } else { 1510 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1511 sdhci_send_command(host, mrq->sbc); 1512 else 1513 sdhci_send_command(host, mrq->cmd); 1514 } 1515 1516 mmiowb(); 1517 spin_unlock_irqrestore(&host->lock, flags); 1518 } 1519 1520 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1521 { 1522 u8 ctrl; 1523 1524 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1525 if (width == MMC_BUS_WIDTH_8) { 1526 ctrl &= ~SDHCI_CTRL_4BITBUS; 1527 if (host->version >= SDHCI_SPEC_300) 1528 ctrl |= SDHCI_CTRL_8BITBUS; 1529 } else { 1530 if (host->version >= SDHCI_SPEC_300) 1531 ctrl &= ~SDHCI_CTRL_8BITBUS; 1532 if (width == MMC_BUS_WIDTH_4) 1533 ctrl |= SDHCI_CTRL_4BITBUS; 1534 else 1535 ctrl &= ~SDHCI_CTRL_4BITBUS; 1536 } 1537 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1538 } 1539 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1540 1541 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1542 { 1543 u16 ctrl_2; 1544 1545 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1546 /* Select Bus Speed Mode for host */ 1547 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1548 if ((timing == MMC_TIMING_MMC_HS200) || 1549 (timing == MMC_TIMING_UHS_SDR104)) 1550 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1551 else if (timing == MMC_TIMING_UHS_SDR12) 1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1553 else if (timing == MMC_TIMING_UHS_SDR25) 1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1555 else if (timing == MMC_TIMING_UHS_SDR50) 1556 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1557 else if ((timing == MMC_TIMING_UHS_DDR50) || 1558 (timing == MMC_TIMING_MMC_DDR52)) 1559 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1560 else if (timing == MMC_TIMING_MMC_HS400) 1561 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1562 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1563 } 1564 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1565 1566 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1567 { 1568 struct sdhci_host *host = mmc_priv(mmc); 1569 unsigned long flags; 1570 u8 ctrl; 1571 1572 spin_lock_irqsave(&host->lock, flags); 1573 1574 if (host->flags & SDHCI_DEVICE_DEAD) { 1575 spin_unlock_irqrestore(&host->lock, flags); 1576 if (!IS_ERR(mmc->supply.vmmc) && 1577 ios->power_mode == MMC_POWER_OFF) 1578 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1579 return; 1580 } 1581 1582 /* 1583 * Reset the chip on each power off. 1584 * Should clear out any weird states. 1585 */ 1586 if (ios->power_mode == MMC_POWER_OFF) { 1587 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1588 sdhci_reinit(host); 1589 } 1590 1591 if (host->version >= SDHCI_SPEC_300 && 1592 (ios->power_mode == MMC_POWER_UP) && 1593 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1594 sdhci_enable_preset_value(host, false); 1595 1596 if (!ios->clock || ios->clock != host->clock) { 1597 host->ops->set_clock(host, ios->clock); 1598 host->clock = ios->clock; 1599 1600 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1601 host->clock) { 1602 host->timeout_clk = host->mmc->actual_clock ? 1603 host->mmc->actual_clock / 1000 : 1604 host->clock / 1000; 1605 host->mmc->max_busy_timeout = 1606 host->ops->get_max_timeout_count ? 1607 host->ops->get_max_timeout_count(host) : 1608 1 << 27; 1609 host->mmc->max_busy_timeout /= host->timeout_clk; 1610 } 1611 } 1612 1613 if (host->ops->set_power) 1614 host->ops->set_power(host, ios->power_mode, ios->vdd); 1615 else 1616 sdhci_set_power(host, ios->power_mode, ios->vdd); 1617 1618 if (host->ops->platform_send_init_74_clocks) 1619 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1620 1621 host->ops->set_bus_width(host, ios->bus_width); 1622 1623 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1624 1625 if ((ios->timing == MMC_TIMING_SD_HS || 1626 ios->timing == MMC_TIMING_MMC_HS) 1627 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1628 ctrl |= SDHCI_CTRL_HISPD; 1629 else 1630 ctrl &= ~SDHCI_CTRL_HISPD; 1631 1632 if (host->version >= SDHCI_SPEC_300) { 1633 u16 clk, ctrl_2; 1634 1635 /* In case of UHS-I modes, set High Speed Enable */ 1636 if ((ios->timing == MMC_TIMING_MMC_HS400) || 1637 (ios->timing == MMC_TIMING_MMC_HS200) || 1638 (ios->timing == MMC_TIMING_MMC_DDR52) || 1639 (ios->timing == MMC_TIMING_UHS_SDR50) || 1640 (ios->timing == MMC_TIMING_UHS_SDR104) || 1641 (ios->timing == MMC_TIMING_UHS_DDR50) || 1642 (ios->timing == MMC_TIMING_UHS_SDR25)) 1643 ctrl |= SDHCI_CTRL_HISPD; 1644 1645 if (!host->preset_enabled) { 1646 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1647 /* 1648 * We only need to set Driver Strength if the 1649 * preset value enable is not set. 1650 */ 1651 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1652 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1653 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1654 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1655 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1656 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1657 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1658 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1659 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1661 else { 1662 pr_warn("%s: invalid driver type, default to driver type B\n", 1663 mmc_hostname(mmc)); 1664 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1665 } 1666 1667 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1668 } else { 1669 /* 1670 * According to SDHC Spec v3.00, if the Preset Value 1671 * Enable in the Host Control 2 register is set, we 1672 * need to reset SD Clock Enable before changing High 1673 * Speed Enable to avoid generating clock gliches. 1674 */ 1675 1676 /* Reset SD Clock Enable */ 1677 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1678 clk &= ~SDHCI_CLOCK_CARD_EN; 1679 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1680 1681 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1682 1683 /* Re-enable SD Clock */ 1684 host->ops->set_clock(host, host->clock); 1685 } 1686 1687 /* Reset SD Clock Enable */ 1688 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1689 clk &= ~SDHCI_CLOCK_CARD_EN; 1690 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1691 1692 host->ops->set_uhs_signaling(host, ios->timing); 1693 host->timing = ios->timing; 1694 1695 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1696 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1697 (ios->timing == MMC_TIMING_UHS_SDR25) || 1698 (ios->timing == MMC_TIMING_UHS_SDR50) || 1699 (ios->timing == MMC_TIMING_UHS_SDR104) || 1700 (ios->timing == MMC_TIMING_UHS_DDR50) || 1701 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1702 u16 preset; 1703 1704 sdhci_enable_preset_value(host, true); 1705 preset = sdhci_get_preset_value(host); 1706 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1707 >> SDHCI_PRESET_DRV_SHIFT; 1708 } 1709 1710 /* Re-enable SD Clock */ 1711 host->ops->set_clock(host, host->clock); 1712 } else 1713 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1714 1715 /* 1716 * Some (ENE) controllers go apeshit on some ios operation, 1717 * signalling timeout and CRC errors even on CMD0. Resetting 1718 * it on each ios seems to solve the problem. 1719 */ 1720 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1721 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1722 1723 mmiowb(); 1724 spin_unlock_irqrestore(&host->lock, flags); 1725 } 1726 1727 static int sdhci_get_cd(struct mmc_host *mmc) 1728 { 1729 struct sdhci_host *host = mmc_priv(mmc); 1730 int gpio_cd = mmc_gpio_get_cd(mmc); 1731 1732 if (host->flags & SDHCI_DEVICE_DEAD) 1733 return 0; 1734 1735 /* If nonremovable, assume that the card is always present. */ 1736 if (!mmc_card_is_removable(host->mmc)) 1737 return 1; 1738 1739 /* 1740 * Try slot gpio detect, if defined it take precedence 1741 * over build in controller functionality 1742 */ 1743 if (gpio_cd >= 0) 1744 return !!gpio_cd; 1745 1746 /* If polling, assume that the card is always present. */ 1747 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1748 return 1; 1749 1750 /* Host native card detect */ 1751 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1752 } 1753 1754 static int sdhci_check_ro(struct sdhci_host *host) 1755 { 1756 unsigned long flags; 1757 int is_readonly; 1758 1759 spin_lock_irqsave(&host->lock, flags); 1760 1761 if (host->flags & SDHCI_DEVICE_DEAD) 1762 is_readonly = 0; 1763 else if (host->ops->get_ro) 1764 is_readonly = host->ops->get_ro(host); 1765 else 1766 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1767 & SDHCI_WRITE_PROTECT); 1768 1769 spin_unlock_irqrestore(&host->lock, flags); 1770 1771 /* This quirk needs to be replaced by a callback-function later */ 1772 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1773 !is_readonly : is_readonly; 1774 } 1775 1776 #define SAMPLE_COUNT 5 1777 1778 static int sdhci_get_ro(struct mmc_host *mmc) 1779 { 1780 struct sdhci_host *host = mmc_priv(mmc); 1781 int i, ro_count; 1782 1783 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1784 return sdhci_check_ro(host); 1785 1786 ro_count = 0; 1787 for (i = 0; i < SAMPLE_COUNT; i++) { 1788 if (sdhci_check_ro(host)) { 1789 if (++ro_count > SAMPLE_COUNT / 2) 1790 return 1; 1791 } 1792 msleep(30); 1793 } 1794 return 0; 1795 } 1796 1797 static void sdhci_hw_reset(struct mmc_host *mmc) 1798 { 1799 struct sdhci_host *host = mmc_priv(mmc); 1800 1801 if (host->ops && host->ops->hw_reset) 1802 host->ops->hw_reset(host); 1803 } 1804 1805 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1806 { 1807 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1808 if (enable) 1809 host->ier |= SDHCI_INT_CARD_INT; 1810 else 1811 host->ier &= ~SDHCI_INT_CARD_INT; 1812 1813 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1814 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1815 mmiowb(); 1816 } 1817 } 1818 1819 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1820 { 1821 struct sdhci_host *host = mmc_priv(mmc); 1822 unsigned long flags; 1823 1824 spin_lock_irqsave(&host->lock, flags); 1825 if (enable) 1826 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1827 else 1828 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1829 1830 sdhci_enable_sdio_irq_nolock(host, enable); 1831 spin_unlock_irqrestore(&host->lock, flags); 1832 } 1833 1834 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1835 struct mmc_ios *ios) 1836 { 1837 struct sdhci_host *host = mmc_priv(mmc); 1838 u16 ctrl; 1839 int ret; 1840 1841 /* 1842 * Signal Voltage Switching is only applicable for Host Controllers 1843 * v3.00 and above. 1844 */ 1845 if (host->version < SDHCI_SPEC_300) 1846 return 0; 1847 1848 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1849 1850 switch (ios->signal_voltage) { 1851 case MMC_SIGNAL_VOLTAGE_330: 1852 if (!(host->flags & SDHCI_SIGNALING_330)) 1853 return -EINVAL; 1854 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1855 ctrl &= ~SDHCI_CTRL_VDD_180; 1856 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1857 1858 if (!IS_ERR(mmc->supply.vqmmc)) { 1859 ret = mmc_regulator_set_vqmmc(mmc, ios); 1860 if (ret) { 1861 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1862 mmc_hostname(mmc)); 1863 return -EIO; 1864 } 1865 } 1866 /* Wait for 5ms */ 1867 usleep_range(5000, 5500); 1868 1869 /* 3.3V regulator output should be stable within 5 ms */ 1870 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1871 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1872 return 0; 1873 1874 pr_warn("%s: 3.3V regulator output did not became stable\n", 1875 mmc_hostname(mmc)); 1876 1877 return -EAGAIN; 1878 case MMC_SIGNAL_VOLTAGE_180: 1879 if (!(host->flags & SDHCI_SIGNALING_180)) 1880 return -EINVAL; 1881 if (!IS_ERR(mmc->supply.vqmmc)) { 1882 ret = mmc_regulator_set_vqmmc(mmc, ios); 1883 if (ret) { 1884 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1885 mmc_hostname(mmc)); 1886 return -EIO; 1887 } 1888 } 1889 1890 /* 1891 * Enable 1.8V Signal Enable in the Host Control2 1892 * register 1893 */ 1894 ctrl |= SDHCI_CTRL_VDD_180; 1895 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1896 1897 /* Some controller need to do more when switching */ 1898 if (host->ops->voltage_switch) 1899 host->ops->voltage_switch(host); 1900 1901 /* 1.8V regulator output should be stable within 5 ms */ 1902 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1903 if (ctrl & SDHCI_CTRL_VDD_180) 1904 return 0; 1905 1906 pr_warn("%s: 1.8V regulator output did not became stable\n", 1907 mmc_hostname(mmc)); 1908 1909 return -EAGAIN; 1910 case MMC_SIGNAL_VOLTAGE_120: 1911 if (!(host->flags & SDHCI_SIGNALING_120)) 1912 return -EINVAL; 1913 if (!IS_ERR(mmc->supply.vqmmc)) { 1914 ret = mmc_regulator_set_vqmmc(mmc, ios); 1915 if (ret) { 1916 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1917 mmc_hostname(mmc)); 1918 return -EIO; 1919 } 1920 } 1921 return 0; 1922 default: 1923 /* No signal voltage switch required */ 1924 return 0; 1925 } 1926 } 1927 1928 static int sdhci_card_busy(struct mmc_host *mmc) 1929 { 1930 struct sdhci_host *host = mmc_priv(mmc); 1931 u32 present_state; 1932 1933 /* Check whether DAT[0] is 0 */ 1934 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1935 1936 return !(present_state & SDHCI_DATA_0_LVL_MASK); 1937 } 1938 1939 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1940 { 1941 struct sdhci_host *host = mmc_priv(mmc); 1942 unsigned long flags; 1943 1944 spin_lock_irqsave(&host->lock, flags); 1945 host->flags |= SDHCI_HS400_TUNING; 1946 spin_unlock_irqrestore(&host->lock, flags); 1947 1948 return 0; 1949 } 1950 1951 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1952 { 1953 struct sdhci_host *host = mmc_priv(mmc); 1954 u16 ctrl; 1955 int tuning_loop_counter = MAX_TUNING_LOOP; 1956 int err = 0; 1957 unsigned long flags; 1958 unsigned int tuning_count = 0; 1959 bool hs400_tuning; 1960 1961 spin_lock_irqsave(&host->lock, flags); 1962 1963 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 1964 host->flags &= ~SDHCI_HS400_TUNING; 1965 1966 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1967 tuning_count = host->tuning_count; 1968 1969 /* 1970 * The Host Controller needs tuning in case of SDR104 and DDR50 1971 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 1972 * the Capabilities register. 1973 * If the Host Controller supports the HS200 mode then the 1974 * tuning function has to be executed. 1975 */ 1976 switch (host->timing) { 1977 /* HS400 tuning is done in HS200 mode */ 1978 case MMC_TIMING_MMC_HS400: 1979 err = -EINVAL; 1980 goto out_unlock; 1981 1982 case MMC_TIMING_MMC_HS200: 1983 /* 1984 * Periodic re-tuning for HS400 is not expected to be needed, so 1985 * disable it here. 1986 */ 1987 if (hs400_tuning) 1988 tuning_count = 0; 1989 break; 1990 1991 case MMC_TIMING_UHS_SDR104: 1992 case MMC_TIMING_UHS_DDR50: 1993 break; 1994 1995 case MMC_TIMING_UHS_SDR50: 1996 if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 1997 break; 1998 /* FALLTHROUGH */ 1999 2000 default: 2001 goto out_unlock; 2002 } 2003 2004 if (host->ops->platform_execute_tuning) { 2005 spin_unlock_irqrestore(&host->lock, flags); 2006 err = host->ops->platform_execute_tuning(host, opcode); 2007 return err; 2008 } 2009 2010 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2011 ctrl |= SDHCI_CTRL_EXEC_TUNING; 2012 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 2013 ctrl |= SDHCI_CTRL_TUNED_CLK; 2014 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2015 2016 /* 2017 * As per the Host Controller spec v3.00, tuning command 2018 * generates Buffer Read Ready interrupt, so enable that. 2019 * 2020 * Note: The spec clearly says that when tuning sequence 2021 * is being performed, the controller does not generate 2022 * interrupts other than Buffer Read Ready interrupt. But 2023 * to make sure we don't hit a controller bug, we _only_ 2024 * enable Buffer Read Ready interrupt here. 2025 */ 2026 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 2027 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 2028 2029 /* 2030 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 2031 * of loops reaches 40 times. 2032 */ 2033 do { 2034 struct mmc_command cmd = {0}; 2035 struct mmc_request mrq = {NULL}; 2036 2037 cmd.opcode = opcode; 2038 cmd.arg = 0; 2039 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2040 cmd.retries = 0; 2041 cmd.data = NULL; 2042 cmd.mrq = &mrq; 2043 cmd.error = 0; 2044 2045 if (tuning_loop_counter-- == 0) 2046 break; 2047 2048 mrq.cmd = &cmd; 2049 2050 /* 2051 * In response to CMD19, the card sends 64 bytes of tuning 2052 * block to the Host Controller. So we set the block size 2053 * to 64 here. 2054 */ 2055 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 2056 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2057 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 2058 SDHCI_BLOCK_SIZE); 2059 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 2060 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2061 SDHCI_BLOCK_SIZE); 2062 } else { 2063 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 2064 SDHCI_BLOCK_SIZE); 2065 } 2066 2067 /* 2068 * The tuning block is sent by the card to the host controller. 2069 * So we set the TRNS_READ bit in the Transfer Mode register. 2070 * This also takes care of setting DMA Enable and Multi Block 2071 * Select in the same register to 0. 2072 */ 2073 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2074 2075 sdhci_send_command(host, &cmd); 2076 2077 host->cmd = NULL; 2078 sdhci_del_timer(host, &mrq); 2079 2080 spin_unlock_irqrestore(&host->lock, flags); 2081 /* Wait for Buffer Read Ready interrupt */ 2082 wait_event_timeout(host->buf_ready_int, 2083 (host->tuning_done == 1), 2084 msecs_to_jiffies(50)); 2085 spin_lock_irqsave(&host->lock, flags); 2086 2087 if (!host->tuning_done) { 2088 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); 2089 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2090 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2091 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2092 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2093 2094 err = -EIO; 2095 goto out; 2096 } 2097 2098 host->tuning_done = 0; 2099 2100 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2101 2102 /* eMMC spec does not require a delay between tuning cycles */ 2103 if (opcode == MMC_SEND_TUNING_BLOCK) 2104 mdelay(1); 2105 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 2106 2107 /* 2108 * The Host Driver has exhausted the maximum number of loops allowed, 2109 * so use fixed sampling frequency. 2110 */ 2111 if (tuning_loop_counter < 0) { 2112 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2113 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2114 } 2115 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 2116 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); 2117 err = -EIO; 2118 } 2119 2120 out: 2121 if (tuning_count) { 2122 /* 2123 * In case tuning fails, host controllers which support 2124 * re-tuning can try tuning again at a later time, when the 2125 * re-tuning timer expires. So for these controllers, we 2126 * return 0. Since there might be other controllers who do not 2127 * have this capability, we return error for them. 2128 */ 2129 err = 0; 2130 } 2131 2132 host->mmc->retune_period = err ? 0 : tuning_count; 2133 2134 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2135 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2136 out_unlock: 2137 spin_unlock_irqrestore(&host->lock, flags); 2138 return err; 2139 } 2140 2141 static int sdhci_select_drive_strength(struct mmc_card *card, 2142 unsigned int max_dtr, int host_drv, 2143 int card_drv, int *drv_type) 2144 { 2145 struct sdhci_host *host = mmc_priv(card->host); 2146 2147 if (!host->ops->select_drive_strength) 2148 return 0; 2149 2150 return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2151 card_drv, drv_type); 2152 } 2153 2154 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2155 { 2156 /* Host Controller v3.00 defines preset value registers */ 2157 if (host->version < SDHCI_SPEC_300) 2158 return; 2159 2160 /* 2161 * We only enable or disable Preset Value if they are not already 2162 * enabled or disabled respectively. Otherwise, we bail out. 2163 */ 2164 if (host->preset_enabled != enable) { 2165 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2166 2167 if (enable) 2168 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2169 else 2170 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2171 2172 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2173 2174 if (enable) 2175 host->flags |= SDHCI_PV_ENABLED; 2176 else 2177 host->flags &= ~SDHCI_PV_ENABLED; 2178 2179 host->preset_enabled = enable; 2180 } 2181 } 2182 2183 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2184 int err) 2185 { 2186 struct sdhci_host *host = mmc_priv(mmc); 2187 struct mmc_data *data = mrq->data; 2188 2189 if (data->host_cookie != COOKIE_UNMAPPED) 2190 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2191 data->flags & MMC_DATA_WRITE ? 2192 DMA_TO_DEVICE : DMA_FROM_DEVICE); 2193 2194 data->host_cookie = COOKIE_UNMAPPED; 2195 } 2196 2197 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 2198 bool is_first_req) 2199 { 2200 struct sdhci_host *host = mmc_priv(mmc); 2201 2202 mrq->data->host_cookie = COOKIE_UNMAPPED; 2203 2204 if (host->flags & SDHCI_REQ_USE_DMA) 2205 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2206 } 2207 2208 static inline bool sdhci_has_requests(struct sdhci_host *host) 2209 { 2210 return host->cmd || host->data_cmd; 2211 } 2212 2213 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 2214 { 2215 if (host->data_cmd) { 2216 host->data_cmd->error = err; 2217 sdhci_finish_mrq(host, host->data_cmd->mrq); 2218 } 2219 2220 if (host->cmd) { 2221 host->cmd->error = err; 2222 sdhci_finish_mrq(host, host->cmd->mrq); 2223 } 2224 } 2225 2226 static void sdhci_card_event(struct mmc_host *mmc) 2227 { 2228 struct sdhci_host *host = mmc_priv(mmc); 2229 unsigned long flags; 2230 int present; 2231 2232 /* First check if client has provided their own card event */ 2233 if (host->ops->card_event) 2234 host->ops->card_event(host); 2235 2236 present = mmc->ops->get_cd(mmc); 2237 2238 spin_lock_irqsave(&host->lock, flags); 2239 2240 /* Check sdhci_has_requests() first in case we are runtime suspended */ 2241 if (sdhci_has_requests(host) && !present) { 2242 pr_err("%s: Card removed during transfer!\n", 2243 mmc_hostname(host->mmc)); 2244 pr_err("%s: Resetting controller.\n", 2245 mmc_hostname(host->mmc)); 2246 2247 sdhci_do_reset(host, SDHCI_RESET_CMD); 2248 sdhci_do_reset(host, SDHCI_RESET_DATA); 2249 2250 sdhci_error_out_mrqs(host, -ENOMEDIUM); 2251 } 2252 2253 spin_unlock_irqrestore(&host->lock, flags); 2254 } 2255 2256 static const struct mmc_host_ops sdhci_ops = { 2257 .request = sdhci_request, 2258 .post_req = sdhci_post_req, 2259 .pre_req = sdhci_pre_req, 2260 .set_ios = sdhci_set_ios, 2261 .get_cd = sdhci_get_cd, 2262 .get_ro = sdhci_get_ro, 2263 .hw_reset = sdhci_hw_reset, 2264 .enable_sdio_irq = sdhci_enable_sdio_irq, 2265 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2266 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2267 .execute_tuning = sdhci_execute_tuning, 2268 .select_drive_strength = sdhci_select_drive_strength, 2269 .card_event = sdhci_card_event, 2270 .card_busy = sdhci_card_busy, 2271 }; 2272 2273 /*****************************************************************************\ 2274 * * 2275 * Tasklets * 2276 * * 2277 \*****************************************************************************/ 2278 2279 static bool sdhci_request_done(struct sdhci_host *host) 2280 { 2281 unsigned long flags; 2282 struct mmc_request *mrq; 2283 int i; 2284 2285 spin_lock_irqsave(&host->lock, flags); 2286 2287 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 2288 mrq = host->mrqs_done[i]; 2289 if (mrq) { 2290 host->mrqs_done[i] = NULL; 2291 break; 2292 } 2293 } 2294 2295 if (!mrq) { 2296 spin_unlock_irqrestore(&host->lock, flags); 2297 return true; 2298 } 2299 2300 sdhci_del_timer(host, mrq); 2301 2302 /* 2303 * Always unmap the data buffers if they were mapped by 2304 * sdhci_prepare_data() whenever we finish with a request. 2305 * This avoids leaking DMA mappings on error. 2306 */ 2307 if (host->flags & SDHCI_REQ_USE_DMA) { 2308 struct mmc_data *data = mrq->data; 2309 2310 if (data && data->host_cookie == COOKIE_MAPPED) { 2311 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2312 (data->flags & MMC_DATA_READ) ? 2313 DMA_FROM_DEVICE : DMA_TO_DEVICE); 2314 data->host_cookie = COOKIE_UNMAPPED; 2315 } 2316 } 2317 2318 /* 2319 * The controller needs a reset of internal state machines 2320 * upon error conditions. 2321 */ 2322 if (sdhci_needs_reset(host, mrq)) { 2323 /* Some controllers need this kick or reset won't work here */ 2324 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2325 /* This is to force an update */ 2326 host->ops->set_clock(host, host->clock); 2327 2328 /* Spec says we should do both at the same time, but Ricoh 2329 controllers do not like that. */ 2330 if (!host->cmd) 2331 sdhci_do_reset(host, SDHCI_RESET_CMD); 2332 if (!host->data_cmd) 2333 sdhci_do_reset(host, SDHCI_RESET_DATA); 2334 2335 host->pending_reset = false; 2336 } 2337 2338 if (!sdhci_has_requests(host)) 2339 sdhci_led_deactivate(host); 2340 2341 mmiowb(); 2342 spin_unlock_irqrestore(&host->lock, flags); 2343 2344 mmc_request_done(host->mmc, mrq); 2345 2346 return false; 2347 } 2348 2349 static void sdhci_tasklet_finish(unsigned long param) 2350 { 2351 struct sdhci_host *host = (struct sdhci_host *)param; 2352 2353 while (!sdhci_request_done(host)) 2354 ; 2355 } 2356 2357 static void sdhci_timeout_timer(unsigned long data) 2358 { 2359 struct sdhci_host *host; 2360 unsigned long flags; 2361 2362 host = (struct sdhci_host*)data; 2363 2364 spin_lock_irqsave(&host->lock, flags); 2365 2366 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2367 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2368 mmc_hostname(host->mmc)); 2369 sdhci_dumpregs(host); 2370 2371 host->cmd->error = -ETIMEDOUT; 2372 sdhci_finish_mrq(host, host->cmd->mrq); 2373 } 2374 2375 mmiowb(); 2376 spin_unlock_irqrestore(&host->lock, flags); 2377 } 2378 2379 static void sdhci_timeout_data_timer(unsigned long data) 2380 { 2381 struct sdhci_host *host; 2382 unsigned long flags; 2383 2384 host = (struct sdhci_host *)data; 2385 2386 spin_lock_irqsave(&host->lock, flags); 2387 2388 if (host->data || host->data_cmd || 2389 (host->cmd && sdhci_data_line_cmd(host->cmd))) { 2390 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2391 mmc_hostname(host->mmc)); 2392 sdhci_dumpregs(host); 2393 2394 if (host->data) { 2395 host->data->error = -ETIMEDOUT; 2396 sdhci_finish_data(host); 2397 } else if (host->data_cmd) { 2398 host->data_cmd->error = -ETIMEDOUT; 2399 sdhci_finish_mrq(host, host->data_cmd->mrq); 2400 } else { 2401 host->cmd->error = -ETIMEDOUT; 2402 sdhci_finish_mrq(host, host->cmd->mrq); 2403 } 2404 } 2405 2406 mmiowb(); 2407 spin_unlock_irqrestore(&host->lock, flags); 2408 } 2409 2410 /*****************************************************************************\ 2411 * * 2412 * Interrupt handling * 2413 * * 2414 \*****************************************************************************/ 2415 2416 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2417 { 2418 if (!host->cmd) { 2419 /* 2420 * SDHCI recovers from errors by resetting the cmd and data 2421 * circuits. Until that is done, there very well might be more 2422 * interrupts, so ignore them in that case. 2423 */ 2424 if (host->pending_reset) 2425 return; 2426 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2427 mmc_hostname(host->mmc), (unsigned)intmask); 2428 sdhci_dumpregs(host); 2429 return; 2430 } 2431 2432 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2433 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2434 if (intmask & SDHCI_INT_TIMEOUT) 2435 host->cmd->error = -ETIMEDOUT; 2436 else 2437 host->cmd->error = -EILSEQ; 2438 2439 /* 2440 * If this command initiates a data phase and a response 2441 * CRC error is signalled, the card can start transferring 2442 * data - the card may have received the command without 2443 * error. We must not terminate the mmc_request early. 2444 * 2445 * If the card did not receive the command or returned an 2446 * error which prevented it sending data, the data phase 2447 * will time out. 2448 */ 2449 if (host->cmd->data && 2450 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2451 SDHCI_INT_CRC) { 2452 host->cmd = NULL; 2453 return; 2454 } 2455 2456 sdhci_finish_mrq(host, host->cmd->mrq); 2457 return; 2458 } 2459 2460 if (intmask & SDHCI_INT_RESPONSE) 2461 sdhci_finish_command(host); 2462 } 2463 2464 #ifdef CONFIG_MMC_DEBUG 2465 static void sdhci_adma_show_error(struct sdhci_host *host) 2466 { 2467 const char *name = mmc_hostname(host->mmc); 2468 void *desc = host->adma_table; 2469 2470 sdhci_dumpregs(host); 2471 2472 while (true) { 2473 struct sdhci_adma2_64_desc *dma_desc = desc; 2474 2475 if (host->flags & SDHCI_USE_64_BIT_DMA) 2476 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2477 name, desc, le32_to_cpu(dma_desc->addr_hi), 2478 le32_to_cpu(dma_desc->addr_lo), 2479 le16_to_cpu(dma_desc->len), 2480 le16_to_cpu(dma_desc->cmd)); 2481 else 2482 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2483 name, desc, le32_to_cpu(dma_desc->addr_lo), 2484 le16_to_cpu(dma_desc->len), 2485 le16_to_cpu(dma_desc->cmd)); 2486 2487 desc += host->desc_sz; 2488 2489 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2490 break; 2491 } 2492 } 2493 #else 2494 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2495 #endif 2496 2497 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2498 { 2499 u32 command; 2500 2501 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2502 if (intmask & SDHCI_INT_DATA_AVAIL) { 2503 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2504 if (command == MMC_SEND_TUNING_BLOCK || 2505 command == MMC_SEND_TUNING_BLOCK_HS200) { 2506 host->tuning_done = 1; 2507 wake_up(&host->buf_ready_int); 2508 return; 2509 } 2510 } 2511 2512 if (!host->data) { 2513 struct mmc_command *data_cmd = host->data_cmd; 2514 2515 if (data_cmd) 2516 host->data_cmd = NULL; 2517 2518 /* 2519 * The "data complete" interrupt is also used to 2520 * indicate that a busy state has ended. See comment 2521 * above in sdhci_cmd_irq(). 2522 */ 2523 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2524 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2525 data_cmd->error = -ETIMEDOUT; 2526 sdhci_finish_mrq(host, data_cmd->mrq); 2527 return; 2528 } 2529 if (intmask & SDHCI_INT_DATA_END) { 2530 /* 2531 * Some cards handle busy-end interrupt 2532 * before the command completed, so make 2533 * sure we do things in the proper order. 2534 */ 2535 if (host->cmd == data_cmd) 2536 return; 2537 2538 sdhci_finish_mrq(host, data_cmd->mrq); 2539 return; 2540 } 2541 } 2542 2543 /* 2544 * SDHCI recovers from errors by resetting the cmd and data 2545 * circuits. Until that is done, there very well might be more 2546 * interrupts, so ignore them in that case. 2547 */ 2548 if (host->pending_reset) 2549 return; 2550 2551 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2552 mmc_hostname(host->mmc), (unsigned)intmask); 2553 sdhci_dumpregs(host); 2554 2555 return; 2556 } 2557 2558 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2559 host->data->error = -ETIMEDOUT; 2560 else if (intmask & SDHCI_INT_DATA_END_BIT) 2561 host->data->error = -EILSEQ; 2562 else if ((intmask & SDHCI_INT_DATA_CRC) && 2563 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2564 != MMC_BUS_TEST_R) 2565 host->data->error = -EILSEQ; 2566 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2567 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2568 sdhci_adma_show_error(host); 2569 host->data->error = -EIO; 2570 if (host->ops->adma_workaround) 2571 host->ops->adma_workaround(host, intmask); 2572 } 2573 2574 if (host->data->error) 2575 sdhci_finish_data(host); 2576 else { 2577 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2578 sdhci_transfer_pio(host); 2579 2580 /* 2581 * We currently don't do anything fancy with DMA 2582 * boundaries, but as we can't disable the feature 2583 * we need to at least restart the transfer. 2584 * 2585 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2586 * should return a valid address to continue from, but as 2587 * some controllers are faulty, don't trust them. 2588 */ 2589 if (intmask & SDHCI_INT_DMA_END) { 2590 u32 dmastart, dmanow; 2591 dmastart = sg_dma_address(host->data->sg); 2592 dmanow = dmastart + host->data->bytes_xfered; 2593 /* 2594 * Force update to the next DMA block boundary. 2595 */ 2596 dmanow = (dmanow & 2597 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2598 SDHCI_DEFAULT_BOUNDARY_SIZE; 2599 host->data->bytes_xfered = dmanow - dmastart; 2600 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2601 " next 0x%08x\n", 2602 mmc_hostname(host->mmc), dmastart, 2603 host->data->bytes_xfered, dmanow); 2604 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2605 } 2606 2607 if (intmask & SDHCI_INT_DATA_END) { 2608 if (host->cmd == host->data_cmd) { 2609 /* 2610 * Data managed to finish before the 2611 * command completed. Make sure we do 2612 * things in the proper order. 2613 */ 2614 host->data_early = 1; 2615 } else { 2616 sdhci_finish_data(host); 2617 } 2618 } 2619 } 2620 } 2621 2622 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2623 { 2624 irqreturn_t result = IRQ_NONE; 2625 struct sdhci_host *host = dev_id; 2626 u32 intmask, mask, unexpected = 0; 2627 int max_loops = 16; 2628 2629 spin_lock(&host->lock); 2630 2631 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2632 spin_unlock(&host->lock); 2633 return IRQ_NONE; 2634 } 2635 2636 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2637 if (!intmask || intmask == 0xffffffff) { 2638 result = IRQ_NONE; 2639 goto out; 2640 } 2641 2642 do { 2643 /* Clear selected interrupts. */ 2644 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2645 SDHCI_INT_BUS_POWER); 2646 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2647 2648 DBG("*** %s got interrupt: 0x%08x\n", 2649 mmc_hostname(host->mmc), intmask); 2650 2651 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2652 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2653 SDHCI_CARD_PRESENT; 2654 2655 /* 2656 * There is a observation on i.mx esdhc. INSERT 2657 * bit will be immediately set again when it gets 2658 * cleared, if a card is inserted. We have to mask 2659 * the irq to prevent interrupt storm which will 2660 * freeze the system. And the REMOVE gets the 2661 * same situation. 2662 * 2663 * More testing are needed here to ensure it works 2664 * for other platforms though. 2665 */ 2666 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2667 SDHCI_INT_CARD_REMOVE); 2668 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2669 SDHCI_INT_CARD_INSERT; 2670 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2671 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2672 2673 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2674 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2675 2676 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2677 SDHCI_INT_CARD_REMOVE); 2678 result = IRQ_WAKE_THREAD; 2679 } 2680 2681 if (intmask & SDHCI_INT_CMD_MASK) 2682 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2683 2684 if (intmask & SDHCI_INT_DATA_MASK) 2685 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2686 2687 if (intmask & SDHCI_INT_BUS_POWER) 2688 pr_err("%s: Card is consuming too much power!\n", 2689 mmc_hostname(host->mmc)); 2690 2691 if (intmask & SDHCI_INT_RETUNE) 2692 mmc_retune_needed(host->mmc); 2693 2694 if (intmask & SDHCI_INT_CARD_INT) { 2695 sdhci_enable_sdio_irq_nolock(host, false); 2696 host->thread_isr |= SDHCI_INT_CARD_INT; 2697 result = IRQ_WAKE_THREAD; 2698 } 2699 2700 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2701 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2702 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2703 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 2704 2705 if (intmask) { 2706 unexpected |= intmask; 2707 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2708 } 2709 2710 if (result == IRQ_NONE) 2711 result = IRQ_HANDLED; 2712 2713 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2714 } while (intmask && --max_loops); 2715 out: 2716 spin_unlock(&host->lock); 2717 2718 if (unexpected) { 2719 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2720 mmc_hostname(host->mmc), unexpected); 2721 sdhci_dumpregs(host); 2722 } 2723 2724 return result; 2725 } 2726 2727 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2728 { 2729 struct sdhci_host *host = dev_id; 2730 unsigned long flags; 2731 u32 isr; 2732 2733 spin_lock_irqsave(&host->lock, flags); 2734 isr = host->thread_isr; 2735 host->thread_isr = 0; 2736 spin_unlock_irqrestore(&host->lock, flags); 2737 2738 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2739 struct mmc_host *mmc = host->mmc; 2740 2741 mmc->ops->card_event(mmc); 2742 mmc_detect_change(mmc, msecs_to_jiffies(200)); 2743 } 2744 2745 if (isr & SDHCI_INT_CARD_INT) { 2746 sdio_run_irqs(host->mmc); 2747 2748 spin_lock_irqsave(&host->lock, flags); 2749 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2750 sdhci_enable_sdio_irq_nolock(host, true); 2751 spin_unlock_irqrestore(&host->lock, flags); 2752 } 2753 2754 return isr ? IRQ_HANDLED : IRQ_NONE; 2755 } 2756 2757 /*****************************************************************************\ 2758 * * 2759 * Suspend/resume * 2760 * * 2761 \*****************************************************************************/ 2762 2763 #ifdef CONFIG_PM 2764 /* 2765 * To enable wakeup events, the corresponding events have to be enabled in 2766 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 2767 * Table' in the SD Host Controller Standard Specification. 2768 * It is useless to restore SDHCI_INT_ENABLE state in 2769 * sdhci_disable_irq_wakeups() since it will be set by 2770 * sdhci_enable_card_detection() or sdhci_init(). 2771 */ 2772 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2773 { 2774 u8 val; 2775 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2776 | SDHCI_WAKE_ON_INT; 2777 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2778 SDHCI_INT_CARD_INT; 2779 2780 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2781 val |= mask ; 2782 /* Avoid fake wake up */ 2783 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { 2784 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2785 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2786 } 2787 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2788 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 2789 } 2790 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2791 2792 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2793 { 2794 u8 val; 2795 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2796 | SDHCI_WAKE_ON_INT; 2797 2798 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2799 val &= ~mask; 2800 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2801 } 2802 2803 int sdhci_suspend_host(struct sdhci_host *host) 2804 { 2805 sdhci_disable_card_detection(host); 2806 2807 mmc_retune_timer_stop(host->mmc); 2808 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2809 mmc_retune_needed(host->mmc); 2810 2811 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2812 host->ier = 0; 2813 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2814 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2815 free_irq(host->irq, host); 2816 } else { 2817 sdhci_enable_irq_wakeups(host); 2818 enable_irq_wake(host->irq); 2819 } 2820 return 0; 2821 } 2822 2823 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2824 2825 int sdhci_resume_host(struct sdhci_host *host) 2826 { 2827 struct mmc_host *mmc = host->mmc; 2828 int ret = 0; 2829 2830 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2831 if (host->ops->enable_dma) 2832 host->ops->enable_dma(host); 2833 } 2834 2835 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2836 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2837 /* Card keeps power but host controller does not */ 2838 sdhci_init(host, 0); 2839 host->pwr = 0; 2840 host->clock = 0; 2841 mmc->ops->set_ios(mmc, &mmc->ios); 2842 } else { 2843 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2844 mmiowb(); 2845 } 2846 2847 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2848 ret = request_threaded_irq(host->irq, sdhci_irq, 2849 sdhci_thread_irq, IRQF_SHARED, 2850 mmc_hostname(host->mmc), host); 2851 if (ret) 2852 return ret; 2853 } else { 2854 sdhci_disable_irq_wakeups(host); 2855 disable_irq_wake(host->irq); 2856 } 2857 2858 sdhci_enable_card_detection(host); 2859 2860 return ret; 2861 } 2862 2863 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2864 2865 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2866 { 2867 unsigned long flags; 2868 2869 mmc_retune_timer_stop(host->mmc); 2870 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2871 mmc_retune_needed(host->mmc); 2872 2873 spin_lock_irqsave(&host->lock, flags); 2874 host->ier &= SDHCI_INT_CARD_INT; 2875 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2876 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2877 spin_unlock_irqrestore(&host->lock, flags); 2878 2879 synchronize_hardirq(host->irq); 2880 2881 spin_lock_irqsave(&host->lock, flags); 2882 host->runtime_suspended = true; 2883 spin_unlock_irqrestore(&host->lock, flags); 2884 2885 return 0; 2886 } 2887 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2888 2889 int sdhci_runtime_resume_host(struct sdhci_host *host) 2890 { 2891 struct mmc_host *mmc = host->mmc; 2892 unsigned long flags; 2893 int host_flags = host->flags; 2894 2895 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2896 if (host->ops->enable_dma) 2897 host->ops->enable_dma(host); 2898 } 2899 2900 sdhci_init(host, 0); 2901 2902 /* Force clock and power re-program */ 2903 host->pwr = 0; 2904 host->clock = 0; 2905 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 2906 mmc->ops->set_ios(mmc, &mmc->ios); 2907 2908 if ((host_flags & SDHCI_PV_ENABLED) && 2909 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2910 spin_lock_irqsave(&host->lock, flags); 2911 sdhci_enable_preset_value(host, true); 2912 spin_unlock_irqrestore(&host->lock, flags); 2913 } 2914 2915 spin_lock_irqsave(&host->lock, flags); 2916 2917 host->runtime_suspended = false; 2918 2919 /* Enable SDIO IRQ */ 2920 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2921 sdhci_enable_sdio_irq_nolock(host, true); 2922 2923 /* Enable Card Detection */ 2924 sdhci_enable_card_detection(host); 2925 2926 spin_unlock_irqrestore(&host->lock, flags); 2927 2928 return 0; 2929 } 2930 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2931 2932 #endif /* CONFIG_PM */ 2933 2934 /*****************************************************************************\ 2935 * * 2936 * Device allocation/registration * 2937 * * 2938 \*****************************************************************************/ 2939 2940 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2941 size_t priv_size) 2942 { 2943 struct mmc_host *mmc; 2944 struct sdhci_host *host; 2945 2946 WARN_ON(dev == NULL); 2947 2948 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2949 if (!mmc) 2950 return ERR_PTR(-ENOMEM); 2951 2952 host = mmc_priv(mmc); 2953 host->mmc = mmc; 2954 host->mmc_host_ops = sdhci_ops; 2955 mmc->ops = &host->mmc_host_ops; 2956 2957 host->flags = SDHCI_SIGNALING_330; 2958 2959 return host; 2960 } 2961 2962 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2963 2964 static int sdhci_set_dma_mask(struct sdhci_host *host) 2965 { 2966 struct mmc_host *mmc = host->mmc; 2967 struct device *dev = mmc_dev(mmc); 2968 int ret = -EINVAL; 2969 2970 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 2971 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2972 2973 /* Try 64-bit mask if hardware is capable of it */ 2974 if (host->flags & SDHCI_USE_64_BIT_DMA) { 2975 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 2976 if (ret) { 2977 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 2978 mmc_hostname(mmc)); 2979 host->flags &= ~SDHCI_USE_64_BIT_DMA; 2980 } 2981 } 2982 2983 /* 32-bit mask as default & fallback */ 2984 if (ret) { 2985 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 2986 if (ret) 2987 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 2988 mmc_hostname(mmc)); 2989 } 2990 2991 return ret; 2992 } 2993 2994 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 2995 { 2996 u16 v; 2997 2998 if (host->read_caps) 2999 return; 3000 3001 host->read_caps = true; 3002 3003 if (debug_quirks) 3004 host->quirks = debug_quirks; 3005 3006 if (debug_quirks2) 3007 host->quirks2 = debug_quirks2; 3008 3009 sdhci_do_reset(host, SDHCI_RESET_ALL); 3010 3011 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 3012 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 3013 3014 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 3015 return; 3016 3017 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES); 3018 3019 if (host->version < SDHCI_SPEC_300) 3020 return; 3021 3022 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1); 3023 } 3024 EXPORT_SYMBOL_GPL(__sdhci_read_caps); 3025 3026 int sdhci_setup_host(struct sdhci_host *host) 3027 { 3028 struct mmc_host *mmc; 3029 u32 max_current_caps; 3030 unsigned int ocr_avail; 3031 unsigned int override_timeout_clk; 3032 u32 max_clk; 3033 int ret; 3034 3035 WARN_ON(host == NULL); 3036 if (host == NULL) 3037 return -EINVAL; 3038 3039 mmc = host->mmc; 3040 3041 /* 3042 * If there are external regulators, get them. Note this must be done 3043 * early before resetting the host and reading the capabilities so that 3044 * the host can take the appropriate action if regulators are not 3045 * available. 3046 */ 3047 ret = mmc_regulator_get_supply(mmc); 3048 if (ret == -EPROBE_DEFER) 3049 return ret; 3050 3051 sdhci_read_caps(host); 3052 3053 override_timeout_clk = host->timeout_clk; 3054 3055 if (host->version > SDHCI_SPEC_300) { 3056 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3057 mmc_hostname(mmc), host->version); 3058 } 3059 3060 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3061 host->flags |= SDHCI_USE_SDMA; 3062 else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3063 DBG("Controller doesn't have SDMA capability\n"); 3064 else 3065 host->flags |= SDHCI_USE_SDMA; 3066 3067 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3068 (host->flags & SDHCI_USE_SDMA)) { 3069 DBG("Disabling DMA as it is marked broken\n"); 3070 host->flags &= ~SDHCI_USE_SDMA; 3071 } 3072 3073 if ((host->version >= SDHCI_SPEC_200) && 3074 (host->caps & SDHCI_CAN_DO_ADMA2)) 3075 host->flags |= SDHCI_USE_ADMA; 3076 3077 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3078 (host->flags & SDHCI_USE_ADMA)) { 3079 DBG("Disabling ADMA as it is marked broken\n"); 3080 host->flags &= ~SDHCI_USE_ADMA; 3081 } 3082 3083 /* 3084 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3085 * and *must* do 64-bit DMA. A driver has the opportunity to change 3086 * that during the first call to ->enable_dma(). Similarly 3087 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3088 * implement. 3089 */ 3090 if (host->caps & SDHCI_CAN_64BIT) 3091 host->flags |= SDHCI_USE_64_BIT_DMA; 3092 3093 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3094 ret = sdhci_set_dma_mask(host); 3095 3096 if (!ret && host->ops->enable_dma) 3097 ret = host->ops->enable_dma(host); 3098 3099 if (ret) { 3100 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3101 mmc_hostname(mmc)); 3102 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 3103 3104 ret = 0; 3105 } 3106 } 3107 3108 /* SDMA does not support 64-bit DMA */ 3109 if (host->flags & SDHCI_USE_64_BIT_DMA) 3110 host->flags &= ~SDHCI_USE_SDMA; 3111 3112 if (host->flags & SDHCI_USE_ADMA) { 3113 dma_addr_t dma; 3114 void *buf; 3115 3116 /* 3117 * The DMA descriptor table size is calculated as the maximum 3118 * number of segments times 2, to allow for an alignment 3119 * descriptor for each segment, plus 1 for a nop end descriptor, 3120 * all multipled by the descriptor size. 3121 */ 3122 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3123 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3124 SDHCI_ADMA2_64_DESC_SZ; 3125 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 3126 } else { 3127 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3128 SDHCI_ADMA2_32_DESC_SZ; 3129 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3130 } 3131 3132 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3133 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 3134 host->adma_table_sz, &dma, GFP_KERNEL); 3135 if (!buf) { 3136 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 3137 mmc_hostname(mmc)); 3138 host->flags &= ~SDHCI_USE_ADMA; 3139 } else if ((dma + host->align_buffer_sz) & 3140 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 3141 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3142 mmc_hostname(mmc)); 3143 host->flags &= ~SDHCI_USE_ADMA; 3144 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3145 host->adma_table_sz, buf, dma); 3146 } else { 3147 host->align_buffer = buf; 3148 host->align_addr = dma; 3149 3150 host->adma_table = buf + host->align_buffer_sz; 3151 host->adma_addr = dma + host->align_buffer_sz; 3152 } 3153 } 3154 3155 /* 3156 * If we use DMA, then it's up to the caller to set the DMA 3157 * mask, but PIO does not need the hw shim so we set a new 3158 * mask here in that case. 3159 */ 3160 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3161 host->dma_mask = DMA_BIT_MASK(64); 3162 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3163 } 3164 3165 if (host->version >= SDHCI_SPEC_300) 3166 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3167 >> SDHCI_CLOCK_BASE_SHIFT; 3168 else 3169 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3170 >> SDHCI_CLOCK_BASE_SHIFT; 3171 3172 host->max_clk *= 1000000; 3173 if (host->max_clk == 0 || host->quirks & 3174 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3175 if (!host->ops->get_max_clock) { 3176 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 3177 mmc_hostname(mmc)); 3178 ret = -ENODEV; 3179 goto undma; 3180 } 3181 host->max_clk = host->ops->get_max_clock(host); 3182 } 3183 3184 /* 3185 * In case of Host Controller v3.00, find out whether clock 3186 * multiplier is supported. 3187 */ 3188 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3189 SDHCI_CLOCK_MUL_SHIFT; 3190 3191 /* 3192 * In case the value in Clock Multiplier is 0, then programmable 3193 * clock mode is not supported, otherwise the actual clock 3194 * multiplier is one more than the value of Clock Multiplier 3195 * in the Capabilities Register. 3196 */ 3197 if (host->clk_mul) 3198 host->clk_mul += 1; 3199 3200 /* 3201 * Set host parameters. 3202 */ 3203 max_clk = host->max_clk; 3204 3205 if (host->ops->get_min_clock) 3206 mmc->f_min = host->ops->get_min_clock(host); 3207 else if (host->version >= SDHCI_SPEC_300) { 3208 if (host->clk_mul) { 3209 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3210 max_clk = host->max_clk * host->clk_mul; 3211 } else 3212 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3213 } else 3214 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3215 3216 if (!mmc->f_max || mmc->f_max > max_clk) 3217 mmc->f_max = max_clk; 3218 3219 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3220 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 3221 SDHCI_TIMEOUT_CLK_SHIFT; 3222 if (host->timeout_clk == 0) { 3223 if (host->ops->get_timeout_clock) { 3224 host->timeout_clk = 3225 host->ops->get_timeout_clock(host); 3226 } else { 3227 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3228 mmc_hostname(mmc)); 3229 ret = -ENODEV; 3230 goto undma; 3231 } 3232 } 3233 3234 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 3235 host->timeout_clk *= 1000; 3236 3237 if (override_timeout_clk) 3238 host->timeout_clk = override_timeout_clk; 3239 3240 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3241 host->ops->get_max_timeout_count(host) : 1 << 27; 3242 mmc->max_busy_timeout /= host->timeout_clk; 3243 } 3244 3245 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3246 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3247 3248 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3249 host->flags |= SDHCI_AUTO_CMD12; 3250 3251 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3252 if ((host->version >= SDHCI_SPEC_300) && 3253 ((host->flags & SDHCI_USE_ADMA) || 3254 !(host->flags & SDHCI_USE_SDMA)) && 3255 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3256 host->flags |= SDHCI_AUTO_CMD23; 3257 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3258 } else { 3259 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3260 } 3261 3262 /* 3263 * A controller may support 8-bit width, but the board itself 3264 * might not have the pins brought out. Boards that support 3265 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3266 * their platform code before calling sdhci_add_host(), and we 3267 * won't assume 8-bit width for hosts without that CAP. 3268 */ 3269 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3270 mmc->caps |= MMC_CAP_4_BIT_DATA; 3271 3272 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3273 mmc->caps &= ~MMC_CAP_CMD23; 3274 3275 if (host->caps & SDHCI_CAN_DO_HISPD) 3276 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3277 3278 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3279 mmc_card_is_removable(mmc) && 3280 mmc_gpio_get_cd(host->mmc) < 0) 3281 mmc->caps |= MMC_CAP_NEEDS_POLL; 3282 3283 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3284 if (!IS_ERR(mmc->supply.vqmmc)) { 3285 ret = regulator_enable(mmc->supply.vqmmc); 3286 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3287 1950000)) 3288 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 3289 SDHCI_SUPPORT_SDR50 | 3290 SDHCI_SUPPORT_DDR50); 3291 if (ret) { 3292 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3293 mmc_hostname(mmc), ret); 3294 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3295 } 3296 } 3297 3298 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 3299 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3300 SDHCI_SUPPORT_DDR50); 3301 } 3302 3303 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3304 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3305 SDHCI_SUPPORT_DDR50)) 3306 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3307 3308 /* SDR104 supports also implies SDR50 support */ 3309 if (host->caps1 & SDHCI_SUPPORT_SDR104) { 3310 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3311 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3312 * field can be promoted to support HS200. 3313 */ 3314 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3315 mmc->caps2 |= MMC_CAP2_HS200; 3316 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 3317 mmc->caps |= MMC_CAP_UHS_SDR50; 3318 } 3319 3320 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3321 (host->caps1 & SDHCI_SUPPORT_HS400)) 3322 mmc->caps2 |= MMC_CAP2_HS400; 3323 3324 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3325 (IS_ERR(mmc->supply.vqmmc) || 3326 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3327 1300000))) 3328 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3329 3330 if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 3331 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3332 mmc->caps |= MMC_CAP_UHS_DDR50; 3333 3334 /* Does the host need tuning for SDR50? */ 3335 if (host->caps1 & SDHCI_USE_SDR50_TUNING) 3336 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3337 3338 /* Driver Type(s) (A, C, D) supported by the host */ 3339 if (host->caps1 & SDHCI_DRIVER_TYPE_A) 3340 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3341 if (host->caps1 & SDHCI_DRIVER_TYPE_C) 3342 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3343 if (host->caps1 & SDHCI_DRIVER_TYPE_D) 3344 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3345 3346 /* Initial value for re-tuning timer count */ 3347 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3348 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3349 3350 /* 3351 * In case Re-tuning Timer is not disabled, the actual value of 3352 * re-tuning timer will be 2 ^ (n - 1). 3353 */ 3354 if (host->tuning_count) 3355 host->tuning_count = 1 << (host->tuning_count - 1); 3356 3357 /* Re-tuning mode supported by the Host Controller */ 3358 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 3359 SDHCI_RETUNING_MODE_SHIFT; 3360 3361 ocr_avail = 0; 3362 3363 /* 3364 * According to SD Host Controller spec v3.00, if the Host System 3365 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3366 * the value is meaningful only if Voltage Support in the Capabilities 3367 * register is set. The actual current value is 4 times the register 3368 * value. 3369 */ 3370 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3371 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3372 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3373 if (curr > 0) { 3374 3375 /* convert to SDHCI_MAX_CURRENT format */ 3376 curr = curr/1000; /* convert to mA */ 3377 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3378 3379 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3380 max_current_caps = 3381 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3382 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3383 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3384 } 3385 } 3386 3387 if (host->caps & SDHCI_CAN_VDD_330) { 3388 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3389 3390 mmc->max_current_330 = ((max_current_caps & 3391 SDHCI_MAX_CURRENT_330_MASK) >> 3392 SDHCI_MAX_CURRENT_330_SHIFT) * 3393 SDHCI_MAX_CURRENT_MULTIPLIER; 3394 } 3395 if (host->caps & SDHCI_CAN_VDD_300) { 3396 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3397 3398 mmc->max_current_300 = ((max_current_caps & 3399 SDHCI_MAX_CURRENT_300_MASK) >> 3400 SDHCI_MAX_CURRENT_300_SHIFT) * 3401 SDHCI_MAX_CURRENT_MULTIPLIER; 3402 } 3403 if (host->caps & SDHCI_CAN_VDD_180) { 3404 ocr_avail |= MMC_VDD_165_195; 3405 3406 mmc->max_current_180 = ((max_current_caps & 3407 SDHCI_MAX_CURRENT_180_MASK) >> 3408 SDHCI_MAX_CURRENT_180_SHIFT) * 3409 SDHCI_MAX_CURRENT_MULTIPLIER; 3410 } 3411 3412 /* If OCR set by host, use it instead. */ 3413 if (host->ocr_mask) 3414 ocr_avail = host->ocr_mask; 3415 3416 /* If OCR set by external regulators, give it highest prio. */ 3417 if (mmc->ocr_avail) 3418 ocr_avail = mmc->ocr_avail; 3419 3420 mmc->ocr_avail = ocr_avail; 3421 mmc->ocr_avail_sdio = ocr_avail; 3422 if (host->ocr_avail_sdio) 3423 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3424 mmc->ocr_avail_sd = ocr_avail; 3425 if (host->ocr_avail_sd) 3426 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3427 else /* normal SD controllers don't support 1.8V */ 3428 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3429 mmc->ocr_avail_mmc = ocr_avail; 3430 if (host->ocr_avail_mmc) 3431 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3432 3433 if (mmc->ocr_avail == 0) { 3434 pr_err("%s: Hardware doesn't report any support voltages.\n", 3435 mmc_hostname(mmc)); 3436 ret = -ENODEV; 3437 goto unreg; 3438 } 3439 3440 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 3441 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 3442 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 3443 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 3444 host->flags |= SDHCI_SIGNALING_180; 3445 3446 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 3447 host->flags |= SDHCI_SIGNALING_120; 3448 3449 spin_lock_init(&host->lock); 3450 3451 /* 3452 * Maximum number of segments. Depends on if the hardware 3453 * can do scatter/gather or not. 3454 */ 3455 if (host->flags & SDHCI_USE_ADMA) 3456 mmc->max_segs = SDHCI_MAX_SEGS; 3457 else if (host->flags & SDHCI_USE_SDMA) 3458 mmc->max_segs = 1; 3459 else /* PIO */ 3460 mmc->max_segs = SDHCI_MAX_SEGS; 3461 3462 /* 3463 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3464 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3465 * is less anyway. 3466 */ 3467 mmc->max_req_size = 524288; 3468 3469 /* 3470 * Maximum segment size. Could be one segment with the maximum number 3471 * of bytes. When doing hardware scatter/gather, each entry cannot 3472 * be larger than 64 KiB though. 3473 */ 3474 if (host->flags & SDHCI_USE_ADMA) { 3475 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3476 mmc->max_seg_size = 65535; 3477 else 3478 mmc->max_seg_size = 65536; 3479 } else { 3480 mmc->max_seg_size = mmc->max_req_size; 3481 } 3482 3483 /* 3484 * Maximum block size. This varies from controller to controller and 3485 * is specified in the capabilities register. 3486 */ 3487 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3488 mmc->max_blk_size = 2; 3489 } else { 3490 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 3491 SDHCI_MAX_BLOCK_SHIFT; 3492 if (mmc->max_blk_size >= 3) { 3493 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3494 mmc_hostname(mmc)); 3495 mmc->max_blk_size = 0; 3496 } 3497 } 3498 3499 mmc->max_blk_size = 512 << mmc->max_blk_size; 3500 3501 /* 3502 * Maximum block count. 3503 */ 3504 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3505 3506 return 0; 3507 3508 unreg: 3509 if (!IS_ERR(mmc->supply.vqmmc)) 3510 regulator_disable(mmc->supply.vqmmc); 3511 undma: 3512 if (host->align_buffer) 3513 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3514 host->adma_table_sz, host->align_buffer, 3515 host->align_addr); 3516 host->adma_table = NULL; 3517 host->align_buffer = NULL; 3518 3519 return ret; 3520 } 3521 EXPORT_SYMBOL_GPL(sdhci_setup_host); 3522 3523 int __sdhci_add_host(struct sdhci_host *host) 3524 { 3525 struct mmc_host *mmc = host->mmc; 3526 int ret; 3527 3528 /* 3529 * Init tasklets. 3530 */ 3531 tasklet_init(&host->finish_tasklet, 3532 sdhci_tasklet_finish, (unsigned long)host); 3533 3534 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3535 setup_timer(&host->data_timer, sdhci_timeout_data_timer, 3536 (unsigned long)host); 3537 3538 init_waitqueue_head(&host->buf_ready_int); 3539 3540 sdhci_init(host, 0); 3541 3542 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3543 IRQF_SHARED, mmc_hostname(mmc), host); 3544 if (ret) { 3545 pr_err("%s: Failed to request IRQ %d: %d\n", 3546 mmc_hostname(mmc), host->irq, ret); 3547 goto untasklet; 3548 } 3549 3550 #ifdef CONFIG_MMC_DEBUG 3551 sdhci_dumpregs(host); 3552 #endif 3553 3554 ret = sdhci_led_register(host); 3555 if (ret) { 3556 pr_err("%s: Failed to register LED device: %d\n", 3557 mmc_hostname(mmc), ret); 3558 goto unirq; 3559 } 3560 3561 mmiowb(); 3562 3563 ret = mmc_add_host(mmc); 3564 if (ret) 3565 goto unled; 3566 3567 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3568 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3569 (host->flags & SDHCI_USE_ADMA) ? 3570 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3571 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3572 3573 sdhci_enable_card_detection(host); 3574 3575 return 0; 3576 3577 unled: 3578 sdhci_led_unregister(host); 3579 unirq: 3580 sdhci_do_reset(host, SDHCI_RESET_ALL); 3581 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3582 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3583 free_irq(host->irq, host); 3584 untasklet: 3585 tasklet_kill(&host->finish_tasklet); 3586 3587 if (!IS_ERR(mmc->supply.vqmmc)) 3588 regulator_disable(mmc->supply.vqmmc); 3589 3590 if (host->align_buffer) 3591 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3592 host->adma_table_sz, host->align_buffer, 3593 host->align_addr); 3594 host->adma_table = NULL; 3595 host->align_buffer = NULL; 3596 3597 return ret; 3598 } 3599 EXPORT_SYMBOL_GPL(__sdhci_add_host); 3600 3601 int sdhci_add_host(struct sdhci_host *host) 3602 { 3603 int ret; 3604 3605 ret = sdhci_setup_host(host); 3606 if (ret) 3607 return ret; 3608 3609 return __sdhci_add_host(host); 3610 } 3611 EXPORT_SYMBOL_GPL(sdhci_add_host); 3612 3613 void sdhci_remove_host(struct sdhci_host *host, int dead) 3614 { 3615 struct mmc_host *mmc = host->mmc; 3616 unsigned long flags; 3617 3618 if (dead) { 3619 spin_lock_irqsave(&host->lock, flags); 3620 3621 host->flags |= SDHCI_DEVICE_DEAD; 3622 3623 if (sdhci_has_requests(host)) { 3624 pr_err("%s: Controller removed during " 3625 " transfer!\n", mmc_hostname(mmc)); 3626 sdhci_error_out_mrqs(host, -ENOMEDIUM); 3627 } 3628 3629 spin_unlock_irqrestore(&host->lock, flags); 3630 } 3631 3632 sdhci_disable_card_detection(host); 3633 3634 mmc_remove_host(mmc); 3635 3636 sdhci_led_unregister(host); 3637 3638 if (!dead) 3639 sdhci_do_reset(host, SDHCI_RESET_ALL); 3640 3641 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3642 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3643 free_irq(host->irq, host); 3644 3645 del_timer_sync(&host->timer); 3646 del_timer_sync(&host->data_timer); 3647 3648 tasklet_kill(&host->finish_tasklet); 3649 3650 if (!IS_ERR(mmc->supply.vqmmc)) 3651 regulator_disable(mmc->supply.vqmmc); 3652 3653 if (host->align_buffer) 3654 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3655 host->adma_table_sz, host->align_buffer, 3656 host->align_addr); 3657 3658 host->adma_table = NULL; 3659 host->align_buffer = NULL; 3660 } 3661 3662 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3663 3664 void sdhci_free_host(struct sdhci_host *host) 3665 { 3666 mmc_free_host(host->mmc); 3667 } 3668 3669 EXPORT_SYMBOL_GPL(sdhci_free_host); 3670 3671 /*****************************************************************************\ 3672 * * 3673 * Driver init/exit * 3674 * * 3675 \*****************************************************************************/ 3676 3677 static int __init sdhci_drv_init(void) 3678 { 3679 pr_info(DRIVER_NAME 3680 ": Secure Digital Host Controller Interface driver\n"); 3681 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3682 3683 return 0; 3684 } 3685 3686 static void __exit sdhci_drv_exit(void) 3687 { 3688 } 3689 3690 module_init(sdhci_drv_init); 3691 module_exit(sdhci_drv_exit); 3692 3693 module_param(debug_quirks, uint, 0444); 3694 module_param(debug_quirks2, uint, 0444); 3695 3696 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3697 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3698 MODULE_LICENSE("GPL"); 3699 3700 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3701 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3702