1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 4 * 5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 6 * 7 * Thanks to the following companies for their support: 8 * 9 * - JMicron (hardware and technical support) 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/ktime.h> 14 #include <linux/highmem.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/scatterlist.h> 20 #include <linux/sizes.h> 21 #include <linux/swiotlb.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/of.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #include "sdhci.h" 35 36 #define DRIVER_NAME "sdhci" 37 38 #define DBG(f, x...) \ 39 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 40 41 #define SDHCI_DUMP(f, x...) \ 42 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 43 44 #define MAX_TUNING_LOOP 40 45 46 static unsigned int debug_quirks = 0; 47 static unsigned int debug_quirks2; 48 49 static void sdhci_finish_data(struct sdhci_host *); 50 51 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 52 53 void sdhci_dumpregs(struct sdhci_host *host) 54 { 55 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n"); 56 57 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n", 58 sdhci_readl(host, SDHCI_DMA_ADDRESS), 59 sdhci_readw(host, SDHCI_HOST_VERSION)); 60 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n", 61 sdhci_readw(host, SDHCI_BLOCK_SIZE), 62 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 63 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n", 64 sdhci_readl(host, SDHCI_ARGUMENT), 65 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 66 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n", 67 sdhci_readl(host, SDHCI_PRESENT_STATE), 68 sdhci_readb(host, SDHCI_HOST_CONTROL)); 69 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n", 70 sdhci_readb(host, SDHCI_POWER_CONTROL), 71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 72 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n", 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 74 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 75 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n", 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 77 sdhci_readl(host, SDHCI_INT_STATUS)); 78 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n", 79 sdhci_readl(host, SDHCI_INT_ENABLE), 80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 81 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n", 82 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS), 83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 84 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n", 85 sdhci_readl(host, SDHCI_CAPABILITIES), 86 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 87 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n", 88 sdhci_readw(host, SDHCI_COMMAND), 89 sdhci_readl(host, SDHCI_MAX_CURRENT)); 90 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n", 91 sdhci_readl(host, SDHCI_RESPONSE), 92 sdhci_readl(host, SDHCI_RESPONSE + 4)); 93 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n", 94 sdhci_readl(host, SDHCI_RESPONSE + 8), 95 sdhci_readl(host, SDHCI_RESPONSE + 12)); 96 SDHCI_DUMP("Host ctl2: 0x%08x\n", 97 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 98 99 if (host->flags & SDHCI_USE_ADMA) { 100 if (host->flags & SDHCI_USE_64_BIT_DMA) { 101 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 102 sdhci_readl(host, SDHCI_ADMA_ERROR), 103 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI), 104 sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 105 } else { 106 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 107 sdhci_readl(host, SDHCI_ADMA_ERROR), 108 sdhci_readl(host, SDHCI_ADMA_ADDRESS)); 109 } 110 } 111 112 SDHCI_DUMP("============================================\n"); 113 } 114 EXPORT_SYMBOL_GPL(sdhci_dumpregs); 115 116 /*****************************************************************************\ 117 * * 118 * Low level functions * 119 * * 120 \*****************************************************************************/ 121 122 static void sdhci_do_enable_v4_mode(struct sdhci_host *host) 123 { 124 u16 ctrl2; 125 126 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 127 if (ctrl2 & SDHCI_CTRL_V4_MODE) 128 return; 129 130 ctrl2 |= SDHCI_CTRL_V4_MODE; 131 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 132 } 133 134 /* 135 * This can be called before sdhci_add_host() by Vendor's host controller 136 * driver to enable v4 mode if supported. 137 */ 138 void sdhci_enable_v4_mode(struct sdhci_host *host) 139 { 140 host->v4_mode = true; 141 sdhci_do_enable_v4_mode(host); 142 } 143 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); 144 145 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 146 { 147 return cmd->data || cmd->flags & MMC_RSP_BUSY; 148 } 149 150 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 151 { 152 u32 present; 153 154 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 155 !mmc_card_is_removable(host->mmc)) 156 return; 157 158 if (enable) { 159 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 160 SDHCI_CARD_PRESENT; 161 162 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 163 SDHCI_INT_CARD_INSERT; 164 } else { 165 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 166 } 167 168 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 169 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 170 } 171 172 static void sdhci_enable_card_detection(struct sdhci_host *host) 173 { 174 sdhci_set_card_detection(host, true); 175 } 176 177 static void sdhci_disable_card_detection(struct sdhci_host *host) 178 { 179 sdhci_set_card_detection(host, false); 180 } 181 182 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 183 { 184 if (host->bus_on) 185 return; 186 host->bus_on = true; 187 pm_runtime_get_noresume(host->mmc->parent); 188 } 189 190 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 191 { 192 if (!host->bus_on) 193 return; 194 host->bus_on = false; 195 pm_runtime_put_noidle(host->mmc->parent); 196 } 197 198 void sdhci_reset(struct sdhci_host *host, u8 mask) 199 { 200 ktime_t timeout; 201 202 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 203 204 if (mask & SDHCI_RESET_ALL) { 205 host->clock = 0; 206 /* Reset-all turns off SD Bus Power */ 207 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 208 sdhci_runtime_pm_bus_off(host); 209 } 210 211 /* Wait max 100 ms */ 212 timeout = ktime_add_ms(ktime_get(), 100); 213 214 /* hw clears the bit when it's done */ 215 while (1) { 216 bool timedout = ktime_after(ktime_get(), timeout); 217 218 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) 219 break; 220 if (timedout) { 221 pr_err("%s: Reset 0x%x never completed.\n", 222 mmc_hostname(host->mmc), (int)mask); 223 sdhci_dumpregs(host); 224 return; 225 } 226 udelay(10); 227 } 228 } 229 EXPORT_SYMBOL_GPL(sdhci_reset); 230 231 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 232 { 233 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 234 struct mmc_host *mmc = host->mmc; 235 236 if (!mmc->ops->get_cd(mmc)) 237 return; 238 } 239 240 host->ops->reset(host, mask); 241 242 if (mask & SDHCI_RESET_ALL) { 243 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 244 if (host->ops->enable_dma) 245 host->ops->enable_dma(host); 246 } 247 248 /* Resetting the controller clears many */ 249 host->preset_enabled = false; 250 } 251 } 252 253 static void sdhci_set_default_irqs(struct sdhci_host *host) 254 { 255 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 256 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 257 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 258 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 259 SDHCI_INT_RESPONSE; 260 261 if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 262 host->tuning_mode == SDHCI_TUNING_MODE_3) 263 host->ier |= SDHCI_INT_RETUNE; 264 265 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 266 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 267 } 268 269 static void sdhci_config_dma(struct sdhci_host *host) 270 { 271 u8 ctrl; 272 u16 ctrl2; 273 274 if (host->version < SDHCI_SPEC_200) 275 return; 276 277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 278 279 /* 280 * Always adjust the DMA selection as some controllers 281 * (e.g. JMicron) can't do PIO properly when the selection 282 * is ADMA. 283 */ 284 ctrl &= ~SDHCI_CTRL_DMA_MASK; 285 if (!(host->flags & SDHCI_REQ_USE_DMA)) 286 goto out; 287 288 /* Note if DMA Select is zero then SDMA is selected */ 289 if (host->flags & SDHCI_USE_ADMA) 290 ctrl |= SDHCI_CTRL_ADMA32; 291 292 if (host->flags & SDHCI_USE_64_BIT_DMA) { 293 /* 294 * If v4 mode, all supported DMA can be 64-bit addressing if 295 * controller supports 64-bit system address, otherwise only 296 * ADMA can support 64-bit addressing. 297 */ 298 if (host->v4_mode) { 299 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 300 ctrl2 |= SDHCI_CTRL_64BIT_ADDR; 301 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 302 } else if (host->flags & SDHCI_USE_ADMA) { 303 /* 304 * Don't need to undo SDHCI_CTRL_ADMA32 in order to 305 * set SDHCI_CTRL_ADMA64. 306 */ 307 ctrl |= SDHCI_CTRL_ADMA64; 308 } 309 } 310 311 out: 312 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 313 } 314 315 static void sdhci_init(struct sdhci_host *host, int soft) 316 { 317 struct mmc_host *mmc = host->mmc; 318 319 if (soft) 320 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 321 else 322 sdhci_do_reset(host, SDHCI_RESET_ALL); 323 324 if (host->v4_mode) 325 sdhci_do_enable_v4_mode(host); 326 327 sdhci_set_default_irqs(host); 328 329 host->cqe_on = false; 330 331 if (soft) { 332 /* force clock reconfiguration */ 333 host->clock = 0; 334 mmc->ops->set_ios(mmc, &mmc->ios); 335 } 336 } 337 338 static void sdhci_reinit(struct sdhci_host *host) 339 { 340 sdhci_init(host, 0); 341 sdhci_enable_card_detection(host); 342 } 343 344 static void __sdhci_led_activate(struct sdhci_host *host) 345 { 346 u8 ctrl; 347 348 if (host->quirks & SDHCI_QUIRK_NO_LED) 349 return; 350 351 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 352 ctrl |= SDHCI_CTRL_LED; 353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 354 } 355 356 static void __sdhci_led_deactivate(struct sdhci_host *host) 357 { 358 u8 ctrl; 359 360 if (host->quirks & SDHCI_QUIRK_NO_LED) 361 return; 362 363 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 364 ctrl &= ~SDHCI_CTRL_LED; 365 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 366 } 367 368 #if IS_REACHABLE(CONFIG_LEDS_CLASS) 369 static void sdhci_led_control(struct led_classdev *led, 370 enum led_brightness brightness) 371 { 372 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 373 unsigned long flags; 374 375 spin_lock_irqsave(&host->lock, flags); 376 377 if (host->runtime_suspended) 378 goto out; 379 380 if (brightness == LED_OFF) 381 __sdhci_led_deactivate(host); 382 else 383 __sdhci_led_activate(host); 384 out: 385 spin_unlock_irqrestore(&host->lock, flags); 386 } 387 388 static int sdhci_led_register(struct sdhci_host *host) 389 { 390 struct mmc_host *mmc = host->mmc; 391 392 if (host->quirks & SDHCI_QUIRK_NO_LED) 393 return 0; 394 395 snprintf(host->led_name, sizeof(host->led_name), 396 "%s::", mmc_hostname(mmc)); 397 398 host->led.name = host->led_name; 399 host->led.brightness = LED_OFF; 400 host->led.default_trigger = mmc_hostname(mmc); 401 host->led.brightness_set = sdhci_led_control; 402 403 return led_classdev_register(mmc_dev(mmc), &host->led); 404 } 405 406 static void sdhci_led_unregister(struct sdhci_host *host) 407 { 408 if (host->quirks & SDHCI_QUIRK_NO_LED) 409 return; 410 411 led_classdev_unregister(&host->led); 412 } 413 414 static inline void sdhci_led_activate(struct sdhci_host *host) 415 { 416 } 417 418 static inline void sdhci_led_deactivate(struct sdhci_host *host) 419 { 420 } 421 422 #else 423 424 static inline int sdhci_led_register(struct sdhci_host *host) 425 { 426 return 0; 427 } 428 429 static inline void sdhci_led_unregister(struct sdhci_host *host) 430 { 431 } 432 433 static inline void sdhci_led_activate(struct sdhci_host *host) 434 { 435 __sdhci_led_activate(host); 436 } 437 438 static inline void sdhci_led_deactivate(struct sdhci_host *host) 439 { 440 __sdhci_led_deactivate(host); 441 } 442 443 #endif 444 445 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 446 unsigned long timeout) 447 { 448 if (sdhci_data_line_cmd(mrq->cmd)) 449 mod_timer(&host->data_timer, timeout); 450 else 451 mod_timer(&host->timer, timeout); 452 } 453 454 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 455 { 456 if (sdhci_data_line_cmd(mrq->cmd)) 457 del_timer(&host->data_timer); 458 else 459 del_timer(&host->timer); 460 } 461 462 static inline bool sdhci_has_requests(struct sdhci_host *host) 463 { 464 return host->cmd || host->data_cmd; 465 } 466 467 /*****************************************************************************\ 468 * * 469 * Core functions * 470 * * 471 \*****************************************************************************/ 472 473 static void sdhci_read_block_pio(struct sdhci_host *host) 474 { 475 unsigned long flags; 476 size_t blksize, len, chunk; 477 u32 uninitialized_var(scratch); 478 u8 *buf; 479 480 DBG("PIO reading\n"); 481 482 blksize = host->data->blksz; 483 chunk = 0; 484 485 local_irq_save(flags); 486 487 while (blksize) { 488 BUG_ON(!sg_miter_next(&host->sg_miter)); 489 490 len = min(host->sg_miter.length, blksize); 491 492 blksize -= len; 493 host->sg_miter.consumed = len; 494 495 buf = host->sg_miter.addr; 496 497 while (len) { 498 if (chunk == 0) { 499 scratch = sdhci_readl(host, SDHCI_BUFFER); 500 chunk = 4; 501 } 502 503 *buf = scratch & 0xFF; 504 505 buf++; 506 scratch >>= 8; 507 chunk--; 508 len--; 509 } 510 } 511 512 sg_miter_stop(&host->sg_miter); 513 514 local_irq_restore(flags); 515 } 516 517 static void sdhci_write_block_pio(struct sdhci_host *host) 518 { 519 unsigned long flags; 520 size_t blksize, len, chunk; 521 u32 scratch; 522 u8 *buf; 523 524 DBG("PIO writing\n"); 525 526 blksize = host->data->blksz; 527 chunk = 0; 528 scratch = 0; 529 530 local_irq_save(flags); 531 532 while (blksize) { 533 BUG_ON(!sg_miter_next(&host->sg_miter)); 534 535 len = min(host->sg_miter.length, blksize); 536 537 blksize -= len; 538 host->sg_miter.consumed = len; 539 540 buf = host->sg_miter.addr; 541 542 while (len) { 543 scratch |= (u32)*buf << (chunk * 8); 544 545 buf++; 546 chunk++; 547 len--; 548 549 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 550 sdhci_writel(host, scratch, SDHCI_BUFFER); 551 chunk = 0; 552 scratch = 0; 553 } 554 } 555 } 556 557 sg_miter_stop(&host->sg_miter); 558 559 local_irq_restore(flags); 560 } 561 562 static void sdhci_transfer_pio(struct sdhci_host *host) 563 { 564 u32 mask; 565 566 if (host->blocks == 0) 567 return; 568 569 if (host->data->flags & MMC_DATA_READ) 570 mask = SDHCI_DATA_AVAILABLE; 571 else 572 mask = SDHCI_SPACE_AVAILABLE; 573 574 /* 575 * Some controllers (JMicron JMB38x) mess up the buffer bits 576 * for transfers < 4 bytes. As long as it is just one block, 577 * we can ignore the bits. 578 */ 579 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 580 (host->data->blocks == 1)) 581 mask = ~0; 582 583 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 584 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 585 udelay(100); 586 587 if (host->data->flags & MMC_DATA_READ) 588 sdhci_read_block_pio(host); 589 else 590 sdhci_write_block_pio(host); 591 592 host->blocks--; 593 if (host->blocks == 0) 594 break; 595 } 596 597 DBG("PIO transfer complete.\n"); 598 } 599 600 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 601 struct mmc_data *data, int cookie) 602 { 603 int sg_count; 604 605 /* 606 * If the data buffers are already mapped, return the previous 607 * dma_map_sg() result. 608 */ 609 if (data->host_cookie == COOKIE_PRE_MAPPED) 610 return data->sg_count; 611 612 /* Bounce write requests to the bounce buffer */ 613 if (host->bounce_buffer) { 614 unsigned int length = data->blksz * data->blocks; 615 616 if (length > host->bounce_buffer_size) { 617 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n", 618 mmc_hostname(host->mmc), length, 619 host->bounce_buffer_size); 620 return -EIO; 621 } 622 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) { 623 /* Copy the data to the bounce buffer */ 624 sg_copy_to_buffer(data->sg, data->sg_len, 625 host->bounce_buffer, 626 length); 627 } 628 /* Switch ownership to the DMA */ 629 dma_sync_single_for_device(host->mmc->parent, 630 host->bounce_addr, 631 host->bounce_buffer_size, 632 mmc_get_dma_dir(data)); 633 /* Just a dummy value */ 634 sg_count = 1; 635 } else { 636 /* Just access the data directly from memory */ 637 sg_count = dma_map_sg(mmc_dev(host->mmc), 638 data->sg, data->sg_len, 639 mmc_get_dma_dir(data)); 640 } 641 642 if (sg_count == 0) 643 return -ENOSPC; 644 645 data->sg_count = sg_count; 646 data->host_cookie = cookie; 647 648 return sg_count; 649 } 650 651 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 652 { 653 local_irq_save(*flags); 654 return kmap_atomic(sg_page(sg)) + sg->offset; 655 } 656 657 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 658 { 659 kunmap_atomic(buffer); 660 local_irq_restore(*flags); 661 } 662 663 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, 664 dma_addr_t addr, int len, unsigned int cmd) 665 { 666 struct sdhci_adma2_64_desc *dma_desc = *desc; 667 668 /* 32-bit and 64-bit descriptors have these members in same position */ 669 dma_desc->cmd = cpu_to_le16(cmd); 670 dma_desc->len = cpu_to_le16(len); 671 dma_desc->addr_lo = cpu_to_le32((u32)addr); 672 673 if (host->flags & SDHCI_USE_64_BIT_DMA) 674 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 675 676 *desc += host->desc_sz; 677 } 678 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc); 679 680 static inline void __sdhci_adma_write_desc(struct sdhci_host *host, 681 void **desc, dma_addr_t addr, 682 int len, unsigned int cmd) 683 { 684 if (host->ops->adma_write_desc) 685 host->ops->adma_write_desc(host, desc, addr, len, cmd); 686 else 687 sdhci_adma_write_desc(host, desc, addr, len, cmd); 688 } 689 690 static void sdhci_adma_mark_end(void *desc) 691 { 692 struct sdhci_adma2_64_desc *dma_desc = desc; 693 694 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 695 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 696 } 697 698 static void sdhci_adma_table_pre(struct sdhci_host *host, 699 struct mmc_data *data, int sg_count) 700 { 701 struct scatterlist *sg; 702 unsigned long flags; 703 dma_addr_t addr, align_addr; 704 void *desc, *align; 705 char *buffer; 706 int len, offset, i; 707 708 /* 709 * The spec does not specify endianness of descriptor table. 710 * We currently guess that it is LE. 711 */ 712 713 host->sg_count = sg_count; 714 715 desc = host->adma_table; 716 align = host->align_buffer; 717 718 align_addr = host->align_addr; 719 720 for_each_sg(data->sg, sg, host->sg_count, i) { 721 addr = sg_dma_address(sg); 722 len = sg_dma_len(sg); 723 724 /* 725 * The SDHCI specification states that ADMA addresses must 726 * be 32-bit aligned. If they aren't, then we use a bounce 727 * buffer for the (up to three) bytes that screw up the 728 * alignment. 729 */ 730 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 731 SDHCI_ADMA2_MASK; 732 if (offset) { 733 if (data->flags & MMC_DATA_WRITE) { 734 buffer = sdhci_kmap_atomic(sg, &flags); 735 memcpy(align, buffer, offset); 736 sdhci_kunmap_atomic(buffer, &flags); 737 } 738 739 /* tran, valid */ 740 __sdhci_adma_write_desc(host, &desc, align_addr, 741 offset, ADMA2_TRAN_VALID); 742 743 BUG_ON(offset > 65536); 744 745 align += SDHCI_ADMA2_ALIGN; 746 align_addr += SDHCI_ADMA2_ALIGN; 747 748 addr += offset; 749 len -= offset; 750 } 751 752 BUG_ON(len > 65536); 753 754 /* tran, valid */ 755 if (len) 756 __sdhci_adma_write_desc(host, &desc, addr, len, 757 ADMA2_TRAN_VALID); 758 759 /* 760 * If this triggers then we have a calculation bug 761 * somewhere. :/ 762 */ 763 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 764 } 765 766 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 767 /* Mark the last descriptor as the terminating descriptor */ 768 if (desc != host->adma_table) { 769 desc -= host->desc_sz; 770 sdhci_adma_mark_end(desc); 771 } 772 } else { 773 /* Add a terminating entry - nop, end, valid */ 774 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID); 775 } 776 } 777 778 static void sdhci_adma_table_post(struct sdhci_host *host, 779 struct mmc_data *data) 780 { 781 struct scatterlist *sg; 782 int i, size; 783 void *align; 784 char *buffer; 785 unsigned long flags; 786 787 if (data->flags & MMC_DATA_READ) { 788 bool has_unaligned = false; 789 790 /* Do a quick scan of the SG list for any unaligned mappings */ 791 for_each_sg(data->sg, sg, host->sg_count, i) 792 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 793 has_unaligned = true; 794 break; 795 } 796 797 if (has_unaligned) { 798 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 799 data->sg_len, DMA_FROM_DEVICE); 800 801 align = host->align_buffer; 802 803 for_each_sg(data->sg, sg, host->sg_count, i) { 804 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 805 size = SDHCI_ADMA2_ALIGN - 806 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 807 808 buffer = sdhci_kmap_atomic(sg, &flags); 809 memcpy(buffer, align, size); 810 sdhci_kunmap_atomic(buffer, &flags); 811 812 align += SDHCI_ADMA2_ALIGN; 813 } 814 } 815 } 816 } 817 } 818 819 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host) 820 { 821 if (host->bounce_buffer) 822 return host->bounce_addr; 823 else 824 return sg_dma_address(host->data->sg); 825 } 826 827 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr) 828 { 829 if (host->v4_mode) { 830 sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS); 831 if (host->flags & SDHCI_USE_64_BIT_DMA) 832 sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI); 833 } else { 834 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS); 835 } 836 } 837 838 static unsigned int sdhci_target_timeout(struct sdhci_host *host, 839 struct mmc_command *cmd, 840 struct mmc_data *data) 841 { 842 unsigned int target_timeout; 843 844 /* timeout in us */ 845 if (!data) { 846 target_timeout = cmd->busy_timeout * 1000; 847 } else { 848 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 849 if (host->clock && data->timeout_clks) { 850 unsigned long long val; 851 852 /* 853 * data->timeout_clks is in units of clock cycles. 854 * host->clock is in Hz. target_timeout is in us. 855 * Hence, us = 1000000 * cycles / Hz. Round up. 856 */ 857 val = 1000000ULL * data->timeout_clks; 858 if (do_div(val, host->clock)) 859 target_timeout++; 860 target_timeout += val; 861 } 862 } 863 864 return target_timeout; 865 } 866 867 static void sdhci_calc_sw_timeout(struct sdhci_host *host, 868 struct mmc_command *cmd) 869 { 870 struct mmc_data *data = cmd->data; 871 struct mmc_host *mmc = host->mmc; 872 struct mmc_ios *ios = &mmc->ios; 873 unsigned char bus_width = 1 << ios->bus_width; 874 unsigned int blksz; 875 unsigned int freq; 876 u64 target_timeout; 877 u64 transfer_time; 878 879 target_timeout = sdhci_target_timeout(host, cmd, data); 880 target_timeout *= NSEC_PER_USEC; 881 882 if (data) { 883 blksz = data->blksz; 884 freq = host->mmc->actual_clock ? : host->clock; 885 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width); 886 do_div(transfer_time, freq); 887 /* multiply by '2' to account for any unknowns */ 888 transfer_time = transfer_time * 2; 889 /* calculate timeout for the entire data */ 890 host->data_timeout = data->blocks * target_timeout + 891 transfer_time; 892 } else { 893 host->data_timeout = target_timeout; 894 } 895 896 if (host->data_timeout) 897 host->data_timeout += MMC_CMD_TRANSFER_TIME; 898 } 899 900 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd, 901 bool *too_big) 902 { 903 u8 count; 904 struct mmc_data *data; 905 unsigned target_timeout, current_timeout; 906 907 *too_big = true; 908 909 /* 910 * If the host controller provides us with an incorrect timeout 911 * value, just skip the check and use 0xE. The hardware may take 912 * longer to time out, but that's much better than having a too-short 913 * timeout value. 914 */ 915 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 916 return 0xE; 917 918 /* Unspecified command, asume max */ 919 if (cmd == NULL) 920 return 0xE; 921 922 data = cmd->data; 923 /* Unspecified timeout, assume max */ 924 if (!data && !cmd->busy_timeout) 925 return 0xE; 926 927 /* timeout in us */ 928 target_timeout = sdhci_target_timeout(host, cmd, data); 929 930 /* 931 * Figure out needed cycles. 932 * We do this in steps in order to fit inside a 32 bit int. 933 * The first step is the minimum timeout, which will have a 934 * minimum resolution of 6 bits: 935 * (1) 2^13*1000 > 2^22, 936 * (2) host->timeout_clk < 2^16 937 * => 938 * (1) / (2) > 2^6 939 */ 940 count = 0; 941 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 942 while (current_timeout < target_timeout) { 943 count++; 944 current_timeout <<= 1; 945 if (count >= 0xF) 946 break; 947 } 948 949 if (count >= 0xF) { 950 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)) 951 DBG("Too large timeout 0x%x requested for CMD%d!\n", 952 count, cmd->opcode); 953 count = 0xE; 954 } else { 955 *too_big = false; 956 } 957 958 return count; 959 } 960 961 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 962 { 963 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 964 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 965 966 if (host->flags & SDHCI_REQ_USE_DMA) 967 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 968 else 969 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 970 971 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12)) 972 host->ier |= SDHCI_INT_AUTO_CMD_ERR; 973 else 974 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR; 975 976 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 977 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 978 } 979 980 static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable) 981 { 982 if (enable) 983 host->ier |= SDHCI_INT_DATA_TIMEOUT; 984 else 985 host->ier &= ~SDHCI_INT_DATA_TIMEOUT; 986 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 987 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 988 } 989 990 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 991 { 992 u8 count; 993 994 if (host->ops->set_timeout) { 995 host->ops->set_timeout(host, cmd); 996 } else { 997 bool too_big = false; 998 999 count = sdhci_calc_timeout(host, cmd, &too_big); 1000 1001 if (too_big && 1002 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) { 1003 sdhci_calc_sw_timeout(host, cmd); 1004 sdhci_set_data_timeout_irq(host, false); 1005 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) { 1006 sdhci_set_data_timeout_irq(host, true); 1007 } 1008 1009 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 1010 } 1011 } 1012 1013 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 1014 { 1015 struct mmc_data *data = cmd->data; 1016 1017 host->data_timeout = 0; 1018 1019 if (sdhci_data_line_cmd(cmd)) 1020 sdhci_set_timeout(host, cmd); 1021 1022 if (!data) 1023 return; 1024 1025 WARN_ON(host->data); 1026 1027 /* Sanity checks */ 1028 BUG_ON(data->blksz * data->blocks > 524288); 1029 BUG_ON(data->blksz > host->mmc->max_blk_size); 1030 BUG_ON(data->blocks > 65535); 1031 1032 host->data = data; 1033 host->data_early = 0; 1034 host->data->bytes_xfered = 0; 1035 1036 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 1037 struct scatterlist *sg; 1038 unsigned int length_mask, offset_mask; 1039 int i; 1040 1041 host->flags |= SDHCI_REQ_USE_DMA; 1042 1043 /* 1044 * FIXME: This doesn't account for merging when mapping the 1045 * scatterlist. 1046 * 1047 * The assumption here being that alignment and lengths are 1048 * the same after DMA mapping to device address space. 1049 */ 1050 length_mask = 0; 1051 offset_mask = 0; 1052 if (host->flags & SDHCI_USE_ADMA) { 1053 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 1054 length_mask = 3; 1055 /* 1056 * As we use up to 3 byte chunks to work 1057 * around alignment problems, we need to 1058 * check the offset as well. 1059 */ 1060 offset_mask = 3; 1061 } 1062 } else { 1063 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 1064 length_mask = 3; 1065 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 1066 offset_mask = 3; 1067 } 1068 1069 if (unlikely(length_mask | offset_mask)) { 1070 for_each_sg(data->sg, sg, data->sg_len, i) { 1071 if (sg->length & length_mask) { 1072 DBG("Reverting to PIO because of transfer size (%d)\n", 1073 sg->length); 1074 host->flags &= ~SDHCI_REQ_USE_DMA; 1075 break; 1076 } 1077 if (sg->offset & offset_mask) { 1078 DBG("Reverting to PIO because of bad alignment\n"); 1079 host->flags &= ~SDHCI_REQ_USE_DMA; 1080 break; 1081 } 1082 } 1083 } 1084 } 1085 1086 if (host->flags & SDHCI_REQ_USE_DMA) { 1087 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 1088 1089 if (sg_cnt <= 0) { 1090 /* 1091 * This only happens when someone fed 1092 * us an invalid request. 1093 */ 1094 WARN_ON(1); 1095 host->flags &= ~SDHCI_REQ_USE_DMA; 1096 } else if (host->flags & SDHCI_USE_ADMA) { 1097 sdhci_adma_table_pre(host, data, sg_cnt); 1098 1099 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 1100 if (host->flags & SDHCI_USE_64_BIT_DMA) 1101 sdhci_writel(host, 1102 (u64)host->adma_addr >> 32, 1103 SDHCI_ADMA_ADDRESS_HI); 1104 } else { 1105 WARN_ON(sg_cnt != 1); 1106 sdhci_set_sdma_addr(host, sdhci_sdma_address(host)); 1107 } 1108 } 1109 1110 sdhci_config_dma(host); 1111 1112 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 1113 int flags; 1114 1115 flags = SG_MITER_ATOMIC; 1116 if (host->data->flags & MMC_DATA_READ) 1117 flags |= SG_MITER_TO_SG; 1118 else 1119 flags |= SG_MITER_FROM_SG; 1120 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 1121 host->blocks = data->blocks; 1122 } 1123 1124 sdhci_set_transfer_irqs(host); 1125 1126 /* Set the DMA boundary value and block size */ 1127 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), 1128 SDHCI_BLOCK_SIZE); 1129 1130 /* 1131 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count 1132 * can be supported, in that case 16-bit block count register must be 0. 1133 */ 1134 if (host->version >= SDHCI_SPEC_410 && host->v4_mode && 1135 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { 1136 if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) 1137 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); 1138 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); 1139 } else { 1140 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 1141 } 1142 } 1143 1144 static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 1145 struct mmc_request *mrq) 1146 { 1147 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 1148 !mrq->cap_cmd_during_tfr; 1149 } 1150 1151 static inline void sdhci_auto_cmd_select(struct sdhci_host *host, 1152 struct mmc_command *cmd, 1153 u16 *mode) 1154 { 1155 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && 1156 (cmd->opcode != SD_IO_RW_EXTENDED); 1157 bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); 1158 u16 ctrl2; 1159 1160 /* 1161 * In case of Version 4.10 or later, use of 'Auto CMD Auto 1162 * Select' is recommended rather than use of 'Auto CMD12 1163 * Enable' or 'Auto CMD23 Enable'. 1164 */ 1165 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { 1166 *mode |= SDHCI_TRNS_AUTO_SEL; 1167 1168 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1169 if (use_cmd23) 1170 ctrl2 |= SDHCI_CMD23_ENABLE; 1171 else 1172 ctrl2 &= ~SDHCI_CMD23_ENABLE; 1173 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 1174 1175 return; 1176 } 1177 1178 /* 1179 * If we are sending CMD23, CMD12 never gets sent 1180 * on successful completion (so no Auto-CMD12). 1181 */ 1182 if (use_cmd12) 1183 *mode |= SDHCI_TRNS_AUTO_CMD12; 1184 else if (use_cmd23) 1185 *mode |= SDHCI_TRNS_AUTO_CMD23; 1186 } 1187 1188 static void sdhci_set_transfer_mode(struct sdhci_host *host, 1189 struct mmc_command *cmd) 1190 { 1191 u16 mode = 0; 1192 struct mmc_data *data = cmd->data; 1193 1194 if (data == NULL) { 1195 if (host->quirks2 & 1196 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 1197 /* must not clear SDHCI_TRANSFER_MODE when tuning */ 1198 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 1199 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1200 } else { 1201 /* clear Auto CMD settings for no data CMDs */ 1202 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1203 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 1204 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 1205 } 1206 return; 1207 } 1208 1209 WARN_ON(!host->data); 1210 1211 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1212 mode = SDHCI_TRNS_BLK_CNT_EN; 1213 1214 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 1215 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 1216 sdhci_auto_cmd_select(host, cmd, &mode); 1217 if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) 1218 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 1219 } 1220 1221 if (data->flags & MMC_DATA_READ) 1222 mode |= SDHCI_TRNS_READ; 1223 if (host->flags & SDHCI_REQ_USE_DMA) 1224 mode |= SDHCI_TRNS_DMA; 1225 1226 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1227 } 1228 1229 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 1230 { 1231 return (!(host->flags & SDHCI_DEVICE_DEAD) && 1232 ((mrq->cmd && mrq->cmd->error) || 1233 (mrq->sbc && mrq->sbc->error) || 1234 (mrq->data && mrq->data->stop && mrq->data->stop->error) || 1235 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 1236 } 1237 1238 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 1239 { 1240 int i; 1241 1242 if (host->cmd && host->cmd->mrq == mrq) 1243 host->cmd = NULL; 1244 1245 if (host->data_cmd && host->data_cmd->mrq == mrq) 1246 host->data_cmd = NULL; 1247 1248 if (host->data && host->data->mrq == mrq) 1249 host->data = NULL; 1250 1251 if (sdhci_needs_reset(host, mrq)) 1252 host->pending_reset = true; 1253 1254 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 1255 if (host->mrqs_done[i] == mrq) { 1256 WARN_ON(1); 1257 return; 1258 } 1259 } 1260 1261 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 1262 if (!host->mrqs_done[i]) { 1263 host->mrqs_done[i] = mrq; 1264 break; 1265 } 1266 } 1267 1268 WARN_ON(i >= SDHCI_MAX_MRQS); 1269 1270 sdhci_del_timer(host, mrq); 1271 1272 if (!sdhci_has_requests(host)) 1273 sdhci_led_deactivate(host); 1274 } 1275 1276 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 1277 { 1278 __sdhci_finish_mrq(host, mrq); 1279 1280 queue_work(host->complete_wq, &host->complete_work); 1281 } 1282 1283 static void sdhci_finish_data(struct sdhci_host *host) 1284 { 1285 struct mmc_command *data_cmd = host->data_cmd; 1286 struct mmc_data *data = host->data; 1287 1288 host->data = NULL; 1289 host->data_cmd = NULL; 1290 1291 /* 1292 * The controller needs a reset of internal state machines upon error 1293 * conditions. 1294 */ 1295 if (data->error) { 1296 if (!host->cmd || host->cmd == data_cmd) 1297 sdhci_do_reset(host, SDHCI_RESET_CMD); 1298 sdhci_do_reset(host, SDHCI_RESET_DATA); 1299 } 1300 1301 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1302 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1303 sdhci_adma_table_post(host, data); 1304 1305 /* 1306 * The specification states that the block count register must 1307 * be updated, but it does not specify at what point in the 1308 * data flow. That makes the register entirely useless to read 1309 * back so we have to assume that nothing made it to the card 1310 * in the event of an error. 1311 */ 1312 if (data->error) 1313 data->bytes_xfered = 0; 1314 else 1315 data->bytes_xfered = data->blksz * data->blocks; 1316 1317 /* 1318 * Need to send CMD12 if - 1319 * a) open-ended multiblock transfer (no CMD23) 1320 * b) error in multiblock transfer 1321 */ 1322 if (data->stop && 1323 (data->error || 1324 !data->mrq->sbc)) { 1325 /* 1326 * 'cap_cmd_during_tfr' request must not use the command line 1327 * after mmc_command_done() has been called. It is upper layer's 1328 * responsibility to send the stop command if required. 1329 */ 1330 if (data->mrq->cap_cmd_during_tfr) { 1331 __sdhci_finish_mrq(host, data->mrq); 1332 } else { 1333 /* Avoid triggering warning in sdhci_send_command() */ 1334 host->cmd = NULL; 1335 sdhci_send_command(host, data->stop); 1336 } 1337 } else { 1338 __sdhci_finish_mrq(host, data->mrq); 1339 } 1340 } 1341 1342 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1343 { 1344 int flags; 1345 u32 mask; 1346 unsigned long timeout; 1347 1348 WARN_ON(host->cmd); 1349 1350 /* Initially, a command has no error */ 1351 cmd->error = 0; 1352 1353 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1354 cmd->opcode == MMC_STOP_TRANSMISSION) 1355 cmd->flags |= MMC_RSP_BUSY; 1356 1357 /* Wait max 10 ms */ 1358 timeout = 10; 1359 1360 mask = SDHCI_CMD_INHIBIT; 1361 if (sdhci_data_line_cmd(cmd)) 1362 mask |= SDHCI_DATA_INHIBIT; 1363 1364 /* We shouldn't wait for data inihibit for stop commands, even 1365 though they might use busy signaling */ 1366 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 1367 mask &= ~SDHCI_DATA_INHIBIT; 1368 1369 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1370 if (timeout == 0) { 1371 pr_err("%s: Controller never released inhibit bit(s).\n", 1372 mmc_hostname(host->mmc)); 1373 sdhci_dumpregs(host); 1374 cmd->error = -EIO; 1375 sdhci_finish_mrq(host, cmd->mrq); 1376 return; 1377 } 1378 timeout--; 1379 mdelay(1); 1380 } 1381 1382 host->cmd = cmd; 1383 if (sdhci_data_line_cmd(cmd)) { 1384 WARN_ON(host->data_cmd); 1385 host->data_cmd = cmd; 1386 } 1387 1388 sdhci_prepare_data(host, cmd); 1389 1390 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1391 1392 sdhci_set_transfer_mode(host, cmd); 1393 1394 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1395 pr_err("%s: Unsupported response type!\n", 1396 mmc_hostname(host->mmc)); 1397 cmd->error = -EINVAL; 1398 sdhci_finish_mrq(host, cmd->mrq); 1399 return; 1400 } 1401 1402 if (!(cmd->flags & MMC_RSP_PRESENT)) 1403 flags = SDHCI_CMD_RESP_NONE; 1404 else if (cmd->flags & MMC_RSP_136) 1405 flags = SDHCI_CMD_RESP_LONG; 1406 else if (cmd->flags & MMC_RSP_BUSY) 1407 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1408 else 1409 flags = SDHCI_CMD_RESP_SHORT; 1410 1411 if (cmd->flags & MMC_RSP_CRC) 1412 flags |= SDHCI_CMD_CRC; 1413 if (cmd->flags & MMC_RSP_OPCODE) 1414 flags |= SDHCI_CMD_INDEX; 1415 1416 /* CMD19 is special in that the Data Present Select should be set */ 1417 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1418 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1419 flags |= SDHCI_CMD_DATA; 1420 1421 timeout = jiffies; 1422 if (host->data_timeout) 1423 timeout += nsecs_to_jiffies(host->data_timeout); 1424 else if (!cmd->data && cmd->busy_timeout > 9000) 1425 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1426 else 1427 timeout += 10 * HZ; 1428 sdhci_mod_timer(host, cmd->mrq, timeout); 1429 1430 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1431 } 1432 EXPORT_SYMBOL_GPL(sdhci_send_command); 1433 1434 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd) 1435 { 1436 int i, reg; 1437 1438 for (i = 0; i < 4; i++) { 1439 reg = SDHCI_RESPONSE + (3 - i) * 4; 1440 cmd->resp[i] = sdhci_readl(host, reg); 1441 } 1442 1443 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC) 1444 return; 1445 1446 /* CRC is stripped so we need to do some shifting */ 1447 for (i = 0; i < 4; i++) { 1448 cmd->resp[i] <<= 8; 1449 if (i != 3) 1450 cmd->resp[i] |= cmd->resp[i + 1] >> 24; 1451 } 1452 } 1453 1454 static void sdhci_finish_command(struct sdhci_host *host) 1455 { 1456 struct mmc_command *cmd = host->cmd; 1457 1458 host->cmd = NULL; 1459 1460 if (cmd->flags & MMC_RSP_PRESENT) { 1461 if (cmd->flags & MMC_RSP_136) { 1462 sdhci_read_rsp_136(host, cmd); 1463 } else { 1464 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1465 } 1466 } 1467 1468 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 1469 mmc_command_done(host->mmc, cmd->mrq); 1470 1471 /* 1472 * The host can send and interrupt when the busy state has 1473 * ended, allowing us to wait without wasting CPU cycles. 1474 * The busy signal uses DAT0 so this is similar to waiting 1475 * for data to complete. 1476 * 1477 * Note: The 1.0 specification is a bit ambiguous about this 1478 * feature so there might be some problems with older 1479 * controllers. 1480 */ 1481 if (cmd->flags & MMC_RSP_BUSY) { 1482 if (cmd->data) { 1483 DBG("Cannot wait for busy signal when also doing a data transfer"); 1484 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1485 cmd == host->data_cmd) { 1486 /* Command complete before busy is ended */ 1487 return; 1488 } 1489 } 1490 1491 /* Finished CMD23, now send actual command. */ 1492 if (cmd == cmd->mrq->sbc) { 1493 sdhci_send_command(host, cmd->mrq->cmd); 1494 } else { 1495 1496 /* Processed actual command. */ 1497 if (host->data && host->data_early) 1498 sdhci_finish_data(host); 1499 1500 if (!cmd->data) 1501 __sdhci_finish_mrq(host, cmd->mrq); 1502 } 1503 } 1504 1505 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1506 { 1507 u16 preset = 0; 1508 1509 switch (host->timing) { 1510 case MMC_TIMING_UHS_SDR12: 1511 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1512 break; 1513 case MMC_TIMING_UHS_SDR25: 1514 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1515 break; 1516 case MMC_TIMING_UHS_SDR50: 1517 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1518 break; 1519 case MMC_TIMING_UHS_SDR104: 1520 case MMC_TIMING_MMC_HS200: 1521 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1522 break; 1523 case MMC_TIMING_UHS_DDR50: 1524 case MMC_TIMING_MMC_DDR52: 1525 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1526 break; 1527 case MMC_TIMING_MMC_HS400: 1528 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1529 break; 1530 default: 1531 pr_warn("%s: Invalid UHS-I mode selected\n", 1532 mmc_hostname(host->mmc)); 1533 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1534 break; 1535 } 1536 return preset; 1537 } 1538 1539 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1540 unsigned int *actual_clock) 1541 { 1542 int div = 0; /* Initialized for compiler warning */ 1543 int real_div = div, clk_mul = 1; 1544 u16 clk = 0; 1545 bool switch_base_clk = false; 1546 1547 if (host->version >= SDHCI_SPEC_300) { 1548 if (host->preset_enabled) { 1549 u16 pre_val; 1550 1551 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1552 pre_val = sdhci_get_preset_value(host); 1553 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1554 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1555 if (host->clk_mul && 1556 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1557 clk = SDHCI_PROG_CLOCK_MODE; 1558 real_div = div + 1; 1559 clk_mul = host->clk_mul; 1560 } else { 1561 real_div = max_t(int, 1, div << 1); 1562 } 1563 goto clock_set; 1564 } 1565 1566 /* 1567 * Check if the Host Controller supports Programmable Clock 1568 * Mode. 1569 */ 1570 if (host->clk_mul) { 1571 for (div = 1; div <= 1024; div++) { 1572 if ((host->max_clk * host->clk_mul / div) 1573 <= clock) 1574 break; 1575 } 1576 if ((host->max_clk * host->clk_mul / div) <= clock) { 1577 /* 1578 * Set Programmable Clock Mode in the Clock 1579 * Control register. 1580 */ 1581 clk = SDHCI_PROG_CLOCK_MODE; 1582 real_div = div; 1583 clk_mul = host->clk_mul; 1584 div--; 1585 } else { 1586 /* 1587 * Divisor can be too small to reach clock 1588 * speed requirement. Then use the base clock. 1589 */ 1590 switch_base_clk = true; 1591 } 1592 } 1593 1594 if (!host->clk_mul || switch_base_clk) { 1595 /* Version 3.00 divisors must be a multiple of 2. */ 1596 if (host->max_clk <= clock) 1597 div = 1; 1598 else { 1599 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1600 div += 2) { 1601 if ((host->max_clk / div) <= clock) 1602 break; 1603 } 1604 } 1605 real_div = div; 1606 div >>= 1; 1607 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1608 && !div && host->max_clk <= 25000000) 1609 div = 1; 1610 } 1611 } else { 1612 /* Version 2.00 divisors must be a power of 2. */ 1613 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1614 if ((host->max_clk / div) <= clock) 1615 break; 1616 } 1617 real_div = div; 1618 div >>= 1; 1619 } 1620 1621 clock_set: 1622 if (real_div) 1623 *actual_clock = (host->max_clk * clk_mul) / real_div; 1624 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1625 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1626 << SDHCI_DIVIDER_HI_SHIFT; 1627 1628 return clk; 1629 } 1630 EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1631 1632 void sdhci_enable_clk(struct sdhci_host *host, u16 clk) 1633 { 1634 ktime_t timeout; 1635 1636 clk |= SDHCI_CLOCK_INT_EN; 1637 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1638 1639 /* Wait max 20 ms */ 1640 timeout = ktime_add_ms(ktime_get(), 20); 1641 while (1) { 1642 bool timedout = ktime_after(ktime_get(), timeout); 1643 1644 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1645 if (clk & SDHCI_CLOCK_INT_STABLE) 1646 break; 1647 if (timedout) { 1648 pr_err("%s: Internal clock never stabilised.\n", 1649 mmc_hostname(host->mmc)); 1650 sdhci_dumpregs(host); 1651 return; 1652 } 1653 udelay(10); 1654 } 1655 1656 clk |= SDHCI_CLOCK_CARD_EN; 1657 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1658 } 1659 EXPORT_SYMBOL_GPL(sdhci_enable_clk); 1660 1661 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1662 { 1663 u16 clk; 1664 1665 host->mmc->actual_clock = 0; 1666 1667 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1668 1669 if (clock == 0) 1670 return; 1671 1672 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1673 sdhci_enable_clk(host, clk); 1674 } 1675 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1676 1677 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 1678 unsigned short vdd) 1679 { 1680 struct mmc_host *mmc = host->mmc; 1681 1682 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1683 1684 if (mode != MMC_POWER_OFF) 1685 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1686 else 1687 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1688 } 1689 1690 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 1691 unsigned short vdd) 1692 { 1693 u8 pwr = 0; 1694 1695 if (mode != MMC_POWER_OFF) { 1696 switch (1 << vdd) { 1697 case MMC_VDD_165_195: 1698 /* 1699 * Without a regulator, SDHCI does not support 2.0v 1700 * so we only get here if the driver deliberately 1701 * added the 2.0v range to ocr_avail. Map it to 1.8v 1702 * for the purpose of turning on the power. 1703 */ 1704 case MMC_VDD_20_21: 1705 pwr = SDHCI_POWER_180; 1706 break; 1707 case MMC_VDD_29_30: 1708 case MMC_VDD_30_31: 1709 pwr = SDHCI_POWER_300; 1710 break; 1711 case MMC_VDD_32_33: 1712 case MMC_VDD_33_34: 1713 pwr = SDHCI_POWER_330; 1714 break; 1715 default: 1716 WARN(1, "%s: Invalid vdd %#x\n", 1717 mmc_hostname(host->mmc), vdd); 1718 break; 1719 } 1720 } 1721 1722 if (host->pwr == pwr) 1723 return; 1724 1725 host->pwr = pwr; 1726 1727 if (pwr == 0) { 1728 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1729 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1730 sdhci_runtime_pm_bus_off(host); 1731 } else { 1732 /* 1733 * Spec says that we should clear the power reg before setting 1734 * a new value. Some controllers don't seem to like this though. 1735 */ 1736 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1737 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1738 1739 /* 1740 * At least the Marvell CaFe chip gets confused if we set the 1741 * voltage and set turn on power at the same time, so set the 1742 * voltage first. 1743 */ 1744 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1745 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1746 1747 pwr |= SDHCI_POWER_ON; 1748 1749 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1750 1751 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1752 sdhci_runtime_pm_bus_on(host); 1753 1754 /* 1755 * Some controllers need an extra 10ms delay of 10ms before 1756 * they can apply clock after applying power 1757 */ 1758 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1759 mdelay(10); 1760 } 1761 } 1762 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 1763 1764 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1765 unsigned short vdd) 1766 { 1767 if (IS_ERR(host->mmc->supply.vmmc)) 1768 sdhci_set_power_noreg(host, mode, vdd); 1769 else 1770 sdhci_set_power_reg(host, mode, vdd); 1771 } 1772 EXPORT_SYMBOL_GPL(sdhci_set_power); 1773 1774 /*****************************************************************************\ 1775 * * 1776 * MMC callbacks * 1777 * * 1778 \*****************************************************************************/ 1779 1780 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1781 { 1782 struct sdhci_host *host; 1783 int present; 1784 unsigned long flags; 1785 1786 host = mmc_priv(mmc); 1787 1788 /* Firstly check card presence */ 1789 present = mmc->ops->get_cd(mmc); 1790 1791 spin_lock_irqsave(&host->lock, flags); 1792 1793 sdhci_led_activate(host); 1794 1795 /* 1796 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1797 * requests if Auto-CMD12 is enabled. 1798 */ 1799 if (sdhci_auto_cmd12(host, mrq)) { 1800 if (mrq->stop) { 1801 mrq->data->stop = NULL; 1802 mrq->stop = NULL; 1803 } 1804 } 1805 1806 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1807 mrq->cmd->error = -ENOMEDIUM; 1808 sdhci_finish_mrq(host, mrq); 1809 } else { 1810 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1811 sdhci_send_command(host, mrq->sbc); 1812 else 1813 sdhci_send_command(host, mrq->cmd); 1814 } 1815 1816 spin_unlock_irqrestore(&host->lock, flags); 1817 } 1818 EXPORT_SYMBOL_GPL(sdhci_request); 1819 1820 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1821 { 1822 u8 ctrl; 1823 1824 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1825 if (width == MMC_BUS_WIDTH_8) { 1826 ctrl &= ~SDHCI_CTRL_4BITBUS; 1827 ctrl |= SDHCI_CTRL_8BITBUS; 1828 } else { 1829 if (host->mmc->caps & MMC_CAP_8_BIT_DATA) 1830 ctrl &= ~SDHCI_CTRL_8BITBUS; 1831 if (width == MMC_BUS_WIDTH_4) 1832 ctrl |= SDHCI_CTRL_4BITBUS; 1833 else 1834 ctrl &= ~SDHCI_CTRL_4BITBUS; 1835 } 1836 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1837 } 1838 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1839 1840 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1841 { 1842 u16 ctrl_2; 1843 1844 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1845 /* Select Bus Speed Mode for host */ 1846 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1847 if ((timing == MMC_TIMING_MMC_HS200) || 1848 (timing == MMC_TIMING_UHS_SDR104)) 1849 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1850 else if (timing == MMC_TIMING_UHS_SDR12) 1851 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1852 else if (timing == MMC_TIMING_UHS_SDR25) 1853 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1854 else if (timing == MMC_TIMING_UHS_SDR50) 1855 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1856 else if ((timing == MMC_TIMING_UHS_DDR50) || 1857 (timing == MMC_TIMING_MMC_DDR52)) 1858 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1859 else if (timing == MMC_TIMING_MMC_HS400) 1860 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1861 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1862 } 1863 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1864 1865 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1866 { 1867 struct sdhci_host *host = mmc_priv(mmc); 1868 u8 ctrl; 1869 1870 if (ios->power_mode == MMC_POWER_UNDEFINED) 1871 return; 1872 1873 if (host->flags & SDHCI_DEVICE_DEAD) { 1874 if (!IS_ERR(mmc->supply.vmmc) && 1875 ios->power_mode == MMC_POWER_OFF) 1876 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1877 return; 1878 } 1879 1880 /* 1881 * Reset the chip on each power off. 1882 * Should clear out any weird states. 1883 */ 1884 if (ios->power_mode == MMC_POWER_OFF) { 1885 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1886 sdhci_reinit(host); 1887 } 1888 1889 if (host->version >= SDHCI_SPEC_300 && 1890 (ios->power_mode == MMC_POWER_UP) && 1891 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1892 sdhci_enable_preset_value(host, false); 1893 1894 if (!ios->clock || ios->clock != host->clock) { 1895 host->ops->set_clock(host, ios->clock); 1896 host->clock = ios->clock; 1897 1898 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1899 host->clock) { 1900 host->timeout_clk = host->mmc->actual_clock ? 1901 host->mmc->actual_clock / 1000 : 1902 host->clock / 1000; 1903 host->mmc->max_busy_timeout = 1904 host->ops->get_max_timeout_count ? 1905 host->ops->get_max_timeout_count(host) : 1906 1 << 27; 1907 host->mmc->max_busy_timeout /= host->timeout_clk; 1908 } 1909 } 1910 1911 if (host->ops->set_power) 1912 host->ops->set_power(host, ios->power_mode, ios->vdd); 1913 else 1914 sdhci_set_power(host, ios->power_mode, ios->vdd); 1915 1916 if (host->ops->platform_send_init_74_clocks) 1917 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1918 1919 host->ops->set_bus_width(host, ios->bus_width); 1920 1921 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1922 1923 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) { 1924 if (ios->timing == MMC_TIMING_SD_HS || 1925 ios->timing == MMC_TIMING_MMC_HS || 1926 ios->timing == MMC_TIMING_MMC_HS400 || 1927 ios->timing == MMC_TIMING_MMC_HS200 || 1928 ios->timing == MMC_TIMING_MMC_DDR52 || 1929 ios->timing == MMC_TIMING_UHS_SDR50 || 1930 ios->timing == MMC_TIMING_UHS_SDR104 || 1931 ios->timing == MMC_TIMING_UHS_DDR50 || 1932 ios->timing == MMC_TIMING_UHS_SDR25) 1933 ctrl |= SDHCI_CTRL_HISPD; 1934 else 1935 ctrl &= ~SDHCI_CTRL_HISPD; 1936 } 1937 1938 if (host->version >= SDHCI_SPEC_300) { 1939 u16 clk, ctrl_2; 1940 1941 if (!host->preset_enabled) { 1942 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1943 /* 1944 * We only need to set Driver Strength if the 1945 * preset value enable is not set. 1946 */ 1947 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1948 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1949 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1950 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1951 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1952 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1953 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1954 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1955 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1956 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1957 else { 1958 pr_warn("%s: invalid driver type, default to driver type B\n", 1959 mmc_hostname(mmc)); 1960 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1961 } 1962 1963 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1964 } else { 1965 /* 1966 * According to SDHC Spec v3.00, if the Preset Value 1967 * Enable in the Host Control 2 register is set, we 1968 * need to reset SD Clock Enable before changing High 1969 * Speed Enable to avoid generating clock gliches. 1970 */ 1971 1972 /* Reset SD Clock Enable */ 1973 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1974 clk &= ~SDHCI_CLOCK_CARD_EN; 1975 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1976 1977 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1978 1979 /* Re-enable SD Clock */ 1980 host->ops->set_clock(host, host->clock); 1981 } 1982 1983 /* Reset SD Clock Enable */ 1984 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1985 clk &= ~SDHCI_CLOCK_CARD_EN; 1986 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1987 1988 host->ops->set_uhs_signaling(host, ios->timing); 1989 host->timing = ios->timing; 1990 1991 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1992 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1993 (ios->timing == MMC_TIMING_UHS_SDR25) || 1994 (ios->timing == MMC_TIMING_UHS_SDR50) || 1995 (ios->timing == MMC_TIMING_UHS_SDR104) || 1996 (ios->timing == MMC_TIMING_UHS_DDR50) || 1997 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1998 u16 preset; 1999 2000 sdhci_enable_preset_value(host, true); 2001 preset = sdhci_get_preset_value(host); 2002 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 2003 >> SDHCI_PRESET_DRV_SHIFT; 2004 } 2005 2006 /* Re-enable SD Clock */ 2007 host->ops->set_clock(host, host->clock); 2008 } else 2009 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 2010 2011 /* 2012 * Some (ENE) controllers go apeshit on some ios operation, 2013 * signalling timeout and CRC errors even on CMD0. Resetting 2014 * it on each ios seems to solve the problem. 2015 */ 2016 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 2017 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 2018 } 2019 EXPORT_SYMBOL_GPL(sdhci_set_ios); 2020 2021 static int sdhci_get_cd(struct mmc_host *mmc) 2022 { 2023 struct sdhci_host *host = mmc_priv(mmc); 2024 int gpio_cd = mmc_gpio_get_cd(mmc); 2025 2026 if (host->flags & SDHCI_DEVICE_DEAD) 2027 return 0; 2028 2029 /* If nonremovable, assume that the card is always present. */ 2030 if (!mmc_card_is_removable(host->mmc)) 2031 return 1; 2032 2033 /* 2034 * Try slot gpio detect, if defined it take precedence 2035 * over build in controller functionality 2036 */ 2037 if (gpio_cd >= 0) 2038 return !!gpio_cd; 2039 2040 /* If polling, assume that the card is always present. */ 2041 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 2042 return 1; 2043 2044 /* Host native card detect */ 2045 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 2046 } 2047 2048 static int sdhci_check_ro(struct sdhci_host *host) 2049 { 2050 unsigned long flags; 2051 int is_readonly; 2052 2053 spin_lock_irqsave(&host->lock, flags); 2054 2055 if (host->flags & SDHCI_DEVICE_DEAD) 2056 is_readonly = 0; 2057 else if (host->ops->get_ro) 2058 is_readonly = host->ops->get_ro(host); 2059 else if (mmc_can_gpio_ro(host->mmc)) 2060 is_readonly = mmc_gpio_get_ro(host->mmc); 2061 else 2062 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 2063 & SDHCI_WRITE_PROTECT); 2064 2065 spin_unlock_irqrestore(&host->lock, flags); 2066 2067 /* This quirk needs to be replaced by a callback-function later */ 2068 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 2069 !is_readonly : is_readonly; 2070 } 2071 2072 #define SAMPLE_COUNT 5 2073 2074 static int sdhci_get_ro(struct mmc_host *mmc) 2075 { 2076 struct sdhci_host *host = mmc_priv(mmc); 2077 int i, ro_count; 2078 2079 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 2080 return sdhci_check_ro(host); 2081 2082 ro_count = 0; 2083 for (i = 0; i < SAMPLE_COUNT; i++) { 2084 if (sdhci_check_ro(host)) { 2085 if (++ro_count > SAMPLE_COUNT / 2) 2086 return 1; 2087 } 2088 msleep(30); 2089 } 2090 return 0; 2091 } 2092 2093 static void sdhci_hw_reset(struct mmc_host *mmc) 2094 { 2095 struct sdhci_host *host = mmc_priv(mmc); 2096 2097 if (host->ops && host->ops->hw_reset) 2098 host->ops->hw_reset(host); 2099 } 2100 2101 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 2102 { 2103 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 2104 if (enable) 2105 host->ier |= SDHCI_INT_CARD_INT; 2106 else 2107 host->ier &= ~SDHCI_INT_CARD_INT; 2108 2109 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2110 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2111 } 2112 } 2113 2114 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 2115 { 2116 struct sdhci_host *host = mmc_priv(mmc); 2117 unsigned long flags; 2118 2119 if (enable) 2120 pm_runtime_get_noresume(host->mmc->parent); 2121 2122 spin_lock_irqsave(&host->lock, flags); 2123 if (enable) 2124 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 2125 else 2126 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 2127 2128 sdhci_enable_sdio_irq_nolock(host, enable); 2129 spin_unlock_irqrestore(&host->lock, flags); 2130 2131 if (!enable) 2132 pm_runtime_put_noidle(host->mmc->parent); 2133 } 2134 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq); 2135 2136 static void sdhci_ack_sdio_irq(struct mmc_host *mmc) 2137 { 2138 struct sdhci_host *host = mmc_priv(mmc); 2139 unsigned long flags; 2140 2141 spin_lock_irqsave(&host->lock, flags); 2142 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2143 sdhci_enable_sdio_irq_nolock(host, true); 2144 spin_unlock_irqrestore(&host->lock, flags); 2145 } 2146 2147 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 2148 struct mmc_ios *ios) 2149 { 2150 struct sdhci_host *host = mmc_priv(mmc); 2151 u16 ctrl; 2152 int ret; 2153 2154 /* 2155 * Signal Voltage Switching is only applicable for Host Controllers 2156 * v3.00 and above. 2157 */ 2158 if (host->version < SDHCI_SPEC_300) 2159 return 0; 2160 2161 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2162 2163 switch (ios->signal_voltage) { 2164 case MMC_SIGNAL_VOLTAGE_330: 2165 if (!(host->flags & SDHCI_SIGNALING_330)) 2166 return -EINVAL; 2167 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 2168 ctrl &= ~SDHCI_CTRL_VDD_180; 2169 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2170 2171 if (!IS_ERR(mmc->supply.vqmmc)) { 2172 ret = mmc_regulator_set_vqmmc(mmc, ios); 2173 if (ret) { 2174 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 2175 mmc_hostname(mmc)); 2176 return -EIO; 2177 } 2178 } 2179 /* Wait for 5ms */ 2180 usleep_range(5000, 5500); 2181 2182 /* 3.3V regulator output should be stable within 5 ms */ 2183 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2184 if (!(ctrl & SDHCI_CTRL_VDD_180)) 2185 return 0; 2186 2187 pr_warn("%s: 3.3V regulator output did not became stable\n", 2188 mmc_hostname(mmc)); 2189 2190 return -EAGAIN; 2191 case MMC_SIGNAL_VOLTAGE_180: 2192 if (!(host->flags & SDHCI_SIGNALING_180)) 2193 return -EINVAL; 2194 if (!IS_ERR(mmc->supply.vqmmc)) { 2195 ret = mmc_regulator_set_vqmmc(mmc, ios); 2196 if (ret) { 2197 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 2198 mmc_hostname(mmc)); 2199 return -EIO; 2200 } 2201 } 2202 2203 /* 2204 * Enable 1.8V Signal Enable in the Host Control2 2205 * register 2206 */ 2207 ctrl |= SDHCI_CTRL_VDD_180; 2208 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2209 2210 /* Some controller need to do more when switching */ 2211 if (host->ops->voltage_switch) 2212 host->ops->voltage_switch(host); 2213 2214 /* 1.8V regulator output should be stable within 5 ms */ 2215 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2216 if (ctrl & SDHCI_CTRL_VDD_180) 2217 return 0; 2218 2219 pr_warn("%s: 1.8V regulator output did not became stable\n", 2220 mmc_hostname(mmc)); 2221 2222 return -EAGAIN; 2223 case MMC_SIGNAL_VOLTAGE_120: 2224 if (!(host->flags & SDHCI_SIGNALING_120)) 2225 return -EINVAL; 2226 if (!IS_ERR(mmc->supply.vqmmc)) { 2227 ret = mmc_regulator_set_vqmmc(mmc, ios); 2228 if (ret) { 2229 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 2230 mmc_hostname(mmc)); 2231 return -EIO; 2232 } 2233 } 2234 return 0; 2235 default: 2236 /* No signal voltage switch required */ 2237 return 0; 2238 } 2239 } 2240 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch); 2241 2242 static int sdhci_card_busy(struct mmc_host *mmc) 2243 { 2244 struct sdhci_host *host = mmc_priv(mmc); 2245 u32 present_state; 2246 2247 /* Check whether DAT[0] is 0 */ 2248 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 2249 2250 return !(present_state & SDHCI_DATA_0_LVL_MASK); 2251 } 2252 2253 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2254 { 2255 struct sdhci_host *host = mmc_priv(mmc); 2256 unsigned long flags; 2257 2258 spin_lock_irqsave(&host->lock, flags); 2259 host->flags |= SDHCI_HS400_TUNING; 2260 spin_unlock_irqrestore(&host->lock, flags); 2261 2262 return 0; 2263 } 2264 2265 void sdhci_start_tuning(struct sdhci_host *host) 2266 { 2267 u16 ctrl; 2268 2269 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2270 ctrl |= SDHCI_CTRL_EXEC_TUNING; 2271 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 2272 ctrl |= SDHCI_CTRL_TUNED_CLK; 2273 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2274 2275 /* 2276 * As per the Host Controller spec v3.00, tuning command 2277 * generates Buffer Read Ready interrupt, so enable that. 2278 * 2279 * Note: The spec clearly says that when tuning sequence 2280 * is being performed, the controller does not generate 2281 * interrupts other than Buffer Read Ready interrupt. But 2282 * to make sure we don't hit a controller bug, we _only_ 2283 * enable Buffer Read Ready interrupt here. 2284 */ 2285 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 2286 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 2287 } 2288 EXPORT_SYMBOL_GPL(sdhci_start_tuning); 2289 2290 void sdhci_end_tuning(struct sdhci_host *host) 2291 { 2292 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2293 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2294 } 2295 EXPORT_SYMBOL_GPL(sdhci_end_tuning); 2296 2297 void sdhci_reset_tuning(struct sdhci_host *host) 2298 { 2299 u16 ctrl; 2300 2301 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2302 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 2303 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 2304 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2305 } 2306 EXPORT_SYMBOL_GPL(sdhci_reset_tuning); 2307 2308 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode) 2309 { 2310 sdhci_reset_tuning(host); 2311 2312 sdhci_do_reset(host, SDHCI_RESET_CMD); 2313 sdhci_do_reset(host, SDHCI_RESET_DATA); 2314 2315 sdhci_end_tuning(host); 2316 2317 mmc_abort_tuning(host->mmc, opcode); 2318 } 2319 2320 /* 2321 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI 2322 * tuning command does not have a data payload (or rather the hardware does it 2323 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command 2324 * interrupt setup is different to other commands and there is no timeout 2325 * interrupt so special handling is needed. 2326 */ 2327 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 2328 { 2329 struct mmc_host *mmc = host->mmc; 2330 struct mmc_command cmd = {}; 2331 struct mmc_request mrq = {}; 2332 unsigned long flags; 2333 u32 b = host->sdma_boundary; 2334 2335 spin_lock_irqsave(&host->lock, flags); 2336 2337 cmd.opcode = opcode; 2338 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2339 cmd.mrq = &mrq; 2340 2341 mrq.cmd = &cmd; 2342 /* 2343 * In response to CMD19, the card sends 64 bytes of tuning 2344 * block to the Host Controller. So we set the block size 2345 * to 64 here. 2346 */ 2347 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && 2348 mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2349 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE); 2350 else 2351 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE); 2352 2353 /* 2354 * The tuning block is sent by the card to the host controller. 2355 * So we set the TRNS_READ bit in the Transfer Mode register. 2356 * This also takes care of setting DMA Enable and Multi Block 2357 * Select in the same register to 0. 2358 */ 2359 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2360 2361 sdhci_send_command(host, &cmd); 2362 2363 host->cmd = NULL; 2364 2365 sdhci_del_timer(host, &mrq); 2366 2367 host->tuning_done = 0; 2368 2369 spin_unlock_irqrestore(&host->lock, flags); 2370 2371 /* Wait for Buffer Read Ready interrupt */ 2372 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), 2373 msecs_to_jiffies(50)); 2374 2375 } 2376 EXPORT_SYMBOL_GPL(sdhci_send_tuning); 2377 2378 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 2379 { 2380 int i; 2381 2382 /* 2383 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 2384 * of loops reaches tuning loop count. 2385 */ 2386 for (i = 0; i < host->tuning_loop_count; i++) { 2387 u16 ctrl; 2388 2389 sdhci_send_tuning(host, opcode); 2390 2391 if (!host->tuning_done) { 2392 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 2393 mmc_hostname(host->mmc)); 2394 sdhci_abort_tuning(host, opcode); 2395 return -ETIMEDOUT; 2396 } 2397 2398 /* Spec does not require a delay between tuning cycles */ 2399 if (host->tuning_delay > 0) 2400 mdelay(host->tuning_delay); 2401 2402 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2403 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 2404 if (ctrl & SDHCI_CTRL_TUNED_CLK) 2405 return 0; /* Success! */ 2406 break; 2407 } 2408 2409 } 2410 2411 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 2412 mmc_hostname(host->mmc)); 2413 sdhci_reset_tuning(host); 2414 return -EAGAIN; 2415 } 2416 2417 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 2418 { 2419 struct sdhci_host *host = mmc_priv(mmc); 2420 int err = 0; 2421 unsigned int tuning_count = 0; 2422 bool hs400_tuning; 2423 2424 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 2425 2426 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 2427 tuning_count = host->tuning_count; 2428 2429 /* 2430 * The Host Controller needs tuning in case of SDR104 and DDR50 2431 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 2432 * the Capabilities register. 2433 * If the Host Controller supports the HS200 mode then the 2434 * tuning function has to be executed. 2435 */ 2436 switch (host->timing) { 2437 /* HS400 tuning is done in HS200 mode */ 2438 case MMC_TIMING_MMC_HS400: 2439 err = -EINVAL; 2440 goto out; 2441 2442 case MMC_TIMING_MMC_HS200: 2443 /* 2444 * Periodic re-tuning for HS400 is not expected to be needed, so 2445 * disable it here. 2446 */ 2447 if (hs400_tuning) 2448 tuning_count = 0; 2449 break; 2450 2451 case MMC_TIMING_UHS_SDR104: 2452 case MMC_TIMING_UHS_DDR50: 2453 break; 2454 2455 case MMC_TIMING_UHS_SDR50: 2456 if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 2457 break; 2458 /* FALLTHROUGH */ 2459 2460 default: 2461 goto out; 2462 } 2463 2464 if (host->ops->platform_execute_tuning) { 2465 err = host->ops->platform_execute_tuning(host, opcode); 2466 goto out; 2467 } 2468 2469 host->mmc->retune_period = tuning_count; 2470 2471 if (host->tuning_delay < 0) 2472 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK; 2473 2474 sdhci_start_tuning(host); 2475 2476 host->tuning_err = __sdhci_execute_tuning(host, opcode); 2477 2478 sdhci_end_tuning(host); 2479 out: 2480 host->flags &= ~SDHCI_HS400_TUNING; 2481 2482 return err; 2483 } 2484 EXPORT_SYMBOL_GPL(sdhci_execute_tuning); 2485 2486 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2487 { 2488 /* Host Controller v3.00 defines preset value registers */ 2489 if (host->version < SDHCI_SPEC_300) 2490 return; 2491 2492 /* 2493 * We only enable or disable Preset Value if they are not already 2494 * enabled or disabled respectively. Otherwise, we bail out. 2495 */ 2496 if (host->preset_enabled != enable) { 2497 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2498 2499 if (enable) 2500 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2501 else 2502 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2503 2504 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2505 2506 if (enable) 2507 host->flags |= SDHCI_PV_ENABLED; 2508 else 2509 host->flags &= ~SDHCI_PV_ENABLED; 2510 2511 host->preset_enabled = enable; 2512 } 2513 } 2514 2515 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2516 int err) 2517 { 2518 struct sdhci_host *host = mmc_priv(mmc); 2519 struct mmc_data *data = mrq->data; 2520 2521 if (data->host_cookie != COOKIE_UNMAPPED) 2522 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2523 mmc_get_dma_dir(data)); 2524 2525 data->host_cookie = COOKIE_UNMAPPED; 2526 } 2527 2528 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 2529 { 2530 struct sdhci_host *host = mmc_priv(mmc); 2531 2532 mrq->data->host_cookie = COOKIE_UNMAPPED; 2533 2534 /* 2535 * No pre-mapping in the pre hook if we're using the bounce buffer, 2536 * for that we would need two bounce buffers since one buffer is 2537 * in flight when this is getting called. 2538 */ 2539 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer) 2540 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2541 } 2542 2543 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 2544 { 2545 if (host->data_cmd) { 2546 host->data_cmd->error = err; 2547 sdhci_finish_mrq(host, host->data_cmd->mrq); 2548 } 2549 2550 if (host->cmd) { 2551 host->cmd->error = err; 2552 sdhci_finish_mrq(host, host->cmd->mrq); 2553 } 2554 } 2555 2556 static void sdhci_card_event(struct mmc_host *mmc) 2557 { 2558 struct sdhci_host *host = mmc_priv(mmc); 2559 unsigned long flags; 2560 int present; 2561 2562 /* First check if client has provided their own card event */ 2563 if (host->ops->card_event) 2564 host->ops->card_event(host); 2565 2566 present = mmc->ops->get_cd(mmc); 2567 2568 spin_lock_irqsave(&host->lock, flags); 2569 2570 /* Check sdhci_has_requests() first in case we are runtime suspended */ 2571 if (sdhci_has_requests(host) && !present) { 2572 pr_err("%s: Card removed during transfer!\n", 2573 mmc_hostname(host->mmc)); 2574 pr_err("%s: Resetting controller.\n", 2575 mmc_hostname(host->mmc)); 2576 2577 sdhci_do_reset(host, SDHCI_RESET_CMD); 2578 sdhci_do_reset(host, SDHCI_RESET_DATA); 2579 2580 sdhci_error_out_mrqs(host, -ENOMEDIUM); 2581 } 2582 2583 spin_unlock_irqrestore(&host->lock, flags); 2584 } 2585 2586 static const struct mmc_host_ops sdhci_ops = { 2587 .request = sdhci_request, 2588 .post_req = sdhci_post_req, 2589 .pre_req = sdhci_pre_req, 2590 .set_ios = sdhci_set_ios, 2591 .get_cd = sdhci_get_cd, 2592 .get_ro = sdhci_get_ro, 2593 .hw_reset = sdhci_hw_reset, 2594 .enable_sdio_irq = sdhci_enable_sdio_irq, 2595 .ack_sdio_irq = sdhci_ack_sdio_irq, 2596 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2597 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2598 .execute_tuning = sdhci_execute_tuning, 2599 .card_event = sdhci_card_event, 2600 .card_busy = sdhci_card_busy, 2601 }; 2602 2603 /*****************************************************************************\ 2604 * * 2605 * Request done * 2606 * * 2607 \*****************************************************************************/ 2608 2609 static bool sdhci_request_done(struct sdhci_host *host) 2610 { 2611 unsigned long flags; 2612 struct mmc_request *mrq; 2613 int i; 2614 2615 spin_lock_irqsave(&host->lock, flags); 2616 2617 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 2618 mrq = host->mrqs_done[i]; 2619 if (mrq) 2620 break; 2621 } 2622 2623 if (!mrq) { 2624 spin_unlock_irqrestore(&host->lock, flags); 2625 return true; 2626 } 2627 2628 /* 2629 * Always unmap the data buffers if they were mapped by 2630 * sdhci_prepare_data() whenever we finish with a request. 2631 * This avoids leaking DMA mappings on error. 2632 */ 2633 if (host->flags & SDHCI_REQ_USE_DMA) { 2634 struct mmc_data *data = mrq->data; 2635 2636 if (data && data->host_cookie == COOKIE_MAPPED) { 2637 if (host->bounce_buffer) { 2638 /* 2639 * On reads, copy the bounced data into the 2640 * sglist 2641 */ 2642 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { 2643 unsigned int length = data->bytes_xfered; 2644 2645 if (length > host->bounce_buffer_size) { 2646 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", 2647 mmc_hostname(host->mmc), 2648 host->bounce_buffer_size, 2649 data->bytes_xfered); 2650 /* Cap it down and continue */ 2651 length = host->bounce_buffer_size; 2652 } 2653 dma_sync_single_for_cpu( 2654 host->mmc->parent, 2655 host->bounce_addr, 2656 host->bounce_buffer_size, 2657 DMA_FROM_DEVICE); 2658 sg_copy_from_buffer(data->sg, 2659 data->sg_len, 2660 host->bounce_buffer, 2661 length); 2662 } else { 2663 /* No copying, just switch ownership */ 2664 dma_sync_single_for_cpu( 2665 host->mmc->parent, 2666 host->bounce_addr, 2667 host->bounce_buffer_size, 2668 mmc_get_dma_dir(data)); 2669 } 2670 } else { 2671 /* Unmap the raw data */ 2672 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 2673 data->sg_len, 2674 mmc_get_dma_dir(data)); 2675 } 2676 data->host_cookie = COOKIE_UNMAPPED; 2677 } 2678 } 2679 2680 /* 2681 * The controller needs a reset of internal state machines 2682 * upon error conditions. 2683 */ 2684 if (sdhci_needs_reset(host, mrq)) { 2685 /* 2686 * Do not finish until command and data lines are available for 2687 * reset. Note there can only be one other mrq, so it cannot 2688 * also be in mrqs_done, otherwise host->cmd and host->data_cmd 2689 * would both be null. 2690 */ 2691 if (host->cmd || host->data_cmd) { 2692 spin_unlock_irqrestore(&host->lock, flags); 2693 return true; 2694 } 2695 2696 /* Some controllers need this kick or reset won't work here */ 2697 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2698 /* This is to force an update */ 2699 host->ops->set_clock(host, host->clock); 2700 2701 /* Spec says we should do both at the same time, but Ricoh 2702 controllers do not like that. */ 2703 sdhci_do_reset(host, SDHCI_RESET_CMD); 2704 sdhci_do_reset(host, SDHCI_RESET_DATA); 2705 2706 host->pending_reset = false; 2707 } 2708 2709 host->mrqs_done[i] = NULL; 2710 2711 spin_unlock_irqrestore(&host->lock, flags); 2712 2713 mmc_request_done(host->mmc, mrq); 2714 2715 return false; 2716 } 2717 2718 static void sdhci_complete_work(struct work_struct *work) 2719 { 2720 struct sdhci_host *host = container_of(work, struct sdhci_host, 2721 complete_work); 2722 2723 while (!sdhci_request_done(host)) 2724 ; 2725 } 2726 2727 static void sdhci_timeout_timer(struct timer_list *t) 2728 { 2729 struct sdhci_host *host; 2730 unsigned long flags; 2731 2732 host = from_timer(host, t, timer); 2733 2734 spin_lock_irqsave(&host->lock, flags); 2735 2736 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2737 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2738 mmc_hostname(host->mmc)); 2739 sdhci_dumpregs(host); 2740 2741 host->cmd->error = -ETIMEDOUT; 2742 sdhci_finish_mrq(host, host->cmd->mrq); 2743 } 2744 2745 spin_unlock_irqrestore(&host->lock, flags); 2746 } 2747 2748 static void sdhci_timeout_data_timer(struct timer_list *t) 2749 { 2750 struct sdhci_host *host; 2751 unsigned long flags; 2752 2753 host = from_timer(host, t, data_timer); 2754 2755 spin_lock_irqsave(&host->lock, flags); 2756 2757 if (host->data || host->data_cmd || 2758 (host->cmd && sdhci_data_line_cmd(host->cmd))) { 2759 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2760 mmc_hostname(host->mmc)); 2761 sdhci_dumpregs(host); 2762 2763 if (host->data) { 2764 host->data->error = -ETIMEDOUT; 2765 sdhci_finish_data(host); 2766 queue_work(host->complete_wq, &host->complete_work); 2767 } else if (host->data_cmd) { 2768 host->data_cmd->error = -ETIMEDOUT; 2769 sdhci_finish_mrq(host, host->data_cmd->mrq); 2770 } else { 2771 host->cmd->error = -ETIMEDOUT; 2772 sdhci_finish_mrq(host, host->cmd->mrq); 2773 } 2774 } 2775 2776 spin_unlock_irqrestore(&host->lock, flags); 2777 } 2778 2779 /*****************************************************************************\ 2780 * * 2781 * Interrupt handling * 2782 * * 2783 \*****************************************************************************/ 2784 2785 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p) 2786 { 2787 /* Handle auto-CMD12 error */ 2788 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) { 2789 struct mmc_request *mrq = host->data_cmd->mrq; 2790 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 2791 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 2792 SDHCI_INT_DATA_TIMEOUT : 2793 SDHCI_INT_DATA_CRC; 2794 2795 /* Treat auto-CMD12 error the same as data error */ 2796 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 2797 *intmask_p |= data_err_bit; 2798 return; 2799 } 2800 } 2801 2802 if (!host->cmd) { 2803 /* 2804 * SDHCI recovers from errors by resetting the cmd and data 2805 * circuits. Until that is done, there very well might be more 2806 * interrupts, so ignore them in that case. 2807 */ 2808 if (host->pending_reset) 2809 return; 2810 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2811 mmc_hostname(host->mmc), (unsigned)intmask); 2812 sdhci_dumpregs(host); 2813 return; 2814 } 2815 2816 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2817 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2818 if (intmask & SDHCI_INT_TIMEOUT) 2819 host->cmd->error = -ETIMEDOUT; 2820 else 2821 host->cmd->error = -EILSEQ; 2822 2823 /* Treat data command CRC error the same as data CRC error */ 2824 if (host->cmd->data && 2825 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2826 SDHCI_INT_CRC) { 2827 host->cmd = NULL; 2828 *intmask_p |= SDHCI_INT_DATA_CRC; 2829 return; 2830 } 2831 2832 __sdhci_finish_mrq(host, host->cmd->mrq); 2833 return; 2834 } 2835 2836 /* Handle auto-CMD23 error */ 2837 if (intmask & SDHCI_INT_AUTO_CMD_ERR) { 2838 struct mmc_request *mrq = host->cmd->mrq; 2839 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS); 2840 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? 2841 -ETIMEDOUT : 2842 -EILSEQ; 2843 2844 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 2845 mrq->sbc->error = err; 2846 __sdhci_finish_mrq(host, mrq); 2847 return; 2848 } 2849 } 2850 2851 if (intmask & SDHCI_INT_RESPONSE) 2852 sdhci_finish_command(host); 2853 } 2854 2855 static void sdhci_adma_show_error(struct sdhci_host *host) 2856 { 2857 void *desc = host->adma_table; 2858 2859 sdhci_dumpregs(host); 2860 2861 while (true) { 2862 struct sdhci_adma2_64_desc *dma_desc = desc; 2863 2864 if (host->flags & SDHCI_USE_64_BIT_DMA) 2865 DBG("%p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2866 desc, le32_to_cpu(dma_desc->addr_hi), 2867 le32_to_cpu(dma_desc->addr_lo), 2868 le16_to_cpu(dma_desc->len), 2869 le16_to_cpu(dma_desc->cmd)); 2870 else 2871 DBG("%p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2872 desc, le32_to_cpu(dma_desc->addr_lo), 2873 le16_to_cpu(dma_desc->len), 2874 le16_to_cpu(dma_desc->cmd)); 2875 2876 desc += host->desc_sz; 2877 2878 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2879 break; 2880 } 2881 } 2882 2883 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2884 { 2885 u32 command; 2886 2887 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2888 if (intmask & SDHCI_INT_DATA_AVAIL) { 2889 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2890 if (command == MMC_SEND_TUNING_BLOCK || 2891 command == MMC_SEND_TUNING_BLOCK_HS200) { 2892 host->tuning_done = 1; 2893 wake_up(&host->buf_ready_int); 2894 return; 2895 } 2896 } 2897 2898 if (!host->data) { 2899 struct mmc_command *data_cmd = host->data_cmd; 2900 2901 /* 2902 * The "data complete" interrupt is also used to 2903 * indicate that a busy state has ended. See comment 2904 * above in sdhci_cmd_irq(). 2905 */ 2906 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2907 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2908 host->data_cmd = NULL; 2909 data_cmd->error = -ETIMEDOUT; 2910 __sdhci_finish_mrq(host, data_cmd->mrq); 2911 return; 2912 } 2913 if (intmask & SDHCI_INT_DATA_END) { 2914 host->data_cmd = NULL; 2915 /* 2916 * Some cards handle busy-end interrupt 2917 * before the command completed, so make 2918 * sure we do things in the proper order. 2919 */ 2920 if (host->cmd == data_cmd) 2921 return; 2922 2923 __sdhci_finish_mrq(host, data_cmd->mrq); 2924 return; 2925 } 2926 } 2927 2928 /* 2929 * SDHCI recovers from errors by resetting the cmd and data 2930 * circuits. Until that is done, there very well might be more 2931 * interrupts, so ignore them in that case. 2932 */ 2933 if (host->pending_reset) 2934 return; 2935 2936 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2937 mmc_hostname(host->mmc), (unsigned)intmask); 2938 sdhci_dumpregs(host); 2939 2940 return; 2941 } 2942 2943 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2944 host->data->error = -ETIMEDOUT; 2945 else if (intmask & SDHCI_INT_DATA_END_BIT) 2946 host->data->error = -EILSEQ; 2947 else if ((intmask & SDHCI_INT_DATA_CRC) && 2948 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2949 != MMC_BUS_TEST_R) 2950 host->data->error = -EILSEQ; 2951 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2952 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2953 sdhci_adma_show_error(host); 2954 host->data->error = -EIO; 2955 if (host->ops->adma_workaround) 2956 host->ops->adma_workaround(host, intmask); 2957 } 2958 2959 if (host->data->error) 2960 sdhci_finish_data(host); 2961 else { 2962 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2963 sdhci_transfer_pio(host); 2964 2965 /* 2966 * We currently don't do anything fancy with DMA 2967 * boundaries, but as we can't disable the feature 2968 * we need to at least restart the transfer. 2969 * 2970 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2971 * should return a valid address to continue from, but as 2972 * some controllers are faulty, don't trust them. 2973 */ 2974 if (intmask & SDHCI_INT_DMA_END) { 2975 dma_addr_t dmastart, dmanow; 2976 2977 dmastart = sdhci_sdma_address(host); 2978 dmanow = dmastart + host->data->bytes_xfered; 2979 /* 2980 * Force update to the next DMA block boundary. 2981 */ 2982 dmanow = (dmanow & 2983 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2984 SDHCI_DEFAULT_BOUNDARY_SIZE; 2985 host->data->bytes_xfered = dmanow - dmastart; 2986 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n", 2987 &dmastart, host->data->bytes_xfered, &dmanow); 2988 sdhci_set_sdma_addr(host, dmanow); 2989 } 2990 2991 if (intmask & SDHCI_INT_DATA_END) { 2992 if (host->cmd == host->data_cmd) { 2993 /* 2994 * Data managed to finish before the 2995 * command completed. Make sure we do 2996 * things in the proper order. 2997 */ 2998 host->data_early = 1; 2999 } else { 3000 sdhci_finish_data(host); 3001 } 3002 } 3003 } 3004 } 3005 3006 static inline bool sdhci_defer_done(struct sdhci_host *host, 3007 struct mmc_request *mrq) 3008 { 3009 struct mmc_data *data = mrq->data; 3010 3011 return host->pending_reset || 3012 ((host->flags & SDHCI_REQ_USE_DMA) && data && 3013 data->host_cookie == COOKIE_MAPPED); 3014 } 3015 3016 static irqreturn_t sdhci_irq(int irq, void *dev_id) 3017 { 3018 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0}; 3019 irqreturn_t result = IRQ_NONE; 3020 struct sdhci_host *host = dev_id; 3021 u32 intmask, mask, unexpected = 0; 3022 int max_loops = 16; 3023 int i; 3024 3025 spin_lock(&host->lock); 3026 3027 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 3028 spin_unlock(&host->lock); 3029 return IRQ_NONE; 3030 } 3031 3032 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 3033 if (!intmask || intmask == 0xffffffff) { 3034 result = IRQ_NONE; 3035 goto out; 3036 } 3037 3038 do { 3039 DBG("IRQ status 0x%08x\n", intmask); 3040 3041 if (host->ops->irq) { 3042 intmask = host->ops->irq(host, intmask); 3043 if (!intmask) 3044 goto cont; 3045 } 3046 3047 /* Clear selected interrupts. */ 3048 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 3049 SDHCI_INT_BUS_POWER); 3050 sdhci_writel(host, mask, SDHCI_INT_STATUS); 3051 3052 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3053 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 3054 SDHCI_CARD_PRESENT; 3055 3056 /* 3057 * There is a observation on i.mx esdhc. INSERT 3058 * bit will be immediately set again when it gets 3059 * cleared, if a card is inserted. We have to mask 3060 * the irq to prevent interrupt storm which will 3061 * freeze the system. And the REMOVE gets the 3062 * same situation. 3063 * 3064 * More testing are needed here to ensure it works 3065 * for other platforms though. 3066 */ 3067 host->ier &= ~(SDHCI_INT_CARD_INSERT | 3068 SDHCI_INT_CARD_REMOVE); 3069 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 3070 SDHCI_INT_CARD_INSERT; 3071 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3072 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3073 3074 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 3075 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 3076 3077 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 3078 SDHCI_INT_CARD_REMOVE); 3079 result = IRQ_WAKE_THREAD; 3080 } 3081 3082 if (intmask & SDHCI_INT_CMD_MASK) 3083 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask); 3084 3085 if (intmask & SDHCI_INT_DATA_MASK) 3086 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 3087 3088 if (intmask & SDHCI_INT_BUS_POWER) 3089 pr_err("%s: Card is consuming too much power!\n", 3090 mmc_hostname(host->mmc)); 3091 3092 if (intmask & SDHCI_INT_RETUNE) 3093 mmc_retune_needed(host->mmc); 3094 3095 if ((intmask & SDHCI_INT_CARD_INT) && 3096 (host->ier & SDHCI_INT_CARD_INT)) { 3097 sdhci_enable_sdio_irq_nolock(host, false); 3098 sdio_signal_irq(host->mmc); 3099 } 3100 3101 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 3102 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 3103 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 3104 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 3105 3106 if (intmask) { 3107 unexpected |= intmask; 3108 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 3109 } 3110 cont: 3111 if (result == IRQ_NONE) 3112 result = IRQ_HANDLED; 3113 3114 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 3115 } while (intmask && --max_loops); 3116 3117 /* Determine if mrqs can be completed immediately */ 3118 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 3119 struct mmc_request *mrq = host->mrqs_done[i]; 3120 3121 if (!mrq) 3122 continue; 3123 3124 if (sdhci_defer_done(host, mrq)) { 3125 result = IRQ_WAKE_THREAD; 3126 } else { 3127 mrqs_done[i] = mrq; 3128 host->mrqs_done[i] = NULL; 3129 } 3130 } 3131 out: 3132 spin_unlock(&host->lock); 3133 3134 /* Process mrqs ready for immediate completion */ 3135 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 3136 if (mrqs_done[i]) 3137 mmc_request_done(host->mmc, mrqs_done[i]); 3138 } 3139 3140 if (unexpected) { 3141 pr_err("%s: Unexpected interrupt 0x%08x.\n", 3142 mmc_hostname(host->mmc), unexpected); 3143 sdhci_dumpregs(host); 3144 } 3145 3146 return result; 3147 } 3148 3149 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 3150 { 3151 struct sdhci_host *host = dev_id; 3152 unsigned long flags; 3153 u32 isr; 3154 3155 while (!sdhci_request_done(host)) 3156 ; 3157 3158 spin_lock_irqsave(&host->lock, flags); 3159 isr = host->thread_isr; 3160 host->thread_isr = 0; 3161 spin_unlock_irqrestore(&host->lock, flags); 3162 3163 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 3164 struct mmc_host *mmc = host->mmc; 3165 3166 mmc->ops->card_event(mmc); 3167 mmc_detect_change(mmc, msecs_to_jiffies(200)); 3168 } 3169 3170 return IRQ_HANDLED; 3171 } 3172 3173 /*****************************************************************************\ 3174 * * 3175 * Suspend/resume * 3176 * * 3177 \*****************************************************************************/ 3178 3179 #ifdef CONFIG_PM 3180 3181 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host) 3182 { 3183 return mmc_card_is_removable(host->mmc) && 3184 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3185 !mmc_can_gpio_cd(host->mmc); 3186 } 3187 3188 /* 3189 * To enable wakeup events, the corresponding events have to be enabled in 3190 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 3191 * Table' in the SD Host Controller Standard Specification. 3192 * It is useless to restore SDHCI_INT_ENABLE state in 3193 * sdhci_disable_irq_wakeups() since it will be set by 3194 * sdhci_enable_card_detection() or sdhci_init(). 3195 */ 3196 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host) 3197 { 3198 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | 3199 SDHCI_WAKE_ON_INT; 3200 u32 irq_val = 0; 3201 u8 wake_val = 0; 3202 u8 val; 3203 3204 if (sdhci_cd_irq_can_wakeup(host)) { 3205 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE; 3206 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE; 3207 } 3208 3209 if (mmc_card_wake_sdio_irq(host->mmc)) { 3210 wake_val |= SDHCI_WAKE_ON_INT; 3211 irq_val |= SDHCI_INT_CARD_INT; 3212 } 3213 3214 if (!irq_val) 3215 return false; 3216 3217 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 3218 val &= ~mask; 3219 val |= wake_val; 3220 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 3221 3222 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 3223 3224 host->irq_wake_enabled = !enable_irq_wake(host->irq); 3225 3226 return host->irq_wake_enabled; 3227 } 3228 3229 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 3230 { 3231 u8 val; 3232 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 3233 | SDHCI_WAKE_ON_INT; 3234 3235 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 3236 val &= ~mask; 3237 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 3238 3239 disable_irq_wake(host->irq); 3240 3241 host->irq_wake_enabled = false; 3242 } 3243 3244 int sdhci_suspend_host(struct sdhci_host *host) 3245 { 3246 sdhci_disable_card_detection(host); 3247 3248 mmc_retune_timer_stop(host->mmc); 3249 3250 if (!device_may_wakeup(mmc_dev(host->mmc)) || 3251 !sdhci_enable_irq_wakeups(host)) { 3252 host->ier = 0; 3253 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3254 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3255 free_irq(host->irq, host); 3256 } 3257 3258 return 0; 3259 } 3260 3261 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 3262 3263 int sdhci_resume_host(struct sdhci_host *host) 3264 { 3265 struct mmc_host *mmc = host->mmc; 3266 int ret = 0; 3267 3268 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3269 if (host->ops->enable_dma) 3270 host->ops->enable_dma(host); 3271 } 3272 3273 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 3274 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 3275 /* Card keeps power but host controller does not */ 3276 sdhci_init(host, 0); 3277 host->pwr = 0; 3278 host->clock = 0; 3279 mmc->ops->set_ios(mmc, &mmc->ios); 3280 } else { 3281 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 3282 } 3283 3284 if (host->irq_wake_enabled) { 3285 sdhci_disable_irq_wakeups(host); 3286 } else { 3287 ret = request_threaded_irq(host->irq, sdhci_irq, 3288 sdhci_thread_irq, IRQF_SHARED, 3289 mmc_hostname(host->mmc), host); 3290 if (ret) 3291 return ret; 3292 } 3293 3294 sdhci_enable_card_detection(host); 3295 3296 return ret; 3297 } 3298 3299 EXPORT_SYMBOL_GPL(sdhci_resume_host); 3300 3301 int sdhci_runtime_suspend_host(struct sdhci_host *host) 3302 { 3303 unsigned long flags; 3304 3305 mmc_retune_timer_stop(host->mmc); 3306 3307 spin_lock_irqsave(&host->lock, flags); 3308 host->ier &= SDHCI_INT_CARD_INT; 3309 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3310 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3311 spin_unlock_irqrestore(&host->lock, flags); 3312 3313 synchronize_hardirq(host->irq); 3314 3315 spin_lock_irqsave(&host->lock, flags); 3316 host->runtime_suspended = true; 3317 spin_unlock_irqrestore(&host->lock, flags); 3318 3319 return 0; 3320 } 3321 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 3322 3323 int sdhci_runtime_resume_host(struct sdhci_host *host) 3324 { 3325 struct mmc_host *mmc = host->mmc; 3326 unsigned long flags; 3327 int host_flags = host->flags; 3328 3329 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3330 if (host->ops->enable_dma) 3331 host->ops->enable_dma(host); 3332 } 3333 3334 sdhci_init(host, 0); 3335 3336 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED && 3337 mmc->ios.power_mode != MMC_POWER_OFF) { 3338 /* Force clock and power re-program */ 3339 host->pwr = 0; 3340 host->clock = 0; 3341 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 3342 mmc->ops->set_ios(mmc, &mmc->ios); 3343 3344 if ((host_flags & SDHCI_PV_ENABLED) && 3345 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 3346 spin_lock_irqsave(&host->lock, flags); 3347 sdhci_enable_preset_value(host, true); 3348 spin_unlock_irqrestore(&host->lock, flags); 3349 } 3350 3351 if ((mmc->caps2 & MMC_CAP2_HS400_ES) && 3352 mmc->ops->hs400_enhanced_strobe) 3353 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); 3354 } 3355 3356 spin_lock_irqsave(&host->lock, flags); 3357 3358 host->runtime_suspended = false; 3359 3360 /* Enable SDIO IRQ */ 3361 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 3362 sdhci_enable_sdio_irq_nolock(host, true); 3363 3364 /* Enable Card Detection */ 3365 sdhci_enable_card_detection(host); 3366 3367 spin_unlock_irqrestore(&host->lock, flags); 3368 3369 return 0; 3370 } 3371 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 3372 3373 #endif /* CONFIG_PM */ 3374 3375 /*****************************************************************************\ 3376 * * 3377 * Command Queue Engine (CQE) helpers * 3378 * * 3379 \*****************************************************************************/ 3380 3381 void sdhci_cqe_enable(struct mmc_host *mmc) 3382 { 3383 struct sdhci_host *host = mmc_priv(mmc); 3384 unsigned long flags; 3385 u8 ctrl; 3386 3387 spin_lock_irqsave(&host->lock, flags); 3388 3389 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 3390 ctrl &= ~SDHCI_CTRL_DMA_MASK; 3391 /* 3392 * Host from V4.10 supports ADMA3 DMA type. 3393 * ADMA3 performs integrated descriptor which is more suitable 3394 * for cmd queuing to fetch both command and transfer descriptors. 3395 */ 3396 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3)) 3397 ctrl |= SDHCI_CTRL_ADMA3; 3398 else if (host->flags & SDHCI_USE_64_BIT_DMA) 3399 ctrl |= SDHCI_CTRL_ADMA64; 3400 else 3401 ctrl |= SDHCI_CTRL_ADMA32; 3402 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 3403 3404 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512), 3405 SDHCI_BLOCK_SIZE); 3406 3407 /* Set maximum timeout */ 3408 sdhci_set_timeout(host, NULL); 3409 3410 host->ier = host->cqe_ier; 3411 3412 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 3413 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 3414 3415 host->cqe_on = true; 3416 3417 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n", 3418 mmc_hostname(mmc), host->ier, 3419 sdhci_readl(host, SDHCI_INT_STATUS)); 3420 3421 spin_unlock_irqrestore(&host->lock, flags); 3422 } 3423 EXPORT_SYMBOL_GPL(sdhci_cqe_enable); 3424 3425 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery) 3426 { 3427 struct sdhci_host *host = mmc_priv(mmc); 3428 unsigned long flags; 3429 3430 spin_lock_irqsave(&host->lock, flags); 3431 3432 sdhci_set_default_irqs(host); 3433 3434 host->cqe_on = false; 3435 3436 if (recovery) { 3437 sdhci_do_reset(host, SDHCI_RESET_CMD); 3438 sdhci_do_reset(host, SDHCI_RESET_DATA); 3439 } 3440 3441 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n", 3442 mmc_hostname(mmc), host->ier, 3443 sdhci_readl(host, SDHCI_INT_STATUS)); 3444 3445 spin_unlock_irqrestore(&host->lock, flags); 3446 } 3447 EXPORT_SYMBOL_GPL(sdhci_cqe_disable); 3448 3449 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, 3450 int *data_error) 3451 { 3452 u32 mask; 3453 3454 if (!host->cqe_on) 3455 return false; 3456 3457 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) 3458 *cmd_error = -EILSEQ; 3459 else if (intmask & SDHCI_INT_TIMEOUT) 3460 *cmd_error = -ETIMEDOUT; 3461 else 3462 *cmd_error = 0; 3463 3464 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC)) 3465 *data_error = -EILSEQ; 3466 else if (intmask & SDHCI_INT_DATA_TIMEOUT) 3467 *data_error = -ETIMEDOUT; 3468 else if (intmask & SDHCI_INT_ADMA_ERROR) 3469 *data_error = -EIO; 3470 else 3471 *data_error = 0; 3472 3473 /* Clear selected interrupts. */ 3474 mask = intmask & host->cqe_ier; 3475 sdhci_writel(host, mask, SDHCI_INT_STATUS); 3476 3477 if (intmask & SDHCI_INT_BUS_POWER) 3478 pr_err("%s: Card is consuming too much power!\n", 3479 mmc_hostname(host->mmc)); 3480 3481 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR); 3482 if (intmask) { 3483 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 3484 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n", 3485 mmc_hostname(host->mmc), intmask); 3486 sdhci_dumpregs(host); 3487 } 3488 3489 return true; 3490 } 3491 EXPORT_SYMBOL_GPL(sdhci_cqe_irq); 3492 3493 /*****************************************************************************\ 3494 * * 3495 * Device allocation/registration * 3496 * * 3497 \*****************************************************************************/ 3498 3499 struct sdhci_host *sdhci_alloc_host(struct device *dev, 3500 size_t priv_size) 3501 { 3502 struct mmc_host *mmc; 3503 struct sdhci_host *host; 3504 3505 WARN_ON(dev == NULL); 3506 3507 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 3508 if (!mmc) 3509 return ERR_PTR(-ENOMEM); 3510 3511 host = mmc_priv(mmc); 3512 host->mmc = mmc; 3513 host->mmc_host_ops = sdhci_ops; 3514 mmc->ops = &host->mmc_host_ops; 3515 3516 host->flags = SDHCI_SIGNALING_330; 3517 3518 host->cqe_ier = SDHCI_CQE_INT_MASK; 3519 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK; 3520 3521 host->tuning_delay = -1; 3522 host->tuning_loop_count = MAX_TUNING_LOOP; 3523 3524 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG; 3525 3526 /* 3527 * The DMA table descriptor count is calculated as the maximum 3528 * number of segments times 2, to allow for an alignment 3529 * descriptor for each segment, plus 1 for a nop end descriptor. 3530 */ 3531 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1; 3532 3533 return host; 3534 } 3535 3536 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 3537 3538 static int sdhci_set_dma_mask(struct sdhci_host *host) 3539 { 3540 struct mmc_host *mmc = host->mmc; 3541 struct device *dev = mmc_dev(mmc); 3542 int ret = -EINVAL; 3543 3544 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 3545 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3546 3547 /* Try 64-bit mask if hardware is capable of it */ 3548 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3549 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 3550 if (ret) { 3551 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 3552 mmc_hostname(mmc)); 3553 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3554 } 3555 } 3556 3557 /* 32-bit mask as default & fallback */ 3558 if (ret) { 3559 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 3560 if (ret) 3561 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 3562 mmc_hostname(mmc)); 3563 } 3564 3565 return ret; 3566 } 3567 3568 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 3569 { 3570 u16 v; 3571 u64 dt_caps_mask = 0; 3572 u64 dt_caps = 0; 3573 3574 if (host->read_caps) 3575 return; 3576 3577 host->read_caps = true; 3578 3579 if (debug_quirks) 3580 host->quirks = debug_quirks; 3581 3582 if (debug_quirks2) 3583 host->quirks2 = debug_quirks2; 3584 3585 sdhci_do_reset(host, SDHCI_RESET_ALL); 3586 3587 if (host->v4_mode) 3588 sdhci_do_enable_v4_mode(host); 3589 3590 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3591 "sdhci-caps-mask", &dt_caps_mask); 3592 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3593 "sdhci-caps", &dt_caps); 3594 3595 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 3596 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 3597 3598 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 3599 return; 3600 3601 if (caps) { 3602 host->caps = *caps; 3603 } else { 3604 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 3605 host->caps &= ~lower_32_bits(dt_caps_mask); 3606 host->caps |= lower_32_bits(dt_caps); 3607 } 3608 3609 if (host->version < SDHCI_SPEC_300) 3610 return; 3611 3612 if (caps1) { 3613 host->caps1 = *caps1; 3614 } else { 3615 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 3616 host->caps1 &= ~upper_32_bits(dt_caps_mask); 3617 host->caps1 |= upper_32_bits(dt_caps); 3618 } 3619 } 3620 EXPORT_SYMBOL_GPL(__sdhci_read_caps); 3621 3622 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host) 3623 { 3624 struct mmc_host *mmc = host->mmc; 3625 unsigned int max_blocks; 3626 unsigned int bounce_size; 3627 int ret; 3628 3629 /* 3630 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer 3631 * has diminishing returns, this is probably because SD/MMC 3632 * cards are usually optimized to handle this size of requests. 3633 */ 3634 bounce_size = SZ_64K; 3635 /* 3636 * Adjust downwards to maximum request size if this is less 3637 * than our segment size, else hammer down the maximum 3638 * request size to the maximum buffer size. 3639 */ 3640 if (mmc->max_req_size < bounce_size) 3641 bounce_size = mmc->max_req_size; 3642 max_blocks = bounce_size / 512; 3643 3644 /* 3645 * When we just support one segment, we can get significant 3646 * speedups by the help of a bounce buffer to group scattered 3647 * reads/writes together. 3648 */ 3649 host->bounce_buffer = devm_kmalloc(mmc->parent, 3650 bounce_size, 3651 GFP_KERNEL); 3652 if (!host->bounce_buffer) { 3653 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n", 3654 mmc_hostname(mmc), 3655 bounce_size); 3656 /* 3657 * Exiting with zero here makes sure we proceed with 3658 * mmc->max_segs == 1. 3659 */ 3660 return; 3661 } 3662 3663 host->bounce_addr = dma_map_single(mmc->parent, 3664 host->bounce_buffer, 3665 bounce_size, 3666 DMA_BIDIRECTIONAL); 3667 ret = dma_mapping_error(mmc->parent, host->bounce_addr); 3668 if (ret) 3669 /* Again fall back to max_segs == 1 */ 3670 return; 3671 host->bounce_buffer_size = bounce_size; 3672 3673 /* Lie about this since we're bouncing */ 3674 mmc->max_segs = max_blocks; 3675 mmc->max_seg_size = bounce_size; 3676 mmc->max_req_size = bounce_size; 3677 3678 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n", 3679 mmc_hostname(mmc), max_blocks, bounce_size); 3680 } 3681 3682 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) 3683 { 3684 /* 3685 * According to SD Host Controller spec v4.10, bit[27] added from 3686 * version 4.10 in Capabilities Register is used as 64-bit System 3687 * Address support for V4 mode. 3688 */ 3689 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) 3690 return host->caps & SDHCI_CAN_64BIT_V4; 3691 3692 return host->caps & SDHCI_CAN_64BIT; 3693 } 3694 3695 int sdhci_setup_host(struct sdhci_host *host) 3696 { 3697 struct mmc_host *mmc; 3698 u32 max_current_caps; 3699 unsigned int ocr_avail; 3700 unsigned int override_timeout_clk; 3701 u32 max_clk; 3702 int ret; 3703 3704 WARN_ON(host == NULL); 3705 if (host == NULL) 3706 return -EINVAL; 3707 3708 mmc = host->mmc; 3709 3710 /* 3711 * If there are external regulators, get them. Note this must be done 3712 * early before resetting the host and reading the capabilities so that 3713 * the host can take the appropriate action if regulators are not 3714 * available. 3715 */ 3716 ret = mmc_regulator_get_supply(mmc); 3717 if (ret) 3718 return ret; 3719 3720 DBG("Version: 0x%08x | Present: 0x%08x\n", 3721 sdhci_readw(host, SDHCI_HOST_VERSION), 3722 sdhci_readl(host, SDHCI_PRESENT_STATE)); 3723 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n", 3724 sdhci_readl(host, SDHCI_CAPABILITIES), 3725 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 3726 3727 sdhci_read_caps(host); 3728 3729 override_timeout_clk = host->timeout_clk; 3730 3731 if (host->version > SDHCI_SPEC_420) { 3732 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3733 mmc_hostname(mmc), host->version); 3734 } 3735 3736 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3737 host->flags |= SDHCI_USE_SDMA; 3738 else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3739 DBG("Controller doesn't have SDMA capability\n"); 3740 else 3741 host->flags |= SDHCI_USE_SDMA; 3742 3743 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3744 (host->flags & SDHCI_USE_SDMA)) { 3745 DBG("Disabling DMA as it is marked broken\n"); 3746 host->flags &= ~SDHCI_USE_SDMA; 3747 } 3748 3749 if ((host->version >= SDHCI_SPEC_200) && 3750 (host->caps & SDHCI_CAN_DO_ADMA2)) 3751 host->flags |= SDHCI_USE_ADMA; 3752 3753 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3754 (host->flags & SDHCI_USE_ADMA)) { 3755 DBG("Disabling ADMA as it is marked broken\n"); 3756 host->flags &= ~SDHCI_USE_ADMA; 3757 } 3758 3759 /* 3760 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3761 * and *must* do 64-bit DMA. A driver has the opportunity to change 3762 * that during the first call to ->enable_dma(). Similarly 3763 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3764 * implement. 3765 */ 3766 if (sdhci_can_64bit_dma(host)) 3767 host->flags |= SDHCI_USE_64_BIT_DMA; 3768 3769 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3770 ret = sdhci_set_dma_mask(host); 3771 3772 if (!ret && host->ops->enable_dma) 3773 ret = host->ops->enable_dma(host); 3774 3775 if (ret) { 3776 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3777 mmc_hostname(mmc)); 3778 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 3779 3780 ret = 0; 3781 } 3782 } 3783 3784 /* SDMA does not support 64-bit DMA if v4 mode not set */ 3785 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode) 3786 host->flags &= ~SDHCI_USE_SDMA; 3787 3788 if (host->flags & SDHCI_USE_ADMA) { 3789 dma_addr_t dma; 3790 void *buf; 3791 3792 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3793 host->adma_table_sz = host->adma_table_cnt * 3794 SDHCI_ADMA2_64_DESC_SZ(host); 3795 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); 3796 } else { 3797 host->adma_table_sz = host->adma_table_cnt * 3798 SDHCI_ADMA2_32_DESC_SZ; 3799 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3800 } 3801 3802 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3803 /* 3804 * Use zalloc to zero the reserved high 32-bits of 128-bit 3805 * descriptors so that they never need to be written. 3806 */ 3807 buf = dma_alloc_coherent(mmc_dev(mmc), 3808 host->align_buffer_sz + host->adma_table_sz, 3809 &dma, GFP_KERNEL); 3810 if (!buf) { 3811 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 3812 mmc_hostname(mmc)); 3813 host->flags &= ~SDHCI_USE_ADMA; 3814 } else if ((dma + host->align_buffer_sz) & 3815 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 3816 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3817 mmc_hostname(mmc)); 3818 host->flags &= ~SDHCI_USE_ADMA; 3819 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3820 host->adma_table_sz, buf, dma); 3821 } else { 3822 host->align_buffer = buf; 3823 host->align_addr = dma; 3824 3825 host->adma_table = buf + host->align_buffer_sz; 3826 host->adma_addr = dma + host->align_buffer_sz; 3827 } 3828 } 3829 3830 /* 3831 * If we use DMA, then it's up to the caller to set the DMA 3832 * mask, but PIO does not need the hw shim so we set a new 3833 * mask here in that case. 3834 */ 3835 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3836 host->dma_mask = DMA_BIT_MASK(64); 3837 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3838 } 3839 3840 if (host->version >= SDHCI_SPEC_300) 3841 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3842 >> SDHCI_CLOCK_BASE_SHIFT; 3843 else 3844 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3845 >> SDHCI_CLOCK_BASE_SHIFT; 3846 3847 host->max_clk *= 1000000; 3848 if (host->max_clk == 0 || host->quirks & 3849 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3850 if (!host->ops->get_max_clock) { 3851 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 3852 mmc_hostname(mmc)); 3853 ret = -ENODEV; 3854 goto undma; 3855 } 3856 host->max_clk = host->ops->get_max_clock(host); 3857 } 3858 3859 /* 3860 * In case of Host Controller v3.00, find out whether clock 3861 * multiplier is supported. 3862 */ 3863 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3864 SDHCI_CLOCK_MUL_SHIFT; 3865 3866 /* 3867 * In case the value in Clock Multiplier is 0, then programmable 3868 * clock mode is not supported, otherwise the actual clock 3869 * multiplier is one more than the value of Clock Multiplier 3870 * in the Capabilities Register. 3871 */ 3872 if (host->clk_mul) 3873 host->clk_mul += 1; 3874 3875 /* 3876 * Set host parameters. 3877 */ 3878 max_clk = host->max_clk; 3879 3880 if (host->ops->get_min_clock) 3881 mmc->f_min = host->ops->get_min_clock(host); 3882 else if (host->version >= SDHCI_SPEC_300) { 3883 if (host->clk_mul) { 3884 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3885 max_clk = host->max_clk * host->clk_mul; 3886 } else 3887 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3888 } else 3889 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3890 3891 if (!mmc->f_max || mmc->f_max > max_clk) 3892 mmc->f_max = max_clk; 3893 3894 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3895 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 3896 SDHCI_TIMEOUT_CLK_SHIFT; 3897 3898 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 3899 host->timeout_clk *= 1000; 3900 3901 if (host->timeout_clk == 0) { 3902 if (!host->ops->get_timeout_clock) { 3903 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3904 mmc_hostname(mmc)); 3905 ret = -ENODEV; 3906 goto undma; 3907 } 3908 3909 host->timeout_clk = 3910 DIV_ROUND_UP(host->ops->get_timeout_clock(host), 3911 1000); 3912 } 3913 3914 if (override_timeout_clk) 3915 host->timeout_clk = override_timeout_clk; 3916 3917 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3918 host->ops->get_max_timeout_count(host) : 1 << 27; 3919 mmc->max_busy_timeout /= host->timeout_clk; 3920 } 3921 3922 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && 3923 !host->ops->get_max_timeout_count) 3924 mmc->max_busy_timeout = 0; 3925 3926 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3927 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3928 3929 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3930 host->flags |= SDHCI_AUTO_CMD12; 3931 3932 /* 3933 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO. 3934 * For v4 mode, SDMA may use Auto-CMD23 as well. 3935 */ 3936 if ((host->version >= SDHCI_SPEC_300) && 3937 ((host->flags & SDHCI_USE_ADMA) || 3938 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && 3939 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3940 host->flags |= SDHCI_AUTO_CMD23; 3941 DBG("Auto-CMD23 available\n"); 3942 } else { 3943 DBG("Auto-CMD23 unavailable\n"); 3944 } 3945 3946 /* 3947 * A controller may support 8-bit width, but the board itself 3948 * might not have the pins brought out. Boards that support 3949 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3950 * their platform code before calling sdhci_add_host(), and we 3951 * won't assume 8-bit width for hosts without that CAP. 3952 */ 3953 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3954 mmc->caps |= MMC_CAP_4_BIT_DATA; 3955 3956 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3957 mmc->caps &= ~MMC_CAP_CMD23; 3958 3959 if (host->caps & SDHCI_CAN_DO_HISPD) 3960 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3961 3962 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3963 mmc_card_is_removable(mmc) && 3964 mmc_gpio_get_cd(host->mmc) < 0) 3965 mmc->caps |= MMC_CAP_NEEDS_POLL; 3966 3967 if (!IS_ERR(mmc->supply.vqmmc)) { 3968 ret = regulator_enable(mmc->supply.vqmmc); 3969 3970 /* If vqmmc provides no 1.8V signalling, then there's no UHS */ 3971 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3972 1950000)) 3973 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 3974 SDHCI_SUPPORT_SDR50 | 3975 SDHCI_SUPPORT_DDR50); 3976 3977 /* In eMMC case vqmmc might be a fixed 1.8V regulator */ 3978 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, 3979 3600000)) 3980 host->flags &= ~SDHCI_SIGNALING_330; 3981 3982 if (ret) { 3983 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3984 mmc_hostname(mmc), ret); 3985 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3986 } 3987 } 3988 3989 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 3990 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3991 SDHCI_SUPPORT_DDR50); 3992 /* 3993 * The SDHCI controller in a SoC might support HS200/HS400 3994 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property), 3995 * but if the board is modeled such that the IO lines are not 3996 * connected to 1.8v then HS200/HS400 cannot be supported. 3997 * Disable HS200/HS400 if the board does not have 1.8v connected 3998 * to the IO lines. (Applicable for other modes in 1.8v) 3999 */ 4000 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES); 4001 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS); 4002 } 4003 4004 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 4005 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 4006 SDHCI_SUPPORT_DDR50)) 4007 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 4008 4009 /* SDR104 supports also implies SDR50 support */ 4010 if (host->caps1 & SDHCI_SUPPORT_SDR104) { 4011 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 4012 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 4013 * field can be promoted to support HS200. 4014 */ 4015 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 4016 mmc->caps2 |= MMC_CAP2_HS200; 4017 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 4018 mmc->caps |= MMC_CAP_UHS_SDR50; 4019 } 4020 4021 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 4022 (host->caps1 & SDHCI_SUPPORT_HS400)) 4023 mmc->caps2 |= MMC_CAP2_HS400; 4024 4025 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 4026 (IS_ERR(mmc->supply.vqmmc) || 4027 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 4028 1300000))) 4029 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 4030 4031 if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 4032 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 4033 mmc->caps |= MMC_CAP_UHS_DDR50; 4034 4035 /* Does the host need tuning for SDR50? */ 4036 if (host->caps1 & SDHCI_USE_SDR50_TUNING) 4037 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 4038 4039 /* Driver Type(s) (A, C, D) supported by the host */ 4040 if (host->caps1 & SDHCI_DRIVER_TYPE_A) 4041 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 4042 if (host->caps1 & SDHCI_DRIVER_TYPE_C) 4043 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 4044 if (host->caps1 & SDHCI_DRIVER_TYPE_D) 4045 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 4046 4047 /* Initial value for re-tuning timer count */ 4048 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 4049 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 4050 4051 /* 4052 * In case Re-tuning Timer is not disabled, the actual value of 4053 * re-tuning timer will be 2 ^ (n - 1). 4054 */ 4055 if (host->tuning_count) 4056 host->tuning_count = 1 << (host->tuning_count - 1); 4057 4058 /* Re-tuning mode supported by the Host Controller */ 4059 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 4060 SDHCI_RETUNING_MODE_SHIFT; 4061 4062 ocr_avail = 0; 4063 4064 /* 4065 * According to SD Host Controller spec v3.00, if the Host System 4066 * can afford more than 150mA, Host Driver should set XPC to 1. Also 4067 * the value is meaningful only if Voltage Support in the Capabilities 4068 * register is set. The actual current value is 4 times the register 4069 * value. 4070 */ 4071 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 4072 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 4073 int curr = regulator_get_current_limit(mmc->supply.vmmc); 4074 if (curr > 0) { 4075 4076 /* convert to SDHCI_MAX_CURRENT format */ 4077 curr = curr/1000; /* convert to mA */ 4078 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 4079 4080 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 4081 max_current_caps = 4082 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 4083 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 4084 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 4085 } 4086 } 4087 4088 if (host->caps & SDHCI_CAN_VDD_330) { 4089 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 4090 4091 mmc->max_current_330 = ((max_current_caps & 4092 SDHCI_MAX_CURRENT_330_MASK) >> 4093 SDHCI_MAX_CURRENT_330_SHIFT) * 4094 SDHCI_MAX_CURRENT_MULTIPLIER; 4095 } 4096 if (host->caps & SDHCI_CAN_VDD_300) { 4097 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 4098 4099 mmc->max_current_300 = ((max_current_caps & 4100 SDHCI_MAX_CURRENT_300_MASK) >> 4101 SDHCI_MAX_CURRENT_300_SHIFT) * 4102 SDHCI_MAX_CURRENT_MULTIPLIER; 4103 } 4104 if (host->caps & SDHCI_CAN_VDD_180) { 4105 ocr_avail |= MMC_VDD_165_195; 4106 4107 mmc->max_current_180 = ((max_current_caps & 4108 SDHCI_MAX_CURRENT_180_MASK) >> 4109 SDHCI_MAX_CURRENT_180_SHIFT) * 4110 SDHCI_MAX_CURRENT_MULTIPLIER; 4111 } 4112 4113 /* If OCR set by host, use it instead. */ 4114 if (host->ocr_mask) 4115 ocr_avail = host->ocr_mask; 4116 4117 /* If OCR set by external regulators, give it highest prio. */ 4118 if (mmc->ocr_avail) 4119 ocr_avail = mmc->ocr_avail; 4120 4121 mmc->ocr_avail = ocr_avail; 4122 mmc->ocr_avail_sdio = ocr_avail; 4123 if (host->ocr_avail_sdio) 4124 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 4125 mmc->ocr_avail_sd = ocr_avail; 4126 if (host->ocr_avail_sd) 4127 mmc->ocr_avail_sd &= host->ocr_avail_sd; 4128 else /* normal SD controllers don't support 1.8V */ 4129 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 4130 mmc->ocr_avail_mmc = ocr_avail; 4131 if (host->ocr_avail_mmc) 4132 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 4133 4134 if (mmc->ocr_avail == 0) { 4135 pr_err("%s: Hardware doesn't report any support voltages.\n", 4136 mmc_hostname(mmc)); 4137 ret = -ENODEV; 4138 goto unreg; 4139 } 4140 4141 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 4142 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 4143 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 4144 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 4145 host->flags |= SDHCI_SIGNALING_180; 4146 4147 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 4148 host->flags |= SDHCI_SIGNALING_120; 4149 4150 spin_lock_init(&host->lock); 4151 4152 /* 4153 * Maximum number of sectors in one transfer. Limited by SDMA boundary 4154 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 4155 * is less anyway. 4156 */ 4157 mmc->max_req_size = 524288; 4158 4159 /* 4160 * Maximum number of segments. Depends on if the hardware 4161 * can do scatter/gather or not. 4162 */ 4163 if (host->flags & SDHCI_USE_ADMA) { 4164 mmc->max_segs = SDHCI_MAX_SEGS; 4165 } else if (host->flags & SDHCI_USE_SDMA) { 4166 mmc->max_segs = 1; 4167 if (swiotlb_max_segment()) { 4168 unsigned int max_req_size = (1 << IO_TLB_SHIFT) * 4169 IO_TLB_SEGSIZE; 4170 mmc->max_req_size = min(mmc->max_req_size, 4171 max_req_size); 4172 } 4173 } else { /* PIO */ 4174 mmc->max_segs = SDHCI_MAX_SEGS; 4175 } 4176 4177 /* 4178 * Maximum segment size. Could be one segment with the maximum number 4179 * of bytes. When doing hardware scatter/gather, each entry cannot 4180 * be larger than 64 KiB though. 4181 */ 4182 if (host->flags & SDHCI_USE_ADMA) { 4183 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 4184 mmc->max_seg_size = 65535; 4185 else 4186 mmc->max_seg_size = 65536; 4187 } else { 4188 mmc->max_seg_size = mmc->max_req_size; 4189 } 4190 4191 /* 4192 * Maximum block size. This varies from controller to controller and 4193 * is specified in the capabilities register. 4194 */ 4195 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 4196 mmc->max_blk_size = 2; 4197 } else { 4198 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 4199 SDHCI_MAX_BLOCK_SHIFT; 4200 if (mmc->max_blk_size >= 3) { 4201 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 4202 mmc_hostname(mmc)); 4203 mmc->max_blk_size = 0; 4204 } 4205 } 4206 4207 mmc->max_blk_size = 512 << mmc->max_blk_size; 4208 4209 /* 4210 * Maximum block count. 4211 */ 4212 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 4213 4214 if (mmc->max_segs == 1) 4215 /* This may alter mmc->*_blk_* parameters */ 4216 sdhci_allocate_bounce_buffer(host); 4217 4218 return 0; 4219 4220 unreg: 4221 if (!IS_ERR(mmc->supply.vqmmc)) 4222 regulator_disable(mmc->supply.vqmmc); 4223 undma: 4224 if (host->align_buffer) 4225 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4226 host->adma_table_sz, host->align_buffer, 4227 host->align_addr); 4228 host->adma_table = NULL; 4229 host->align_buffer = NULL; 4230 4231 return ret; 4232 } 4233 EXPORT_SYMBOL_GPL(sdhci_setup_host); 4234 4235 void sdhci_cleanup_host(struct sdhci_host *host) 4236 { 4237 struct mmc_host *mmc = host->mmc; 4238 4239 if (!IS_ERR(mmc->supply.vqmmc)) 4240 regulator_disable(mmc->supply.vqmmc); 4241 4242 if (host->align_buffer) 4243 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4244 host->adma_table_sz, host->align_buffer, 4245 host->align_addr); 4246 host->adma_table = NULL; 4247 host->align_buffer = NULL; 4248 } 4249 EXPORT_SYMBOL_GPL(sdhci_cleanup_host); 4250 4251 int __sdhci_add_host(struct sdhci_host *host) 4252 { 4253 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; 4254 struct mmc_host *mmc = host->mmc; 4255 int ret; 4256 4257 host->complete_wq = alloc_workqueue("sdhci", flags, 0); 4258 if (!host->complete_wq) 4259 return -ENOMEM; 4260 4261 INIT_WORK(&host->complete_work, sdhci_complete_work); 4262 4263 timer_setup(&host->timer, sdhci_timeout_timer, 0); 4264 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); 4265 4266 init_waitqueue_head(&host->buf_ready_int); 4267 4268 sdhci_init(host, 0); 4269 4270 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 4271 IRQF_SHARED, mmc_hostname(mmc), host); 4272 if (ret) { 4273 pr_err("%s: Failed to request IRQ %d: %d\n", 4274 mmc_hostname(mmc), host->irq, ret); 4275 goto unwq; 4276 } 4277 4278 ret = sdhci_led_register(host); 4279 if (ret) { 4280 pr_err("%s: Failed to register LED device: %d\n", 4281 mmc_hostname(mmc), ret); 4282 goto unirq; 4283 } 4284 4285 ret = mmc_add_host(mmc); 4286 if (ret) 4287 goto unled; 4288 4289 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 4290 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 4291 (host->flags & SDHCI_USE_ADMA) ? 4292 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 4293 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 4294 4295 sdhci_enable_card_detection(host); 4296 4297 return 0; 4298 4299 unled: 4300 sdhci_led_unregister(host); 4301 unirq: 4302 sdhci_do_reset(host, SDHCI_RESET_ALL); 4303 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 4305 free_irq(host->irq, host); 4306 unwq: 4307 destroy_workqueue(host->complete_wq); 4308 4309 return ret; 4310 } 4311 EXPORT_SYMBOL_GPL(__sdhci_add_host); 4312 4313 int sdhci_add_host(struct sdhci_host *host) 4314 { 4315 int ret; 4316 4317 ret = sdhci_setup_host(host); 4318 if (ret) 4319 return ret; 4320 4321 ret = __sdhci_add_host(host); 4322 if (ret) 4323 goto cleanup; 4324 4325 return 0; 4326 4327 cleanup: 4328 sdhci_cleanup_host(host); 4329 4330 return ret; 4331 } 4332 EXPORT_SYMBOL_GPL(sdhci_add_host); 4333 4334 void sdhci_remove_host(struct sdhci_host *host, int dead) 4335 { 4336 struct mmc_host *mmc = host->mmc; 4337 unsigned long flags; 4338 4339 if (dead) { 4340 spin_lock_irqsave(&host->lock, flags); 4341 4342 host->flags |= SDHCI_DEVICE_DEAD; 4343 4344 if (sdhci_has_requests(host)) { 4345 pr_err("%s: Controller removed during " 4346 " transfer!\n", mmc_hostname(mmc)); 4347 sdhci_error_out_mrqs(host, -ENOMEDIUM); 4348 } 4349 4350 spin_unlock_irqrestore(&host->lock, flags); 4351 } 4352 4353 sdhci_disable_card_detection(host); 4354 4355 mmc_remove_host(mmc); 4356 4357 sdhci_led_unregister(host); 4358 4359 if (!dead) 4360 sdhci_do_reset(host, SDHCI_RESET_ALL); 4361 4362 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 4363 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 4364 free_irq(host->irq, host); 4365 4366 del_timer_sync(&host->timer); 4367 del_timer_sync(&host->data_timer); 4368 4369 destroy_workqueue(host->complete_wq); 4370 4371 if (!IS_ERR(mmc->supply.vqmmc)) 4372 regulator_disable(mmc->supply.vqmmc); 4373 4374 if (host->align_buffer) 4375 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 4376 host->adma_table_sz, host->align_buffer, 4377 host->align_addr); 4378 4379 host->adma_table = NULL; 4380 host->align_buffer = NULL; 4381 } 4382 4383 EXPORT_SYMBOL_GPL(sdhci_remove_host); 4384 4385 void sdhci_free_host(struct sdhci_host *host) 4386 { 4387 mmc_free_host(host->mmc); 4388 } 4389 4390 EXPORT_SYMBOL_GPL(sdhci_free_host); 4391 4392 /*****************************************************************************\ 4393 * * 4394 * Driver init/exit * 4395 * * 4396 \*****************************************************************************/ 4397 4398 static int __init sdhci_drv_init(void) 4399 { 4400 pr_info(DRIVER_NAME 4401 ": Secure Digital Host Controller Interface driver\n"); 4402 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 4403 4404 return 0; 4405 } 4406 4407 static void __exit sdhci_drv_exit(void) 4408 { 4409 } 4410 4411 module_init(sdhci_drv_init); 4412 module_exit(sdhci_drv_exit); 4413 4414 module_param(debug_quirks, uint, 0444); 4415 module_param(debug_quirks2, uint, 0444); 4416 4417 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 4418 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 4419 MODULE_LICENSE("GPL"); 4420 4421 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 4422 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 4423