1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/scatterlist.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <linux/leds.h> 25 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/host.h> 28 29 #include "sdhci.h" 30 31 #define DRIVER_NAME "sdhci" 32 33 #define DBG(f, x...) \ 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 35 36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 37 defined(CONFIG_MMC_SDHCI_MODULE)) 38 #define SDHCI_USE_LEDS_CLASS 39 #endif 40 41 #define MAX_TUNING_LOOP 40 42 43 static unsigned int debug_quirks = 0; 44 45 static void sdhci_finish_data(struct sdhci_host *); 46 47 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 48 static void sdhci_finish_command(struct sdhci_host *); 49 static int sdhci_execute_tuning(struct mmc_host *mmc); 50 static void sdhci_tuning_timer(unsigned long data); 51 52 static void sdhci_dumpregs(struct sdhci_host *host) 53 { 54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 55 mmc_hostname(host->mmc)); 56 57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 58 sdhci_readl(host, SDHCI_DMA_ADDRESS), 59 sdhci_readw(host, SDHCI_HOST_VERSION)); 60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 61 sdhci_readw(host, SDHCI_BLOCK_SIZE), 62 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 64 sdhci_readl(host, SDHCI_ARGUMENT), 65 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 67 sdhci_readl(host, SDHCI_PRESENT_STATE), 68 sdhci_readb(host, SDHCI_HOST_CONTROL)); 69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 70 sdhci_readb(host, SDHCI_POWER_CONTROL), 71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 74 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 77 sdhci_readl(host, SDHCI_INT_STATUS)); 78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 79 sdhci_readl(host, SDHCI_INT_ENABLE), 80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 82 sdhci_readw(host, SDHCI_ACMD12_ERR), 83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 85 sdhci_readl(host, SDHCI_CAPABILITIES), 86 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 88 sdhci_readw(host, SDHCI_COMMAND), 89 sdhci_readl(host, SDHCI_MAX_CURRENT)); 90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n", 91 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 92 93 if (host->flags & SDHCI_USE_ADMA) 94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 95 readl(host->ioaddr + SDHCI_ADMA_ERROR), 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 97 98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); 99 } 100 101 /*****************************************************************************\ 102 * * 103 * Low level functions * 104 * * 105 \*****************************************************************************/ 106 107 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 108 { 109 u32 ier; 110 111 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 112 ier &= ~clear; 113 ier |= set; 114 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 116 } 117 118 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 119 { 120 sdhci_clear_set_irqs(host, 0, irqs); 121 } 122 123 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 124 { 125 sdhci_clear_set_irqs(host, irqs, 0); 126 } 127 128 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 129 { 130 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; 131 132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 133 return; 134 135 if (enable) 136 sdhci_unmask_irqs(host, irqs); 137 else 138 sdhci_mask_irqs(host, irqs); 139 } 140 141 static void sdhci_enable_card_detection(struct sdhci_host *host) 142 { 143 sdhci_set_card_detection(host, true); 144 } 145 146 static void sdhci_disable_card_detection(struct sdhci_host *host) 147 { 148 sdhci_set_card_detection(host, false); 149 } 150 151 static void sdhci_reset(struct sdhci_host *host, u8 mask) 152 { 153 unsigned long timeout; 154 u32 uninitialized_var(ier); 155 156 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 157 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 158 SDHCI_CARD_PRESENT)) 159 return; 160 } 161 162 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 163 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 164 165 if (host->ops->platform_reset_enter) 166 host->ops->platform_reset_enter(host, mask); 167 168 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 169 170 if (mask & SDHCI_RESET_ALL) 171 host->clock = 0; 172 173 /* Wait max 100 ms */ 174 timeout = 100; 175 176 /* hw clears the bit when it's done */ 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 178 if (timeout == 0) { 179 printk(KERN_ERR "%s: Reset 0x%x never completed.\n", 180 mmc_hostname(host->mmc), (int)mask); 181 sdhci_dumpregs(host); 182 return; 183 } 184 timeout--; 185 mdelay(1); 186 } 187 188 if (host->ops->platform_reset_exit) 189 host->ops->platform_reset_exit(host, mask); 190 191 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 192 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 193 } 194 195 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 196 197 static void sdhci_init(struct sdhci_host *host, int soft) 198 { 199 if (soft) 200 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 201 else 202 sdhci_reset(host, SDHCI_RESET_ALL); 203 204 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 205 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 206 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 207 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 208 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 209 210 if (soft) { 211 /* force clock reconfiguration */ 212 host->clock = 0; 213 sdhci_set_ios(host->mmc, &host->mmc->ios); 214 } 215 } 216 217 static void sdhci_reinit(struct sdhci_host *host) 218 { 219 sdhci_init(host, 0); 220 sdhci_enable_card_detection(host); 221 } 222 223 static void sdhci_activate_led(struct sdhci_host *host) 224 { 225 u8 ctrl; 226 227 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 228 ctrl |= SDHCI_CTRL_LED; 229 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 230 } 231 232 static void sdhci_deactivate_led(struct sdhci_host *host) 233 { 234 u8 ctrl; 235 236 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 237 ctrl &= ~SDHCI_CTRL_LED; 238 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 239 } 240 241 #ifdef SDHCI_USE_LEDS_CLASS 242 static void sdhci_led_control(struct led_classdev *led, 243 enum led_brightness brightness) 244 { 245 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 246 unsigned long flags; 247 248 spin_lock_irqsave(&host->lock, flags); 249 250 if (brightness == LED_OFF) 251 sdhci_deactivate_led(host); 252 else 253 sdhci_activate_led(host); 254 255 spin_unlock_irqrestore(&host->lock, flags); 256 } 257 #endif 258 259 /*****************************************************************************\ 260 * * 261 * Core functions * 262 * * 263 \*****************************************************************************/ 264 265 static void sdhci_read_block_pio(struct sdhci_host *host) 266 { 267 unsigned long flags; 268 size_t blksize, len, chunk; 269 u32 uninitialized_var(scratch); 270 u8 *buf; 271 272 DBG("PIO reading\n"); 273 274 blksize = host->data->blksz; 275 chunk = 0; 276 277 local_irq_save(flags); 278 279 while (blksize) { 280 if (!sg_miter_next(&host->sg_miter)) 281 BUG(); 282 283 len = min(host->sg_miter.length, blksize); 284 285 blksize -= len; 286 host->sg_miter.consumed = len; 287 288 buf = host->sg_miter.addr; 289 290 while (len) { 291 if (chunk == 0) { 292 scratch = sdhci_readl(host, SDHCI_BUFFER); 293 chunk = 4; 294 } 295 296 *buf = scratch & 0xFF; 297 298 buf++; 299 scratch >>= 8; 300 chunk--; 301 len--; 302 } 303 } 304 305 sg_miter_stop(&host->sg_miter); 306 307 local_irq_restore(flags); 308 } 309 310 static void sdhci_write_block_pio(struct sdhci_host *host) 311 { 312 unsigned long flags; 313 size_t blksize, len, chunk; 314 u32 scratch; 315 u8 *buf; 316 317 DBG("PIO writing\n"); 318 319 blksize = host->data->blksz; 320 chunk = 0; 321 scratch = 0; 322 323 local_irq_save(flags); 324 325 while (blksize) { 326 if (!sg_miter_next(&host->sg_miter)) 327 BUG(); 328 329 len = min(host->sg_miter.length, blksize); 330 331 blksize -= len; 332 host->sg_miter.consumed = len; 333 334 buf = host->sg_miter.addr; 335 336 while (len) { 337 scratch |= (u32)*buf << (chunk * 8); 338 339 buf++; 340 chunk++; 341 len--; 342 343 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 344 sdhci_writel(host, scratch, SDHCI_BUFFER); 345 chunk = 0; 346 scratch = 0; 347 } 348 } 349 } 350 351 sg_miter_stop(&host->sg_miter); 352 353 local_irq_restore(flags); 354 } 355 356 static void sdhci_transfer_pio(struct sdhci_host *host) 357 { 358 u32 mask; 359 360 BUG_ON(!host->data); 361 362 if (host->blocks == 0) 363 return; 364 365 if (host->data->flags & MMC_DATA_READ) 366 mask = SDHCI_DATA_AVAILABLE; 367 else 368 mask = SDHCI_SPACE_AVAILABLE; 369 370 /* 371 * Some controllers (JMicron JMB38x) mess up the buffer bits 372 * for transfers < 4 bytes. As long as it is just one block, 373 * we can ignore the bits. 374 */ 375 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 376 (host->data->blocks == 1)) 377 mask = ~0; 378 379 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 380 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 381 udelay(100); 382 383 if (host->data->flags & MMC_DATA_READ) 384 sdhci_read_block_pio(host); 385 else 386 sdhci_write_block_pio(host); 387 388 host->blocks--; 389 if (host->blocks == 0) 390 break; 391 } 392 393 DBG("PIO transfer complete.\n"); 394 } 395 396 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 397 { 398 local_irq_save(*flags); 399 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 400 } 401 402 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 403 { 404 kunmap_atomic(buffer, KM_BIO_SRC_IRQ); 405 local_irq_restore(*flags); 406 } 407 408 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 409 { 410 __le32 *dataddr = (__le32 __force *)(desc + 4); 411 __le16 *cmdlen = (__le16 __force *)desc; 412 413 /* SDHCI specification says ADMA descriptors should be 4 byte 414 * aligned, so using 16 or 32bit operations should be safe. */ 415 416 cmdlen[0] = cpu_to_le16(cmd); 417 cmdlen[1] = cpu_to_le16(len); 418 419 dataddr[0] = cpu_to_le32(addr); 420 } 421 422 static int sdhci_adma_table_pre(struct sdhci_host *host, 423 struct mmc_data *data) 424 { 425 int direction; 426 427 u8 *desc; 428 u8 *align; 429 dma_addr_t addr; 430 dma_addr_t align_addr; 431 int len, offset; 432 433 struct scatterlist *sg; 434 int i; 435 char *buffer; 436 unsigned long flags; 437 438 /* 439 * The spec does not specify endianness of descriptor table. 440 * We currently guess that it is LE. 441 */ 442 443 if (data->flags & MMC_DATA_READ) 444 direction = DMA_FROM_DEVICE; 445 else 446 direction = DMA_TO_DEVICE; 447 448 /* 449 * The ADMA descriptor table is mapped further down as we 450 * need to fill it with data first. 451 */ 452 453 host->align_addr = dma_map_single(mmc_dev(host->mmc), 454 host->align_buffer, 128 * 4, direction); 455 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 456 goto fail; 457 BUG_ON(host->align_addr & 0x3); 458 459 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 460 data->sg, data->sg_len, direction); 461 if (host->sg_count == 0) 462 goto unmap_align; 463 464 desc = host->adma_desc; 465 align = host->align_buffer; 466 467 align_addr = host->align_addr; 468 469 for_each_sg(data->sg, sg, host->sg_count, i) { 470 addr = sg_dma_address(sg); 471 len = sg_dma_len(sg); 472 473 /* 474 * The SDHCI specification states that ADMA 475 * addresses must be 32-bit aligned. If they 476 * aren't, then we use a bounce buffer for 477 * the (up to three) bytes that screw up the 478 * alignment. 479 */ 480 offset = (4 - (addr & 0x3)) & 0x3; 481 if (offset) { 482 if (data->flags & MMC_DATA_WRITE) { 483 buffer = sdhci_kmap_atomic(sg, &flags); 484 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 485 memcpy(align, buffer, offset); 486 sdhci_kunmap_atomic(buffer, &flags); 487 } 488 489 /* tran, valid */ 490 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 491 492 BUG_ON(offset > 65536); 493 494 align += 4; 495 align_addr += 4; 496 497 desc += 8; 498 499 addr += offset; 500 len -= offset; 501 } 502 503 BUG_ON(len > 65536); 504 505 /* tran, valid */ 506 sdhci_set_adma_desc(desc, addr, len, 0x21); 507 desc += 8; 508 509 /* 510 * If this triggers then we have a calculation bug 511 * somewhere. :/ 512 */ 513 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 514 } 515 516 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 517 /* 518 * Mark the last descriptor as the terminating descriptor 519 */ 520 if (desc != host->adma_desc) { 521 desc -= 8; 522 desc[0] |= 0x2; /* end */ 523 } 524 } else { 525 /* 526 * Add a terminating entry. 527 */ 528 529 /* nop, end, valid */ 530 sdhci_set_adma_desc(desc, 0, 0, 0x3); 531 } 532 533 /* 534 * Resync align buffer as we might have changed it. 535 */ 536 if (data->flags & MMC_DATA_WRITE) { 537 dma_sync_single_for_device(mmc_dev(host->mmc), 538 host->align_addr, 128 * 4, direction); 539 } 540 541 host->adma_addr = dma_map_single(mmc_dev(host->mmc), 542 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 543 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 544 goto unmap_entries; 545 BUG_ON(host->adma_addr & 0x3); 546 547 return 0; 548 549 unmap_entries: 550 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 551 data->sg_len, direction); 552 unmap_align: 553 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 554 128 * 4, direction); 555 fail: 556 return -EINVAL; 557 } 558 559 static void sdhci_adma_table_post(struct sdhci_host *host, 560 struct mmc_data *data) 561 { 562 int direction; 563 564 struct scatterlist *sg; 565 int i, size; 566 u8 *align; 567 char *buffer; 568 unsigned long flags; 569 570 if (data->flags & MMC_DATA_READ) 571 direction = DMA_FROM_DEVICE; 572 else 573 direction = DMA_TO_DEVICE; 574 575 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 576 (128 * 2 + 1) * 4, DMA_TO_DEVICE); 577 578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 579 128 * 4, direction); 580 581 if (data->flags & MMC_DATA_READ) { 582 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 583 data->sg_len, direction); 584 585 align = host->align_buffer; 586 587 for_each_sg(data->sg, sg, host->sg_count, i) { 588 if (sg_dma_address(sg) & 0x3) { 589 size = 4 - (sg_dma_address(sg) & 0x3); 590 591 buffer = sdhci_kmap_atomic(sg, &flags); 592 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 593 memcpy(buffer, align, size); 594 sdhci_kunmap_atomic(buffer, &flags); 595 596 align += 4; 597 } 598 } 599 } 600 601 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 602 data->sg_len, direction); 603 } 604 605 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 606 { 607 u8 count; 608 struct mmc_data *data = cmd->data; 609 unsigned target_timeout, current_timeout; 610 611 /* 612 * If the host controller provides us with an incorrect timeout 613 * value, just skip the check and use 0xE. The hardware may take 614 * longer to time out, but that's much better than having a too-short 615 * timeout value. 616 */ 617 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 618 return 0xE; 619 620 /* Unspecified timeout, assume max */ 621 if (!data && !cmd->cmd_timeout_ms) 622 return 0xE; 623 624 /* timeout in us */ 625 if (!data) 626 target_timeout = cmd->cmd_timeout_ms * 1000; 627 else 628 target_timeout = data->timeout_ns / 1000 + 629 data->timeout_clks / host->clock; 630 631 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 632 host->timeout_clk = host->clock / 1000; 633 634 /* 635 * Figure out needed cycles. 636 * We do this in steps in order to fit inside a 32 bit int. 637 * The first step is the minimum timeout, which will have a 638 * minimum resolution of 6 bits: 639 * (1) 2^13*1000 > 2^22, 640 * (2) host->timeout_clk < 2^16 641 * => 642 * (1) / (2) > 2^6 643 */ 644 BUG_ON(!host->timeout_clk); 645 count = 0; 646 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 647 while (current_timeout < target_timeout) { 648 count++; 649 current_timeout <<= 1; 650 if (count >= 0xF) 651 break; 652 } 653 654 if (count >= 0xF) { 655 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n", 656 mmc_hostname(host->mmc), cmd->opcode); 657 count = 0xE; 658 } 659 660 return count; 661 } 662 663 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 664 { 665 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 666 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 667 668 if (host->flags & SDHCI_REQ_USE_DMA) 669 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 670 else 671 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 672 } 673 674 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 675 { 676 u8 count; 677 u8 ctrl; 678 struct mmc_data *data = cmd->data; 679 int ret; 680 681 WARN_ON(host->data); 682 683 if (data || (cmd->flags & MMC_RSP_BUSY)) { 684 count = sdhci_calc_timeout(host, cmd); 685 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 686 } 687 688 if (!data) 689 return; 690 691 /* Sanity checks */ 692 BUG_ON(data->blksz * data->blocks > 524288); 693 BUG_ON(data->blksz > host->mmc->max_blk_size); 694 BUG_ON(data->blocks > 65535); 695 696 host->data = data; 697 host->data_early = 0; 698 host->data->bytes_xfered = 0; 699 700 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 701 host->flags |= SDHCI_REQ_USE_DMA; 702 703 /* 704 * FIXME: This doesn't account for merging when mapping the 705 * scatterlist. 706 */ 707 if (host->flags & SDHCI_REQ_USE_DMA) { 708 int broken, i; 709 struct scatterlist *sg; 710 711 broken = 0; 712 if (host->flags & SDHCI_USE_ADMA) { 713 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 714 broken = 1; 715 } else { 716 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 717 broken = 1; 718 } 719 720 if (unlikely(broken)) { 721 for_each_sg(data->sg, sg, data->sg_len, i) { 722 if (sg->length & 0x3) { 723 DBG("Reverting to PIO because of " 724 "transfer size (%d)\n", 725 sg->length); 726 host->flags &= ~SDHCI_REQ_USE_DMA; 727 break; 728 } 729 } 730 } 731 } 732 733 /* 734 * The assumption here being that alignment is the same after 735 * translation to device address space. 736 */ 737 if (host->flags & SDHCI_REQ_USE_DMA) { 738 int broken, i; 739 struct scatterlist *sg; 740 741 broken = 0; 742 if (host->flags & SDHCI_USE_ADMA) { 743 /* 744 * As we use 3 byte chunks to work around 745 * alignment problems, we need to check this 746 * quirk. 747 */ 748 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 749 broken = 1; 750 } else { 751 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 752 broken = 1; 753 } 754 755 if (unlikely(broken)) { 756 for_each_sg(data->sg, sg, data->sg_len, i) { 757 if (sg->offset & 0x3) { 758 DBG("Reverting to PIO because of " 759 "bad alignment\n"); 760 host->flags &= ~SDHCI_REQ_USE_DMA; 761 break; 762 } 763 } 764 } 765 } 766 767 if (host->flags & SDHCI_REQ_USE_DMA) { 768 if (host->flags & SDHCI_USE_ADMA) { 769 ret = sdhci_adma_table_pre(host, data); 770 if (ret) { 771 /* 772 * This only happens when someone fed 773 * us an invalid request. 774 */ 775 WARN_ON(1); 776 host->flags &= ~SDHCI_REQ_USE_DMA; 777 } else { 778 sdhci_writel(host, host->adma_addr, 779 SDHCI_ADMA_ADDRESS); 780 } 781 } else { 782 int sg_cnt; 783 784 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 785 data->sg, data->sg_len, 786 (data->flags & MMC_DATA_READ) ? 787 DMA_FROM_DEVICE : 788 DMA_TO_DEVICE); 789 if (sg_cnt == 0) { 790 /* 791 * This only happens when someone fed 792 * us an invalid request. 793 */ 794 WARN_ON(1); 795 host->flags &= ~SDHCI_REQ_USE_DMA; 796 } else { 797 WARN_ON(sg_cnt != 1); 798 sdhci_writel(host, sg_dma_address(data->sg), 799 SDHCI_DMA_ADDRESS); 800 } 801 } 802 } 803 804 /* 805 * Always adjust the DMA selection as some controllers 806 * (e.g. JMicron) can't do PIO properly when the selection 807 * is ADMA. 808 */ 809 if (host->version >= SDHCI_SPEC_200) { 810 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 811 ctrl &= ~SDHCI_CTRL_DMA_MASK; 812 if ((host->flags & SDHCI_REQ_USE_DMA) && 813 (host->flags & SDHCI_USE_ADMA)) 814 ctrl |= SDHCI_CTRL_ADMA32; 815 else 816 ctrl |= SDHCI_CTRL_SDMA; 817 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 818 } 819 820 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 821 int flags; 822 823 flags = SG_MITER_ATOMIC; 824 if (host->data->flags & MMC_DATA_READ) 825 flags |= SG_MITER_TO_SG; 826 else 827 flags |= SG_MITER_FROM_SG; 828 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 829 host->blocks = data->blocks; 830 } 831 832 sdhci_set_transfer_irqs(host); 833 834 /* Set the DMA boundary value and block size */ 835 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 836 data->blksz), SDHCI_BLOCK_SIZE); 837 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 838 } 839 840 static void sdhci_set_transfer_mode(struct sdhci_host *host, 841 struct mmc_command *cmd) 842 { 843 u16 mode; 844 struct mmc_data *data = cmd->data; 845 846 if (data == NULL) 847 return; 848 849 WARN_ON(!host->data); 850 851 mode = SDHCI_TRNS_BLK_CNT_EN; 852 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 853 mode |= SDHCI_TRNS_MULTI; 854 /* 855 * If we are sending CMD23, CMD12 never gets sent 856 * on successful completion (so no Auto-CMD12). 857 */ 858 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 859 mode |= SDHCI_TRNS_AUTO_CMD12; 860 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 861 mode |= SDHCI_TRNS_AUTO_CMD23; 862 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 863 } 864 } 865 866 if (data->flags & MMC_DATA_READ) 867 mode |= SDHCI_TRNS_READ; 868 if (host->flags & SDHCI_REQ_USE_DMA) 869 mode |= SDHCI_TRNS_DMA; 870 871 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 872 } 873 874 static void sdhci_finish_data(struct sdhci_host *host) 875 { 876 struct mmc_data *data; 877 878 BUG_ON(!host->data); 879 880 data = host->data; 881 host->data = NULL; 882 883 if (host->flags & SDHCI_REQ_USE_DMA) { 884 if (host->flags & SDHCI_USE_ADMA) 885 sdhci_adma_table_post(host, data); 886 else { 887 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 888 data->sg_len, (data->flags & MMC_DATA_READ) ? 889 DMA_FROM_DEVICE : DMA_TO_DEVICE); 890 } 891 } 892 893 /* 894 * The specification states that the block count register must 895 * be updated, but it does not specify at what point in the 896 * data flow. That makes the register entirely useless to read 897 * back so we have to assume that nothing made it to the card 898 * in the event of an error. 899 */ 900 if (data->error) 901 data->bytes_xfered = 0; 902 else 903 data->bytes_xfered = data->blksz * data->blocks; 904 905 /* 906 * Need to send CMD12 if - 907 * a) open-ended multiblock transfer (no CMD23) 908 * b) error in multiblock transfer 909 */ 910 if (data->stop && 911 (data->error || 912 !host->mrq->sbc)) { 913 914 /* 915 * The controller needs a reset of internal state machines 916 * upon error conditions. 917 */ 918 if (data->error) { 919 sdhci_reset(host, SDHCI_RESET_CMD); 920 sdhci_reset(host, SDHCI_RESET_DATA); 921 } 922 923 sdhci_send_command(host, data->stop); 924 } else 925 tasklet_schedule(&host->finish_tasklet); 926 } 927 928 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 929 { 930 int flags; 931 u32 mask; 932 unsigned long timeout; 933 934 WARN_ON(host->cmd); 935 936 /* Wait max 10 ms */ 937 timeout = 10; 938 939 mask = SDHCI_CMD_INHIBIT; 940 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 941 mask |= SDHCI_DATA_INHIBIT; 942 943 /* We shouldn't wait for data inihibit for stop commands, even 944 though they might use busy signaling */ 945 if (host->mrq->data && (cmd == host->mrq->data->stop)) 946 mask &= ~SDHCI_DATA_INHIBIT; 947 948 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 949 if (timeout == 0) { 950 printk(KERN_ERR "%s: Controller never released " 951 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 952 sdhci_dumpregs(host); 953 cmd->error = -EIO; 954 tasklet_schedule(&host->finish_tasklet); 955 return; 956 } 957 timeout--; 958 mdelay(1); 959 } 960 961 mod_timer(&host->timer, jiffies + 10 * HZ); 962 963 host->cmd = cmd; 964 965 sdhci_prepare_data(host, cmd); 966 967 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 968 969 sdhci_set_transfer_mode(host, cmd); 970 971 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 972 printk(KERN_ERR "%s: Unsupported response type!\n", 973 mmc_hostname(host->mmc)); 974 cmd->error = -EINVAL; 975 tasklet_schedule(&host->finish_tasklet); 976 return; 977 } 978 979 if (!(cmd->flags & MMC_RSP_PRESENT)) 980 flags = SDHCI_CMD_RESP_NONE; 981 else if (cmd->flags & MMC_RSP_136) 982 flags = SDHCI_CMD_RESP_LONG; 983 else if (cmd->flags & MMC_RSP_BUSY) 984 flags = SDHCI_CMD_RESP_SHORT_BUSY; 985 else 986 flags = SDHCI_CMD_RESP_SHORT; 987 988 if (cmd->flags & MMC_RSP_CRC) 989 flags |= SDHCI_CMD_CRC; 990 if (cmd->flags & MMC_RSP_OPCODE) 991 flags |= SDHCI_CMD_INDEX; 992 993 /* CMD19 is special in that the Data Present Select should be set */ 994 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK)) 995 flags |= SDHCI_CMD_DATA; 996 997 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 998 } 999 1000 static void sdhci_finish_command(struct sdhci_host *host) 1001 { 1002 int i; 1003 1004 BUG_ON(host->cmd == NULL); 1005 1006 if (host->cmd->flags & MMC_RSP_PRESENT) { 1007 if (host->cmd->flags & MMC_RSP_136) { 1008 /* CRC is stripped so we need to do some shifting. */ 1009 for (i = 0;i < 4;i++) { 1010 host->cmd->resp[i] = sdhci_readl(host, 1011 SDHCI_RESPONSE + (3-i)*4) << 8; 1012 if (i != 3) 1013 host->cmd->resp[i] |= 1014 sdhci_readb(host, 1015 SDHCI_RESPONSE + (3-i)*4-1); 1016 } 1017 } else { 1018 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1019 } 1020 } 1021 1022 host->cmd->error = 0; 1023 1024 /* Finished CMD23, now send actual command. */ 1025 if (host->cmd == host->mrq->sbc) { 1026 host->cmd = NULL; 1027 sdhci_send_command(host, host->mrq->cmd); 1028 } else { 1029 1030 /* Processed actual command. */ 1031 if (host->data && host->data_early) 1032 sdhci_finish_data(host); 1033 1034 if (!host->cmd->data) 1035 tasklet_schedule(&host->finish_tasklet); 1036 1037 host->cmd = NULL; 1038 } 1039 } 1040 1041 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1042 { 1043 int div = 0; /* Initialized for compiler warning */ 1044 u16 clk = 0; 1045 unsigned long timeout; 1046 1047 if (clock == host->clock) 1048 return; 1049 1050 if (host->ops->set_clock) { 1051 host->ops->set_clock(host, clock); 1052 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1053 return; 1054 } 1055 1056 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1057 1058 if (clock == 0) 1059 goto out; 1060 1061 if (host->version >= SDHCI_SPEC_300) { 1062 /* 1063 * Check if the Host Controller supports Programmable Clock 1064 * Mode. 1065 */ 1066 if (host->clk_mul) { 1067 u16 ctrl; 1068 1069 /* 1070 * We need to figure out whether the Host Driver needs 1071 * to select Programmable Clock Mode, or the value can 1072 * be set automatically by the Host Controller based on 1073 * the Preset Value registers. 1074 */ 1075 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1076 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1077 for (div = 1; div <= 1024; div++) { 1078 if (((host->max_clk * host->clk_mul) / 1079 div) <= clock) 1080 break; 1081 } 1082 /* 1083 * Set Programmable Clock Mode in the Clock 1084 * Control register. 1085 */ 1086 clk = SDHCI_PROG_CLOCK_MODE; 1087 div--; 1088 } 1089 } else { 1090 /* Version 3.00 divisors must be a multiple of 2. */ 1091 if (host->max_clk <= clock) 1092 div = 1; 1093 else { 1094 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1095 div += 2) { 1096 if ((host->max_clk / div) <= clock) 1097 break; 1098 } 1099 } 1100 div >>= 1; 1101 } 1102 } else { 1103 /* Version 2.00 divisors must be a power of 2. */ 1104 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1105 if ((host->max_clk / div) <= clock) 1106 break; 1107 } 1108 div >>= 1; 1109 } 1110 1111 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1112 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1113 << SDHCI_DIVIDER_HI_SHIFT; 1114 clk |= SDHCI_CLOCK_INT_EN; 1115 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1116 1117 /* Wait max 20 ms */ 1118 timeout = 20; 1119 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1120 & SDHCI_CLOCK_INT_STABLE)) { 1121 if (timeout == 0) { 1122 printk(KERN_ERR "%s: Internal clock never " 1123 "stabilised.\n", mmc_hostname(host->mmc)); 1124 sdhci_dumpregs(host); 1125 return; 1126 } 1127 timeout--; 1128 mdelay(1); 1129 } 1130 1131 clk |= SDHCI_CLOCK_CARD_EN; 1132 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1133 1134 out: 1135 host->clock = clock; 1136 } 1137 1138 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 1139 { 1140 u8 pwr = 0; 1141 1142 if (power != (unsigned short)-1) { 1143 switch (1 << power) { 1144 case MMC_VDD_165_195: 1145 pwr = SDHCI_POWER_180; 1146 break; 1147 case MMC_VDD_29_30: 1148 case MMC_VDD_30_31: 1149 pwr = SDHCI_POWER_300; 1150 break; 1151 case MMC_VDD_32_33: 1152 case MMC_VDD_33_34: 1153 pwr = SDHCI_POWER_330; 1154 break; 1155 default: 1156 BUG(); 1157 } 1158 } 1159 1160 if (host->pwr == pwr) 1161 return; 1162 1163 host->pwr = pwr; 1164 1165 if (pwr == 0) { 1166 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1167 return; 1168 } 1169 1170 /* 1171 * Spec says that we should clear the power reg before setting 1172 * a new value. Some controllers don't seem to like this though. 1173 */ 1174 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1175 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1176 1177 /* 1178 * At least the Marvell CaFe chip gets confused if we set the voltage 1179 * and set turn on power at the same time, so set the voltage first. 1180 */ 1181 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1182 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1183 1184 pwr |= SDHCI_POWER_ON; 1185 1186 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1187 1188 /* 1189 * Some controllers need an extra 10ms delay of 10ms before they 1190 * can apply clock after applying power 1191 */ 1192 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1193 mdelay(10); 1194 } 1195 1196 /*****************************************************************************\ 1197 * * 1198 * MMC callbacks * 1199 * * 1200 \*****************************************************************************/ 1201 1202 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1203 { 1204 struct sdhci_host *host; 1205 bool present; 1206 unsigned long flags; 1207 1208 host = mmc_priv(mmc); 1209 1210 spin_lock_irqsave(&host->lock, flags); 1211 1212 WARN_ON(host->mrq != NULL); 1213 1214 #ifndef SDHCI_USE_LEDS_CLASS 1215 sdhci_activate_led(host); 1216 #endif 1217 1218 /* 1219 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1220 * requests if Auto-CMD12 is enabled. 1221 */ 1222 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1223 if (mrq->stop) { 1224 mrq->data->stop = NULL; 1225 mrq->stop = NULL; 1226 } 1227 } 1228 1229 host->mrq = mrq; 1230 1231 /* If polling, assume that the card is always present. */ 1232 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1233 present = true; 1234 else 1235 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1236 SDHCI_CARD_PRESENT; 1237 1238 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1239 host->mrq->cmd->error = -ENOMEDIUM; 1240 tasklet_schedule(&host->finish_tasklet); 1241 } else { 1242 u32 present_state; 1243 1244 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1245 /* 1246 * Check if the re-tuning timer has already expired and there 1247 * is no on-going data transfer. If so, we need to execute 1248 * tuning procedure before sending command. 1249 */ 1250 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1251 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1252 spin_unlock_irqrestore(&host->lock, flags); 1253 sdhci_execute_tuning(mmc); 1254 spin_lock_irqsave(&host->lock, flags); 1255 1256 /* Restore original mmc_request structure */ 1257 host->mrq = mrq; 1258 } 1259 1260 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1261 sdhci_send_command(host, mrq->sbc); 1262 else 1263 sdhci_send_command(host, mrq->cmd); 1264 } 1265 1266 mmiowb(); 1267 spin_unlock_irqrestore(&host->lock, flags); 1268 } 1269 1270 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1271 { 1272 struct sdhci_host *host; 1273 unsigned long flags; 1274 u8 ctrl; 1275 1276 host = mmc_priv(mmc); 1277 1278 spin_lock_irqsave(&host->lock, flags); 1279 1280 if (host->flags & SDHCI_DEVICE_DEAD) 1281 goto out; 1282 1283 /* 1284 * Reset the chip on each power off. 1285 * Should clear out any weird states. 1286 */ 1287 if (ios->power_mode == MMC_POWER_OFF) { 1288 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1289 sdhci_reinit(host); 1290 } 1291 1292 sdhci_set_clock(host, ios->clock); 1293 1294 if (ios->power_mode == MMC_POWER_OFF) 1295 sdhci_set_power(host, -1); 1296 else 1297 sdhci_set_power(host, ios->vdd); 1298 1299 if (host->ops->platform_send_init_74_clocks) 1300 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1301 1302 /* 1303 * If your platform has 8-bit width support but is not a v3 controller, 1304 * or if it requires special setup code, you should implement that in 1305 * platform_8bit_width(). 1306 */ 1307 if (host->ops->platform_8bit_width) 1308 host->ops->platform_8bit_width(host, ios->bus_width); 1309 else { 1310 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1311 if (ios->bus_width == MMC_BUS_WIDTH_8) { 1312 ctrl &= ~SDHCI_CTRL_4BITBUS; 1313 if (host->version >= SDHCI_SPEC_300) 1314 ctrl |= SDHCI_CTRL_8BITBUS; 1315 } else { 1316 if (host->version >= SDHCI_SPEC_300) 1317 ctrl &= ~SDHCI_CTRL_8BITBUS; 1318 if (ios->bus_width == MMC_BUS_WIDTH_4) 1319 ctrl |= SDHCI_CTRL_4BITBUS; 1320 else 1321 ctrl &= ~SDHCI_CTRL_4BITBUS; 1322 } 1323 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1324 } 1325 1326 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1327 1328 if ((ios->timing == MMC_TIMING_SD_HS || 1329 ios->timing == MMC_TIMING_MMC_HS) 1330 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1331 ctrl |= SDHCI_CTRL_HISPD; 1332 else 1333 ctrl &= ~SDHCI_CTRL_HISPD; 1334 1335 if (host->version >= SDHCI_SPEC_300) { 1336 u16 clk, ctrl_2; 1337 unsigned int clock; 1338 1339 /* In case of UHS-I modes, set High Speed Enable */ 1340 if ((ios->timing == MMC_TIMING_UHS_SDR50) || 1341 (ios->timing == MMC_TIMING_UHS_SDR104) || 1342 (ios->timing == MMC_TIMING_UHS_DDR50) || 1343 (ios->timing == MMC_TIMING_UHS_SDR25) || 1344 (ios->timing == MMC_TIMING_UHS_SDR12)) 1345 ctrl |= SDHCI_CTRL_HISPD; 1346 1347 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1348 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1349 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1350 /* 1351 * We only need to set Driver Strength if the 1352 * preset value enable is not set. 1353 */ 1354 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1355 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1356 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1357 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1358 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1359 1360 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1361 } else { 1362 /* 1363 * According to SDHC Spec v3.00, if the Preset Value 1364 * Enable in the Host Control 2 register is set, we 1365 * need to reset SD Clock Enable before changing High 1366 * Speed Enable to avoid generating clock gliches. 1367 */ 1368 1369 /* Reset SD Clock Enable */ 1370 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1371 clk &= ~SDHCI_CLOCK_CARD_EN; 1372 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1373 1374 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1375 1376 /* Re-enable SD Clock */ 1377 clock = host->clock; 1378 host->clock = 0; 1379 sdhci_set_clock(host, clock); 1380 } 1381 1382 1383 /* Reset SD Clock Enable */ 1384 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1385 clk &= ~SDHCI_CLOCK_CARD_EN; 1386 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1387 1388 if (host->ops->set_uhs_signaling) 1389 host->ops->set_uhs_signaling(host, ios->timing); 1390 else { 1391 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1392 /* Select Bus Speed Mode for host */ 1393 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1394 if (ios->timing == MMC_TIMING_UHS_SDR12) 1395 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1396 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1397 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1398 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1399 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1400 else if (ios->timing == MMC_TIMING_UHS_SDR104) 1401 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1402 else if (ios->timing == MMC_TIMING_UHS_DDR50) 1403 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1404 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1405 } 1406 1407 /* Re-enable SD Clock */ 1408 clock = host->clock; 1409 host->clock = 0; 1410 sdhci_set_clock(host, clock); 1411 } else 1412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1413 1414 /* 1415 * Some (ENE) controllers go apeshit on some ios operation, 1416 * signalling timeout and CRC errors even on CMD0. Resetting 1417 * it on each ios seems to solve the problem. 1418 */ 1419 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1420 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1421 1422 out: 1423 mmiowb(); 1424 spin_unlock_irqrestore(&host->lock, flags); 1425 } 1426 1427 static int check_ro(struct sdhci_host *host) 1428 { 1429 unsigned long flags; 1430 int is_readonly; 1431 1432 spin_lock_irqsave(&host->lock, flags); 1433 1434 if (host->flags & SDHCI_DEVICE_DEAD) 1435 is_readonly = 0; 1436 else if (host->ops->get_ro) 1437 is_readonly = host->ops->get_ro(host); 1438 else 1439 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1440 & SDHCI_WRITE_PROTECT); 1441 1442 spin_unlock_irqrestore(&host->lock, flags); 1443 1444 /* This quirk needs to be replaced by a callback-function later */ 1445 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1446 !is_readonly : is_readonly; 1447 } 1448 1449 #define SAMPLE_COUNT 5 1450 1451 static int sdhci_get_ro(struct mmc_host *mmc) 1452 { 1453 struct sdhci_host *host; 1454 int i, ro_count; 1455 1456 host = mmc_priv(mmc); 1457 1458 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1459 return check_ro(host); 1460 1461 ro_count = 0; 1462 for (i = 0; i < SAMPLE_COUNT; i++) { 1463 if (check_ro(host)) { 1464 if (++ro_count > SAMPLE_COUNT / 2) 1465 return 1; 1466 } 1467 msleep(30); 1468 } 1469 return 0; 1470 } 1471 1472 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1473 { 1474 struct sdhci_host *host; 1475 unsigned long flags; 1476 1477 host = mmc_priv(mmc); 1478 1479 spin_lock_irqsave(&host->lock, flags); 1480 1481 if (host->flags & SDHCI_DEVICE_DEAD) 1482 goto out; 1483 1484 if (enable) 1485 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 1486 else 1487 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1488 out: 1489 mmiowb(); 1490 1491 spin_unlock_irqrestore(&host->lock, flags); 1492 } 1493 1494 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1495 struct mmc_ios *ios) 1496 { 1497 struct sdhci_host *host; 1498 u8 pwr; 1499 u16 clk, ctrl; 1500 u32 present_state; 1501 1502 host = mmc_priv(mmc); 1503 1504 /* 1505 * Signal Voltage Switching is only applicable for Host Controllers 1506 * v3.00 and above. 1507 */ 1508 if (host->version < SDHCI_SPEC_300) 1509 return 0; 1510 1511 /* 1512 * We first check whether the request is to set signalling voltage 1513 * to 3.3V. If so, we change the voltage to 3.3V and return quickly. 1514 */ 1515 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1516 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 1517 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1518 ctrl &= ~SDHCI_CTRL_VDD_180; 1519 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1520 1521 /* Wait for 5ms */ 1522 usleep_range(5000, 5500); 1523 1524 /* 3.3V regulator output should be stable within 5 ms */ 1525 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1526 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1527 return 0; 1528 else { 1529 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V " 1530 "signalling voltage failed\n"); 1531 return -EIO; 1532 } 1533 } else if (!(ctrl & SDHCI_CTRL_VDD_180) && 1534 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) { 1535 /* Stop SDCLK */ 1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1537 clk &= ~SDHCI_CLOCK_CARD_EN; 1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1539 1540 /* Check whether DAT[3:0] is 0000 */ 1541 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1542 if (!((present_state & SDHCI_DATA_LVL_MASK) >> 1543 SDHCI_DATA_LVL_SHIFT)) { 1544 /* 1545 * Enable 1.8V Signal Enable in the Host Control2 1546 * register 1547 */ 1548 ctrl |= SDHCI_CTRL_VDD_180; 1549 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1550 1551 /* Wait for 5ms */ 1552 usleep_range(5000, 5500); 1553 1554 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1555 if (ctrl & SDHCI_CTRL_VDD_180) { 1556 /* Provide SDCLK again and wait for 1ms*/ 1557 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1558 clk |= SDHCI_CLOCK_CARD_EN; 1559 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1560 usleep_range(1000, 1500); 1561 1562 /* 1563 * If DAT[3:0] level is 1111b, then the card 1564 * was successfully switched to 1.8V signaling. 1565 */ 1566 present_state = sdhci_readl(host, 1567 SDHCI_PRESENT_STATE); 1568 if ((present_state & SDHCI_DATA_LVL_MASK) == 1569 SDHCI_DATA_LVL_MASK) 1570 return 0; 1571 } 1572 } 1573 1574 /* 1575 * If we are here, that means the switch to 1.8V signaling 1576 * failed. We power cycle the card, and retry initialization 1577 * sequence by setting S18R to 0. 1578 */ 1579 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL); 1580 pwr &= ~SDHCI_POWER_ON; 1581 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1582 1583 /* Wait for 1ms as per the spec */ 1584 usleep_range(1000, 1500); 1585 pwr |= SDHCI_POWER_ON; 1586 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1587 1588 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling " 1589 "voltage failed, retrying with S18R set to 0\n"); 1590 return -EAGAIN; 1591 } else 1592 /* No signal voltage switch required */ 1593 return 0; 1594 } 1595 1596 static int sdhci_execute_tuning(struct mmc_host *mmc) 1597 { 1598 struct sdhci_host *host; 1599 u16 ctrl; 1600 u32 ier; 1601 int tuning_loop_counter = MAX_TUNING_LOOP; 1602 unsigned long timeout; 1603 int err = 0; 1604 1605 host = mmc_priv(mmc); 1606 1607 disable_irq(host->irq); 1608 spin_lock(&host->lock); 1609 1610 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1611 1612 /* 1613 * Host Controller needs tuning only in case of SDR104 mode 1614 * and for SDR50 mode when Use Tuning for SDR50 is set in 1615 * Capabilities register. 1616 */ 1617 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1618 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1619 (host->flags & SDHCI_SDR50_NEEDS_TUNING))) 1620 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1621 else { 1622 spin_unlock(&host->lock); 1623 enable_irq(host->irq); 1624 return 0; 1625 } 1626 1627 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1628 1629 /* 1630 * As per the Host Controller spec v3.00, tuning command 1631 * generates Buffer Read Ready interrupt, so enable that. 1632 * 1633 * Note: The spec clearly says that when tuning sequence 1634 * is being performed, the controller does not generate 1635 * interrupts other than Buffer Read Ready interrupt. But 1636 * to make sure we don't hit a controller bug, we _only_ 1637 * enable Buffer Read Ready interrupt here. 1638 */ 1639 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1640 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1641 1642 /* 1643 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1644 * of loops reaches 40 times or a timeout of 150ms occurs. 1645 */ 1646 timeout = 150; 1647 do { 1648 struct mmc_command cmd = {0}; 1649 struct mmc_request mrq = {0}; 1650 1651 if (!tuning_loop_counter && !timeout) 1652 break; 1653 1654 cmd.opcode = MMC_SEND_TUNING_BLOCK; 1655 cmd.arg = 0; 1656 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1657 cmd.retries = 0; 1658 cmd.data = NULL; 1659 cmd.error = 0; 1660 1661 mrq.cmd = &cmd; 1662 host->mrq = &mrq; 1663 1664 /* 1665 * In response to CMD19, the card sends 64 bytes of tuning 1666 * block to the Host Controller. So we set the block size 1667 * to 64 here. 1668 */ 1669 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 1670 1671 /* 1672 * The tuning block is sent by the card to the host controller. 1673 * So we set the TRNS_READ bit in the Transfer Mode register. 1674 * This also takes care of setting DMA Enable and Multi Block 1675 * Select in the same register to 0. 1676 */ 1677 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1678 1679 sdhci_send_command(host, &cmd); 1680 1681 host->cmd = NULL; 1682 host->mrq = NULL; 1683 1684 spin_unlock(&host->lock); 1685 enable_irq(host->irq); 1686 1687 /* Wait for Buffer Read Ready interrupt */ 1688 wait_event_interruptible_timeout(host->buf_ready_int, 1689 (host->tuning_done == 1), 1690 msecs_to_jiffies(50)); 1691 disable_irq(host->irq); 1692 spin_lock(&host->lock); 1693 1694 if (!host->tuning_done) { 1695 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for " 1696 "Buffer Read Ready interrupt during tuning " 1697 "procedure, falling back to fixed sampling " 1698 "clock\n"); 1699 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1700 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1701 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1702 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1703 1704 err = -EIO; 1705 goto out; 1706 } 1707 1708 host->tuning_done = 0; 1709 1710 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1711 tuning_loop_counter--; 1712 timeout--; 1713 mdelay(1); 1714 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1715 1716 /* 1717 * The Host Driver has exhausted the maximum number of loops allowed, 1718 * so use fixed sampling frequency. 1719 */ 1720 if (!tuning_loop_counter || !timeout) { 1721 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1722 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1723 } else { 1724 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1725 printk(KERN_INFO DRIVER_NAME ": Tuning procedure" 1726 " failed, falling back to fixed sampling" 1727 " clock\n"); 1728 err = -EIO; 1729 } 1730 } 1731 1732 out: 1733 /* 1734 * If this is the very first time we are here, we start the retuning 1735 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1736 * flag won't be set, we check this condition before actually starting 1737 * the timer. 1738 */ 1739 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1740 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1741 mod_timer(&host->tuning_timer, jiffies + 1742 host->tuning_count * HZ); 1743 /* Tuning mode 1 limits the maximum data length to 4MB */ 1744 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1745 } else { 1746 host->flags &= ~SDHCI_NEEDS_RETUNING; 1747 /* Reload the new initial value for timer */ 1748 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1749 mod_timer(&host->tuning_timer, jiffies + 1750 host->tuning_count * HZ); 1751 } 1752 1753 /* 1754 * In case tuning fails, host controllers which support re-tuning can 1755 * try tuning again at a later time, when the re-tuning timer expires. 1756 * So for these controllers, we return 0. Since there might be other 1757 * controllers who do not have this capability, we return error for 1758 * them. 1759 */ 1760 if (err && host->tuning_count && 1761 host->tuning_mode == SDHCI_TUNING_MODE_1) 1762 err = 0; 1763 1764 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 1765 spin_unlock(&host->lock); 1766 enable_irq(host->irq); 1767 1768 return err; 1769 } 1770 1771 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) 1772 { 1773 struct sdhci_host *host; 1774 u16 ctrl; 1775 unsigned long flags; 1776 1777 host = mmc_priv(mmc); 1778 1779 /* Host Controller v3.00 defines preset value registers */ 1780 if (host->version < SDHCI_SPEC_300) 1781 return; 1782 1783 spin_lock_irqsave(&host->lock, flags); 1784 1785 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1786 1787 /* 1788 * We only enable or disable Preset Value if they are not already 1789 * enabled or disabled respectively. Otherwise, we bail out. 1790 */ 1791 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1792 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 1793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1794 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1795 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 1796 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1797 } 1798 1799 spin_unlock_irqrestore(&host->lock, flags); 1800 } 1801 1802 static const struct mmc_host_ops sdhci_ops = { 1803 .request = sdhci_request, 1804 .set_ios = sdhci_set_ios, 1805 .get_ro = sdhci_get_ro, 1806 .enable_sdio_irq = sdhci_enable_sdio_irq, 1807 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 1808 .execute_tuning = sdhci_execute_tuning, 1809 .enable_preset_value = sdhci_enable_preset_value, 1810 }; 1811 1812 /*****************************************************************************\ 1813 * * 1814 * Tasklets * 1815 * * 1816 \*****************************************************************************/ 1817 1818 static void sdhci_tasklet_card(unsigned long param) 1819 { 1820 struct sdhci_host *host; 1821 unsigned long flags; 1822 1823 host = (struct sdhci_host*)param; 1824 1825 spin_lock_irqsave(&host->lock, flags); 1826 1827 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 1828 if (host->mrq) { 1829 printk(KERN_ERR "%s: Card removed during transfer!\n", 1830 mmc_hostname(host->mmc)); 1831 printk(KERN_ERR "%s: Resetting controller.\n", 1832 mmc_hostname(host->mmc)); 1833 1834 sdhci_reset(host, SDHCI_RESET_CMD); 1835 sdhci_reset(host, SDHCI_RESET_DATA); 1836 1837 host->mrq->cmd->error = -ENOMEDIUM; 1838 tasklet_schedule(&host->finish_tasklet); 1839 } 1840 } 1841 1842 spin_unlock_irqrestore(&host->lock, flags); 1843 1844 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 1845 } 1846 1847 static void sdhci_tasklet_finish(unsigned long param) 1848 { 1849 struct sdhci_host *host; 1850 unsigned long flags; 1851 struct mmc_request *mrq; 1852 1853 host = (struct sdhci_host*)param; 1854 1855 /* 1856 * If this tasklet gets rescheduled while running, it will 1857 * be run again afterwards but without any active request. 1858 */ 1859 if (!host->mrq) 1860 return; 1861 1862 spin_lock_irqsave(&host->lock, flags); 1863 1864 del_timer(&host->timer); 1865 1866 if (host->version >= SDHCI_SPEC_300) 1867 del_timer(&host->tuning_timer); 1868 1869 mrq = host->mrq; 1870 1871 /* 1872 * The controller needs a reset of internal state machines 1873 * upon error conditions. 1874 */ 1875 if (!(host->flags & SDHCI_DEVICE_DEAD) && 1876 ((mrq->cmd && mrq->cmd->error) || 1877 (mrq->data && (mrq->data->error || 1878 (mrq->data->stop && mrq->data->stop->error))) || 1879 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 1880 1881 /* Some controllers need this kick or reset won't work here */ 1882 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { 1883 unsigned int clock; 1884 1885 /* This is to force an update */ 1886 clock = host->clock; 1887 host->clock = 0; 1888 sdhci_set_clock(host, clock); 1889 } 1890 1891 /* Spec says we should do both at the same time, but Ricoh 1892 controllers do not like that. */ 1893 sdhci_reset(host, SDHCI_RESET_CMD); 1894 sdhci_reset(host, SDHCI_RESET_DATA); 1895 } 1896 1897 host->mrq = NULL; 1898 host->cmd = NULL; 1899 host->data = NULL; 1900 1901 #ifndef SDHCI_USE_LEDS_CLASS 1902 sdhci_deactivate_led(host); 1903 #endif 1904 1905 mmiowb(); 1906 spin_unlock_irqrestore(&host->lock, flags); 1907 1908 mmc_request_done(host->mmc, mrq); 1909 } 1910 1911 static void sdhci_timeout_timer(unsigned long data) 1912 { 1913 struct sdhci_host *host; 1914 unsigned long flags; 1915 1916 host = (struct sdhci_host*)data; 1917 1918 spin_lock_irqsave(&host->lock, flags); 1919 1920 if (host->mrq) { 1921 printk(KERN_ERR "%s: Timeout waiting for hardware " 1922 "interrupt.\n", mmc_hostname(host->mmc)); 1923 sdhci_dumpregs(host); 1924 1925 if (host->data) { 1926 host->data->error = -ETIMEDOUT; 1927 sdhci_finish_data(host); 1928 } else { 1929 if (host->cmd) 1930 host->cmd->error = -ETIMEDOUT; 1931 else 1932 host->mrq->cmd->error = -ETIMEDOUT; 1933 1934 tasklet_schedule(&host->finish_tasklet); 1935 } 1936 } 1937 1938 mmiowb(); 1939 spin_unlock_irqrestore(&host->lock, flags); 1940 } 1941 1942 static void sdhci_tuning_timer(unsigned long data) 1943 { 1944 struct sdhci_host *host; 1945 unsigned long flags; 1946 1947 host = (struct sdhci_host *)data; 1948 1949 spin_lock_irqsave(&host->lock, flags); 1950 1951 host->flags |= SDHCI_NEEDS_RETUNING; 1952 1953 spin_unlock_irqrestore(&host->lock, flags); 1954 } 1955 1956 /*****************************************************************************\ 1957 * * 1958 * Interrupt handling * 1959 * * 1960 \*****************************************************************************/ 1961 1962 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 1963 { 1964 BUG_ON(intmask == 0); 1965 1966 if (!host->cmd) { 1967 printk(KERN_ERR "%s: Got command interrupt 0x%08x even " 1968 "though no command operation was in progress.\n", 1969 mmc_hostname(host->mmc), (unsigned)intmask); 1970 sdhci_dumpregs(host); 1971 return; 1972 } 1973 1974 if (intmask & SDHCI_INT_TIMEOUT) 1975 host->cmd->error = -ETIMEDOUT; 1976 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 1977 SDHCI_INT_INDEX)) 1978 host->cmd->error = -EILSEQ; 1979 1980 if (host->cmd->error) { 1981 tasklet_schedule(&host->finish_tasklet); 1982 return; 1983 } 1984 1985 /* 1986 * The host can send and interrupt when the busy state has 1987 * ended, allowing us to wait without wasting CPU cycles. 1988 * Unfortunately this is overloaded on the "data complete" 1989 * interrupt, so we need to take some care when handling 1990 * it. 1991 * 1992 * Note: The 1.0 specification is a bit ambiguous about this 1993 * feature so there might be some problems with older 1994 * controllers. 1995 */ 1996 if (host->cmd->flags & MMC_RSP_BUSY) { 1997 if (host->cmd->data) 1998 DBG("Cannot wait for busy signal when also " 1999 "doing a data transfer"); 2000 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2001 return; 2002 2003 /* The controller does not support the end-of-busy IRQ, 2004 * fall through and take the SDHCI_INT_RESPONSE */ 2005 } 2006 2007 if (intmask & SDHCI_INT_RESPONSE) 2008 sdhci_finish_command(host); 2009 } 2010 2011 #ifdef CONFIG_MMC_DEBUG 2012 static void sdhci_show_adma_error(struct sdhci_host *host) 2013 { 2014 const char *name = mmc_hostname(host->mmc); 2015 u8 *desc = host->adma_desc; 2016 __le32 *dma; 2017 __le16 *len; 2018 u8 attr; 2019 2020 sdhci_dumpregs(host); 2021 2022 while (true) { 2023 dma = (__le32 *)(desc + 4); 2024 len = (__le16 *)(desc + 2); 2025 attr = *desc; 2026 2027 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2028 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2029 2030 desc += 8; 2031 2032 if (attr & 2) 2033 break; 2034 } 2035 } 2036 #else 2037 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2038 #endif 2039 2040 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2041 { 2042 BUG_ON(intmask == 0); 2043 2044 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2045 if (intmask & SDHCI_INT_DATA_AVAIL) { 2046 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) == 2047 MMC_SEND_TUNING_BLOCK) { 2048 host->tuning_done = 1; 2049 wake_up(&host->buf_ready_int); 2050 return; 2051 } 2052 } 2053 2054 if (!host->data) { 2055 /* 2056 * The "data complete" interrupt is also used to 2057 * indicate that a busy state has ended. See comment 2058 * above in sdhci_cmd_irq(). 2059 */ 2060 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2061 if (intmask & SDHCI_INT_DATA_END) { 2062 sdhci_finish_command(host); 2063 return; 2064 } 2065 } 2066 2067 printk(KERN_ERR "%s: Got data interrupt 0x%08x even " 2068 "though no data operation was in progress.\n", 2069 mmc_hostname(host->mmc), (unsigned)intmask); 2070 sdhci_dumpregs(host); 2071 2072 return; 2073 } 2074 2075 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2076 host->data->error = -ETIMEDOUT; 2077 else if (intmask & SDHCI_INT_DATA_END_BIT) 2078 host->data->error = -EILSEQ; 2079 else if ((intmask & SDHCI_INT_DATA_CRC) && 2080 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2081 != MMC_BUS_TEST_R) 2082 host->data->error = -EILSEQ; 2083 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2084 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); 2085 sdhci_show_adma_error(host); 2086 host->data->error = -EIO; 2087 } 2088 2089 if (host->data->error) 2090 sdhci_finish_data(host); 2091 else { 2092 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2093 sdhci_transfer_pio(host); 2094 2095 /* 2096 * We currently don't do anything fancy with DMA 2097 * boundaries, but as we can't disable the feature 2098 * we need to at least restart the transfer. 2099 * 2100 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2101 * should return a valid address to continue from, but as 2102 * some controllers are faulty, don't trust them. 2103 */ 2104 if (intmask & SDHCI_INT_DMA_END) { 2105 u32 dmastart, dmanow; 2106 dmastart = sg_dma_address(host->data->sg); 2107 dmanow = dmastart + host->data->bytes_xfered; 2108 /* 2109 * Force update to the next DMA block boundary. 2110 */ 2111 dmanow = (dmanow & 2112 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2113 SDHCI_DEFAULT_BOUNDARY_SIZE; 2114 host->data->bytes_xfered = dmanow - dmastart; 2115 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2116 " next 0x%08x\n", 2117 mmc_hostname(host->mmc), dmastart, 2118 host->data->bytes_xfered, dmanow); 2119 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2120 } 2121 2122 if (intmask & SDHCI_INT_DATA_END) { 2123 if (host->cmd) { 2124 /* 2125 * Data managed to finish before the 2126 * command completed. Make sure we do 2127 * things in the proper order. 2128 */ 2129 host->data_early = 1; 2130 } else { 2131 sdhci_finish_data(host); 2132 } 2133 } 2134 } 2135 } 2136 2137 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2138 { 2139 irqreturn_t result; 2140 struct sdhci_host* host = dev_id; 2141 u32 intmask; 2142 int cardint = 0; 2143 2144 spin_lock(&host->lock); 2145 2146 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2147 2148 if (!intmask || intmask == 0xffffffff) { 2149 result = IRQ_NONE; 2150 goto out; 2151 } 2152 2153 DBG("*** %s got interrupt: 0x%08x\n", 2154 mmc_hostname(host->mmc), intmask); 2155 2156 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2157 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2158 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2159 tasklet_schedule(&host->card_tasklet); 2160 } 2161 2162 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2163 2164 if (intmask & SDHCI_INT_CMD_MASK) { 2165 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 2166 SDHCI_INT_STATUS); 2167 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2168 } 2169 2170 if (intmask & SDHCI_INT_DATA_MASK) { 2171 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 2172 SDHCI_INT_STATUS); 2173 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2174 } 2175 2176 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 2177 2178 intmask &= ~SDHCI_INT_ERROR; 2179 2180 if (intmask & SDHCI_INT_BUS_POWER) { 2181 printk(KERN_ERR "%s: Card is consuming too much power!\n", 2182 mmc_hostname(host->mmc)); 2183 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 2184 } 2185 2186 intmask &= ~SDHCI_INT_BUS_POWER; 2187 2188 if (intmask & SDHCI_INT_CARD_INT) 2189 cardint = 1; 2190 2191 intmask &= ~SDHCI_INT_CARD_INT; 2192 2193 if (intmask) { 2194 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", 2195 mmc_hostname(host->mmc), intmask); 2196 sdhci_dumpregs(host); 2197 2198 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2199 } 2200 2201 result = IRQ_HANDLED; 2202 2203 mmiowb(); 2204 out: 2205 spin_unlock(&host->lock); 2206 2207 /* 2208 * We have to delay this as it calls back into the driver. 2209 */ 2210 if (cardint) 2211 mmc_signal_sdio_irq(host->mmc); 2212 2213 return result; 2214 } 2215 2216 /*****************************************************************************\ 2217 * * 2218 * Suspend/resume * 2219 * * 2220 \*****************************************************************************/ 2221 2222 #ifdef CONFIG_PM 2223 2224 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) 2225 { 2226 int ret; 2227 2228 sdhci_disable_card_detection(host); 2229 2230 /* Disable tuning since we are suspending */ 2231 if (host->version >= SDHCI_SPEC_300 && host->tuning_count && 2232 host->tuning_mode == SDHCI_TUNING_MODE_1) { 2233 host->flags &= ~SDHCI_NEEDS_RETUNING; 2234 mod_timer(&host->tuning_timer, jiffies + 2235 host->tuning_count * HZ); 2236 } 2237 2238 ret = mmc_suspend_host(host->mmc); 2239 if (ret) 2240 return ret; 2241 2242 free_irq(host->irq, host); 2243 2244 if (host->vmmc) 2245 ret = regulator_disable(host->vmmc); 2246 2247 return ret; 2248 } 2249 2250 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2251 2252 int sdhci_resume_host(struct sdhci_host *host) 2253 { 2254 int ret; 2255 2256 if (host->vmmc) { 2257 int ret = regulator_enable(host->vmmc); 2258 if (ret) 2259 return ret; 2260 } 2261 2262 2263 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2264 if (host->ops->enable_dma) 2265 host->ops->enable_dma(host); 2266 } 2267 2268 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2269 mmc_hostname(host->mmc), host); 2270 if (ret) 2271 return ret; 2272 2273 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2274 mmiowb(); 2275 2276 ret = mmc_resume_host(host->mmc); 2277 sdhci_enable_card_detection(host); 2278 2279 /* Set the re-tuning expiration flag */ 2280 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count && 2281 (host->tuning_mode == SDHCI_TUNING_MODE_1)) 2282 host->flags |= SDHCI_NEEDS_RETUNING; 2283 2284 return ret; 2285 } 2286 2287 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2288 2289 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2290 { 2291 u8 val; 2292 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2293 val |= SDHCI_WAKE_ON_INT; 2294 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2295 } 2296 2297 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2298 2299 #endif /* CONFIG_PM */ 2300 2301 /*****************************************************************************\ 2302 * * 2303 * Device allocation/registration * 2304 * * 2305 \*****************************************************************************/ 2306 2307 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2308 size_t priv_size) 2309 { 2310 struct mmc_host *mmc; 2311 struct sdhci_host *host; 2312 2313 WARN_ON(dev == NULL); 2314 2315 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2316 if (!mmc) 2317 return ERR_PTR(-ENOMEM); 2318 2319 host = mmc_priv(mmc); 2320 host->mmc = mmc; 2321 2322 return host; 2323 } 2324 2325 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2326 2327 int sdhci_add_host(struct sdhci_host *host) 2328 { 2329 struct mmc_host *mmc; 2330 u32 caps[2]; 2331 u32 max_current_caps; 2332 unsigned int ocr_avail; 2333 int ret; 2334 2335 WARN_ON(host == NULL); 2336 if (host == NULL) 2337 return -EINVAL; 2338 2339 mmc = host->mmc; 2340 2341 if (debug_quirks) 2342 host->quirks = debug_quirks; 2343 2344 sdhci_reset(host, SDHCI_RESET_ALL); 2345 2346 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2347 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2348 >> SDHCI_SPEC_VER_SHIFT; 2349 if (host->version > SDHCI_SPEC_300) { 2350 printk(KERN_ERR "%s: Unknown controller version (%d). " 2351 "You may experience problems.\n", mmc_hostname(mmc), 2352 host->version); 2353 } 2354 2355 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2356 sdhci_readl(host, SDHCI_CAPABILITIES); 2357 2358 caps[1] = (host->version >= SDHCI_SPEC_300) ? 2359 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0; 2360 2361 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2362 host->flags |= SDHCI_USE_SDMA; 2363 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2364 DBG("Controller doesn't have SDMA capability\n"); 2365 else 2366 host->flags |= SDHCI_USE_SDMA; 2367 2368 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2369 (host->flags & SDHCI_USE_SDMA)) { 2370 DBG("Disabling DMA as it is marked broken\n"); 2371 host->flags &= ~SDHCI_USE_SDMA; 2372 } 2373 2374 if ((host->version >= SDHCI_SPEC_200) && 2375 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2376 host->flags |= SDHCI_USE_ADMA; 2377 2378 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2379 (host->flags & SDHCI_USE_ADMA)) { 2380 DBG("Disabling ADMA as it is marked broken\n"); 2381 host->flags &= ~SDHCI_USE_ADMA; 2382 } 2383 2384 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2385 if (host->ops->enable_dma) { 2386 if (host->ops->enable_dma(host)) { 2387 printk(KERN_WARNING "%s: No suitable DMA " 2388 "available. Falling back to PIO.\n", 2389 mmc_hostname(mmc)); 2390 host->flags &= 2391 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2392 } 2393 } 2394 } 2395 2396 if (host->flags & SDHCI_USE_ADMA) { 2397 /* 2398 * We need to allocate descriptors for all sg entries 2399 * (128) and potentially one alignment transfer for 2400 * each of those entries. 2401 */ 2402 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 2403 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2404 if (!host->adma_desc || !host->align_buffer) { 2405 kfree(host->adma_desc); 2406 kfree(host->align_buffer); 2407 printk(KERN_WARNING "%s: Unable to allocate ADMA " 2408 "buffers. Falling back to standard DMA.\n", 2409 mmc_hostname(mmc)); 2410 host->flags &= ~SDHCI_USE_ADMA; 2411 } 2412 } 2413 2414 /* 2415 * If we use DMA, then it's up to the caller to set the DMA 2416 * mask, but PIO does not need the hw shim so we set a new 2417 * mask here in that case. 2418 */ 2419 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2420 host->dma_mask = DMA_BIT_MASK(64); 2421 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2422 } 2423 2424 if (host->version >= SDHCI_SPEC_300) 2425 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2426 >> SDHCI_CLOCK_BASE_SHIFT; 2427 else 2428 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2429 >> SDHCI_CLOCK_BASE_SHIFT; 2430 2431 host->max_clk *= 1000000; 2432 if (host->max_clk == 0 || host->quirks & 2433 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2434 if (!host->ops->get_max_clock) { 2435 printk(KERN_ERR 2436 "%s: Hardware doesn't specify base clock " 2437 "frequency.\n", mmc_hostname(mmc)); 2438 return -ENODEV; 2439 } 2440 host->max_clk = host->ops->get_max_clock(host); 2441 } 2442 2443 host->timeout_clk = 2444 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2445 if (host->timeout_clk == 0) { 2446 if (host->ops->get_timeout_clock) { 2447 host->timeout_clk = host->ops->get_timeout_clock(host); 2448 } else if (!(host->quirks & 2449 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2450 printk(KERN_ERR 2451 "%s: Hardware doesn't specify timeout clock " 2452 "frequency.\n", mmc_hostname(mmc)); 2453 return -ENODEV; 2454 } 2455 } 2456 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2457 host->timeout_clk *= 1000; 2458 2459 /* 2460 * In case of Host Controller v3.00, find out whether clock 2461 * multiplier is supported. 2462 */ 2463 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2464 SDHCI_CLOCK_MUL_SHIFT; 2465 2466 /* 2467 * In case the value in Clock Multiplier is 0, then programmable 2468 * clock mode is not supported, otherwise the actual clock 2469 * multiplier is one more than the value of Clock Multiplier 2470 * in the Capabilities Register. 2471 */ 2472 if (host->clk_mul) 2473 host->clk_mul += 1; 2474 2475 /* 2476 * Set host parameters. 2477 */ 2478 mmc->ops = &sdhci_ops; 2479 mmc->f_max = host->max_clk; 2480 if (host->ops->get_min_clock) 2481 mmc->f_min = host->ops->get_min_clock(host); 2482 else if (host->version >= SDHCI_SPEC_300) { 2483 if (host->clk_mul) { 2484 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2485 mmc->f_max = host->max_clk * host->clk_mul; 2486 } else 2487 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2488 } else 2489 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2490 2491 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2492 2493 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2494 host->flags |= SDHCI_AUTO_CMD12; 2495 2496 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2497 if ((host->version >= SDHCI_SPEC_300) && 2498 ((host->flags & SDHCI_USE_ADMA) || 2499 !(host->flags & SDHCI_USE_SDMA))) { 2500 host->flags |= SDHCI_AUTO_CMD23; 2501 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2502 } else { 2503 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2504 } 2505 2506 /* 2507 * A controller may support 8-bit width, but the board itself 2508 * might not have the pins brought out. Boards that support 2509 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2510 * their platform code before calling sdhci_add_host(), and we 2511 * won't assume 8-bit width for hosts without that CAP. 2512 */ 2513 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2514 mmc->caps |= MMC_CAP_4_BIT_DATA; 2515 2516 if (caps[0] & SDHCI_CAN_DO_HISPD) 2517 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2518 2519 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2520 mmc_card_is_removable(mmc)) 2521 mmc->caps |= MMC_CAP_NEEDS_POLL; 2522 2523 /* UHS-I mode(s) supported by the host controller. */ 2524 if (host->version >= SDHCI_SPEC_300) 2525 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2526 2527 /* SDR104 supports also implies SDR50 support */ 2528 if (caps[1] & SDHCI_SUPPORT_SDR104) 2529 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2530 else if (caps[1] & SDHCI_SUPPORT_SDR50) 2531 mmc->caps |= MMC_CAP_UHS_SDR50; 2532 2533 if (caps[1] & SDHCI_SUPPORT_DDR50) 2534 mmc->caps |= MMC_CAP_UHS_DDR50; 2535 2536 /* Does the host needs tuning for SDR50? */ 2537 if (caps[1] & SDHCI_USE_SDR50_TUNING) 2538 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 2539 2540 /* Driver Type(s) (A, C, D) supported by the host */ 2541 if (caps[1] & SDHCI_DRIVER_TYPE_A) 2542 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 2543 if (caps[1] & SDHCI_DRIVER_TYPE_C) 2544 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 2545 if (caps[1] & SDHCI_DRIVER_TYPE_D) 2546 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 2547 2548 /* Initial value for re-tuning timer count */ 2549 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 2550 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 2551 2552 /* 2553 * In case Re-tuning Timer is not disabled, the actual value of 2554 * re-tuning timer will be 2 ^ (n - 1). 2555 */ 2556 if (host->tuning_count) 2557 host->tuning_count = 1 << (host->tuning_count - 1); 2558 2559 /* Re-tuning mode supported by the Host Controller */ 2560 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 2561 SDHCI_RETUNING_MODE_SHIFT; 2562 2563 ocr_avail = 0; 2564 /* 2565 * According to SD Host Controller spec v3.00, if the Host System 2566 * can afford more than 150mA, Host Driver should set XPC to 1. Also 2567 * the value is meaningful only if Voltage Support in the Capabilities 2568 * register is set. The actual current value is 4 times the register 2569 * value. 2570 */ 2571 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 2572 2573 if (caps[0] & SDHCI_CAN_VDD_330) { 2574 int max_current_330; 2575 2576 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 2577 2578 max_current_330 = ((max_current_caps & 2579 SDHCI_MAX_CURRENT_330_MASK) >> 2580 SDHCI_MAX_CURRENT_330_SHIFT) * 2581 SDHCI_MAX_CURRENT_MULTIPLIER; 2582 2583 if (max_current_330 > 150) 2584 mmc->caps |= MMC_CAP_SET_XPC_330; 2585 } 2586 if (caps[0] & SDHCI_CAN_VDD_300) { 2587 int max_current_300; 2588 2589 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 2590 2591 max_current_300 = ((max_current_caps & 2592 SDHCI_MAX_CURRENT_300_MASK) >> 2593 SDHCI_MAX_CURRENT_300_SHIFT) * 2594 SDHCI_MAX_CURRENT_MULTIPLIER; 2595 2596 if (max_current_300 > 150) 2597 mmc->caps |= MMC_CAP_SET_XPC_300; 2598 } 2599 if (caps[0] & SDHCI_CAN_VDD_180) { 2600 int max_current_180; 2601 2602 ocr_avail |= MMC_VDD_165_195; 2603 2604 max_current_180 = ((max_current_caps & 2605 SDHCI_MAX_CURRENT_180_MASK) >> 2606 SDHCI_MAX_CURRENT_180_SHIFT) * 2607 SDHCI_MAX_CURRENT_MULTIPLIER; 2608 2609 if (max_current_180 > 150) 2610 mmc->caps |= MMC_CAP_SET_XPC_180; 2611 2612 /* Maximum current capabilities of the host at 1.8V */ 2613 if (max_current_180 >= 800) 2614 mmc->caps |= MMC_CAP_MAX_CURRENT_800; 2615 else if (max_current_180 >= 600) 2616 mmc->caps |= MMC_CAP_MAX_CURRENT_600; 2617 else if (max_current_180 >= 400) 2618 mmc->caps |= MMC_CAP_MAX_CURRENT_400; 2619 else 2620 mmc->caps |= MMC_CAP_MAX_CURRENT_200; 2621 } 2622 2623 mmc->ocr_avail = ocr_avail; 2624 mmc->ocr_avail_sdio = ocr_avail; 2625 if (host->ocr_avail_sdio) 2626 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 2627 mmc->ocr_avail_sd = ocr_avail; 2628 if (host->ocr_avail_sd) 2629 mmc->ocr_avail_sd &= host->ocr_avail_sd; 2630 else /* normal SD controllers don't support 1.8V */ 2631 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 2632 mmc->ocr_avail_mmc = ocr_avail; 2633 if (host->ocr_avail_mmc) 2634 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 2635 2636 if (mmc->ocr_avail == 0) { 2637 printk(KERN_ERR "%s: Hardware doesn't report any " 2638 "support voltages.\n", mmc_hostname(mmc)); 2639 return -ENODEV; 2640 } 2641 2642 spin_lock_init(&host->lock); 2643 2644 /* 2645 * Maximum number of segments. Depends on if the hardware 2646 * can do scatter/gather or not. 2647 */ 2648 if (host->flags & SDHCI_USE_ADMA) 2649 mmc->max_segs = 128; 2650 else if (host->flags & SDHCI_USE_SDMA) 2651 mmc->max_segs = 1; 2652 else /* PIO */ 2653 mmc->max_segs = 128; 2654 2655 /* 2656 * Maximum number of sectors in one transfer. Limited by DMA boundary 2657 * size (512KiB). 2658 */ 2659 mmc->max_req_size = 524288; 2660 2661 /* 2662 * Maximum segment size. Could be one segment with the maximum number 2663 * of bytes. When doing hardware scatter/gather, each entry cannot 2664 * be larger than 64 KiB though. 2665 */ 2666 if (host->flags & SDHCI_USE_ADMA) { 2667 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 2668 mmc->max_seg_size = 65535; 2669 else 2670 mmc->max_seg_size = 65536; 2671 } else { 2672 mmc->max_seg_size = mmc->max_req_size; 2673 } 2674 2675 /* 2676 * Maximum block size. This varies from controller to controller and 2677 * is specified in the capabilities register. 2678 */ 2679 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 2680 mmc->max_blk_size = 2; 2681 } else { 2682 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 2683 SDHCI_MAX_BLOCK_SHIFT; 2684 if (mmc->max_blk_size >= 3) { 2685 printk(KERN_WARNING "%s: Invalid maximum block size, " 2686 "assuming 512 bytes\n", mmc_hostname(mmc)); 2687 mmc->max_blk_size = 0; 2688 } 2689 } 2690 2691 mmc->max_blk_size = 512 << mmc->max_blk_size; 2692 2693 /* 2694 * Maximum block count. 2695 */ 2696 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 2697 2698 /* 2699 * Init tasklets. 2700 */ 2701 tasklet_init(&host->card_tasklet, 2702 sdhci_tasklet_card, (unsigned long)host); 2703 tasklet_init(&host->finish_tasklet, 2704 sdhci_tasklet_finish, (unsigned long)host); 2705 2706 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 2707 2708 if (host->version >= SDHCI_SPEC_300) { 2709 init_waitqueue_head(&host->buf_ready_int); 2710 2711 /* Initialize re-tuning timer */ 2712 init_timer(&host->tuning_timer); 2713 host->tuning_timer.data = (unsigned long)host; 2714 host->tuning_timer.function = sdhci_tuning_timer; 2715 } 2716 2717 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2718 mmc_hostname(mmc), host); 2719 if (ret) 2720 goto untasklet; 2721 2722 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 2723 if (IS_ERR(host->vmmc)) { 2724 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); 2725 host->vmmc = NULL; 2726 } else { 2727 regulator_enable(host->vmmc); 2728 } 2729 2730 sdhci_init(host, 0); 2731 2732 #ifdef CONFIG_MMC_DEBUG 2733 sdhci_dumpregs(host); 2734 #endif 2735 2736 #ifdef SDHCI_USE_LEDS_CLASS 2737 snprintf(host->led_name, sizeof(host->led_name), 2738 "%s::", mmc_hostname(mmc)); 2739 host->led.name = host->led_name; 2740 host->led.brightness = LED_OFF; 2741 host->led.default_trigger = mmc_hostname(mmc); 2742 host->led.brightness_set = sdhci_led_control; 2743 2744 ret = led_classdev_register(mmc_dev(mmc), &host->led); 2745 if (ret) 2746 goto reset; 2747 #endif 2748 2749 mmiowb(); 2750 2751 mmc_add_host(mmc); 2752 2753 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n", 2754 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 2755 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 2756 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 2757 2758 sdhci_enable_card_detection(host); 2759 2760 return 0; 2761 2762 #ifdef SDHCI_USE_LEDS_CLASS 2763 reset: 2764 sdhci_reset(host, SDHCI_RESET_ALL); 2765 free_irq(host->irq, host); 2766 #endif 2767 untasklet: 2768 tasklet_kill(&host->card_tasklet); 2769 tasklet_kill(&host->finish_tasklet); 2770 2771 return ret; 2772 } 2773 2774 EXPORT_SYMBOL_GPL(sdhci_add_host); 2775 2776 void sdhci_remove_host(struct sdhci_host *host, int dead) 2777 { 2778 unsigned long flags; 2779 2780 if (dead) { 2781 spin_lock_irqsave(&host->lock, flags); 2782 2783 host->flags |= SDHCI_DEVICE_DEAD; 2784 2785 if (host->mrq) { 2786 printk(KERN_ERR "%s: Controller removed during " 2787 " transfer!\n", mmc_hostname(host->mmc)); 2788 2789 host->mrq->cmd->error = -ENOMEDIUM; 2790 tasklet_schedule(&host->finish_tasklet); 2791 } 2792 2793 spin_unlock_irqrestore(&host->lock, flags); 2794 } 2795 2796 sdhci_disable_card_detection(host); 2797 2798 mmc_remove_host(host->mmc); 2799 2800 #ifdef SDHCI_USE_LEDS_CLASS 2801 led_classdev_unregister(&host->led); 2802 #endif 2803 2804 if (!dead) 2805 sdhci_reset(host, SDHCI_RESET_ALL); 2806 2807 free_irq(host->irq, host); 2808 2809 del_timer_sync(&host->timer); 2810 if (host->version >= SDHCI_SPEC_300) 2811 del_timer_sync(&host->tuning_timer); 2812 2813 tasklet_kill(&host->card_tasklet); 2814 tasklet_kill(&host->finish_tasklet); 2815 2816 if (host->vmmc) { 2817 regulator_disable(host->vmmc); 2818 regulator_put(host->vmmc); 2819 } 2820 2821 kfree(host->adma_desc); 2822 kfree(host->align_buffer); 2823 2824 host->adma_desc = NULL; 2825 host->align_buffer = NULL; 2826 } 2827 2828 EXPORT_SYMBOL_GPL(sdhci_remove_host); 2829 2830 void sdhci_free_host(struct sdhci_host *host) 2831 { 2832 mmc_free_host(host->mmc); 2833 } 2834 2835 EXPORT_SYMBOL_GPL(sdhci_free_host); 2836 2837 /*****************************************************************************\ 2838 * * 2839 * Driver init/exit * 2840 * * 2841 \*****************************************************************************/ 2842 2843 static int __init sdhci_drv_init(void) 2844 { 2845 printk(KERN_INFO DRIVER_NAME 2846 ": Secure Digital Host Controller Interface driver\n"); 2847 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 2848 2849 return 0; 2850 } 2851 2852 static void __exit sdhci_drv_exit(void) 2853 { 2854 } 2855 2856 module_init(sdhci_drv_init); 2857 module_exit(sdhci_drv_exit); 2858 2859 module_param(debug_quirks, uint, 0444); 2860 2861 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2862 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 2863 MODULE_LICENSE("GPL"); 2864 2865 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 2866