1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/of.h> 26 27 #include <linux/leds.h> 28 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/card.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "sdhci.h" 36 37 #define DRIVER_NAME "sdhci" 38 39 #define DBG(f, x...) \ 40 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 41 42 #define MAX_TUNING_LOOP 40 43 44 static unsigned int debug_quirks = 0; 45 static unsigned int debug_quirks2; 46 47 static void sdhci_finish_data(struct sdhci_host *); 48 49 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); 50 51 static void sdhci_dumpregs(struct sdhci_host *host) 52 { 53 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 54 mmc_hostname(host->mmc)); 55 56 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 57 sdhci_readl(host, SDHCI_DMA_ADDRESS), 58 sdhci_readw(host, SDHCI_HOST_VERSION)); 59 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 60 sdhci_readw(host, SDHCI_BLOCK_SIZE), 61 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 62 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 63 sdhci_readl(host, SDHCI_ARGUMENT), 64 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 65 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 66 sdhci_readl(host, SDHCI_PRESENT_STATE), 67 sdhci_readb(host, SDHCI_HOST_CONTROL)); 68 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 69 sdhci_readb(host, SDHCI_POWER_CONTROL), 70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 71 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 73 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 74 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 76 sdhci_readl(host, SDHCI_INT_STATUS)); 77 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 78 sdhci_readl(host, SDHCI_INT_ENABLE), 79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 80 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 81 sdhci_readw(host, SDHCI_ACMD12_ERR), 82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 83 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 84 sdhci_readl(host, SDHCI_CAPABILITIES), 85 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 86 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 87 sdhci_readw(host, SDHCI_COMMAND), 88 sdhci_readl(host, SDHCI_MAX_CURRENT)); 89 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", 90 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 91 92 if (host->flags & SDHCI_USE_ADMA) { 93 if (host->flags & SDHCI_USE_64_BIT_DMA) 94 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", 95 readl(host->ioaddr + SDHCI_ADMA_ERROR), 96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), 97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 98 else 99 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 100 readl(host->ioaddr + SDHCI_ADMA_ERROR), 101 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 102 } 103 104 pr_err(DRIVER_NAME ": ===========================================\n"); 105 } 106 107 /*****************************************************************************\ 108 * * 109 * Low level functions * 110 * * 111 \*****************************************************************************/ 112 113 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) 114 { 115 return cmd->data || cmd->flags & MMC_RSP_BUSY; 116 } 117 118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 119 { 120 u32 present; 121 122 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 123 !mmc_card_is_removable(host->mmc)) 124 return; 125 126 if (enable) { 127 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 128 SDHCI_CARD_PRESENT; 129 130 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 131 SDHCI_INT_CARD_INSERT; 132 } else { 133 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 134 } 135 136 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 137 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 138 } 139 140 static void sdhci_enable_card_detection(struct sdhci_host *host) 141 { 142 sdhci_set_card_detection(host, true); 143 } 144 145 static void sdhci_disable_card_detection(struct sdhci_host *host) 146 { 147 sdhci_set_card_detection(host, false); 148 } 149 150 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) 151 { 152 if (host->bus_on) 153 return; 154 host->bus_on = true; 155 pm_runtime_get_noresume(host->mmc->parent); 156 } 157 158 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) 159 { 160 if (!host->bus_on) 161 return; 162 host->bus_on = false; 163 pm_runtime_put_noidle(host->mmc->parent); 164 } 165 166 void sdhci_reset(struct sdhci_host *host, u8 mask) 167 { 168 unsigned long timeout; 169 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 171 172 if (mask & SDHCI_RESET_ALL) { 173 host->clock = 0; 174 /* Reset-all turns off SD Bus Power */ 175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 176 sdhci_runtime_pm_bus_off(host); 177 } 178 179 /* Wait max 100 ms */ 180 timeout = 100; 181 182 /* hw clears the bit when it's done */ 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 184 if (timeout == 0) { 185 pr_err("%s: Reset 0x%x never completed.\n", 186 mmc_hostname(host->mmc), (int)mask); 187 sdhci_dumpregs(host); 188 return; 189 } 190 timeout--; 191 mdelay(1); 192 } 193 } 194 EXPORT_SYMBOL_GPL(sdhci_reset); 195 196 static void sdhci_do_reset(struct sdhci_host *host, u8 mask) 197 { 198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 199 struct mmc_host *mmc = host->mmc; 200 201 if (!mmc->ops->get_cd(mmc)) 202 return; 203 } 204 205 host->ops->reset(host, mask); 206 207 if (mask & SDHCI_RESET_ALL) { 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 209 if (host->ops->enable_dma) 210 host->ops->enable_dma(host); 211 } 212 213 /* Resetting the controller clears many */ 214 host->preset_enabled = false; 215 } 216 } 217 218 static void sdhci_init(struct sdhci_host *host, int soft) 219 { 220 struct mmc_host *mmc = host->mmc; 221 222 if (soft) 223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 224 else 225 sdhci_do_reset(host, SDHCI_RESET_ALL); 226 227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | 229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | 230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | 231 SDHCI_INT_RESPONSE; 232 233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 || 234 host->tuning_mode == SDHCI_TUNING_MODE_3) 235 host->ier |= SDHCI_INT_RETUNE; 236 237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 239 240 if (soft) { 241 /* force clock reconfiguration */ 242 host->clock = 0; 243 mmc->ops->set_ios(mmc, &mmc->ios); 244 } 245 } 246 247 static void sdhci_reinit(struct sdhci_host *host) 248 { 249 sdhci_init(host, 0); 250 sdhci_enable_card_detection(host); 251 } 252 253 static void __sdhci_led_activate(struct sdhci_host *host) 254 { 255 u8 ctrl; 256 257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 258 ctrl |= SDHCI_CTRL_LED; 259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 260 } 261 262 static void __sdhci_led_deactivate(struct sdhci_host *host) 263 { 264 u8 ctrl; 265 266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 267 ctrl &= ~SDHCI_CTRL_LED; 268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 269 } 270 271 #if IS_REACHABLE(CONFIG_LEDS_CLASS) 272 static void sdhci_led_control(struct led_classdev *led, 273 enum led_brightness brightness) 274 { 275 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 276 unsigned long flags; 277 278 spin_lock_irqsave(&host->lock, flags); 279 280 if (host->runtime_suspended) 281 goto out; 282 283 if (brightness == LED_OFF) 284 __sdhci_led_deactivate(host); 285 else 286 __sdhci_led_activate(host); 287 out: 288 spin_unlock_irqrestore(&host->lock, flags); 289 } 290 291 static int sdhci_led_register(struct sdhci_host *host) 292 { 293 struct mmc_host *mmc = host->mmc; 294 295 snprintf(host->led_name, sizeof(host->led_name), 296 "%s::", mmc_hostname(mmc)); 297 298 host->led.name = host->led_name; 299 host->led.brightness = LED_OFF; 300 host->led.default_trigger = mmc_hostname(mmc); 301 host->led.brightness_set = sdhci_led_control; 302 303 return led_classdev_register(mmc_dev(mmc), &host->led); 304 } 305 306 static void sdhci_led_unregister(struct sdhci_host *host) 307 { 308 led_classdev_unregister(&host->led); 309 } 310 311 static inline void sdhci_led_activate(struct sdhci_host *host) 312 { 313 } 314 315 static inline void sdhci_led_deactivate(struct sdhci_host *host) 316 { 317 } 318 319 #else 320 321 static inline int sdhci_led_register(struct sdhci_host *host) 322 { 323 return 0; 324 } 325 326 static inline void sdhci_led_unregister(struct sdhci_host *host) 327 { 328 } 329 330 static inline void sdhci_led_activate(struct sdhci_host *host) 331 { 332 __sdhci_led_activate(host); 333 } 334 335 static inline void sdhci_led_deactivate(struct sdhci_host *host) 336 { 337 __sdhci_led_deactivate(host); 338 } 339 340 #endif 341 342 /*****************************************************************************\ 343 * * 344 * Core functions * 345 * * 346 \*****************************************************************************/ 347 348 static void sdhci_read_block_pio(struct sdhci_host *host) 349 { 350 unsigned long flags; 351 size_t blksize, len, chunk; 352 u32 uninitialized_var(scratch); 353 u8 *buf; 354 355 DBG("PIO reading\n"); 356 357 blksize = host->data->blksz; 358 chunk = 0; 359 360 local_irq_save(flags); 361 362 while (blksize) { 363 BUG_ON(!sg_miter_next(&host->sg_miter)); 364 365 len = min(host->sg_miter.length, blksize); 366 367 blksize -= len; 368 host->sg_miter.consumed = len; 369 370 buf = host->sg_miter.addr; 371 372 while (len) { 373 if (chunk == 0) { 374 scratch = sdhci_readl(host, SDHCI_BUFFER); 375 chunk = 4; 376 } 377 378 *buf = scratch & 0xFF; 379 380 buf++; 381 scratch >>= 8; 382 chunk--; 383 len--; 384 } 385 } 386 387 sg_miter_stop(&host->sg_miter); 388 389 local_irq_restore(flags); 390 } 391 392 static void sdhci_write_block_pio(struct sdhci_host *host) 393 { 394 unsigned long flags; 395 size_t blksize, len, chunk; 396 u32 scratch; 397 u8 *buf; 398 399 DBG("PIO writing\n"); 400 401 blksize = host->data->blksz; 402 chunk = 0; 403 scratch = 0; 404 405 local_irq_save(flags); 406 407 while (blksize) { 408 BUG_ON(!sg_miter_next(&host->sg_miter)); 409 410 len = min(host->sg_miter.length, blksize); 411 412 blksize -= len; 413 host->sg_miter.consumed = len; 414 415 buf = host->sg_miter.addr; 416 417 while (len) { 418 scratch |= (u32)*buf << (chunk * 8); 419 420 buf++; 421 chunk++; 422 len--; 423 424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 425 sdhci_writel(host, scratch, SDHCI_BUFFER); 426 chunk = 0; 427 scratch = 0; 428 } 429 } 430 } 431 432 sg_miter_stop(&host->sg_miter); 433 434 local_irq_restore(flags); 435 } 436 437 static void sdhci_transfer_pio(struct sdhci_host *host) 438 { 439 u32 mask; 440 441 if (host->blocks == 0) 442 return; 443 444 if (host->data->flags & MMC_DATA_READ) 445 mask = SDHCI_DATA_AVAILABLE; 446 else 447 mask = SDHCI_SPACE_AVAILABLE; 448 449 /* 450 * Some controllers (JMicron JMB38x) mess up the buffer bits 451 * for transfers < 4 bytes. As long as it is just one block, 452 * we can ignore the bits. 453 */ 454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 455 (host->data->blocks == 1)) 456 mask = ~0; 457 458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 460 udelay(100); 461 462 if (host->data->flags & MMC_DATA_READ) 463 sdhci_read_block_pio(host); 464 else 465 sdhci_write_block_pio(host); 466 467 host->blocks--; 468 if (host->blocks == 0) 469 break; 470 } 471 472 DBG("PIO transfer complete.\n"); 473 } 474 475 static int sdhci_pre_dma_transfer(struct sdhci_host *host, 476 struct mmc_data *data, int cookie) 477 { 478 int sg_count; 479 480 /* 481 * If the data buffers are already mapped, return the previous 482 * dma_map_sg() result. 483 */ 484 if (data->host_cookie == COOKIE_PRE_MAPPED) 485 return data->sg_count; 486 487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 488 data->flags & MMC_DATA_WRITE ? 489 DMA_TO_DEVICE : DMA_FROM_DEVICE); 490 491 if (sg_count == 0) 492 return -ENOSPC; 493 494 data->sg_count = sg_count; 495 data->host_cookie = cookie; 496 497 return sg_count; 498 } 499 500 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 501 { 502 local_irq_save(*flags); 503 return kmap_atomic(sg_page(sg)) + sg->offset; 504 } 505 506 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 507 { 508 kunmap_atomic(buffer); 509 local_irq_restore(*flags); 510 } 511 512 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, 513 dma_addr_t addr, int len, unsigned cmd) 514 { 515 struct sdhci_adma2_64_desc *dma_desc = desc; 516 517 /* 32-bit and 64-bit descriptors have these members in same position */ 518 dma_desc->cmd = cpu_to_le16(cmd); 519 dma_desc->len = cpu_to_le16(len); 520 dma_desc->addr_lo = cpu_to_le32((u32)addr); 521 522 if (host->flags & SDHCI_USE_64_BIT_DMA) 523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); 524 } 525 526 static void sdhci_adma_mark_end(void *desc) 527 { 528 struct sdhci_adma2_64_desc *dma_desc = desc; 529 530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */ 531 dma_desc->cmd |= cpu_to_le16(ADMA2_END); 532 } 533 534 static void sdhci_adma_table_pre(struct sdhci_host *host, 535 struct mmc_data *data, int sg_count) 536 { 537 struct scatterlist *sg; 538 unsigned long flags; 539 dma_addr_t addr, align_addr; 540 void *desc, *align; 541 char *buffer; 542 int len, offset, i; 543 544 /* 545 * The spec does not specify endianness of descriptor table. 546 * We currently guess that it is LE. 547 */ 548 549 host->sg_count = sg_count; 550 551 desc = host->adma_table; 552 align = host->align_buffer; 553 554 align_addr = host->align_addr; 555 556 for_each_sg(data->sg, sg, host->sg_count, i) { 557 addr = sg_dma_address(sg); 558 len = sg_dma_len(sg); 559 560 /* 561 * The SDHCI specification states that ADMA addresses must 562 * be 32-bit aligned. If they aren't, then we use a bounce 563 * buffer for the (up to three) bytes that screw up the 564 * alignment. 565 */ 566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & 567 SDHCI_ADMA2_MASK; 568 if (offset) { 569 if (data->flags & MMC_DATA_WRITE) { 570 buffer = sdhci_kmap_atomic(sg, &flags); 571 memcpy(align, buffer, offset); 572 sdhci_kunmap_atomic(buffer, &flags); 573 } 574 575 /* tran, valid */ 576 sdhci_adma_write_desc(host, desc, align_addr, offset, 577 ADMA2_TRAN_VALID); 578 579 BUG_ON(offset > 65536); 580 581 align += SDHCI_ADMA2_ALIGN; 582 align_addr += SDHCI_ADMA2_ALIGN; 583 584 desc += host->desc_sz; 585 586 addr += offset; 587 len -= offset; 588 } 589 590 BUG_ON(len > 65536); 591 592 if (len) { 593 /* tran, valid */ 594 sdhci_adma_write_desc(host, desc, addr, len, 595 ADMA2_TRAN_VALID); 596 desc += host->desc_sz; 597 } 598 599 /* 600 * If this triggers then we have a calculation bug 601 * somewhere. :/ 602 */ 603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz); 604 } 605 606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 607 /* Mark the last descriptor as the terminating descriptor */ 608 if (desc != host->adma_table) { 609 desc -= host->desc_sz; 610 sdhci_adma_mark_end(desc); 611 } 612 } else { 613 /* Add a terminating entry - nop, end, valid */ 614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); 615 } 616 } 617 618 static void sdhci_adma_table_post(struct sdhci_host *host, 619 struct mmc_data *data) 620 { 621 struct scatterlist *sg; 622 int i, size; 623 void *align; 624 char *buffer; 625 unsigned long flags; 626 627 if (data->flags & MMC_DATA_READ) { 628 bool has_unaligned = false; 629 630 /* Do a quick scan of the SG list for any unaligned mappings */ 631 for_each_sg(data->sg, sg, host->sg_count, i) 632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 633 has_unaligned = true; 634 break; 635 } 636 637 if (has_unaligned) { 638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 639 data->sg_len, DMA_FROM_DEVICE); 640 641 align = host->align_buffer; 642 643 for_each_sg(data->sg, sg, host->sg_count, i) { 644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { 645 size = SDHCI_ADMA2_ALIGN - 646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK); 647 648 buffer = sdhci_kmap_atomic(sg, &flags); 649 memcpy(buffer, align, size); 650 sdhci_kunmap_atomic(buffer, &flags); 651 652 align += SDHCI_ADMA2_ALIGN; 653 } 654 } 655 } 656 } 657 } 658 659 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 660 { 661 u8 count; 662 struct mmc_data *data = cmd->data; 663 unsigned target_timeout, current_timeout; 664 665 /* 666 * If the host controller provides us with an incorrect timeout 667 * value, just skip the check and use 0xE. The hardware may take 668 * longer to time out, but that's much better than having a too-short 669 * timeout value. 670 */ 671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 672 return 0xE; 673 674 /* Unspecified timeout, assume max */ 675 if (!data && !cmd->busy_timeout) 676 return 0xE; 677 678 /* timeout in us */ 679 if (!data) 680 target_timeout = cmd->busy_timeout * 1000; 681 else { 682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); 683 if (host->clock && data->timeout_clks) { 684 unsigned long long val; 685 686 /* 687 * data->timeout_clks is in units of clock cycles. 688 * host->clock is in Hz. target_timeout is in us. 689 * Hence, us = 1000000 * cycles / Hz. Round up. 690 */ 691 val = 1000000ULL * data->timeout_clks; 692 if (do_div(val, host->clock)) 693 target_timeout++; 694 target_timeout += val; 695 } 696 } 697 698 /* 699 * Figure out needed cycles. 700 * We do this in steps in order to fit inside a 32 bit int. 701 * The first step is the minimum timeout, which will have a 702 * minimum resolution of 6 bits: 703 * (1) 2^13*1000 > 2^22, 704 * (2) host->timeout_clk < 2^16 705 * => 706 * (1) / (2) > 2^6 707 */ 708 count = 0; 709 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 710 while (current_timeout < target_timeout) { 711 count++; 712 current_timeout <<= 1; 713 if (count >= 0xF) 714 break; 715 } 716 717 if (count >= 0xF) { 718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 719 mmc_hostname(host->mmc), count, cmd->opcode); 720 count = 0xE; 721 } 722 723 return count; 724 } 725 726 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 727 { 728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 730 731 if (host->flags & SDHCI_REQ_USE_DMA) 732 host->ier = (host->ier & ~pio_irqs) | dma_irqs; 733 else 734 host->ier = (host->ier & ~dma_irqs) | pio_irqs; 735 736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 738 } 739 740 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 741 { 742 u8 count; 743 744 if (host->ops->set_timeout) { 745 host->ops->set_timeout(host, cmd); 746 } else { 747 count = sdhci_calc_timeout(host, cmd); 748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 749 } 750 } 751 752 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 753 { 754 u8 ctrl; 755 struct mmc_data *data = cmd->data; 756 757 if (sdhci_data_line_cmd(cmd)) 758 sdhci_set_timeout(host, cmd); 759 760 if (!data) 761 return; 762 763 WARN_ON(host->data); 764 765 /* Sanity checks */ 766 BUG_ON(data->blksz * data->blocks > 524288); 767 BUG_ON(data->blksz > host->mmc->max_blk_size); 768 BUG_ON(data->blocks > 65535); 769 770 host->data = data; 771 host->data_early = 0; 772 host->data->bytes_xfered = 0; 773 774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 775 struct scatterlist *sg; 776 unsigned int length_mask, offset_mask; 777 int i; 778 779 host->flags |= SDHCI_REQ_USE_DMA; 780 781 /* 782 * FIXME: This doesn't account for merging when mapping the 783 * scatterlist. 784 * 785 * The assumption here being that alignment and lengths are 786 * the same after DMA mapping to device address space. 787 */ 788 length_mask = 0; 789 offset_mask = 0; 790 if (host->flags & SDHCI_USE_ADMA) { 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { 792 length_mask = 3; 793 /* 794 * As we use up to 3 byte chunks to work 795 * around alignment problems, we need to 796 * check the offset as well. 797 */ 798 offset_mask = 3; 799 } 800 } else { 801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 802 length_mask = 3; 803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 804 offset_mask = 3; 805 } 806 807 if (unlikely(length_mask | offset_mask)) { 808 for_each_sg(data->sg, sg, data->sg_len, i) { 809 if (sg->length & length_mask) { 810 DBG("Reverting to PIO because of transfer size (%d)\n", 811 sg->length); 812 host->flags &= ~SDHCI_REQ_USE_DMA; 813 break; 814 } 815 if (sg->offset & offset_mask) { 816 DBG("Reverting to PIO because of bad alignment\n"); 817 host->flags &= ~SDHCI_REQ_USE_DMA; 818 break; 819 } 820 } 821 } 822 } 823 824 if (host->flags & SDHCI_REQ_USE_DMA) { 825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); 826 827 if (sg_cnt <= 0) { 828 /* 829 * This only happens when someone fed 830 * us an invalid request. 831 */ 832 WARN_ON(1); 833 host->flags &= ~SDHCI_REQ_USE_DMA; 834 } else if (host->flags & SDHCI_USE_ADMA) { 835 sdhci_adma_table_pre(host, data, sg_cnt); 836 837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); 838 if (host->flags & SDHCI_USE_64_BIT_DMA) 839 sdhci_writel(host, 840 (u64)host->adma_addr >> 32, 841 SDHCI_ADMA_ADDRESS_HI); 842 } else { 843 WARN_ON(sg_cnt != 1); 844 sdhci_writel(host, sg_dma_address(data->sg), 845 SDHCI_DMA_ADDRESS); 846 } 847 } 848 849 /* 850 * Always adjust the DMA selection as some controllers 851 * (e.g. JMicron) can't do PIO properly when the selection 852 * is ADMA. 853 */ 854 if (host->version >= SDHCI_SPEC_200) { 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 856 ctrl &= ~SDHCI_CTRL_DMA_MASK; 857 if ((host->flags & SDHCI_REQ_USE_DMA) && 858 (host->flags & SDHCI_USE_ADMA)) { 859 if (host->flags & SDHCI_USE_64_BIT_DMA) 860 ctrl |= SDHCI_CTRL_ADMA64; 861 else 862 ctrl |= SDHCI_CTRL_ADMA32; 863 } else { 864 ctrl |= SDHCI_CTRL_SDMA; 865 } 866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 867 } 868 869 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 870 int flags; 871 872 flags = SG_MITER_ATOMIC; 873 if (host->data->flags & MMC_DATA_READ) 874 flags |= SG_MITER_TO_SG; 875 else 876 flags |= SG_MITER_FROM_SG; 877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 878 host->blocks = data->blocks; 879 } 880 881 sdhci_set_transfer_irqs(host); 882 883 /* Set the DMA boundary value and block size */ 884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 885 data->blksz), SDHCI_BLOCK_SIZE); 886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 887 } 888 889 static inline bool sdhci_auto_cmd12(struct sdhci_host *host, 890 struct mmc_request *mrq) 891 { 892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && 893 !mrq->cap_cmd_during_tfr; 894 } 895 896 static void sdhci_set_transfer_mode(struct sdhci_host *host, 897 struct mmc_command *cmd) 898 { 899 u16 mode = 0; 900 struct mmc_data *data = cmd->data; 901 902 if (data == NULL) { 903 if (host->quirks2 & 904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { 905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 906 } else { 907 /* clear Auto CMD settings for no data CMDs */ 908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | 910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); 911 } 912 return; 913 } 914 915 WARN_ON(!host->data); 916 917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 918 mode = SDHCI_TRNS_BLK_CNT_EN; 919 920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; 922 /* 923 * If we are sending CMD23, CMD12 never gets sent 924 * on successful completion (so no Auto-CMD12). 925 */ 926 if (sdhci_auto_cmd12(host, cmd->mrq) && 927 (cmd->opcode != SD_IO_RW_EXTENDED)) 928 mode |= SDHCI_TRNS_AUTO_CMD12; 929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 930 mode |= SDHCI_TRNS_AUTO_CMD23; 931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); 932 } 933 } 934 935 if (data->flags & MMC_DATA_READ) 936 mode |= SDHCI_TRNS_READ; 937 if (host->flags & SDHCI_REQ_USE_DMA) 938 mode |= SDHCI_TRNS_DMA; 939 940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 941 } 942 943 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) 944 { 945 return (!(host->flags & SDHCI_DEVICE_DEAD) && 946 ((mrq->cmd && mrq->cmd->error) || 947 (mrq->sbc && mrq->sbc->error) || 948 (mrq->data && ((mrq->data->error && !mrq->data->stop) || 949 (mrq->data->stop && mrq->data->stop->error))) || 950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); 951 } 952 953 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 954 { 955 int i; 956 957 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 958 if (host->mrqs_done[i] == mrq) { 959 WARN_ON(1); 960 return; 961 } 962 } 963 964 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 965 if (!host->mrqs_done[i]) { 966 host->mrqs_done[i] = mrq; 967 break; 968 } 969 } 970 971 WARN_ON(i >= SDHCI_MAX_MRQS); 972 973 tasklet_schedule(&host->finish_tasklet); 974 } 975 976 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) 977 { 978 if (host->cmd && host->cmd->mrq == mrq) 979 host->cmd = NULL; 980 981 if (host->data_cmd && host->data_cmd->mrq == mrq) 982 host->data_cmd = NULL; 983 984 if (host->data && host->data->mrq == mrq) 985 host->data = NULL; 986 987 if (sdhci_needs_reset(host, mrq)) 988 host->pending_reset = true; 989 990 __sdhci_finish_mrq(host, mrq); 991 } 992 993 static void sdhci_finish_data(struct sdhci_host *host) 994 { 995 struct mmc_command *data_cmd = host->data_cmd; 996 struct mmc_data *data = host->data; 997 998 host->data = NULL; 999 host->data_cmd = NULL; 1000 1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == 1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) 1003 sdhci_adma_table_post(host, data); 1004 1005 /* 1006 * The specification states that the block count register must 1007 * be updated, but it does not specify at what point in the 1008 * data flow. That makes the register entirely useless to read 1009 * back so we have to assume that nothing made it to the card 1010 * in the event of an error. 1011 */ 1012 if (data->error) 1013 data->bytes_xfered = 0; 1014 else 1015 data->bytes_xfered = data->blksz * data->blocks; 1016 1017 /* 1018 * Need to send CMD12 if - 1019 * a) open-ended multiblock transfer (no CMD23) 1020 * b) error in multiblock transfer 1021 */ 1022 if (data->stop && 1023 (data->error || 1024 !data->mrq->sbc)) { 1025 1026 /* 1027 * The controller needs a reset of internal state machines 1028 * upon error conditions. 1029 */ 1030 if (data->error) { 1031 if (!host->cmd || host->cmd == data_cmd) 1032 sdhci_do_reset(host, SDHCI_RESET_CMD); 1033 sdhci_do_reset(host, SDHCI_RESET_DATA); 1034 } 1035 1036 /* 1037 * 'cap_cmd_during_tfr' request must not use the command line 1038 * after mmc_command_done() has been called. It is upper layer's 1039 * responsibility to send the stop command if required. 1040 */ 1041 if (data->mrq->cap_cmd_during_tfr) { 1042 sdhci_finish_mrq(host, data->mrq); 1043 } else { 1044 /* Avoid triggering warning in sdhci_send_command() */ 1045 host->cmd = NULL; 1046 sdhci_send_command(host, data->stop); 1047 } 1048 } else { 1049 sdhci_finish_mrq(host, data->mrq); 1050 } 1051 } 1052 1053 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, 1054 unsigned long timeout) 1055 { 1056 if (sdhci_data_line_cmd(mrq->cmd)) 1057 mod_timer(&host->data_timer, timeout); 1058 else 1059 mod_timer(&host->timer, timeout); 1060 } 1061 1062 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) 1063 { 1064 if (sdhci_data_line_cmd(mrq->cmd)) 1065 del_timer(&host->data_timer); 1066 else 1067 del_timer(&host->timer); 1068 } 1069 1070 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 1071 { 1072 int flags; 1073 u32 mask; 1074 unsigned long timeout; 1075 1076 WARN_ON(host->cmd); 1077 1078 /* Initially, a command has no error */ 1079 cmd->error = 0; 1080 1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && 1082 cmd->opcode == MMC_STOP_TRANSMISSION) 1083 cmd->flags |= MMC_RSP_BUSY; 1084 1085 /* Wait max 10 ms */ 1086 timeout = 10; 1087 1088 mask = SDHCI_CMD_INHIBIT; 1089 if (sdhci_data_line_cmd(cmd)) 1090 mask |= SDHCI_DATA_INHIBIT; 1091 1092 /* We shouldn't wait for data inihibit for stop commands, even 1093 though they might use busy signaling */ 1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) 1095 mask &= ~SDHCI_DATA_INHIBIT; 1096 1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 1098 if (timeout == 0) { 1099 pr_err("%s: Controller never released inhibit bit(s).\n", 1100 mmc_hostname(host->mmc)); 1101 sdhci_dumpregs(host); 1102 cmd->error = -EIO; 1103 sdhci_finish_mrq(host, cmd->mrq); 1104 return; 1105 } 1106 timeout--; 1107 mdelay(1); 1108 } 1109 1110 timeout = jiffies; 1111 if (!cmd->data && cmd->busy_timeout > 9000) 1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 1113 else 1114 timeout += 10 * HZ; 1115 sdhci_mod_timer(host, cmd->mrq, timeout); 1116 1117 host->cmd = cmd; 1118 if (sdhci_data_line_cmd(cmd)) { 1119 WARN_ON(host->data_cmd); 1120 host->data_cmd = cmd; 1121 } 1122 1123 sdhci_prepare_data(host, cmd); 1124 1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1126 1127 sdhci_set_transfer_mode(host, cmd); 1128 1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1130 pr_err("%s: Unsupported response type!\n", 1131 mmc_hostname(host->mmc)); 1132 cmd->error = -EINVAL; 1133 sdhci_finish_mrq(host, cmd->mrq); 1134 return; 1135 } 1136 1137 if (!(cmd->flags & MMC_RSP_PRESENT)) 1138 flags = SDHCI_CMD_RESP_NONE; 1139 else if (cmd->flags & MMC_RSP_136) 1140 flags = SDHCI_CMD_RESP_LONG; 1141 else if (cmd->flags & MMC_RSP_BUSY) 1142 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1143 else 1144 flags = SDHCI_CMD_RESP_SHORT; 1145 1146 if (cmd->flags & MMC_RSP_CRC) 1147 flags |= SDHCI_CMD_CRC; 1148 if (cmd->flags & MMC_RSP_OPCODE) 1149 flags |= SDHCI_CMD_INDEX; 1150 1151 /* CMD19 is special in that the Data Present Select should be set */ 1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1154 flags |= SDHCI_CMD_DATA; 1155 1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1157 } 1158 EXPORT_SYMBOL_GPL(sdhci_send_command); 1159 1160 static void sdhci_finish_command(struct sdhci_host *host) 1161 { 1162 struct mmc_command *cmd = host->cmd; 1163 int i; 1164 1165 host->cmd = NULL; 1166 1167 if (cmd->flags & MMC_RSP_PRESENT) { 1168 if (cmd->flags & MMC_RSP_136) { 1169 /* CRC is stripped so we need to do some shifting. */ 1170 for (i = 0;i < 4;i++) { 1171 cmd->resp[i] = sdhci_readl(host, 1172 SDHCI_RESPONSE + (3-i)*4) << 8; 1173 if (i != 3) 1174 cmd->resp[i] |= 1175 sdhci_readb(host, 1176 SDHCI_RESPONSE + (3-i)*4-1); 1177 } 1178 } else { 1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1180 } 1181 } 1182 1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) 1184 mmc_command_done(host->mmc, cmd->mrq); 1185 1186 /* 1187 * The host can send and interrupt when the busy state has 1188 * ended, allowing us to wait without wasting CPU cycles. 1189 * The busy signal uses DAT0 so this is similar to waiting 1190 * for data to complete. 1191 * 1192 * Note: The 1.0 specification is a bit ambiguous about this 1193 * feature so there might be some problems with older 1194 * controllers. 1195 */ 1196 if (cmd->flags & MMC_RSP_BUSY) { 1197 if (cmd->data) { 1198 DBG("Cannot wait for busy signal when also doing a data transfer"); 1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 1200 cmd == host->data_cmd) { 1201 /* Command complete before busy is ended */ 1202 return; 1203 } 1204 } 1205 1206 /* Finished CMD23, now send actual command. */ 1207 if (cmd == cmd->mrq->sbc) { 1208 sdhci_send_command(host, cmd->mrq->cmd); 1209 } else { 1210 1211 /* Processed actual command. */ 1212 if (host->data && host->data_early) 1213 sdhci_finish_data(host); 1214 1215 if (!cmd->data) 1216 sdhci_finish_mrq(host, cmd->mrq); 1217 } 1218 } 1219 1220 static u16 sdhci_get_preset_value(struct sdhci_host *host) 1221 { 1222 u16 preset = 0; 1223 1224 switch (host->timing) { 1225 case MMC_TIMING_UHS_SDR12: 1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1227 break; 1228 case MMC_TIMING_UHS_SDR25: 1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); 1230 break; 1231 case MMC_TIMING_UHS_SDR50: 1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); 1233 break; 1234 case MMC_TIMING_UHS_SDR104: 1235 case MMC_TIMING_MMC_HS200: 1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); 1237 break; 1238 case MMC_TIMING_UHS_DDR50: 1239 case MMC_TIMING_MMC_DDR52: 1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); 1241 break; 1242 case MMC_TIMING_MMC_HS400: 1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); 1244 break; 1245 default: 1246 pr_warn("%s: Invalid UHS-I mode selected\n", 1247 mmc_hostname(host->mmc)); 1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); 1249 break; 1250 } 1251 return preset; 1252 } 1253 1254 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, 1255 unsigned int *actual_clock) 1256 { 1257 int div = 0; /* Initialized for compiler warning */ 1258 int real_div = div, clk_mul = 1; 1259 u16 clk = 0; 1260 bool switch_base_clk = false; 1261 1262 if (host->version >= SDHCI_SPEC_300) { 1263 if (host->preset_enabled) { 1264 u16 pre_val; 1265 1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1267 pre_val = sdhci_get_preset_value(host); 1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) 1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; 1270 if (host->clk_mul && 1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { 1272 clk = SDHCI_PROG_CLOCK_MODE; 1273 real_div = div + 1; 1274 clk_mul = host->clk_mul; 1275 } else { 1276 real_div = max_t(int, 1, div << 1); 1277 } 1278 goto clock_set; 1279 } 1280 1281 /* 1282 * Check if the Host Controller supports Programmable Clock 1283 * Mode. 1284 */ 1285 if (host->clk_mul) { 1286 for (div = 1; div <= 1024; div++) { 1287 if ((host->max_clk * host->clk_mul / div) 1288 <= clock) 1289 break; 1290 } 1291 if ((host->max_clk * host->clk_mul / div) <= clock) { 1292 /* 1293 * Set Programmable Clock Mode in the Clock 1294 * Control register. 1295 */ 1296 clk = SDHCI_PROG_CLOCK_MODE; 1297 real_div = div; 1298 clk_mul = host->clk_mul; 1299 div--; 1300 } else { 1301 /* 1302 * Divisor can be too small to reach clock 1303 * speed requirement. Then use the base clock. 1304 */ 1305 switch_base_clk = true; 1306 } 1307 } 1308 1309 if (!host->clk_mul || switch_base_clk) { 1310 /* Version 3.00 divisors must be a multiple of 2. */ 1311 if (host->max_clk <= clock) 1312 div = 1; 1313 else { 1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1315 div += 2) { 1316 if ((host->max_clk / div) <= clock) 1317 break; 1318 } 1319 } 1320 real_div = div; 1321 div >>= 1; 1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) 1323 && !div && host->max_clk <= 25000000) 1324 div = 1; 1325 } 1326 } else { 1327 /* Version 2.00 divisors must be a power of 2. */ 1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1329 if ((host->max_clk / div) <= clock) 1330 break; 1331 } 1332 real_div = div; 1333 div >>= 1; 1334 } 1335 1336 clock_set: 1337 if (real_div) 1338 *actual_clock = (host->max_clk * clk_mul) / real_div; 1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1341 << SDHCI_DIVIDER_HI_SHIFT; 1342 1343 return clk; 1344 } 1345 EXPORT_SYMBOL_GPL(sdhci_calc_clk); 1346 1347 void sdhci_enable_clk(struct sdhci_host *host, u16 clk) 1348 { 1349 unsigned long timeout; 1350 1351 clk |= SDHCI_CLOCK_INT_EN; 1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1353 1354 /* Wait max 20 ms */ 1355 timeout = 20; 1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1357 & SDHCI_CLOCK_INT_STABLE)) { 1358 if (timeout == 0) { 1359 pr_err("%s: Internal clock never stabilised.\n", 1360 mmc_hostname(host->mmc)); 1361 sdhci_dumpregs(host); 1362 return; 1363 } 1364 timeout--; 1365 mdelay(1); 1366 } 1367 1368 clk |= SDHCI_CLOCK_CARD_EN; 1369 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1370 } 1371 EXPORT_SYMBOL_GPL(sdhci_enable_clk); 1372 1373 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1374 { 1375 u16 clk; 1376 1377 host->mmc->actual_clock = 0; 1378 1379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1380 1381 if (clock == 0) 1382 return; 1383 1384 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1385 sdhci_enable_clk(host, clk); 1386 } 1387 EXPORT_SYMBOL_GPL(sdhci_set_clock); 1388 1389 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, 1390 unsigned short vdd) 1391 { 1392 struct mmc_host *mmc = host->mmc; 1393 1394 spin_unlock_irq(&host->lock); 1395 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 1396 spin_lock_irq(&host->lock); 1397 1398 if (mode != MMC_POWER_OFF) 1399 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); 1400 else 1401 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1402 } 1403 1404 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, 1405 unsigned short vdd) 1406 { 1407 u8 pwr = 0; 1408 1409 if (mode != MMC_POWER_OFF) { 1410 switch (1 << vdd) { 1411 case MMC_VDD_165_195: 1412 pwr = SDHCI_POWER_180; 1413 break; 1414 case MMC_VDD_29_30: 1415 case MMC_VDD_30_31: 1416 pwr = SDHCI_POWER_300; 1417 break; 1418 case MMC_VDD_32_33: 1419 case MMC_VDD_33_34: 1420 pwr = SDHCI_POWER_330; 1421 break; 1422 default: 1423 WARN(1, "%s: Invalid vdd %#x\n", 1424 mmc_hostname(host->mmc), vdd); 1425 break; 1426 } 1427 } 1428 1429 if (host->pwr == pwr) 1430 return; 1431 1432 host->pwr = pwr; 1433 1434 if (pwr == 0) { 1435 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1436 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1437 sdhci_runtime_pm_bus_off(host); 1438 } else { 1439 /* 1440 * Spec says that we should clear the power reg before setting 1441 * a new value. Some controllers don't seem to like this though. 1442 */ 1443 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1444 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1445 1446 /* 1447 * At least the Marvell CaFe chip gets confused if we set the 1448 * voltage and set turn on power at the same time, so set the 1449 * voltage first. 1450 */ 1451 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1452 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1453 1454 pwr |= SDHCI_POWER_ON; 1455 1456 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1457 1458 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) 1459 sdhci_runtime_pm_bus_on(host); 1460 1461 /* 1462 * Some controllers need an extra 10ms delay of 10ms before 1463 * they can apply clock after applying power 1464 */ 1465 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1466 mdelay(10); 1467 } 1468 } 1469 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg); 1470 1471 void sdhci_set_power(struct sdhci_host *host, unsigned char mode, 1472 unsigned short vdd) 1473 { 1474 if (IS_ERR(host->mmc->supply.vmmc)) 1475 sdhci_set_power_noreg(host, mode, vdd); 1476 else 1477 sdhci_set_power_reg(host, mode, vdd); 1478 } 1479 EXPORT_SYMBOL_GPL(sdhci_set_power); 1480 1481 /*****************************************************************************\ 1482 * * 1483 * MMC callbacks * 1484 * * 1485 \*****************************************************************************/ 1486 1487 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1488 { 1489 struct sdhci_host *host; 1490 int present; 1491 unsigned long flags; 1492 1493 host = mmc_priv(mmc); 1494 1495 /* Firstly check card presence */ 1496 present = mmc->ops->get_cd(mmc); 1497 1498 spin_lock_irqsave(&host->lock, flags); 1499 1500 sdhci_led_activate(host); 1501 1502 /* 1503 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1504 * requests if Auto-CMD12 is enabled. 1505 */ 1506 if (sdhci_auto_cmd12(host, mrq)) { 1507 if (mrq->stop) { 1508 mrq->data->stop = NULL; 1509 mrq->stop = NULL; 1510 } 1511 } 1512 1513 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1514 mrq->cmd->error = -ENOMEDIUM; 1515 sdhci_finish_mrq(host, mrq); 1516 } else { 1517 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1518 sdhci_send_command(host, mrq->sbc); 1519 else 1520 sdhci_send_command(host, mrq->cmd); 1521 } 1522 1523 mmiowb(); 1524 spin_unlock_irqrestore(&host->lock, flags); 1525 } 1526 1527 void sdhci_set_bus_width(struct sdhci_host *host, int width) 1528 { 1529 u8 ctrl; 1530 1531 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1532 if (width == MMC_BUS_WIDTH_8) { 1533 ctrl &= ~SDHCI_CTRL_4BITBUS; 1534 if (host->version >= SDHCI_SPEC_300) 1535 ctrl |= SDHCI_CTRL_8BITBUS; 1536 } else { 1537 if (host->version >= SDHCI_SPEC_300) 1538 ctrl &= ~SDHCI_CTRL_8BITBUS; 1539 if (width == MMC_BUS_WIDTH_4) 1540 ctrl |= SDHCI_CTRL_4BITBUS; 1541 else 1542 ctrl &= ~SDHCI_CTRL_4BITBUS; 1543 } 1544 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1545 } 1546 EXPORT_SYMBOL_GPL(sdhci_set_bus_width); 1547 1548 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1549 { 1550 u16 ctrl_2; 1551 1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1553 /* Select Bus Speed Mode for host */ 1554 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1555 if ((timing == MMC_TIMING_MMC_HS200) || 1556 (timing == MMC_TIMING_UHS_SDR104)) 1557 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1558 else if (timing == MMC_TIMING_UHS_SDR12) 1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1560 else if (timing == MMC_TIMING_UHS_SDR25) 1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1562 else if (timing == MMC_TIMING_UHS_SDR50) 1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1564 else if ((timing == MMC_TIMING_UHS_DDR50) || 1565 (timing == MMC_TIMING_MMC_DDR52)) 1566 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1567 else if (timing == MMC_TIMING_MMC_HS400) 1568 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1569 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1570 } 1571 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); 1572 1573 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1574 { 1575 struct sdhci_host *host = mmc_priv(mmc); 1576 unsigned long flags; 1577 u8 ctrl; 1578 1579 spin_lock_irqsave(&host->lock, flags); 1580 1581 if (host->flags & SDHCI_DEVICE_DEAD) { 1582 spin_unlock_irqrestore(&host->lock, flags); 1583 if (!IS_ERR(mmc->supply.vmmc) && 1584 ios->power_mode == MMC_POWER_OFF) 1585 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1586 return; 1587 } 1588 1589 /* 1590 * Reset the chip on each power off. 1591 * Should clear out any weird states. 1592 */ 1593 if (ios->power_mode == MMC_POWER_OFF) { 1594 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1595 sdhci_reinit(host); 1596 } 1597 1598 if (host->version >= SDHCI_SPEC_300 && 1599 (ios->power_mode == MMC_POWER_UP) && 1600 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) 1601 sdhci_enable_preset_value(host, false); 1602 1603 if (!ios->clock || ios->clock != host->clock) { 1604 host->ops->set_clock(host, ios->clock); 1605 host->clock = ios->clock; 1606 1607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && 1608 host->clock) { 1609 host->timeout_clk = host->mmc->actual_clock ? 1610 host->mmc->actual_clock / 1000 : 1611 host->clock / 1000; 1612 host->mmc->max_busy_timeout = 1613 host->ops->get_max_timeout_count ? 1614 host->ops->get_max_timeout_count(host) : 1615 1 << 27; 1616 host->mmc->max_busy_timeout /= host->timeout_clk; 1617 } 1618 } 1619 1620 if (host->ops->set_power) 1621 host->ops->set_power(host, ios->power_mode, ios->vdd); 1622 else 1623 sdhci_set_power(host, ios->power_mode, ios->vdd); 1624 1625 if (host->ops->platform_send_init_74_clocks) 1626 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1627 1628 host->ops->set_bus_width(host, ios->bus_width); 1629 1630 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1631 1632 if ((ios->timing == MMC_TIMING_SD_HS || 1633 ios->timing == MMC_TIMING_MMC_HS || 1634 ios->timing == MMC_TIMING_MMC_HS400 || 1635 ios->timing == MMC_TIMING_MMC_HS200 || 1636 ios->timing == MMC_TIMING_MMC_DDR52 || 1637 ios->timing == MMC_TIMING_UHS_SDR50 || 1638 ios->timing == MMC_TIMING_UHS_SDR104 || 1639 ios->timing == MMC_TIMING_UHS_DDR50 || 1640 ios->timing == MMC_TIMING_UHS_SDR25) 1641 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1642 ctrl |= SDHCI_CTRL_HISPD; 1643 else 1644 ctrl &= ~SDHCI_CTRL_HISPD; 1645 1646 if (host->version >= SDHCI_SPEC_300) { 1647 u16 clk, ctrl_2; 1648 1649 if (!host->preset_enabled) { 1650 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1651 /* 1652 * We only need to set Driver Strength if the 1653 * preset value enable is not set. 1654 */ 1655 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1656 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1657 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1658 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1659 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) 1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1661 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1662 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1663 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) 1664 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; 1665 else { 1666 pr_warn("%s: invalid driver type, default to driver type B\n", 1667 mmc_hostname(mmc)); 1668 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; 1669 } 1670 1671 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1672 } else { 1673 /* 1674 * According to SDHC Spec v3.00, if the Preset Value 1675 * Enable in the Host Control 2 register is set, we 1676 * need to reset SD Clock Enable before changing High 1677 * Speed Enable to avoid generating clock gliches. 1678 */ 1679 1680 /* Reset SD Clock Enable */ 1681 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1682 clk &= ~SDHCI_CLOCK_CARD_EN; 1683 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1684 1685 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1686 1687 /* Re-enable SD Clock */ 1688 host->ops->set_clock(host, host->clock); 1689 } 1690 1691 /* Reset SD Clock Enable */ 1692 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1693 clk &= ~SDHCI_CLOCK_CARD_EN; 1694 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1695 1696 host->ops->set_uhs_signaling(host, ios->timing); 1697 host->timing = ios->timing; 1698 1699 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && 1700 ((ios->timing == MMC_TIMING_UHS_SDR12) || 1701 (ios->timing == MMC_TIMING_UHS_SDR25) || 1702 (ios->timing == MMC_TIMING_UHS_SDR50) || 1703 (ios->timing == MMC_TIMING_UHS_SDR104) || 1704 (ios->timing == MMC_TIMING_UHS_DDR50) || 1705 (ios->timing == MMC_TIMING_MMC_DDR52))) { 1706 u16 preset; 1707 1708 sdhci_enable_preset_value(host, true); 1709 preset = sdhci_get_preset_value(host); 1710 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) 1711 >> SDHCI_PRESET_DRV_SHIFT; 1712 } 1713 1714 /* Re-enable SD Clock */ 1715 host->ops->set_clock(host, host->clock); 1716 } else 1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1718 1719 /* 1720 * Some (ENE) controllers go apeshit on some ios operation, 1721 * signalling timeout and CRC errors even on CMD0. Resetting 1722 * it on each ios seems to solve the problem. 1723 */ 1724 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1725 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1726 1727 mmiowb(); 1728 spin_unlock_irqrestore(&host->lock, flags); 1729 } 1730 1731 static int sdhci_get_cd(struct mmc_host *mmc) 1732 { 1733 struct sdhci_host *host = mmc_priv(mmc); 1734 int gpio_cd = mmc_gpio_get_cd(mmc); 1735 1736 if (host->flags & SDHCI_DEVICE_DEAD) 1737 return 0; 1738 1739 /* If nonremovable, assume that the card is always present. */ 1740 if (!mmc_card_is_removable(host->mmc)) 1741 return 1; 1742 1743 /* 1744 * Try slot gpio detect, if defined it take precedence 1745 * over build in controller functionality 1746 */ 1747 if (gpio_cd >= 0) 1748 return !!gpio_cd; 1749 1750 /* If polling, assume that the card is always present. */ 1751 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1752 return 1; 1753 1754 /* Host native card detect */ 1755 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 1756 } 1757 1758 static int sdhci_check_ro(struct sdhci_host *host) 1759 { 1760 unsigned long flags; 1761 int is_readonly; 1762 1763 spin_lock_irqsave(&host->lock, flags); 1764 1765 if (host->flags & SDHCI_DEVICE_DEAD) 1766 is_readonly = 0; 1767 else if (host->ops->get_ro) 1768 is_readonly = host->ops->get_ro(host); 1769 else 1770 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1771 & SDHCI_WRITE_PROTECT); 1772 1773 spin_unlock_irqrestore(&host->lock, flags); 1774 1775 /* This quirk needs to be replaced by a callback-function later */ 1776 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1777 !is_readonly : is_readonly; 1778 } 1779 1780 #define SAMPLE_COUNT 5 1781 1782 static int sdhci_get_ro(struct mmc_host *mmc) 1783 { 1784 struct sdhci_host *host = mmc_priv(mmc); 1785 int i, ro_count; 1786 1787 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1788 return sdhci_check_ro(host); 1789 1790 ro_count = 0; 1791 for (i = 0; i < SAMPLE_COUNT; i++) { 1792 if (sdhci_check_ro(host)) { 1793 if (++ro_count > SAMPLE_COUNT / 2) 1794 return 1; 1795 } 1796 msleep(30); 1797 } 1798 return 0; 1799 } 1800 1801 static void sdhci_hw_reset(struct mmc_host *mmc) 1802 { 1803 struct sdhci_host *host = mmc_priv(mmc); 1804 1805 if (host->ops && host->ops->hw_reset) 1806 host->ops->hw_reset(host); 1807 } 1808 1809 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1810 { 1811 if (!(host->flags & SDHCI_DEVICE_DEAD)) { 1812 if (enable) 1813 host->ier |= SDHCI_INT_CARD_INT; 1814 else 1815 host->ier &= ~SDHCI_INT_CARD_INT; 1816 1817 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1818 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1819 mmiowb(); 1820 } 1821 } 1822 1823 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1824 { 1825 struct sdhci_host *host = mmc_priv(mmc); 1826 unsigned long flags; 1827 1828 spin_lock_irqsave(&host->lock, flags); 1829 if (enable) 1830 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1831 else 1832 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1833 1834 sdhci_enable_sdio_irq_nolock(host, enable); 1835 spin_unlock_irqrestore(&host->lock, flags); 1836 } 1837 1838 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1839 struct mmc_ios *ios) 1840 { 1841 struct sdhci_host *host = mmc_priv(mmc); 1842 u16 ctrl; 1843 int ret; 1844 1845 /* 1846 * Signal Voltage Switching is only applicable for Host Controllers 1847 * v3.00 and above. 1848 */ 1849 if (host->version < SDHCI_SPEC_300) 1850 return 0; 1851 1852 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1853 1854 switch (ios->signal_voltage) { 1855 case MMC_SIGNAL_VOLTAGE_330: 1856 if (!(host->flags & SDHCI_SIGNALING_330)) 1857 return -EINVAL; 1858 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1859 ctrl &= ~SDHCI_CTRL_VDD_180; 1860 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1861 1862 if (!IS_ERR(mmc->supply.vqmmc)) { 1863 ret = mmc_regulator_set_vqmmc(mmc, ios); 1864 if (ret) { 1865 pr_warn("%s: Switching to 3.3V signalling voltage failed\n", 1866 mmc_hostname(mmc)); 1867 return -EIO; 1868 } 1869 } 1870 /* Wait for 5ms */ 1871 usleep_range(5000, 5500); 1872 1873 /* 3.3V regulator output should be stable within 5 ms */ 1874 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1875 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1876 return 0; 1877 1878 pr_warn("%s: 3.3V regulator output did not became stable\n", 1879 mmc_hostname(mmc)); 1880 1881 return -EAGAIN; 1882 case MMC_SIGNAL_VOLTAGE_180: 1883 if (!(host->flags & SDHCI_SIGNALING_180)) 1884 return -EINVAL; 1885 if (!IS_ERR(mmc->supply.vqmmc)) { 1886 ret = mmc_regulator_set_vqmmc(mmc, ios); 1887 if (ret) { 1888 pr_warn("%s: Switching to 1.8V signalling voltage failed\n", 1889 mmc_hostname(mmc)); 1890 return -EIO; 1891 } 1892 } 1893 1894 /* 1895 * Enable 1.8V Signal Enable in the Host Control2 1896 * register 1897 */ 1898 ctrl |= SDHCI_CTRL_VDD_180; 1899 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1900 1901 /* Some controller need to do more when switching */ 1902 if (host->ops->voltage_switch) 1903 host->ops->voltage_switch(host); 1904 1905 /* 1.8V regulator output should be stable within 5 ms */ 1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1907 if (ctrl & SDHCI_CTRL_VDD_180) 1908 return 0; 1909 1910 pr_warn("%s: 1.8V regulator output did not became stable\n", 1911 mmc_hostname(mmc)); 1912 1913 return -EAGAIN; 1914 case MMC_SIGNAL_VOLTAGE_120: 1915 if (!(host->flags & SDHCI_SIGNALING_120)) 1916 return -EINVAL; 1917 if (!IS_ERR(mmc->supply.vqmmc)) { 1918 ret = mmc_regulator_set_vqmmc(mmc, ios); 1919 if (ret) { 1920 pr_warn("%s: Switching to 1.2V signalling voltage failed\n", 1921 mmc_hostname(mmc)); 1922 return -EIO; 1923 } 1924 } 1925 return 0; 1926 default: 1927 /* No signal voltage switch required */ 1928 return 0; 1929 } 1930 } 1931 1932 static int sdhci_card_busy(struct mmc_host *mmc) 1933 { 1934 struct sdhci_host *host = mmc_priv(mmc); 1935 u32 present_state; 1936 1937 /* Check whether DAT[0] is 0 */ 1938 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1939 1940 return !(present_state & SDHCI_DATA_0_LVL_MASK); 1941 } 1942 1943 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1944 { 1945 struct sdhci_host *host = mmc_priv(mmc); 1946 unsigned long flags; 1947 1948 spin_lock_irqsave(&host->lock, flags); 1949 host->flags |= SDHCI_HS400_TUNING; 1950 spin_unlock_irqrestore(&host->lock, flags); 1951 1952 return 0; 1953 } 1954 1955 static void sdhci_start_tuning(struct sdhci_host *host) 1956 { 1957 u16 ctrl; 1958 1959 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1960 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1961 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) 1962 ctrl |= SDHCI_CTRL_TUNED_CLK; 1963 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1964 1965 /* 1966 * As per the Host Controller spec v3.00, tuning command 1967 * generates Buffer Read Ready interrupt, so enable that. 1968 * 1969 * Note: The spec clearly says that when tuning sequence 1970 * is being performed, the controller does not generate 1971 * interrupts other than Buffer Read Ready interrupt. But 1972 * to make sure we don't hit a controller bug, we _only_ 1973 * enable Buffer Read Ready interrupt here. 1974 */ 1975 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); 1976 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); 1977 } 1978 1979 static void sdhci_end_tuning(struct sdhci_host *host) 1980 { 1981 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1982 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1983 } 1984 1985 static void sdhci_reset_tuning(struct sdhci_host *host) 1986 { 1987 u16 ctrl; 1988 1989 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1991 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1992 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1993 } 1994 1995 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode, 1996 unsigned long flags) 1997 { 1998 sdhci_reset_tuning(host); 1999 2000 sdhci_do_reset(host, SDHCI_RESET_CMD); 2001 sdhci_do_reset(host, SDHCI_RESET_DATA); 2002 2003 sdhci_end_tuning(host); 2004 2005 spin_unlock_irqrestore(&host->lock, flags); 2006 mmc_abort_tuning(host->mmc, opcode); 2007 spin_lock_irqsave(&host->lock, flags); 2008 } 2009 2010 /* 2011 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI 2012 * tuning command does not have a data payload (or rather the hardware does it 2013 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command 2014 * interrupt setup is different to other commands and there is no timeout 2015 * interrupt so special handling is needed. 2016 */ 2017 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode, 2018 unsigned long flags) 2019 { 2020 struct mmc_host *mmc = host->mmc; 2021 struct mmc_command cmd = {0}; 2022 struct mmc_request mrq = {NULL}; 2023 2024 cmd.opcode = opcode; 2025 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 2026 cmd.mrq = &mrq; 2027 2028 mrq.cmd = &cmd; 2029 /* 2030 * In response to CMD19, the card sends 64 bytes of tuning 2031 * block to the Host Controller. So we set the block size 2032 * to 64 here. 2033 */ 2034 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 && 2035 mmc->ios.bus_width == MMC_BUS_WIDTH_8) 2036 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 2037 else 2038 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 2039 2040 /* 2041 * The tuning block is sent by the card to the host controller. 2042 * So we set the TRNS_READ bit in the Transfer Mode register. 2043 * This also takes care of setting DMA Enable and Multi Block 2044 * Select in the same register to 0. 2045 */ 2046 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 2047 2048 sdhci_send_command(host, &cmd); 2049 2050 host->cmd = NULL; 2051 2052 sdhci_del_timer(host, &mrq); 2053 2054 host->tuning_done = 0; 2055 2056 spin_unlock_irqrestore(&host->lock, flags); 2057 2058 /* Wait for Buffer Read Ready interrupt */ 2059 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1), 2060 msecs_to_jiffies(50)); 2061 2062 spin_lock_irqsave(&host->lock, flags); 2063 } 2064 2065 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode, 2066 unsigned long flags) 2067 { 2068 int i; 2069 2070 /* 2071 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 2072 * of loops reaches 40 times. 2073 */ 2074 for (i = 0; i < MAX_TUNING_LOOP; i++) { 2075 u16 ctrl; 2076 2077 sdhci_send_tuning(host, opcode, flags); 2078 2079 if (!host->tuning_done) { 2080 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 2081 mmc_hostname(host->mmc)); 2082 sdhci_abort_tuning(host, opcode, flags); 2083 return; 2084 } 2085 2086 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2087 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 2088 if (ctrl & SDHCI_CTRL_TUNED_CLK) 2089 return; /* Success! */ 2090 break; 2091 } 2092 2093 /* eMMC spec does not require a delay between tuning cycles */ 2094 if (opcode == MMC_SEND_TUNING_BLOCK) 2095 mdelay(1); 2096 } 2097 2098 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 2099 mmc_hostname(host->mmc)); 2100 sdhci_reset_tuning(host); 2101 } 2102 2103 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 2104 { 2105 struct sdhci_host *host = mmc_priv(mmc); 2106 int err = 0; 2107 unsigned long flags; 2108 unsigned int tuning_count = 0; 2109 bool hs400_tuning; 2110 2111 spin_lock_irqsave(&host->lock, flags); 2112 2113 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 2114 host->flags &= ~SDHCI_HS400_TUNING; 2115 2116 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 2117 tuning_count = host->tuning_count; 2118 2119 /* 2120 * The Host Controller needs tuning in case of SDR104 and DDR50 2121 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 2122 * the Capabilities register. 2123 * If the Host Controller supports the HS200 mode then the 2124 * tuning function has to be executed. 2125 */ 2126 switch (host->timing) { 2127 /* HS400 tuning is done in HS200 mode */ 2128 case MMC_TIMING_MMC_HS400: 2129 err = -EINVAL; 2130 goto out_unlock; 2131 2132 case MMC_TIMING_MMC_HS200: 2133 /* 2134 * Periodic re-tuning for HS400 is not expected to be needed, so 2135 * disable it here. 2136 */ 2137 if (hs400_tuning) 2138 tuning_count = 0; 2139 break; 2140 2141 case MMC_TIMING_UHS_SDR104: 2142 case MMC_TIMING_UHS_DDR50: 2143 break; 2144 2145 case MMC_TIMING_UHS_SDR50: 2146 if (host->flags & SDHCI_SDR50_NEEDS_TUNING) 2147 break; 2148 /* FALLTHROUGH */ 2149 2150 default: 2151 goto out_unlock; 2152 } 2153 2154 if (host->ops->platform_execute_tuning) { 2155 spin_unlock_irqrestore(&host->lock, flags); 2156 return host->ops->platform_execute_tuning(host, opcode); 2157 } 2158 2159 host->mmc->retune_period = tuning_count; 2160 2161 sdhci_start_tuning(host); 2162 2163 __sdhci_execute_tuning(host, opcode, flags); 2164 2165 sdhci_end_tuning(host); 2166 out_unlock: 2167 spin_unlock_irqrestore(&host->lock, flags); 2168 2169 return err; 2170 } 2171 EXPORT_SYMBOL_GPL(sdhci_execute_tuning); 2172 2173 static int sdhci_select_drive_strength(struct mmc_card *card, 2174 unsigned int max_dtr, int host_drv, 2175 int card_drv, int *drv_type) 2176 { 2177 struct sdhci_host *host = mmc_priv(card->host); 2178 2179 if (!host->ops->select_drive_strength) 2180 return 0; 2181 2182 return host->ops->select_drive_strength(host, card, max_dtr, host_drv, 2183 card_drv, drv_type); 2184 } 2185 2186 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) 2187 { 2188 /* Host Controller v3.00 defines preset value registers */ 2189 if (host->version < SDHCI_SPEC_300) 2190 return; 2191 2192 /* 2193 * We only enable or disable Preset Value if they are not already 2194 * enabled or disabled respectively. Otherwise, we bail out. 2195 */ 2196 if (host->preset_enabled != enable) { 2197 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 2198 2199 if (enable) 2200 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 2201 else 2202 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 2203 2204 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 2205 2206 if (enable) 2207 host->flags |= SDHCI_PV_ENABLED; 2208 else 2209 host->flags &= ~SDHCI_PV_ENABLED; 2210 2211 host->preset_enabled = enable; 2212 } 2213 } 2214 2215 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 2216 int err) 2217 { 2218 struct sdhci_host *host = mmc_priv(mmc); 2219 struct mmc_data *data = mrq->data; 2220 2221 if (data->host_cookie != COOKIE_UNMAPPED) 2222 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2223 data->flags & MMC_DATA_WRITE ? 2224 DMA_TO_DEVICE : DMA_FROM_DEVICE); 2225 2226 data->host_cookie = COOKIE_UNMAPPED; 2227 } 2228 2229 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 2230 { 2231 struct sdhci_host *host = mmc_priv(mmc); 2232 2233 mrq->data->host_cookie = COOKIE_UNMAPPED; 2234 2235 if (host->flags & SDHCI_REQ_USE_DMA) 2236 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); 2237 } 2238 2239 static inline bool sdhci_has_requests(struct sdhci_host *host) 2240 { 2241 return host->cmd || host->data_cmd; 2242 } 2243 2244 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) 2245 { 2246 if (host->data_cmd) { 2247 host->data_cmd->error = err; 2248 sdhci_finish_mrq(host, host->data_cmd->mrq); 2249 } 2250 2251 if (host->cmd) { 2252 host->cmd->error = err; 2253 sdhci_finish_mrq(host, host->cmd->mrq); 2254 } 2255 } 2256 2257 static void sdhci_card_event(struct mmc_host *mmc) 2258 { 2259 struct sdhci_host *host = mmc_priv(mmc); 2260 unsigned long flags; 2261 int present; 2262 2263 /* First check if client has provided their own card event */ 2264 if (host->ops->card_event) 2265 host->ops->card_event(host); 2266 2267 present = mmc->ops->get_cd(mmc); 2268 2269 spin_lock_irqsave(&host->lock, flags); 2270 2271 /* Check sdhci_has_requests() first in case we are runtime suspended */ 2272 if (sdhci_has_requests(host) && !present) { 2273 pr_err("%s: Card removed during transfer!\n", 2274 mmc_hostname(host->mmc)); 2275 pr_err("%s: Resetting controller.\n", 2276 mmc_hostname(host->mmc)); 2277 2278 sdhci_do_reset(host, SDHCI_RESET_CMD); 2279 sdhci_do_reset(host, SDHCI_RESET_DATA); 2280 2281 sdhci_error_out_mrqs(host, -ENOMEDIUM); 2282 } 2283 2284 spin_unlock_irqrestore(&host->lock, flags); 2285 } 2286 2287 static const struct mmc_host_ops sdhci_ops = { 2288 .request = sdhci_request, 2289 .post_req = sdhci_post_req, 2290 .pre_req = sdhci_pre_req, 2291 .set_ios = sdhci_set_ios, 2292 .get_cd = sdhci_get_cd, 2293 .get_ro = sdhci_get_ro, 2294 .hw_reset = sdhci_hw_reset, 2295 .enable_sdio_irq = sdhci_enable_sdio_irq, 2296 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2297 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, 2298 .execute_tuning = sdhci_execute_tuning, 2299 .select_drive_strength = sdhci_select_drive_strength, 2300 .card_event = sdhci_card_event, 2301 .card_busy = sdhci_card_busy, 2302 }; 2303 2304 /*****************************************************************************\ 2305 * * 2306 * Tasklets * 2307 * * 2308 \*****************************************************************************/ 2309 2310 static bool sdhci_request_done(struct sdhci_host *host) 2311 { 2312 unsigned long flags; 2313 struct mmc_request *mrq; 2314 int i; 2315 2316 spin_lock_irqsave(&host->lock, flags); 2317 2318 for (i = 0; i < SDHCI_MAX_MRQS; i++) { 2319 mrq = host->mrqs_done[i]; 2320 if (mrq) 2321 break; 2322 } 2323 2324 if (!mrq) { 2325 spin_unlock_irqrestore(&host->lock, flags); 2326 return true; 2327 } 2328 2329 sdhci_del_timer(host, mrq); 2330 2331 /* 2332 * Always unmap the data buffers if they were mapped by 2333 * sdhci_prepare_data() whenever we finish with a request. 2334 * This avoids leaking DMA mappings on error. 2335 */ 2336 if (host->flags & SDHCI_REQ_USE_DMA) { 2337 struct mmc_data *data = mrq->data; 2338 2339 if (data && data->host_cookie == COOKIE_MAPPED) { 2340 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 2341 (data->flags & MMC_DATA_READ) ? 2342 DMA_FROM_DEVICE : DMA_TO_DEVICE); 2343 data->host_cookie = COOKIE_UNMAPPED; 2344 } 2345 } 2346 2347 /* 2348 * The controller needs a reset of internal state machines 2349 * upon error conditions. 2350 */ 2351 if (sdhci_needs_reset(host, mrq)) { 2352 /* 2353 * Do not finish until command and data lines are available for 2354 * reset. Note there can only be one other mrq, so it cannot 2355 * also be in mrqs_done, otherwise host->cmd and host->data_cmd 2356 * would both be null. 2357 */ 2358 if (host->cmd || host->data_cmd) { 2359 spin_unlock_irqrestore(&host->lock, flags); 2360 return true; 2361 } 2362 2363 /* Some controllers need this kick or reset won't work here */ 2364 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) 2365 /* This is to force an update */ 2366 host->ops->set_clock(host, host->clock); 2367 2368 /* Spec says we should do both at the same time, but Ricoh 2369 controllers do not like that. */ 2370 sdhci_do_reset(host, SDHCI_RESET_CMD); 2371 sdhci_do_reset(host, SDHCI_RESET_DATA); 2372 2373 host->pending_reset = false; 2374 } 2375 2376 if (!sdhci_has_requests(host)) 2377 sdhci_led_deactivate(host); 2378 2379 host->mrqs_done[i] = NULL; 2380 2381 mmiowb(); 2382 spin_unlock_irqrestore(&host->lock, flags); 2383 2384 mmc_request_done(host->mmc, mrq); 2385 2386 return false; 2387 } 2388 2389 static void sdhci_tasklet_finish(unsigned long param) 2390 { 2391 struct sdhci_host *host = (struct sdhci_host *)param; 2392 2393 while (!sdhci_request_done(host)) 2394 ; 2395 } 2396 2397 static void sdhci_timeout_timer(unsigned long data) 2398 { 2399 struct sdhci_host *host; 2400 unsigned long flags; 2401 2402 host = (struct sdhci_host*)data; 2403 2404 spin_lock_irqsave(&host->lock, flags); 2405 2406 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { 2407 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", 2408 mmc_hostname(host->mmc)); 2409 sdhci_dumpregs(host); 2410 2411 host->cmd->error = -ETIMEDOUT; 2412 sdhci_finish_mrq(host, host->cmd->mrq); 2413 } 2414 2415 mmiowb(); 2416 spin_unlock_irqrestore(&host->lock, flags); 2417 } 2418 2419 static void sdhci_timeout_data_timer(unsigned long data) 2420 { 2421 struct sdhci_host *host; 2422 unsigned long flags; 2423 2424 host = (struct sdhci_host *)data; 2425 2426 spin_lock_irqsave(&host->lock, flags); 2427 2428 if (host->data || host->data_cmd || 2429 (host->cmd && sdhci_data_line_cmd(host->cmd))) { 2430 pr_err("%s: Timeout waiting for hardware interrupt.\n", 2431 mmc_hostname(host->mmc)); 2432 sdhci_dumpregs(host); 2433 2434 if (host->data) { 2435 host->data->error = -ETIMEDOUT; 2436 sdhci_finish_data(host); 2437 } else if (host->data_cmd) { 2438 host->data_cmd->error = -ETIMEDOUT; 2439 sdhci_finish_mrq(host, host->data_cmd->mrq); 2440 } else { 2441 host->cmd->error = -ETIMEDOUT; 2442 sdhci_finish_mrq(host, host->cmd->mrq); 2443 } 2444 } 2445 2446 mmiowb(); 2447 spin_unlock_irqrestore(&host->lock, flags); 2448 } 2449 2450 /*****************************************************************************\ 2451 * * 2452 * Interrupt handling * 2453 * * 2454 \*****************************************************************************/ 2455 2456 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2457 { 2458 if (!host->cmd) { 2459 /* 2460 * SDHCI recovers from errors by resetting the cmd and data 2461 * circuits. Until that is done, there very well might be more 2462 * interrupts, so ignore them in that case. 2463 */ 2464 if (host->pending_reset) 2465 return; 2466 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", 2467 mmc_hostname(host->mmc), (unsigned)intmask); 2468 sdhci_dumpregs(host); 2469 return; 2470 } 2471 2472 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | 2473 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { 2474 if (intmask & SDHCI_INT_TIMEOUT) 2475 host->cmd->error = -ETIMEDOUT; 2476 else 2477 host->cmd->error = -EILSEQ; 2478 2479 /* 2480 * If this command initiates a data phase and a response 2481 * CRC error is signalled, the card can start transferring 2482 * data - the card may have received the command without 2483 * error. We must not terminate the mmc_request early. 2484 * 2485 * If the card did not receive the command or returned an 2486 * error which prevented it sending data, the data phase 2487 * will time out. 2488 */ 2489 if (host->cmd->data && 2490 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == 2491 SDHCI_INT_CRC) { 2492 host->cmd = NULL; 2493 return; 2494 } 2495 2496 sdhci_finish_mrq(host, host->cmd->mrq); 2497 return; 2498 } 2499 2500 if (intmask & SDHCI_INT_RESPONSE) 2501 sdhci_finish_command(host); 2502 } 2503 2504 #ifdef CONFIG_MMC_DEBUG 2505 static void sdhci_adma_show_error(struct sdhci_host *host) 2506 { 2507 const char *name = mmc_hostname(host->mmc); 2508 void *desc = host->adma_table; 2509 2510 sdhci_dumpregs(host); 2511 2512 while (true) { 2513 struct sdhci_adma2_64_desc *dma_desc = desc; 2514 2515 if (host->flags & SDHCI_USE_64_BIT_DMA) 2516 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", 2517 name, desc, le32_to_cpu(dma_desc->addr_hi), 2518 le32_to_cpu(dma_desc->addr_lo), 2519 le16_to_cpu(dma_desc->len), 2520 le16_to_cpu(dma_desc->cmd)); 2521 else 2522 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2523 name, desc, le32_to_cpu(dma_desc->addr_lo), 2524 le16_to_cpu(dma_desc->len), 2525 le16_to_cpu(dma_desc->cmd)); 2526 2527 desc += host->desc_sz; 2528 2529 if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) 2530 break; 2531 } 2532 } 2533 #else 2534 static void sdhci_adma_show_error(struct sdhci_host *host) { } 2535 #endif 2536 2537 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2538 { 2539 u32 command; 2540 2541 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2542 if (intmask & SDHCI_INT_DATA_AVAIL) { 2543 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2544 if (command == MMC_SEND_TUNING_BLOCK || 2545 command == MMC_SEND_TUNING_BLOCK_HS200) { 2546 host->tuning_done = 1; 2547 wake_up(&host->buf_ready_int); 2548 return; 2549 } 2550 } 2551 2552 if (!host->data) { 2553 struct mmc_command *data_cmd = host->data_cmd; 2554 2555 /* 2556 * The "data complete" interrupt is also used to 2557 * indicate that a busy state has ended. See comment 2558 * above in sdhci_cmd_irq(). 2559 */ 2560 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { 2561 if (intmask & SDHCI_INT_DATA_TIMEOUT) { 2562 host->data_cmd = NULL; 2563 data_cmd->error = -ETIMEDOUT; 2564 sdhci_finish_mrq(host, data_cmd->mrq); 2565 return; 2566 } 2567 if (intmask & SDHCI_INT_DATA_END) { 2568 host->data_cmd = NULL; 2569 /* 2570 * Some cards handle busy-end interrupt 2571 * before the command completed, so make 2572 * sure we do things in the proper order. 2573 */ 2574 if (host->cmd == data_cmd) 2575 return; 2576 2577 sdhci_finish_mrq(host, data_cmd->mrq); 2578 return; 2579 } 2580 } 2581 2582 /* 2583 * SDHCI recovers from errors by resetting the cmd and data 2584 * circuits. Until that is done, there very well might be more 2585 * interrupts, so ignore them in that case. 2586 */ 2587 if (host->pending_reset) 2588 return; 2589 2590 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", 2591 mmc_hostname(host->mmc), (unsigned)intmask); 2592 sdhci_dumpregs(host); 2593 2594 return; 2595 } 2596 2597 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2598 host->data->error = -ETIMEDOUT; 2599 else if (intmask & SDHCI_INT_DATA_END_BIT) 2600 host->data->error = -EILSEQ; 2601 else if ((intmask & SDHCI_INT_DATA_CRC) && 2602 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2603 != MMC_BUS_TEST_R) 2604 host->data->error = -EILSEQ; 2605 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2606 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2607 sdhci_adma_show_error(host); 2608 host->data->error = -EIO; 2609 if (host->ops->adma_workaround) 2610 host->ops->adma_workaround(host, intmask); 2611 } 2612 2613 if (host->data->error) 2614 sdhci_finish_data(host); 2615 else { 2616 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2617 sdhci_transfer_pio(host); 2618 2619 /* 2620 * We currently don't do anything fancy with DMA 2621 * boundaries, but as we can't disable the feature 2622 * we need to at least restart the transfer. 2623 * 2624 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2625 * should return a valid address to continue from, but as 2626 * some controllers are faulty, don't trust them. 2627 */ 2628 if (intmask & SDHCI_INT_DMA_END) { 2629 u32 dmastart, dmanow; 2630 dmastart = sg_dma_address(host->data->sg); 2631 dmanow = dmastart + host->data->bytes_xfered; 2632 /* 2633 * Force update to the next DMA block boundary. 2634 */ 2635 dmanow = (dmanow & 2636 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2637 SDHCI_DEFAULT_BOUNDARY_SIZE; 2638 host->data->bytes_xfered = dmanow - dmastart; 2639 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2640 " next 0x%08x\n", 2641 mmc_hostname(host->mmc), dmastart, 2642 host->data->bytes_xfered, dmanow); 2643 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2644 } 2645 2646 if (intmask & SDHCI_INT_DATA_END) { 2647 if (host->cmd == host->data_cmd) { 2648 /* 2649 * Data managed to finish before the 2650 * command completed. Make sure we do 2651 * things in the proper order. 2652 */ 2653 host->data_early = 1; 2654 } else { 2655 sdhci_finish_data(host); 2656 } 2657 } 2658 } 2659 } 2660 2661 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2662 { 2663 irqreturn_t result = IRQ_NONE; 2664 struct sdhci_host *host = dev_id; 2665 u32 intmask, mask, unexpected = 0; 2666 int max_loops = 16; 2667 2668 spin_lock(&host->lock); 2669 2670 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { 2671 spin_unlock(&host->lock); 2672 return IRQ_NONE; 2673 } 2674 2675 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2676 if (!intmask || intmask == 0xffffffff) { 2677 result = IRQ_NONE; 2678 goto out; 2679 } 2680 2681 do { 2682 /* Clear selected interrupts. */ 2683 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2684 SDHCI_INT_BUS_POWER); 2685 sdhci_writel(host, mask, SDHCI_INT_STATUS); 2686 2687 DBG("*** %s got interrupt: 0x%08x\n", 2688 mmc_hostname(host->mmc), intmask); 2689 2690 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2691 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2692 SDHCI_CARD_PRESENT; 2693 2694 /* 2695 * There is a observation on i.mx esdhc. INSERT 2696 * bit will be immediately set again when it gets 2697 * cleared, if a card is inserted. We have to mask 2698 * the irq to prevent interrupt storm which will 2699 * freeze the system. And the REMOVE gets the 2700 * same situation. 2701 * 2702 * More testing are needed here to ensure it works 2703 * for other platforms though. 2704 */ 2705 host->ier &= ~(SDHCI_INT_CARD_INSERT | 2706 SDHCI_INT_CARD_REMOVE); 2707 host->ier |= present ? SDHCI_INT_CARD_REMOVE : 2708 SDHCI_INT_CARD_INSERT; 2709 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2710 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2711 2712 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2713 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2714 2715 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | 2716 SDHCI_INT_CARD_REMOVE); 2717 result = IRQ_WAKE_THREAD; 2718 } 2719 2720 if (intmask & SDHCI_INT_CMD_MASK) 2721 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2722 2723 if (intmask & SDHCI_INT_DATA_MASK) 2724 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2725 2726 if (intmask & SDHCI_INT_BUS_POWER) 2727 pr_err("%s: Card is consuming too much power!\n", 2728 mmc_hostname(host->mmc)); 2729 2730 if (intmask & SDHCI_INT_RETUNE) 2731 mmc_retune_needed(host->mmc); 2732 2733 if (intmask & SDHCI_INT_CARD_INT) { 2734 sdhci_enable_sdio_irq_nolock(host, false); 2735 host->thread_isr |= SDHCI_INT_CARD_INT; 2736 result = IRQ_WAKE_THREAD; 2737 } 2738 2739 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2740 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | 2741 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | 2742 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT); 2743 2744 if (intmask) { 2745 unexpected |= intmask; 2746 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2747 } 2748 2749 if (result == IRQ_NONE) 2750 result = IRQ_HANDLED; 2751 2752 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2753 } while (intmask && --max_loops); 2754 out: 2755 spin_unlock(&host->lock); 2756 2757 if (unexpected) { 2758 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2759 mmc_hostname(host->mmc), unexpected); 2760 sdhci_dumpregs(host); 2761 } 2762 2763 return result; 2764 } 2765 2766 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) 2767 { 2768 struct sdhci_host *host = dev_id; 2769 unsigned long flags; 2770 u32 isr; 2771 2772 spin_lock_irqsave(&host->lock, flags); 2773 isr = host->thread_isr; 2774 host->thread_isr = 0; 2775 spin_unlock_irqrestore(&host->lock, flags); 2776 2777 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2778 struct mmc_host *mmc = host->mmc; 2779 2780 mmc->ops->card_event(mmc); 2781 mmc_detect_change(mmc, msecs_to_jiffies(200)); 2782 } 2783 2784 if (isr & SDHCI_INT_CARD_INT) { 2785 sdio_run_irqs(host->mmc); 2786 2787 spin_lock_irqsave(&host->lock, flags); 2788 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2789 sdhci_enable_sdio_irq_nolock(host, true); 2790 spin_unlock_irqrestore(&host->lock, flags); 2791 } 2792 2793 return isr ? IRQ_HANDLED : IRQ_NONE; 2794 } 2795 2796 /*****************************************************************************\ 2797 * * 2798 * Suspend/resume * 2799 * * 2800 \*****************************************************************************/ 2801 2802 #ifdef CONFIG_PM 2803 /* 2804 * To enable wakeup events, the corresponding events have to be enabled in 2805 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal 2806 * Table' in the SD Host Controller Standard Specification. 2807 * It is useless to restore SDHCI_INT_ENABLE state in 2808 * sdhci_disable_irq_wakeups() since it will be set by 2809 * sdhci_enable_card_detection() or sdhci_init(). 2810 */ 2811 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2812 { 2813 u8 val; 2814 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2815 | SDHCI_WAKE_ON_INT; 2816 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | 2817 SDHCI_INT_CARD_INT; 2818 2819 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2820 val |= mask ; 2821 /* Avoid fake wake up */ 2822 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { 2823 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); 2824 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2825 } 2826 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2827 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); 2828 } 2829 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2830 2831 static void sdhci_disable_irq_wakeups(struct sdhci_host *host) 2832 { 2833 u8 val; 2834 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE 2835 | SDHCI_WAKE_ON_INT; 2836 2837 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2838 val &= ~mask; 2839 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2840 } 2841 2842 int sdhci_suspend_host(struct sdhci_host *host) 2843 { 2844 sdhci_disable_card_detection(host); 2845 2846 mmc_retune_timer_stop(host->mmc); 2847 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2848 mmc_retune_needed(host->mmc); 2849 2850 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2851 host->ier = 0; 2852 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 2853 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 2854 free_irq(host->irq, host); 2855 } else { 2856 sdhci_enable_irq_wakeups(host); 2857 enable_irq_wake(host->irq); 2858 } 2859 return 0; 2860 } 2861 2862 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2863 2864 int sdhci_resume_host(struct sdhci_host *host) 2865 { 2866 struct mmc_host *mmc = host->mmc; 2867 int ret = 0; 2868 2869 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2870 if (host->ops->enable_dma) 2871 host->ops->enable_dma(host); 2872 } 2873 2874 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2875 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2876 /* Card keeps power but host controller does not */ 2877 sdhci_init(host, 0); 2878 host->pwr = 0; 2879 host->clock = 0; 2880 mmc->ops->set_ios(mmc, &mmc->ios); 2881 } else { 2882 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2883 mmiowb(); 2884 } 2885 2886 if (!device_may_wakeup(mmc_dev(host->mmc))) { 2887 ret = request_threaded_irq(host->irq, sdhci_irq, 2888 sdhci_thread_irq, IRQF_SHARED, 2889 mmc_hostname(host->mmc), host); 2890 if (ret) 2891 return ret; 2892 } else { 2893 sdhci_disable_irq_wakeups(host); 2894 disable_irq_wake(host->irq); 2895 } 2896 2897 sdhci_enable_card_detection(host); 2898 2899 return ret; 2900 } 2901 2902 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2903 2904 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2905 { 2906 unsigned long flags; 2907 2908 mmc_retune_timer_stop(host->mmc); 2909 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 2910 mmc_retune_needed(host->mmc); 2911 2912 spin_lock_irqsave(&host->lock, flags); 2913 host->ier &= SDHCI_INT_CARD_INT; 2914 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 2915 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 2916 spin_unlock_irqrestore(&host->lock, flags); 2917 2918 synchronize_hardirq(host->irq); 2919 2920 spin_lock_irqsave(&host->lock, flags); 2921 host->runtime_suspended = true; 2922 spin_unlock_irqrestore(&host->lock, flags); 2923 2924 return 0; 2925 } 2926 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2927 2928 int sdhci_runtime_resume_host(struct sdhci_host *host) 2929 { 2930 struct mmc_host *mmc = host->mmc; 2931 unsigned long flags; 2932 int host_flags = host->flags; 2933 2934 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2935 if (host->ops->enable_dma) 2936 host->ops->enable_dma(host); 2937 } 2938 2939 sdhci_init(host, 0); 2940 2941 /* Force clock and power re-program */ 2942 host->pwr = 0; 2943 host->clock = 0; 2944 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); 2945 mmc->ops->set_ios(mmc, &mmc->ios); 2946 2947 if ((host_flags & SDHCI_PV_ENABLED) && 2948 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { 2949 spin_lock_irqsave(&host->lock, flags); 2950 sdhci_enable_preset_value(host, true); 2951 spin_unlock_irqrestore(&host->lock, flags); 2952 } 2953 2954 if ((mmc->caps2 & MMC_CAP2_HS400_ES) && 2955 mmc->ops->hs400_enhanced_strobe) 2956 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios); 2957 2958 spin_lock_irqsave(&host->lock, flags); 2959 2960 host->runtime_suspended = false; 2961 2962 /* Enable SDIO IRQ */ 2963 if (host->flags & SDHCI_SDIO_IRQ_ENABLED) 2964 sdhci_enable_sdio_irq_nolock(host, true); 2965 2966 /* Enable Card Detection */ 2967 sdhci_enable_card_detection(host); 2968 2969 spin_unlock_irqrestore(&host->lock, flags); 2970 2971 return 0; 2972 } 2973 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2974 2975 #endif /* CONFIG_PM */ 2976 2977 /*****************************************************************************\ 2978 * * 2979 * Device allocation/registration * 2980 * * 2981 \*****************************************************************************/ 2982 2983 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2984 size_t priv_size) 2985 { 2986 struct mmc_host *mmc; 2987 struct sdhci_host *host; 2988 2989 WARN_ON(dev == NULL); 2990 2991 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2992 if (!mmc) 2993 return ERR_PTR(-ENOMEM); 2994 2995 host = mmc_priv(mmc); 2996 host->mmc = mmc; 2997 host->mmc_host_ops = sdhci_ops; 2998 mmc->ops = &host->mmc_host_ops; 2999 3000 host->flags = SDHCI_SIGNALING_330; 3001 3002 return host; 3003 } 3004 3005 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 3006 3007 static int sdhci_set_dma_mask(struct sdhci_host *host) 3008 { 3009 struct mmc_host *mmc = host->mmc; 3010 struct device *dev = mmc_dev(mmc); 3011 int ret = -EINVAL; 3012 3013 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) 3014 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3015 3016 /* Try 64-bit mask if hardware is capable of it */ 3017 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3018 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 3019 if (ret) { 3020 pr_warn("%s: Failed to set 64-bit DMA mask.\n", 3021 mmc_hostname(mmc)); 3022 host->flags &= ~SDHCI_USE_64_BIT_DMA; 3023 } 3024 } 3025 3026 /* 32-bit mask as default & fallback */ 3027 if (ret) { 3028 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 3029 if (ret) 3030 pr_warn("%s: Failed to set 32-bit DMA mask.\n", 3031 mmc_hostname(mmc)); 3032 } 3033 3034 return ret; 3035 } 3036 3037 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) 3038 { 3039 u16 v; 3040 u64 dt_caps_mask = 0; 3041 u64 dt_caps = 0; 3042 3043 if (host->read_caps) 3044 return; 3045 3046 host->read_caps = true; 3047 3048 if (debug_quirks) 3049 host->quirks = debug_quirks; 3050 3051 if (debug_quirks2) 3052 host->quirks2 = debug_quirks2; 3053 3054 sdhci_do_reset(host, SDHCI_RESET_ALL); 3055 3056 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3057 "sdhci-caps-mask", &dt_caps_mask); 3058 of_property_read_u64(mmc_dev(host->mmc)->of_node, 3059 "sdhci-caps", &dt_caps); 3060 3061 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); 3062 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; 3063 3064 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) 3065 return; 3066 3067 if (caps) { 3068 host->caps = *caps; 3069 } else { 3070 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 3071 host->caps &= ~lower_32_bits(dt_caps_mask); 3072 host->caps |= lower_32_bits(dt_caps); 3073 } 3074 3075 if (host->version < SDHCI_SPEC_300) 3076 return; 3077 3078 if (caps1) { 3079 host->caps1 = *caps1; 3080 } else { 3081 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 3082 host->caps1 &= ~upper_32_bits(dt_caps_mask); 3083 host->caps1 |= upper_32_bits(dt_caps); 3084 } 3085 } 3086 EXPORT_SYMBOL_GPL(__sdhci_read_caps); 3087 3088 int sdhci_setup_host(struct sdhci_host *host) 3089 { 3090 struct mmc_host *mmc; 3091 u32 max_current_caps; 3092 unsigned int ocr_avail; 3093 unsigned int override_timeout_clk; 3094 u32 max_clk; 3095 int ret; 3096 3097 WARN_ON(host == NULL); 3098 if (host == NULL) 3099 return -EINVAL; 3100 3101 mmc = host->mmc; 3102 3103 /* 3104 * If there are external regulators, get them. Note this must be done 3105 * early before resetting the host and reading the capabilities so that 3106 * the host can take the appropriate action if regulators are not 3107 * available. 3108 */ 3109 ret = mmc_regulator_get_supply(mmc); 3110 if (ret == -EPROBE_DEFER) 3111 return ret; 3112 3113 sdhci_read_caps(host); 3114 3115 override_timeout_clk = host->timeout_clk; 3116 3117 if (host->version > SDHCI_SPEC_300) { 3118 pr_err("%s: Unknown controller version (%d). You may experience problems.\n", 3119 mmc_hostname(mmc), host->version); 3120 } 3121 3122 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 3123 host->flags |= SDHCI_USE_SDMA; 3124 else if (!(host->caps & SDHCI_CAN_DO_SDMA)) 3125 DBG("Controller doesn't have SDMA capability\n"); 3126 else 3127 host->flags |= SDHCI_USE_SDMA; 3128 3129 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 3130 (host->flags & SDHCI_USE_SDMA)) { 3131 DBG("Disabling DMA as it is marked broken\n"); 3132 host->flags &= ~SDHCI_USE_SDMA; 3133 } 3134 3135 if ((host->version >= SDHCI_SPEC_200) && 3136 (host->caps & SDHCI_CAN_DO_ADMA2)) 3137 host->flags |= SDHCI_USE_ADMA; 3138 3139 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 3140 (host->flags & SDHCI_USE_ADMA)) { 3141 DBG("Disabling ADMA as it is marked broken\n"); 3142 host->flags &= ~SDHCI_USE_ADMA; 3143 } 3144 3145 /* 3146 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask 3147 * and *must* do 64-bit DMA. A driver has the opportunity to change 3148 * that during the first call to ->enable_dma(). Similarly 3149 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to 3150 * implement. 3151 */ 3152 if (host->caps & SDHCI_CAN_64BIT) 3153 host->flags |= SDHCI_USE_64_BIT_DMA; 3154 3155 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 3156 ret = sdhci_set_dma_mask(host); 3157 3158 if (!ret && host->ops->enable_dma) 3159 ret = host->ops->enable_dma(host); 3160 3161 if (ret) { 3162 pr_warn("%s: No suitable DMA available - falling back to PIO\n", 3163 mmc_hostname(mmc)); 3164 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 3165 3166 ret = 0; 3167 } 3168 } 3169 3170 /* SDMA does not support 64-bit DMA */ 3171 if (host->flags & SDHCI_USE_64_BIT_DMA) 3172 host->flags &= ~SDHCI_USE_SDMA; 3173 3174 if (host->flags & SDHCI_USE_ADMA) { 3175 dma_addr_t dma; 3176 void *buf; 3177 3178 /* 3179 * The DMA descriptor table size is calculated as the maximum 3180 * number of segments times 2, to allow for an alignment 3181 * descriptor for each segment, plus 1 for a nop end descriptor, 3182 * all multipled by the descriptor size. 3183 */ 3184 if (host->flags & SDHCI_USE_64_BIT_DMA) { 3185 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3186 SDHCI_ADMA2_64_DESC_SZ; 3187 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; 3188 } else { 3189 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * 3190 SDHCI_ADMA2_32_DESC_SZ; 3191 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; 3192 } 3193 3194 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; 3195 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + 3196 host->adma_table_sz, &dma, GFP_KERNEL); 3197 if (!buf) { 3198 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", 3199 mmc_hostname(mmc)); 3200 host->flags &= ~SDHCI_USE_ADMA; 3201 } else if ((dma + host->align_buffer_sz) & 3202 (SDHCI_ADMA2_DESC_ALIGN - 1)) { 3203 pr_warn("%s: unable to allocate aligned ADMA descriptor\n", 3204 mmc_hostname(mmc)); 3205 host->flags &= ~SDHCI_USE_ADMA; 3206 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3207 host->adma_table_sz, buf, dma); 3208 } else { 3209 host->align_buffer = buf; 3210 host->align_addr = dma; 3211 3212 host->adma_table = buf + host->align_buffer_sz; 3213 host->adma_addr = dma + host->align_buffer_sz; 3214 } 3215 } 3216 3217 /* 3218 * If we use DMA, then it's up to the caller to set the DMA 3219 * mask, but PIO does not need the hw shim so we set a new 3220 * mask here in that case. 3221 */ 3222 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 3223 host->dma_mask = DMA_BIT_MASK(64); 3224 mmc_dev(mmc)->dma_mask = &host->dma_mask; 3225 } 3226 3227 if (host->version >= SDHCI_SPEC_300) 3228 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) 3229 >> SDHCI_CLOCK_BASE_SHIFT; 3230 else 3231 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) 3232 >> SDHCI_CLOCK_BASE_SHIFT; 3233 3234 host->max_clk *= 1000000; 3235 if (host->max_clk == 0 || host->quirks & 3236 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 3237 if (!host->ops->get_max_clock) { 3238 pr_err("%s: Hardware doesn't specify base clock frequency.\n", 3239 mmc_hostname(mmc)); 3240 ret = -ENODEV; 3241 goto undma; 3242 } 3243 host->max_clk = host->ops->get_max_clock(host); 3244 } 3245 3246 /* 3247 * In case of Host Controller v3.00, find out whether clock 3248 * multiplier is supported. 3249 */ 3250 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> 3251 SDHCI_CLOCK_MUL_SHIFT; 3252 3253 /* 3254 * In case the value in Clock Multiplier is 0, then programmable 3255 * clock mode is not supported, otherwise the actual clock 3256 * multiplier is one more than the value of Clock Multiplier 3257 * in the Capabilities Register. 3258 */ 3259 if (host->clk_mul) 3260 host->clk_mul += 1; 3261 3262 /* 3263 * Set host parameters. 3264 */ 3265 max_clk = host->max_clk; 3266 3267 if (host->ops->get_min_clock) 3268 mmc->f_min = host->ops->get_min_clock(host); 3269 else if (host->version >= SDHCI_SPEC_300) { 3270 if (host->clk_mul) { 3271 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 3272 max_clk = host->max_clk * host->clk_mul; 3273 } else 3274 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 3275 } else 3276 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 3277 3278 if (!mmc->f_max || mmc->f_max > max_clk) 3279 mmc->f_max = max_clk; 3280 3281 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 3282 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> 3283 SDHCI_TIMEOUT_CLK_SHIFT; 3284 if (host->timeout_clk == 0) { 3285 if (host->ops->get_timeout_clock) { 3286 host->timeout_clk = 3287 host->ops->get_timeout_clock(host); 3288 } else { 3289 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", 3290 mmc_hostname(mmc)); 3291 ret = -ENODEV; 3292 goto undma; 3293 } 3294 } 3295 3296 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) 3297 host->timeout_clk *= 1000; 3298 3299 if (override_timeout_clk) 3300 host->timeout_clk = override_timeout_clk; 3301 3302 mmc->max_busy_timeout = host->ops->get_max_timeout_count ? 3303 host->ops->get_max_timeout_count(host) : 1 << 27; 3304 mmc->max_busy_timeout /= host->timeout_clk; 3305 } 3306 3307 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 3308 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 3309 3310 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 3311 host->flags |= SDHCI_AUTO_CMD12; 3312 3313 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 3314 if ((host->version >= SDHCI_SPEC_300) && 3315 ((host->flags & SDHCI_USE_ADMA) || 3316 !(host->flags & SDHCI_USE_SDMA)) && 3317 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { 3318 host->flags |= SDHCI_AUTO_CMD23; 3319 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 3320 } else { 3321 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 3322 } 3323 3324 /* 3325 * A controller may support 8-bit width, but the board itself 3326 * might not have the pins brought out. Boards that support 3327 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 3328 * their platform code before calling sdhci_add_host(), and we 3329 * won't assume 8-bit width for hosts without that CAP. 3330 */ 3331 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 3332 mmc->caps |= MMC_CAP_4_BIT_DATA; 3333 3334 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 3335 mmc->caps &= ~MMC_CAP_CMD23; 3336 3337 if (host->caps & SDHCI_CAN_DO_HISPD) 3338 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 3339 3340 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 3341 mmc_card_is_removable(mmc) && 3342 mmc_gpio_get_cd(host->mmc) < 0) 3343 mmc->caps |= MMC_CAP_NEEDS_POLL; 3344 3345 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 3346 if (!IS_ERR(mmc->supply.vqmmc)) { 3347 ret = regulator_enable(mmc->supply.vqmmc); 3348 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, 3349 1950000)) 3350 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | 3351 SDHCI_SUPPORT_SDR50 | 3352 SDHCI_SUPPORT_DDR50); 3353 if (ret) { 3354 pr_warn("%s: Failed to enable vqmmc regulator: %d\n", 3355 mmc_hostname(mmc), ret); 3356 mmc->supply.vqmmc = ERR_PTR(-EINVAL); 3357 } 3358 } 3359 3360 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { 3361 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3362 SDHCI_SUPPORT_DDR50); 3363 } 3364 3365 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 3366 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 3367 SDHCI_SUPPORT_DDR50)) 3368 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 3369 3370 /* SDR104 supports also implies SDR50 support */ 3371 if (host->caps1 & SDHCI_SUPPORT_SDR104) { 3372 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 3373 /* SD3.0: SDR104 is supported so (for eMMC) the caps2 3374 * field can be promoted to support HS200. 3375 */ 3376 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) 3377 mmc->caps2 |= MMC_CAP2_HS200; 3378 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { 3379 mmc->caps |= MMC_CAP_UHS_SDR50; 3380 } 3381 3382 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && 3383 (host->caps1 & SDHCI_SUPPORT_HS400)) 3384 mmc->caps2 |= MMC_CAP2_HS400; 3385 3386 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && 3387 (IS_ERR(mmc->supply.vqmmc) || 3388 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 3389 1300000))) 3390 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; 3391 3392 if ((host->caps1 & SDHCI_SUPPORT_DDR50) && 3393 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) 3394 mmc->caps |= MMC_CAP_UHS_DDR50; 3395 3396 /* Does the host need tuning for SDR50? */ 3397 if (host->caps1 & SDHCI_USE_SDR50_TUNING) 3398 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 3399 3400 /* Driver Type(s) (A, C, D) supported by the host */ 3401 if (host->caps1 & SDHCI_DRIVER_TYPE_A) 3402 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 3403 if (host->caps1 & SDHCI_DRIVER_TYPE_C) 3404 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 3405 if (host->caps1 & SDHCI_DRIVER_TYPE_D) 3406 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 3407 3408 /* Initial value for re-tuning timer count */ 3409 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 3410 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 3411 3412 /* 3413 * In case Re-tuning Timer is not disabled, the actual value of 3414 * re-tuning timer will be 2 ^ (n - 1). 3415 */ 3416 if (host->tuning_count) 3417 host->tuning_count = 1 << (host->tuning_count - 1); 3418 3419 /* Re-tuning mode supported by the Host Controller */ 3420 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> 3421 SDHCI_RETUNING_MODE_SHIFT; 3422 3423 ocr_avail = 0; 3424 3425 /* 3426 * According to SD Host Controller spec v3.00, if the Host System 3427 * can afford more than 150mA, Host Driver should set XPC to 1. Also 3428 * the value is meaningful only if Voltage Support in the Capabilities 3429 * register is set. The actual current value is 4 times the register 3430 * value. 3431 */ 3432 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 3433 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { 3434 int curr = regulator_get_current_limit(mmc->supply.vmmc); 3435 if (curr > 0) { 3436 3437 /* convert to SDHCI_MAX_CURRENT format */ 3438 curr = curr/1000; /* convert to mA */ 3439 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 3440 3441 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 3442 max_current_caps = 3443 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 3444 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 3445 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 3446 } 3447 } 3448 3449 if (host->caps & SDHCI_CAN_VDD_330) { 3450 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 3451 3452 mmc->max_current_330 = ((max_current_caps & 3453 SDHCI_MAX_CURRENT_330_MASK) >> 3454 SDHCI_MAX_CURRENT_330_SHIFT) * 3455 SDHCI_MAX_CURRENT_MULTIPLIER; 3456 } 3457 if (host->caps & SDHCI_CAN_VDD_300) { 3458 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 3459 3460 mmc->max_current_300 = ((max_current_caps & 3461 SDHCI_MAX_CURRENT_300_MASK) >> 3462 SDHCI_MAX_CURRENT_300_SHIFT) * 3463 SDHCI_MAX_CURRENT_MULTIPLIER; 3464 } 3465 if (host->caps & SDHCI_CAN_VDD_180) { 3466 ocr_avail |= MMC_VDD_165_195; 3467 3468 mmc->max_current_180 = ((max_current_caps & 3469 SDHCI_MAX_CURRENT_180_MASK) >> 3470 SDHCI_MAX_CURRENT_180_SHIFT) * 3471 SDHCI_MAX_CURRENT_MULTIPLIER; 3472 } 3473 3474 /* If OCR set by host, use it instead. */ 3475 if (host->ocr_mask) 3476 ocr_avail = host->ocr_mask; 3477 3478 /* If OCR set by external regulators, give it highest prio. */ 3479 if (mmc->ocr_avail) 3480 ocr_avail = mmc->ocr_avail; 3481 3482 mmc->ocr_avail = ocr_avail; 3483 mmc->ocr_avail_sdio = ocr_avail; 3484 if (host->ocr_avail_sdio) 3485 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3486 mmc->ocr_avail_sd = ocr_avail; 3487 if (host->ocr_avail_sd) 3488 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3489 else /* normal SD controllers don't support 1.8V */ 3490 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3491 mmc->ocr_avail_mmc = ocr_avail; 3492 if (host->ocr_avail_mmc) 3493 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3494 3495 if (mmc->ocr_avail == 0) { 3496 pr_err("%s: Hardware doesn't report any support voltages.\n", 3497 mmc_hostname(mmc)); 3498 ret = -ENODEV; 3499 goto unreg; 3500 } 3501 3502 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | 3503 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | 3504 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || 3505 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) 3506 host->flags |= SDHCI_SIGNALING_180; 3507 3508 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) 3509 host->flags |= SDHCI_SIGNALING_120; 3510 3511 spin_lock_init(&host->lock); 3512 3513 /* 3514 * Maximum number of segments. Depends on if the hardware 3515 * can do scatter/gather or not. 3516 */ 3517 if (host->flags & SDHCI_USE_ADMA) 3518 mmc->max_segs = SDHCI_MAX_SEGS; 3519 else if (host->flags & SDHCI_USE_SDMA) 3520 mmc->max_segs = 1; 3521 else /* PIO */ 3522 mmc->max_segs = SDHCI_MAX_SEGS; 3523 3524 /* 3525 * Maximum number of sectors in one transfer. Limited by SDMA boundary 3526 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this 3527 * is less anyway. 3528 */ 3529 mmc->max_req_size = 524288; 3530 3531 /* 3532 * Maximum segment size. Could be one segment with the maximum number 3533 * of bytes. When doing hardware scatter/gather, each entry cannot 3534 * be larger than 64 KiB though. 3535 */ 3536 if (host->flags & SDHCI_USE_ADMA) { 3537 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3538 mmc->max_seg_size = 65535; 3539 else 3540 mmc->max_seg_size = 65536; 3541 } else { 3542 mmc->max_seg_size = mmc->max_req_size; 3543 } 3544 3545 /* 3546 * Maximum block size. This varies from controller to controller and 3547 * is specified in the capabilities register. 3548 */ 3549 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3550 mmc->max_blk_size = 2; 3551 } else { 3552 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> 3553 SDHCI_MAX_BLOCK_SHIFT; 3554 if (mmc->max_blk_size >= 3) { 3555 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", 3556 mmc_hostname(mmc)); 3557 mmc->max_blk_size = 0; 3558 } 3559 } 3560 3561 mmc->max_blk_size = 512 << mmc->max_blk_size; 3562 3563 /* 3564 * Maximum block count. 3565 */ 3566 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3567 3568 return 0; 3569 3570 unreg: 3571 if (!IS_ERR(mmc->supply.vqmmc)) 3572 regulator_disable(mmc->supply.vqmmc); 3573 undma: 3574 if (host->align_buffer) 3575 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3576 host->adma_table_sz, host->align_buffer, 3577 host->align_addr); 3578 host->adma_table = NULL; 3579 host->align_buffer = NULL; 3580 3581 return ret; 3582 } 3583 EXPORT_SYMBOL_GPL(sdhci_setup_host); 3584 3585 int __sdhci_add_host(struct sdhci_host *host) 3586 { 3587 struct mmc_host *mmc = host->mmc; 3588 int ret; 3589 3590 /* 3591 * Init tasklets. 3592 */ 3593 tasklet_init(&host->finish_tasklet, 3594 sdhci_tasklet_finish, (unsigned long)host); 3595 3596 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3597 setup_timer(&host->data_timer, sdhci_timeout_data_timer, 3598 (unsigned long)host); 3599 3600 init_waitqueue_head(&host->buf_ready_int); 3601 3602 sdhci_init(host, 0); 3603 3604 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, 3605 IRQF_SHARED, mmc_hostname(mmc), host); 3606 if (ret) { 3607 pr_err("%s: Failed to request IRQ %d: %d\n", 3608 mmc_hostname(mmc), host->irq, ret); 3609 goto untasklet; 3610 } 3611 3612 #ifdef CONFIG_MMC_DEBUG 3613 sdhci_dumpregs(host); 3614 #endif 3615 3616 ret = sdhci_led_register(host); 3617 if (ret) { 3618 pr_err("%s: Failed to register LED device: %d\n", 3619 mmc_hostname(mmc), ret); 3620 goto unirq; 3621 } 3622 3623 mmiowb(); 3624 3625 ret = mmc_add_host(mmc); 3626 if (ret) 3627 goto unled; 3628 3629 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3630 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3631 (host->flags & SDHCI_USE_ADMA) ? 3632 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : 3633 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3634 3635 sdhci_enable_card_detection(host); 3636 3637 return 0; 3638 3639 unled: 3640 sdhci_led_unregister(host); 3641 unirq: 3642 sdhci_do_reset(host, SDHCI_RESET_ALL); 3643 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3644 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3645 free_irq(host->irq, host); 3646 untasklet: 3647 tasklet_kill(&host->finish_tasklet); 3648 3649 if (!IS_ERR(mmc->supply.vqmmc)) 3650 regulator_disable(mmc->supply.vqmmc); 3651 3652 if (host->align_buffer) 3653 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3654 host->adma_table_sz, host->align_buffer, 3655 host->align_addr); 3656 host->adma_table = NULL; 3657 host->align_buffer = NULL; 3658 3659 return ret; 3660 } 3661 EXPORT_SYMBOL_GPL(__sdhci_add_host); 3662 3663 int sdhci_add_host(struct sdhci_host *host) 3664 { 3665 int ret; 3666 3667 ret = sdhci_setup_host(host); 3668 if (ret) 3669 return ret; 3670 3671 return __sdhci_add_host(host); 3672 } 3673 EXPORT_SYMBOL_GPL(sdhci_add_host); 3674 3675 void sdhci_remove_host(struct sdhci_host *host, int dead) 3676 { 3677 struct mmc_host *mmc = host->mmc; 3678 unsigned long flags; 3679 3680 if (dead) { 3681 spin_lock_irqsave(&host->lock, flags); 3682 3683 host->flags |= SDHCI_DEVICE_DEAD; 3684 3685 if (sdhci_has_requests(host)) { 3686 pr_err("%s: Controller removed during " 3687 " transfer!\n", mmc_hostname(mmc)); 3688 sdhci_error_out_mrqs(host, -ENOMEDIUM); 3689 } 3690 3691 spin_unlock_irqrestore(&host->lock, flags); 3692 } 3693 3694 sdhci_disable_card_detection(host); 3695 3696 mmc_remove_host(mmc); 3697 3698 sdhci_led_unregister(host); 3699 3700 if (!dead) 3701 sdhci_do_reset(host, SDHCI_RESET_ALL); 3702 3703 sdhci_writel(host, 0, SDHCI_INT_ENABLE); 3704 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 3705 free_irq(host->irq, host); 3706 3707 del_timer_sync(&host->timer); 3708 del_timer_sync(&host->data_timer); 3709 3710 tasklet_kill(&host->finish_tasklet); 3711 3712 if (!IS_ERR(mmc->supply.vqmmc)) 3713 regulator_disable(mmc->supply.vqmmc); 3714 3715 if (host->align_buffer) 3716 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + 3717 host->adma_table_sz, host->align_buffer, 3718 host->align_addr); 3719 3720 host->adma_table = NULL; 3721 host->align_buffer = NULL; 3722 } 3723 3724 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3725 3726 void sdhci_free_host(struct sdhci_host *host) 3727 { 3728 mmc_free_host(host->mmc); 3729 } 3730 3731 EXPORT_SYMBOL_GPL(sdhci_free_host); 3732 3733 /*****************************************************************************\ 3734 * * 3735 * Driver init/exit * 3736 * * 3737 \*****************************************************************************/ 3738 3739 static int __init sdhci_drv_init(void) 3740 { 3741 pr_info(DRIVER_NAME 3742 ": Secure Digital Host Controller Interface driver\n"); 3743 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3744 3745 return 0; 3746 } 3747 3748 static void __exit sdhci_drv_exit(void) 3749 { 3750 } 3751 3752 module_init(sdhci_drv_init); 3753 module_exit(sdhci_drv_exit); 3754 3755 module_param(debug_quirks, uint, 0444); 3756 module_param(debug_quirks2, uint, 0444); 3757 3758 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3759 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3760 MODULE_LICENSE("GPL"); 3761 3762 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3763 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3764