1 /* 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 * 11 * Thanks to the following companies for their support: 12 * 13 * - JMicron (hardware and technical support) 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/slab.h> 22 #include <linux/scatterlist.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/pm_runtime.h> 25 26 #include <linux/leds.h> 27 28 #include <linux/mmc/mmc.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/slot-gpio.h> 32 33 #include "sdhci.h" 34 35 #define DRIVER_NAME "sdhci" 36 37 #define DBG(f, x...) \ 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) 39 40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ 41 defined(CONFIG_MMC_SDHCI_MODULE)) 42 #define SDHCI_USE_LEDS_CLASS 43 #endif 44 45 #define MAX_TUNING_LOOP 40 46 47 static unsigned int debug_quirks = 0; 48 static unsigned int debug_quirks2; 49 50 static void sdhci_finish_data(struct sdhci_host *); 51 52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); 53 static void sdhci_finish_command(struct sdhci_host *); 54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); 55 static void sdhci_tuning_timer(unsigned long data); 56 57 #ifdef CONFIG_PM_RUNTIME 58 static int sdhci_runtime_pm_get(struct sdhci_host *host); 59 static int sdhci_runtime_pm_put(struct sdhci_host *host); 60 #else 61 static inline int sdhci_runtime_pm_get(struct sdhci_host *host) 62 { 63 return 0; 64 } 65 static inline int sdhci_runtime_pm_put(struct sdhci_host *host) 66 { 67 return 0; 68 } 69 #endif 70 71 static void sdhci_dumpregs(struct sdhci_host *host) 72 { 73 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", 74 mmc_hostname(host->mmc)); 75 76 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", 77 sdhci_readl(host, SDHCI_DMA_ADDRESS), 78 sdhci_readw(host, SDHCI_HOST_VERSION)); 79 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", 80 sdhci_readw(host, SDHCI_BLOCK_SIZE), 81 sdhci_readw(host, SDHCI_BLOCK_COUNT)); 82 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", 83 sdhci_readl(host, SDHCI_ARGUMENT), 84 sdhci_readw(host, SDHCI_TRANSFER_MODE)); 85 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", 86 sdhci_readl(host, SDHCI_PRESENT_STATE), 87 sdhci_readb(host, SDHCI_HOST_CONTROL)); 88 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", 89 sdhci_readb(host, SDHCI_POWER_CONTROL), 90 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); 91 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", 92 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), 93 sdhci_readw(host, SDHCI_CLOCK_CONTROL)); 94 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", 95 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), 96 sdhci_readl(host, SDHCI_INT_STATUS)); 97 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", 98 sdhci_readl(host, SDHCI_INT_ENABLE), 99 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); 100 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", 101 sdhci_readw(host, SDHCI_ACMD12_ERR), 102 sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); 103 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", 104 sdhci_readl(host, SDHCI_CAPABILITIES), 105 sdhci_readl(host, SDHCI_CAPABILITIES_1)); 106 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", 107 sdhci_readw(host, SDHCI_COMMAND), 108 sdhci_readl(host, SDHCI_MAX_CURRENT)); 109 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", 110 sdhci_readw(host, SDHCI_HOST_CONTROL2)); 111 112 if (host->flags & SDHCI_USE_ADMA) 113 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", 114 readl(host->ioaddr + SDHCI_ADMA_ERROR), 115 readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); 116 117 pr_debug(DRIVER_NAME ": ===========================================\n"); 118 } 119 120 /*****************************************************************************\ 121 * * 122 * Low level functions * 123 * * 124 \*****************************************************************************/ 125 126 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) 127 { 128 u32 ier; 129 130 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 131 ier &= ~clear; 132 ier |= set; 133 sdhci_writel(host, ier, SDHCI_INT_ENABLE); 134 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); 135 } 136 137 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) 138 { 139 sdhci_clear_set_irqs(host, 0, irqs); 140 } 141 142 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) 143 { 144 sdhci_clear_set_irqs(host, irqs, 0); 145 } 146 147 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) 148 { 149 u32 present, irqs; 150 151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || 152 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 153 return; 154 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 156 SDHCI_CARD_PRESENT; 157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; 158 159 if (enable) 160 sdhci_unmask_irqs(host, irqs); 161 else 162 sdhci_mask_irqs(host, irqs); 163 } 164 165 static void sdhci_enable_card_detection(struct sdhci_host *host) 166 { 167 sdhci_set_card_detection(host, true); 168 } 169 170 static void sdhci_disable_card_detection(struct sdhci_host *host) 171 { 172 sdhci_set_card_detection(host, false); 173 } 174 175 static void sdhci_reset(struct sdhci_host *host, u8 mask) 176 { 177 unsigned long timeout; 178 u32 uninitialized_var(ier); 179 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & 182 SDHCI_CARD_PRESENT)) 183 return; 184 } 185 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 187 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 188 189 if (host->ops->platform_reset_enter) 190 host->ops->platform_reset_enter(host, mask); 191 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 193 194 if (mask & SDHCI_RESET_ALL) 195 host->clock = 0; 196 197 /* Wait max 100 ms */ 198 timeout = 100; 199 200 /* hw clears the bit when it's done */ 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 202 if (timeout == 0) { 203 pr_err("%s: Reset 0x%x never completed.\n", 204 mmc_hostname(host->mmc), (int)mask); 205 sdhci_dumpregs(host); 206 return; 207 } 208 timeout--; 209 mdelay(1); 210 } 211 212 if (host->ops->platform_reset_exit) 213 host->ops->platform_reset_exit(host, mask); 214 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) 216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); 217 218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 219 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) 220 host->ops->enable_dma(host); 221 } 222 } 223 224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); 225 226 static void sdhci_init(struct sdhci_host *host, int soft) 227 { 228 if (soft) 229 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); 230 else 231 sdhci_reset(host, SDHCI_RESET_ALL); 232 233 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, 234 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | 235 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | 236 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | 237 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); 238 239 if (soft) { 240 /* force clock reconfiguration */ 241 host->clock = 0; 242 sdhci_set_ios(host->mmc, &host->mmc->ios); 243 } 244 } 245 246 static void sdhci_reinit(struct sdhci_host *host) 247 { 248 sdhci_init(host, 0); 249 /* 250 * Retuning stuffs are affected by different cards inserted and only 251 * applicable to UHS-I cards. So reset these fields to their initial 252 * value when card is removed. 253 */ 254 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 255 host->flags &= ~SDHCI_USING_RETUNING_TIMER; 256 257 del_timer_sync(&host->tuning_timer); 258 host->flags &= ~SDHCI_NEEDS_RETUNING; 259 host->mmc->max_blk_count = 260 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 261 } 262 sdhci_enable_card_detection(host); 263 } 264 265 static void sdhci_activate_led(struct sdhci_host *host) 266 { 267 u8 ctrl; 268 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 270 ctrl |= SDHCI_CTRL_LED; 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 272 } 273 274 static void sdhci_deactivate_led(struct sdhci_host *host) 275 { 276 u8 ctrl; 277 278 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 279 ctrl &= ~SDHCI_CTRL_LED; 280 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 281 } 282 283 #ifdef SDHCI_USE_LEDS_CLASS 284 static void sdhci_led_control(struct led_classdev *led, 285 enum led_brightness brightness) 286 { 287 struct sdhci_host *host = container_of(led, struct sdhci_host, led); 288 unsigned long flags; 289 290 spin_lock_irqsave(&host->lock, flags); 291 292 if (host->runtime_suspended) 293 goto out; 294 295 if (brightness == LED_OFF) 296 sdhci_deactivate_led(host); 297 else 298 sdhci_activate_led(host); 299 out: 300 spin_unlock_irqrestore(&host->lock, flags); 301 } 302 #endif 303 304 /*****************************************************************************\ 305 * * 306 * Core functions * 307 * * 308 \*****************************************************************************/ 309 310 static void sdhci_read_block_pio(struct sdhci_host *host) 311 { 312 unsigned long flags; 313 size_t blksize, len, chunk; 314 u32 uninitialized_var(scratch); 315 u8 *buf; 316 317 DBG("PIO reading\n"); 318 319 blksize = host->data->blksz; 320 chunk = 0; 321 322 local_irq_save(flags); 323 324 while (blksize) { 325 if (!sg_miter_next(&host->sg_miter)) 326 BUG(); 327 328 len = min(host->sg_miter.length, blksize); 329 330 blksize -= len; 331 host->sg_miter.consumed = len; 332 333 buf = host->sg_miter.addr; 334 335 while (len) { 336 if (chunk == 0) { 337 scratch = sdhci_readl(host, SDHCI_BUFFER); 338 chunk = 4; 339 } 340 341 *buf = scratch & 0xFF; 342 343 buf++; 344 scratch >>= 8; 345 chunk--; 346 len--; 347 } 348 } 349 350 sg_miter_stop(&host->sg_miter); 351 352 local_irq_restore(flags); 353 } 354 355 static void sdhci_write_block_pio(struct sdhci_host *host) 356 { 357 unsigned long flags; 358 size_t blksize, len, chunk; 359 u32 scratch; 360 u8 *buf; 361 362 DBG("PIO writing\n"); 363 364 blksize = host->data->blksz; 365 chunk = 0; 366 scratch = 0; 367 368 local_irq_save(flags); 369 370 while (blksize) { 371 if (!sg_miter_next(&host->sg_miter)) 372 BUG(); 373 374 len = min(host->sg_miter.length, blksize); 375 376 blksize -= len; 377 host->sg_miter.consumed = len; 378 379 buf = host->sg_miter.addr; 380 381 while (len) { 382 scratch |= (u32)*buf << (chunk * 8); 383 384 buf++; 385 chunk++; 386 len--; 387 388 if ((chunk == 4) || ((len == 0) && (blksize == 0))) { 389 sdhci_writel(host, scratch, SDHCI_BUFFER); 390 chunk = 0; 391 scratch = 0; 392 } 393 } 394 } 395 396 sg_miter_stop(&host->sg_miter); 397 398 local_irq_restore(flags); 399 } 400 401 static void sdhci_transfer_pio(struct sdhci_host *host) 402 { 403 u32 mask; 404 405 BUG_ON(!host->data); 406 407 if (host->blocks == 0) 408 return; 409 410 if (host->data->flags & MMC_DATA_READ) 411 mask = SDHCI_DATA_AVAILABLE; 412 else 413 mask = SDHCI_SPACE_AVAILABLE; 414 415 /* 416 * Some controllers (JMicron JMB38x) mess up the buffer bits 417 * for transfers < 4 bytes. As long as it is just one block, 418 * we can ignore the bits. 419 */ 420 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && 421 (host->data->blocks == 1)) 422 mask = ~0; 423 424 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 425 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) 426 udelay(100); 427 428 if (host->data->flags & MMC_DATA_READ) 429 sdhci_read_block_pio(host); 430 else 431 sdhci_write_block_pio(host); 432 433 host->blocks--; 434 if (host->blocks == 0) 435 break; 436 } 437 438 DBG("PIO transfer complete.\n"); 439 } 440 441 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 442 { 443 local_irq_save(*flags); 444 return kmap_atomic(sg_page(sg)) + sg->offset; 445 } 446 447 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) 448 { 449 kunmap_atomic(buffer); 450 local_irq_restore(*flags); 451 } 452 453 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) 454 { 455 __le32 *dataddr = (__le32 __force *)(desc + 4); 456 __le16 *cmdlen = (__le16 __force *)desc; 457 458 /* SDHCI specification says ADMA descriptors should be 4 byte 459 * aligned, so using 16 or 32bit operations should be safe. */ 460 461 cmdlen[0] = cpu_to_le16(cmd); 462 cmdlen[1] = cpu_to_le16(len); 463 464 dataddr[0] = cpu_to_le32(addr); 465 } 466 467 static int sdhci_adma_table_pre(struct sdhci_host *host, 468 struct mmc_data *data) 469 { 470 int direction; 471 472 u8 *desc; 473 u8 *align; 474 dma_addr_t addr; 475 dma_addr_t align_addr; 476 int len, offset; 477 478 struct scatterlist *sg; 479 int i; 480 char *buffer; 481 unsigned long flags; 482 483 /* 484 * The spec does not specify endianness of descriptor table. 485 * We currently guess that it is LE. 486 */ 487 488 if (data->flags & MMC_DATA_READ) 489 direction = DMA_FROM_DEVICE; 490 else 491 direction = DMA_TO_DEVICE; 492 493 /* 494 * The ADMA descriptor table is mapped further down as we 495 * need to fill it with data first. 496 */ 497 498 host->align_addr = dma_map_single(mmc_dev(host->mmc), 499 host->align_buffer, 128 * 4, direction); 500 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) 501 goto fail; 502 BUG_ON(host->align_addr & 0x3); 503 504 host->sg_count = dma_map_sg(mmc_dev(host->mmc), 505 data->sg, data->sg_len, direction); 506 if (host->sg_count == 0) 507 goto unmap_align; 508 509 desc = host->adma_desc; 510 align = host->align_buffer; 511 512 align_addr = host->align_addr; 513 514 for_each_sg(data->sg, sg, host->sg_count, i) { 515 addr = sg_dma_address(sg); 516 len = sg_dma_len(sg); 517 518 /* 519 * The SDHCI specification states that ADMA 520 * addresses must be 32-bit aligned. If they 521 * aren't, then we use a bounce buffer for 522 * the (up to three) bytes that screw up the 523 * alignment. 524 */ 525 offset = (4 - (addr & 0x3)) & 0x3; 526 if (offset) { 527 if (data->flags & MMC_DATA_WRITE) { 528 buffer = sdhci_kmap_atomic(sg, &flags); 529 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 530 memcpy(align, buffer, offset); 531 sdhci_kunmap_atomic(buffer, &flags); 532 } 533 534 /* tran, valid */ 535 sdhci_set_adma_desc(desc, align_addr, offset, 0x21); 536 537 BUG_ON(offset > 65536); 538 539 align += 4; 540 align_addr += 4; 541 542 desc += 8; 543 544 addr += offset; 545 len -= offset; 546 } 547 548 BUG_ON(len > 65536); 549 550 /* tran, valid */ 551 sdhci_set_adma_desc(desc, addr, len, 0x21); 552 desc += 8; 553 554 /* 555 * If this triggers then we have a calculation bug 556 * somewhere. :/ 557 */ 558 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); 559 } 560 561 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { 562 /* 563 * Mark the last descriptor as the terminating descriptor 564 */ 565 if (desc != host->adma_desc) { 566 desc -= 8; 567 desc[0] |= 0x2; /* end */ 568 } 569 } else { 570 /* 571 * Add a terminating entry. 572 */ 573 574 /* nop, end, valid */ 575 sdhci_set_adma_desc(desc, 0, 0, 0x3); 576 } 577 578 /* 579 * Resync align buffer as we might have changed it. 580 */ 581 if (data->flags & MMC_DATA_WRITE) { 582 dma_sync_single_for_device(mmc_dev(host->mmc), 583 host->align_addr, 128 * 4, direction); 584 } 585 586 host->adma_addr = dma_map_single(mmc_dev(host->mmc), 587 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); 588 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) 589 goto unmap_entries; 590 BUG_ON(host->adma_addr & 0x3); 591 592 return 0; 593 594 unmap_entries: 595 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 596 data->sg_len, direction); 597 unmap_align: 598 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 599 128 * 4, direction); 600 fail: 601 return -EINVAL; 602 } 603 604 static void sdhci_adma_table_post(struct sdhci_host *host, 605 struct mmc_data *data) 606 { 607 int direction; 608 609 struct scatterlist *sg; 610 int i, size; 611 u8 *align; 612 char *buffer; 613 unsigned long flags; 614 615 if (data->flags & MMC_DATA_READ) 616 direction = DMA_FROM_DEVICE; 617 else 618 direction = DMA_TO_DEVICE; 619 620 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, 621 (128 * 2 + 1) * 4, DMA_TO_DEVICE); 622 623 dma_unmap_single(mmc_dev(host->mmc), host->align_addr, 624 128 * 4, direction); 625 626 if (data->flags & MMC_DATA_READ) { 627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, 628 data->sg_len, direction); 629 630 align = host->align_buffer; 631 632 for_each_sg(data->sg, sg, host->sg_count, i) { 633 if (sg_dma_address(sg) & 0x3) { 634 size = 4 - (sg_dma_address(sg) & 0x3); 635 636 buffer = sdhci_kmap_atomic(sg, &flags); 637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); 638 memcpy(buffer, align, size); 639 sdhci_kunmap_atomic(buffer, &flags); 640 641 align += 4; 642 } 643 } 644 } 645 646 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 647 data->sg_len, direction); 648 } 649 650 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) 651 { 652 u8 count; 653 struct mmc_data *data = cmd->data; 654 unsigned target_timeout, current_timeout; 655 656 /* 657 * If the host controller provides us with an incorrect timeout 658 * value, just skip the check and use 0xE. The hardware may take 659 * longer to time out, but that's much better than having a too-short 660 * timeout value. 661 */ 662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) 663 return 0xE; 664 665 /* Unspecified timeout, assume max */ 666 if (!data && !cmd->cmd_timeout_ms) 667 return 0xE; 668 669 /* timeout in us */ 670 if (!data) 671 target_timeout = cmd->cmd_timeout_ms * 1000; 672 else { 673 target_timeout = data->timeout_ns / 1000; 674 if (host->clock) 675 target_timeout += data->timeout_clks / host->clock; 676 } 677 678 /* 679 * Figure out needed cycles. 680 * We do this in steps in order to fit inside a 32 bit int. 681 * The first step is the minimum timeout, which will have a 682 * minimum resolution of 6 bits: 683 * (1) 2^13*1000 > 2^22, 684 * (2) host->timeout_clk < 2^16 685 * => 686 * (1) / (2) > 2^6 687 */ 688 count = 0; 689 current_timeout = (1 << 13) * 1000 / host->timeout_clk; 690 while (current_timeout < target_timeout) { 691 count++; 692 current_timeout <<= 1; 693 if (count >= 0xF) 694 break; 695 } 696 697 if (count >= 0xF) { 698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", 699 mmc_hostname(host->mmc), count, cmd->opcode); 700 count = 0xE; 701 } 702 703 return count; 704 } 705 706 static void sdhci_set_transfer_irqs(struct sdhci_host *host) 707 { 708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; 709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; 710 711 if (host->flags & SDHCI_REQ_USE_DMA) 712 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); 713 else 714 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); 715 } 716 717 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) 718 { 719 u8 count; 720 u8 ctrl; 721 struct mmc_data *data = cmd->data; 722 int ret; 723 724 WARN_ON(host->data); 725 726 if (data || (cmd->flags & MMC_RSP_BUSY)) { 727 count = sdhci_calc_timeout(host, cmd); 728 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); 729 } 730 731 if (!data) 732 return; 733 734 /* Sanity checks */ 735 BUG_ON(data->blksz * data->blocks > 524288); 736 BUG_ON(data->blksz > host->mmc->max_blk_size); 737 BUG_ON(data->blocks > 65535); 738 739 host->data = data; 740 host->data_early = 0; 741 host->data->bytes_xfered = 0; 742 743 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) 744 host->flags |= SDHCI_REQ_USE_DMA; 745 746 /* 747 * FIXME: This doesn't account for merging when mapping the 748 * scatterlist. 749 */ 750 if (host->flags & SDHCI_REQ_USE_DMA) { 751 int broken, i; 752 struct scatterlist *sg; 753 754 broken = 0; 755 if (host->flags & SDHCI_USE_ADMA) { 756 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 757 broken = 1; 758 } else { 759 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) 760 broken = 1; 761 } 762 763 if (unlikely(broken)) { 764 for_each_sg(data->sg, sg, data->sg_len, i) { 765 if (sg->length & 0x3) { 766 DBG("Reverting to PIO because of " 767 "transfer size (%d)\n", 768 sg->length); 769 host->flags &= ~SDHCI_REQ_USE_DMA; 770 break; 771 } 772 } 773 } 774 } 775 776 /* 777 * The assumption here being that alignment is the same after 778 * translation to device address space. 779 */ 780 if (host->flags & SDHCI_REQ_USE_DMA) { 781 int broken, i; 782 struct scatterlist *sg; 783 784 broken = 0; 785 if (host->flags & SDHCI_USE_ADMA) { 786 /* 787 * As we use 3 byte chunks to work around 788 * alignment problems, we need to check this 789 * quirk. 790 */ 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) 792 broken = 1; 793 } else { 794 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) 795 broken = 1; 796 } 797 798 if (unlikely(broken)) { 799 for_each_sg(data->sg, sg, data->sg_len, i) { 800 if (sg->offset & 0x3) { 801 DBG("Reverting to PIO because of " 802 "bad alignment\n"); 803 host->flags &= ~SDHCI_REQ_USE_DMA; 804 break; 805 } 806 } 807 } 808 } 809 810 if (host->flags & SDHCI_REQ_USE_DMA) { 811 if (host->flags & SDHCI_USE_ADMA) { 812 ret = sdhci_adma_table_pre(host, data); 813 if (ret) { 814 /* 815 * This only happens when someone fed 816 * us an invalid request. 817 */ 818 WARN_ON(1); 819 host->flags &= ~SDHCI_REQ_USE_DMA; 820 } else { 821 sdhci_writel(host, host->adma_addr, 822 SDHCI_ADMA_ADDRESS); 823 } 824 } else { 825 int sg_cnt; 826 827 sg_cnt = dma_map_sg(mmc_dev(host->mmc), 828 data->sg, data->sg_len, 829 (data->flags & MMC_DATA_READ) ? 830 DMA_FROM_DEVICE : 831 DMA_TO_DEVICE); 832 if (sg_cnt == 0) { 833 /* 834 * This only happens when someone fed 835 * us an invalid request. 836 */ 837 WARN_ON(1); 838 host->flags &= ~SDHCI_REQ_USE_DMA; 839 } else { 840 WARN_ON(sg_cnt != 1); 841 sdhci_writel(host, sg_dma_address(data->sg), 842 SDHCI_DMA_ADDRESS); 843 } 844 } 845 } 846 847 /* 848 * Always adjust the DMA selection as some controllers 849 * (e.g. JMicron) can't do PIO properly when the selection 850 * is ADMA. 851 */ 852 if (host->version >= SDHCI_SPEC_200) { 853 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 854 ctrl &= ~SDHCI_CTRL_DMA_MASK; 855 if ((host->flags & SDHCI_REQ_USE_DMA) && 856 (host->flags & SDHCI_USE_ADMA)) 857 ctrl |= SDHCI_CTRL_ADMA32; 858 else 859 ctrl |= SDHCI_CTRL_SDMA; 860 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 861 } 862 863 if (!(host->flags & SDHCI_REQ_USE_DMA)) { 864 int flags; 865 866 flags = SG_MITER_ATOMIC; 867 if (host->data->flags & MMC_DATA_READ) 868 flags |= SG_MITER_TO_SG; 869 else 870 flags |= SG_MITER_FROM_SG; 871 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 872 host->blocks = data->blocks; 873 } 874 875 sdhci_set_transfer_irqs(host); 876 877 /* Set the DMA boundary value and block size */ 878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 879 data->blksz), SDHCI_BLOCK_SIZE); 880 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 881 } 882 883 static void sdhci_set_transfer_mode(struct sdhci_host *host, 884 struct mmc_command *cmd) 885 { 886 u16 mode; 887 struct mmc_data *data = cmd->data; 888 889 if (data == NULL) 890 return; 891 892 WARN_ON(!host->data); 893 894 mode = SDHCI_TRNS_BLK_CNT_EN; 895 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { 896 mode |= SDHCI_TRNS_MULTI; 897 /* 898 * If we are sending CMD23, CMD12 never gets sent 899 * on successful completion (so no Auto-CMD12). 900 */ 901 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) 902 mode |= SDHCI_TRNS_AUTO_CMD12; 903 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { 904 mode |= SDHCI_TRNS_AUTO_CMD23; 905 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); 906 } 907 } 908 909 if (data->flags & MMC_DATA_READ) 910 mode |= SDHCI_TRNS_READ; 911 if (host->flags & SDHCI_REQ_USE_DMA) 912 mode |= SDHCI_TRNS_DMA; 913 914 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 915 } 916 917 static void sdhci_finish_data(struct sdhci_host *host) 918 { 919 struct mmc_data *data; 920 921 BUG_ON(!host->data); 922 923 data = host->data; 924 host->data = NULL; 925 926 if (host->flags & SDHCI_REQ_USE_DMA) { 927 if (host->flags & SDHCI_USE_ADMA) 928 sdhci_adma_table_post(host, data); 929 else { 930 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 931 data->sg_len, (data->flags & MMC_DATA_READ) ? 932 DMA_FROM_DEVICE : DMA_TO_DEVICE); 933 } 934 } 935 936 /* 937 * The specification states that the block count register must 938 * be updated, but it does not specify at what point in the 939 * data flow. That makes the register entirely useless to read 940 * back so we have to assume that nothing made it to the card 941 * in the event of an error. 942 */ 943 if (data->error) 944 data->bytes_xfered = 0; 945 else 946 data->bytes_xfered = data->blksz * data->blocks; 947 948 /* 949 * Need to send CMD12 if - 950 * a) open-ended multiblock transfer (no CMD23) 951 * b) error in multiblock transfer 952 */ 953 if (data->stop && 954 (data->error || 955 !host->mrq->sbc)) { 956 957 /* 958 * The controller needs a reset of internal state machines 959 * upon error conditions. 960 */ 961 if (data->error) { 962 sdhci_reset(host, SDHCI_RESET_CMD); 963 sdhci_reset(host, SDHCI_RESET_DATA); 964 } 965 966 sdhci_send_command(host, data->stop); 967 } else 968 tasklet_schedule(&host->finish_tasklet); 969 } 970 971 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) 972 { 973 int flags; 974 u32 mask; 975 unsigned long timeout; 976 977 WARN_ON(host->cmd); 978 979 /* Wait max 10 ms */ 980 timeout = 10; 981 982 mask = SDHCI_CMD_INHIBIT; 983 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) 984 mask |= SDHCI_DATA_INHIBIT; 985 986 /* We shouldn't wait for data inihibit for stop commands, even 987 though they might use busy signaling */ 988 if (host->mrq->data && (cmd == host->mrq->data->stop)) 989 mask &= ~SDHCI_DATA_INHIBIT; 990 991 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 992 if (timeout == 0) { 993 pr_err("%s: Controller never released " 994 "inhibit bit(s).\n", mmc_hostname(host->mmc)); 995 sdhci_dumpregs(host); 996 cmd->error = -EIO; 997 tasklet_schedule(&host->finish_tasklet); 998 return; 999 } 1000 timeout--; 1001 mdelay(1); 1002 } 1003 1004 mod_timer(&host->timer, jiffies + 10 * HZ); 1005 1006 host->cmd = cmd; 1007 1008 sdhci_prepare_data(host, cmd); 1009 1010 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); 1011 1012 sdhci_set_transfer_mode(host, cmd); 1013 1014 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 1015 pr_err("%s: Unsupported response type!\n", 1016 mmc_hostname(host->mmc)); 1017 cmd->error = -EINVAL; 1018 tasklet_schedule(&host->finish_tasklet); 1019 return; 1020 } 1021 1022 if (!(cmd->flags & MMC_RSP_PRESENT)) 1023 flags = SDHCI_CMD_RESP_NONE; 1024 else if (cmd->flags & MMC_RSP_136) 1025 flags = SDHCI_CMD_RESP_LONG; 1026 else if (cmd->flags & MMC_RSP_BUSY) 1027 flags = SDHCI_CMD_RESP_SHORT_BUSY; 1028 else 1029 flags = SDHCI_CMD_RESP_SHORT; 1030 1031 if (cmd->flags & MMC_RSP_CRC) 1032 flags |= SDHCI_CMD_CRC; 1033 if (cmd->flags & MMC_RSP_OPCODE) 1034 flags |= SDHCI_CMD_INDEX; 1035 1036 /* CMD19 is special in that the Data Present Select should be set */ 1037 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || 1038 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) 1039 flags |= SDHCI_CMD_DATA; 1040 1041 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); 1042 } 1043 1044 static void sdhci_finish_command(struct sdhci_host *host) 1045 { 1046 int i; 1047 1048 BUG_ON(host->cmd == NULL); 1049 1050 if (host->cmd->flags & MMC_RSP_PRESENT) { 1051 if (host->cmd->flags & MMC_RSP_136) { 1052 /* CRC is stripped so we need to do some shifting. */ 1053 for (i = 0;i < 4;i++) { 1054 host->cmd->resp[i] = sdhci_readl(host, 1055 SDHCI_RESPONSE + (3-i)*4) << 8; 1056 if (i != 3) 1057 host->cmd->resp[i] |= 1058 sdhci_readb(host, 1059 SDHCI_RESPONSE + (3-i)*4-1); 1060 } 1061 } else { 1062 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); 1063 } 1064 } 1065 1066 host->cmd->error = 0; 1067 1068 /* Finished CMD23, now send actual command. */ 1069 if (host->cmd == host->mrq->sbc) { 1070 host->cmd = NULL; 1071 sdhci_send_command(host, host->mrq->cmd); 1072 } else { 1073 1074 /* Processed actual command. */ 1075 if (host->data && host->data_early) 1076 sdhci_finish_data(host); 1077 1078 if (!host->cmd->data) 1079 tasklet_schedule(&host->finish_tasklet); 1080 1081 host->cmd = NULL; 1082 } 1083 } 1084 1085 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 1086 { 1087 int div = 0; /* Initialized for compiler warning */ 1088 int real_div = div, clk_mul = 1; 1089 u16 clk = 0; 1090 unsigned long timeout; 1091 1092 if (clock && clock == host->clock) 1093 return; 1094 1095 host->mmc->actual_clock = 0; 1096 1097 if (host->ops->set_clock) { 1098 host->ops->set_clock(host, clock); 1099 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) 1100 return; 1101 } 1102 1103 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1104 1105 if (clock == 0) 1106 goto out; 1107 1108 if (host->version >= SDHCI_SPEC_300) { 1109 /* 1110 * Check if the Host Controller supports Programmable Clock 1111 * Mode. 1112 */ 1113 if (host->clk_mul) { 1114 u16 ctrl; 1115 1116 /* 1117 * We need to figure out whether the Host Driver needs 1118 * to select Programmable Clock Mode, or the value can 1119 * be set automatically by the Host Controller based on 1120 * the Preset Value registers. 1121 */ 1122 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1123 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1124 for (div = 1; div <= 1024; div++) { 1125 if (((host->max_clk * host->clk_mul) / 1126 div) <= clock) 1127 break; 1128 } 1129 /* 1130 * Set Programmable Clock Mode in the Clock 1131 * Control register. 1132 */ 1133 clk = SDHCI_PROG_CLOCK_MODE; 1134 real_div = div; 1135 clk_mul = host->clk_mul; 1136 div--; 1137 } 1138 } else { 1139 /* Version 3.00 divisors must be a multiple of 2. */ 1140 if (host->max_clk <= clock) 1141 div = 1; 1142 else { 1143 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; 1144 div += 2) { 1145 if ((host->max_clk / div) <= clock) 1146 break; 1147 } 1148 } 1149 real_div = div; 1150 div >>= 1; 1151 } 1152 } else { 1153 /* Version 2.00 divisors must be a power of 2. */ 1154 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 1155 if ((host->max_clk / div) <= clock) 1156 break; 1157 } 1158 real_div = div; 1159 div >>= 1; 1160 } 1161 1162 if (real_div) 1163 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; 1164 1165 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 1166 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 1167 << SDHCI_DIVIDER_HI_SHIFT; 1168 clk |= SDHCI_CLOCK_INT_EN; 1169 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1170 1171 /* Wait max 20 ms */ 1172 timeout = 20; 1173 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 1174 & SDHCI_CLOCK_INT_STABLE)) { 1175 if (timeout == 0) { 1176 pr_err("%s: Internal clock never " 1177 "stabilised.\n", mmc_hostname(host->mmc)); 1178 sdhci_dumpregs(host); 1179 return; 1180 } 1181 timeout--; 1182 mdelay(1); 1183 } 1184 1185 clk |= SDHCI_CLOCK_CARD_EN; 1186 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1187 1188 out: 1189 host->clock = clock; 1190 } 1191 1192 static int sdhci_set_power(struct sdhci_host *host, unsigned short power) 1193 { 1194 u8 pwr = 0; 1195 1196 if (power != (unsigned short)-1) { 1197 switch (1 << power) { 1198 case MMC_VDD_165_195: 1199 pwr = SDHCI_POWER_180; 1200 break; 1201 case MMC_VDD_29_30: 1202 case MMC_VDD_30_31: 1203 pwr = SDHCI_POWER_300; 1204 break; 1205 case MMC_VDD_32_33: 1206 case MMC_VDD_33_34: 1207 pwr = SDHCI_POWER_330; 1208 break; 1209 default: 1210 BUG(); 1211 } 1212 } 1213 1214 if (host->pwr == pwr) 1215 return -1; 1216 1217 host->pwr = pwr; 1218 1219 if (pwr == 0) { 1220 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1221 return 0; 1222 } 1223 1224 /* 1225 * Spec says that we should clear the power reg before setting 1226 * a new value. Some controllers don't seem to like this though. 1227 */ 1228 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) 1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1230 1231 /* 1232 * At least the Marvell CaFe chip gets confused if we set the voltage 1233 * and set turn on power at the same time, so set the voltage first. 1234 */ 1235 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) 1236 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1237 1238 pwr |= SDHCI_POWER_ON; 1239 1240 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1241 1242 /* 1243 * Some controllers need an extra 10ms delay of 10ms before they 1244 * can apply clock after applying power 1245 */ 1246 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) 1247 mdelay(10); 1248 1249 return power; 1250 } 1251 1252 /*****************************************************************************\ 1253 * * 1254 * MMC callbacks * 1255 * * 1256 \*****************************************************************************/ 1257 1258 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1259 { 1260 struct sdhci_host *host; 1261 bool present; 1262 unsigned long flags; 1263 u32 tuning_opcode; 1264 1265 host = mmc_priv(mmc); 1266 1267 sdhci_runtime_pm_get(host); 1268 1269 spin_lock_irqsave(&host->lock, flags); 1270 1271 WARN_ON(host->mrq != NULL); 1272 1273 #ifndef SDHCI_USE_LEDS_CLASS 1274 sdhci_activate_led(host); 1275 #endif 1276 1277 /* 1278 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED 1279 * requests if Auto-CMD12 is enabled. 1280 */ 1281 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { 1282 if (mrq->stop) { 1283 mrq->data->stop = NULL; 1284 mrq->stop = NULL; 1285 } 1286 } 1287 1288 host->mrq = mrq; 1289 1290 /* If polling, assume that the card is always present. */ 1291 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) 1292 present = true; 1293 else 1294 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 1295 SDHCI_CARD_PRESENT; 1296 1297 /* If we're using a cd-gpio, testing the presence bit might fail. */ 1298 if (!present) { 1299 int ret = mmc_gpio_get_cd(host->mmc); 1300 if (ret > 0) 1301 present = true; 1302 } 1303 1304 if (!present || host->flags & SDHCI_DEVICE_DEAD) { 1305 host->mrq->cmd->error = -ENOMEDIUM; 1306 tasklet_schedule(&host->finish_tasklet); 1307 } else { 1308 u32 present_state; 1309 1310 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1311 /* 1312 * Check if the re-tuning timer has already expired and there 1313 * is no on-going data transfer. If so, we need to execute 1314 * tuning procedure before sending command. 1315 */ 1316 if ((host->flags & SDHCI_NEEDS_RETUNING) && 1317 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { 1318 if (mmc->card) { 1319 /* eMMC uses cmd21 but sd and sdio use cmd19 */ 1320 tuning_opcode = 1321 mmc->card->type == MMC_TYPE_MMC ? 1322 MMC_SEND_TUNING_BLOCK_HS200 : 1323 MMC_SEND_TUNING_BLOCK; 1324 spin_unlock_irqrestore(&host->lock, flags); 1325 sdhci_execute_tuning(mmc, tuning_opcode); 1326 spin_lock_irqsave(&host->lock, flags); 1327 1328 /* Restore original mmc_request structure */ 1329 host->mrq = mrq; 1330 } 1331 } 1332 1333 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) 1334 sdhci_send_command(host, mrq->sbc); 1335 else 1336 sdhci_send_command(host, mrq->cmd); 1337 } 1338 1339 mmiowb(); 1340 spin_unlock_irqrestore(&host->lock, flags); 1341 } 1342 1343 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 1344 { 1345 unsigned long flags; 1346 int vdd_bit = -1; 1347 u8 ctrl; 1348 1349 spin_lock_irqsave(&host->lock, flags); 1350 1351 if (host->flags & SDHCI_DEVICE_DEAD) { 1352 spin_unlock_irqrestore(&host->lock, flags); 1353 if (host->vmmc && ios->power_mode == MMC_POWER_OFF) 1354 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); 1355 return; 1356 } 1357 1358 /* 1359 * Reset the chip on each power off. 1360 * Should clear out any weird states. 1361 */ 1362 if (ios->power_mode == MMC_POWER_OFF) { 1363 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); 1364 sdhci_reinit(host); 1365 } 1366 1367 sdhci_set_clock(host, ios->clock); 1368 1369 if (ios->power_mode == MMC_POWER_OFF) 1370 vdd_bit = sdhci_set_power(host, -1); 1371 else 1372 vdd_bit = sdhci_set_power(host, ios->vdd); 1373 1374 if (host->vmmc && vdd_bit != -1) { 1375 spin_unlock_irqrestore(&host->lock, flags); 1376 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); 1377 spin_lock_irqsave(&host->lock, flags); 1378 } 1379 1380 if (host->ops->platform_send_init_74_clocks) 1381 host->ops->platform_send_init_74_clocks(host, ios->power_mode); 1382 1383 /* 1384 * If your platform has 8-bit width support but is not a v3 controller, 1385 * or if it requires special setup code, you should implement that in 1386 * platform_8bit_width(). 1387 */ 1388 if (host->ops->platform_8bit_width) 1389 host->ops->platform_8bit_width(host, ios->bus_width); 1390 else { 1391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1392 if (ios->bus_width == MMC_BUS_WIDTH_8) { 1393 ctrl &= ~SDHCI_CTRL_4BITBUS; 1394 if (host->version >= SDHCI_SPEC_300) 1395 ctrl |= SDHCI_CTRL_8BITBUS; 1396 } else { 1397 if (host->version >= SDHCI_SPEC_300) 1398 ctrl &= ~SDHCI_CTRL_8BITBUS; 1399 if (ios->bus_width == MMC_BUS_WIDTH_4) 1400 ctrl |= SDHCI_CTRL_4BITBUS; 1401 else 1402 ctrl &= ~SDHCI_CTRL_4BITBUS; 1403 } 1404 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1405 } 1406 1407 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 1408 1409 if ((ios->timing == MMC_TIMING_SD_HS || 1410 ios->timing == MMC_TIMING_MMC_HS) 1411 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 1412 ctrl |= SDHCI_CTRL_HISPD; 1413 else 1414 ctrl &= ~SDHCI_CTRL_HISPD; 1415 1416 if (host->version >= SDHCI_SPEC_300) { 1417 u16 clk, ctrl_2; 1418 unsigned int clock; 1419 1420 /* In case of UHS-I modes, set High Speed Enable */ 1421 if ((ios->timing == MMC_TIMING_MMC_HS200) || 1422 (ios->timing == MMC_TIMING_UHS_SDR50) || 1423 (ios->timing == MMC_TIMING_UHS_SDR104) || 1424 (ios->timing == MMC_TIMING_UHS_DDR50) || 1425 (ios->timing == MMC_TIMING_UHS_SDR25)) 1426 ctrl |= SDHCI_CTRL_HISPD; 1427 1428 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1429 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1430 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1431 /* 1432 * We only need to set Driver Strength if the 1433 * preset value enable is not set. 1434 */ 1435 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; 1436 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) 1437 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; 1438 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) 1439 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; 1440 1441 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1442 } else { 1443 /* 1444 * According to SDHC Spec v3.00, if the Preset Value 1445 * Enable in the Host Control 2 register is set, we 1446 * need to reset SD Clock Enable before changing High 1447 * Speed Enable to avoid generating clock gliches. 1448 */ 1449 1450 /* Reset SD Clock Enable */ 1451 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1452 clk &= ~SDHCI_CLOCK_CARD_EN; 1453 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1454 1455 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1456 1457 /* Re-enable SD Clock */ 1458 clock = host->clock; 1459 host->clock = 0; 1460 sdhci_set_clock(host, clock); 1461 } 1462 1463 1464 /* Reset SD Clock Enable */ 1465 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1466 clk &= ~SDHCI_CLOCK_CARD_EN; 1467 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1468 1469 if (host->ops->set_uhs_signaling) 1470 host->ops->set_uhs_signaling(host, ios->timing); 1471 else { 1472 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1473 /* Select Bus Speed Mode for host */ 1474 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1475 if (ios->timing == MMC_TIMING_MMC_HS200) 1476 ctrl_2 |= SDHCI_CTRL_HS_SDR200; 1477 else if (ios->timing == MMC_TIMING_UHS_SDR12) 1478 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1479 else if (ios->timing == MMC_TIMING_UHS_SDR25) 1480 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1481 else if (ios->timing == MMC_TIMING_UHS_SDR50) 1482 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1483 else if (ios->timing == MMC_TIMING_UHS_SDR104) 1484 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1485 else if (ios->timing == MMC_TIMING_UHS_DDR50) 1486 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1487 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1488 } 1489 1490 /* Re-enable SD Clock */ 1491 clock = host->clock; 1492 host->clock = 0; 1493 sdhci_set_clock(host, clock); 1494 } else 1495 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 1496 1497 /* 1498 * Some (ENE) controllers go apeshit on some ios operation, 1499 * signalling timeout and CRC errors even on CMD0. Resetting 1500 * it on each ios seems to solve the problem. 1501 */ 1502 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) 1503 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 1504 1505 mmiowb(); 1506 spin_unlock_irqrestore(&host->lock, flags); 1507 } 1508 1509 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1510 { 1511 struct sdhci_host *host = mmc_priv(mmc); 1512 1513 sdhci_runtime_pm_get(host); 1514 sdhci_do_set_ios(host, ios); 1515 sdhci_runtime_pm_put(host); 1516 } 1517 1518 static int sdhci_check_ro(struct sdhci_host *host) 1519 { 1520 unsigned long flags; 1521 int is_readonly; 1522 1523 spin_lock_irqsave(&host->lock, flags); 1524 1525 if (host->flags & SDHCI_DEVICE_DEAD) 1526 is_readonly = 0; 1527 else if (host->ops->get_ro) 1528 is_readonly = host->ops->get_ro(host); 1529 else 1530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) 1531 & SDHCI_WRITE_PROTECT); 1532 1533 spin_unlock_irqrestore(&host->lock, flags); 1534 1535 /* This quirk needs to be replaced by a callback-function later */ 1536 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? 1537 !is_readonly : is_readonly; 1538 } 1539 1540 #define SAMPLE_COUNT 5 1541 1542 static int sdhci_do_get_ro(struct sdhci_host *host) 1543 { 1544 int i, ro_count; 1545 1546 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) 1547 return sdhci_check_ro(host); 1548 1549 ro_count = 0; 1550 for (i = 0; i < SAMPLE_COUNT; i++) { 1551 if (sdhci_check_ro(host)) { 1552 if (++ro_count > SAMPLE_COUNT / 2) 1553 return 1; 1554 } 1555 msleep(30); 1556 } 1557 return 0; 1558 } 1559 1560 static void sdhci_hw_reset(struct mmc_host *mmc) 1561 { 1562 struct sdhci_host *host = mmc_priv(mmc); 1563 1564 if (host->ops && host->ops->hw_reset) 1565 host->ops->hw_reset(host); 1566 } 1567 1568 static int sdhci_get_ro(struct mmc_host *mmc) 1569 { 1570 struct sdhci_host *host = mmc_priv(mmc); 1571 int ret; 1572 1573 sdhci_runtime_pm_get(host); 1574 ret = sdhci_do_get_ro(host); 1575 sdhci_runtime_pm_put(host); 1576 return ret; 1577 } 1578 1579 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) 1580 { 1581 if (host->flags & SDHCI_DEVICE_DEAD) 1582 goto out; 1583 1584 if (enable) 1585 host->flags |= SDHCI_SDIO_IRQ_ENABLED; 1586 else 1587 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; 1588 1589 /* SDIO IRQ will be enabled as appropriate in runtime resume */ 1590 if (host->runtime_suspended) 1591 goto out; 1592 1593 if (enable) 1594 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); 1595 else 1596 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); 1597 out: 1598 mmiowb(); 1599 } 1600 1601 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1602 { 1603 struct sdhci_host *host = mmc_priv(mmc); 1604 unsigned long flags; 1605 1606 spin_lock_irqsave(&host->lock, flags); 1607 sdhci_enable_sdio_irq_nolock(host, enable); 1608 spin_unlock_irqrestore(&host->lock, flags); 1609 } 1610 1611 static int sdhci_do_3_3v_signal_voltage_switch(struct sdhci_host *host, 1612 u16 ctrl) 1613 { 1614 int ret; 1615 1616 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ 1617 ctrl &= ~SDHCI_CTRL_VDD_180; 1618 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1619 1620 if (host->vqmmc) { 1621 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); 1622 if (ret) { 1623 pr_warning("%s: Switching to 3.3V signalling voltage " 1624 " failed\n", mmc_hostname(host->mmc)); 1625 return -EIO; 1626 } 1627 } 1628 /* Wait for 5ms */ 1629 usleep_range(5000, 5500); 1630 1631 /* 3.3V regulator output should be stable within 5 ms */ 1632 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1633 if (!(ctrl & SDHCI_CTRL_VDD_180)) 1634 return 0; 1635 1636 pr_warning("%s: 3.3V regulator output did not became stable\n", 1637 mmc_hostname(host->mmc)); 1638 1639 return -EIO; 1640 } 1641 1642 static int sdhci_do_1_8v_signal_voltage_switch(struct sdhci_host *host, 1643 u16 ctrl) 1644 { 1645 u8 pwr; 1646 u16 clk; 1647 u32 present_state; 1648 int ret; 1649 1650 /* Stop SDCLK */ 1651 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1652 clk &= ~SDHCI_CLOCK_CARD_EN; 1653 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1654 1655 /* Check whether DAT[3:0] is 0000 */ 1656 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 1657 if (!((present_state & SDHCI_DATA_LVL_MASK) >> 1658 SDHCI_DATA_LVL_SHIFT)) { 1659 /* 1660 * Enable 1.8V Signal Enable in the Host Control2 1661 * register 1662 */ 1663 if (host->vqmmc) 1664 ret = regulator_set_voltage(host->vqmmc, 1665 1700000, 1950000); 1666 else 1667 ret = 0; 1668 1669 if (!ret) { 1670 ctrl |= SDHCI_CTRL_VDD_180; 1671 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1672 1673 /* Wait for 5ms */ 1674 usleep_range(5000, 5500); 1675 1676 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1677 if (ctrl & SDHCI_CTRL_VDD_180) { 1678 /* Provide SDCLK again and wait for 1ms */ 1679 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1680 clk |= SDHCI_CLOCK_CARD_EN; 1681 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1682 usleep_range(1000, 1500); 1683 1684 /* 1685 * If DAT[3:0] level is 1111b, then the card 1686 * was successfully switched to 1.8V signaling. 1687 */ 1688 present_state = sdhci_readl(host, 1689 SDHCI_PRESENT_STATE); 1690 if ((present_state & SDHCI_DATA_LVL_MASK) == 1691 SDHCI_DATA_LVL_MASK) 1692 return 0; 1693 } 1694 } 1695 } 1696 1697 /* 1698 * If we are here, that means the switch to 1.8V signaling 1699 * failed. We power cycle the card, and retry initialization 1700 * sequence by setting S18R to 0. 1701 */ 1702 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL); 1703 pwr &= ~SDHCI_POWER_ON; 1704 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1705 if (host->vmmc) 1706 regulator_disable(host->vmmc); 1707 1708 /* Wait for 1ms as per the spec */ 1709 usleep_range(1000, 1500); 1710 pwr |= SDHCI_POWER_ON; 1711 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1712 if (host->vmmc) 1713 regulator_enable(host->vmmc); 1714 1715 pr_warning("%s: Switching to 1.8V signalling voltage failed, " 1716 "retrying with S18R set to 0\n", mmc_hostname(host->mmc)); 1717 1718 return -EAGAIN; 1719 } 1720 1721 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, 1722 struct mmc_ios *ios) 1723 { 1724 u16 ctrl; 1725 1726 /* 1727 * Signal Voltage Switching is only applicable for Host Controllers 1728 * v3.00 and above. 1729 */ 1730 if (host->version < SDHCI_SPEC_300) 1731 return 0; 1732 1733 /* 1734 * We first check whether the request is to set signalling voltage 1735 * to 3.3V. If so, we change the voltage to 3.3V and return quickly. 1736 */ 1737 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1738 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1739 return sdhci_do_3_3v_signal_voltage_switch(host, ctrl); 1740 else if (!(ctrl & SDHCI_CTRL_VDD_180) && 1741 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) 1742 return sdhci_do_1_8v_signal_voltage_switch(host, ctrl); 1743 else 1744 /* No signal voltage switch required */ 1745 return 0; 1746 } 1747 1748 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, 1749 struct mmc_ios *ios) 1750 { 1751 struct sdhci_host *host = mmc_priv(mmc); 1752 int err; 1753 1754 if (host->version < SDHCI_SPEC_300) 1755 return 0; 1756 sdhci_runtime_pm_get(host); 1757 err = sdhci_do_start_signal_voltage_switch(host, ios); 1758 sdhci_runtime_pm_put(host); 1759 return err; 1760 } 1761 1762 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 1763 { 1764 struct sdhci_host *host; 1765 u16 ctrl; 1766 u32 ier; 1767 int tuning_loop_counter = MAX_TUNING_LOOP; 1768 unsigned long timeout; 1769 int err = 0; 1770 bool requires_tuning_nonuhs = false; 1771 1772 host = mmc_priv(mmc); 1773 1774 sdhci_runtime_pm_get(host); 1775 disable_irq(host->irq); 1776 spin_lock(&host->lock); 1777 1778 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1779 1780 /* 1781 * The Host Controller needs tuning only in case of SDR104 mode 1782 * and for SDR50 mode when Use Tuning for SDR50 is set in the 1783 * Capabilities register. 1784 * If the Host Controller supports the HS200 mode then the 1785 * tuning function has to be executed. 1786 */ 1787 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && 1788 (host->flags & SDHCI_SDR50_NEEDS_TUNING || 1789 host->flags & SDHCI_HS200_NEEDS_TUNING)) 1790 requires_tuning_nonuhs = true; 1791 1792 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || 1793 requires_tuning_nonuhs) 1794 ctrl |= SDHCI_CTRL_EXEC_TUNING; 1795 else { 1796 spin_unlock(&host->lock); 1797 enable_irq(host->irq); 1798 sdhci_runtime_pm_put(host); 1799 return 0; 1800 } 1801 1802 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1803 1804 /* 1805 * As per the Host Controller spec v3.00, tuning command 1806 * generates Buffer Read Ready interrupt, so enable that. 1807 * 1808 * Note: The spec clearly says that when tuning sequence 1809 * is being performed, the controller does not generate 1810 * interrupts other than Buffer Read Ready interrupt. But 1811 * to make sure we don't hit a controller bug, we _only_ 1812 * enable Buffer Read Ready interrupt here. 1813 */ 1814 ier = sdhci_readl(host, SDHCI_INT_ENABLE); 1815 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); 1816 1817 /* 1818 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number 1819 * of loops reaches 40 times or a timeout of 150ms occurs. 1820 */ 1821 timeout = 150; 1822 do { 1823 struct mmc_command cmd = {0}; 1824 struct mmc_request mrq = {NULL}; 1825 1826 if (!tuning_loop_counter && !timeout) 1827 break; 1828 1829 cmd.opcode = opcode; 1830 cmd.arg = 0; 1831 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 1832 cmd.retries = 0; 1833 cmd.data = NULL; 1834 cmd.error = 0; 1835 1836 mrq.cmd = &cmd; 1837 host->mrq = &mrq; 1838 1839 /* 1840 * In response to CMD19, the card sends 64 bytes of tuning 1841 * block to the Host Controller. So we set the block size 1842 * to 64 here. 1843 */ 1844 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { 1845 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) 1846 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), 1847 SDHCI_BLOCK_SIZE); 1848 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) 1849 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1850 SDHCI_BLOCK_SIZE); 1851 } else { 1852 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), 1853 SDHCI_BLOCK_SIZE); 1854 } 1855 1856 /* 1857 * The tuning block is sent by the card to the host controller. 1858 * So we set the TRNS_READ bit in the Transfer Mode register. 1859 * This also takes care of setting DMA Enable and Multi Block 1860 * Select in the same register to 0. 1861 */ 1862 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 1863 1864 sdhci_send_command(host, &cmd); 1865 1866 host->cmd = NULL; 1867 host->mrq = NULL; 1868 1869 spin_unlock(&host->lock); 1870 enable_irq(host->irq); 1871 1872 /* Wait for Buffer Read Ready interrupt */ 1873 wait_event_interruptible_timeout(host->buf_ready_int, 1874 (host->tuning_done == 1), 1875 msecs_to_jiffies(50)); 1876 disable_irq(host->irq); 1877 spin_lock(&host->lock); 1878 1879 if (!host->tuning_done) { 1880 pr_info(DRIVER_NAME ": Timeout waiting for " 1881 "Buffer Read Ready interrupt during tuning " 1882 "procedure, falling back to fixed sampling " 1883 "clock\n"); 1884 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1885 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1886 ctrl &= ~SDHCI_CTRL_EXEC_TUNING; 1887 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1888 1889 err = -EIO; 1890 goto out; 1891 } 1892 1893 host->tuning_done = 0; 1894 1895 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1896 tuning_loop_counter--; 1897 timeout--; 1898 mdelay(1); 1899 } while (ctrl & SDHCI_CTRL_EXEC_TUNING); 1900 1901 /* 1902 * The Host Driver has exhausted the maximum number of loops allowed, 1903 * so use fixed sampling frequency. 1904 */ 1905 if (!tuning_loop_counter || !timeout) { 1906 ctrl &= ~SDHCI_CTRL_TUNED_CLK; 1907 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1908 } else { 1909 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { 1910 pr_info(DRIVER_NAME ": Tuning procedure" 1911 " failed, falling back to fixed sampling" 1912 " clock\n"); 1913 err = -EIO; 1914 } 1915 } 1916 1917 out: 1918 /* 1919 * If this is the very first time we are here, we start the retuning 1920 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING 1921 * flag won't be set, we check this condition before actually starting 1922 * the timer. 1923 */ 1924 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && 1925 (host->tuning_mode == SDHCI_TUNING_MODE_1)) { 1926 host->flags |= SDHCI_USING_RETUNING_TIMER; 1927 mod_timer(&host->tuning_timer, jiffies + 1928 host->tuning_count * HZ); 1929 /* Tuning mode 1 limits the maximum data length to 4MB */ 1930 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; 1931 } else { 1932 host->flags &= ~SDHCI_NEEDS_RETUNING; 1933 /* Reload the new initial value for timer */ 1934 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 1935 mod_timer(&host->tuning_timer, jiffies + 1936 host->tuning_count * HZ); 1937 } 1938 1939 /* 1940 * In case tuning fails, host controllers which support re-tuning can 1941 * try tuning again at a later time, when the re-tuning timer expires. 1942 * So for these controllers, we return 0. Since there might be other 1943 * controllers who do not have this capability, we return error for 1944 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using 1945 * a retuning timer to do the retuning for the card. 1946 */ 1947 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) 1948 err = 0; 1949 1950 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); 1951 spin_unlock(&host->lock); 1952 enable_irq(host->irq); 1953 sdhci_runtime_pm_put(host); 1954 1955 return err; 1956 } 1957 1958 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable) 1959 { 1960 u16 ctrl; 1961 unsigned long flags; 1962 1963 /* Host Controller v3.00 defines preset value registers */ 1964 if (host->version < SDHCI_SPEC_300) 1965 return; 1966 1967 spin_lock_irqsave(&host->lock, flags); 1968 1969 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1970 1971 /* 1972 * We only enable or disable Preset Value if they are not already 1973 * enabled or disabled respectively. Otherwise, we bail out. 1974 */ 1975 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1976 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; 1977 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1978 host->flags |= SDHCI_PV_ENABLED; 1979 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { 1980 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 1981 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 1982 host->flags &= ~SDHCI_PV_ENABLED; 1983 } 1984 1985 spin_unlock_irqrestore(&host->lock, flags); 1986 } 1987 1988 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) 1989 { 1990 struct sdhci_host *host = mmc_priv(mmc); 1991 1992 sdhci_runtime_pm_get(host); 1993 sdhci_do_enable_preset_value(host, enable); 1994 sdhci_runtime_pm_put(host); 1995 } 1996 1997 static void sdhci_card_event(struct mmc_host *mmc) 1998 { 1999 struct sdhci_host *host = mmc_priv(mmc); 2000 unsigned long flags; 2001 2002 spin_lock_irqsave(&host->lock, flags); 2003 2004 /* Check host->mrq first in case we are runtime suspended */ 2005 if (host->mrq && 2006 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { 2007 pr_err("%s: Card removed during transfer!\n", 2008 mmc_hostname(host->mmc)); 2009 pr_err("%s: Resetting controller.\n", 2010 mmc_hostname(host->mmc)); 2011 2012 sdhci_reset(host, SDHCI_RESET_CMD); 2013 sdhci_reset(host, SDHCI_RESET_DATA); 2014 2015 host->mrq->cmd->error = -ENOMEDIUM; 2016 tasklet_schedule(&host->finish_tasklet); 2017 } 2018 2019 spin_unlock_irqrestore(&host->lock, flags); 2020 } 2021 2022 static const struct mmc_host_ops sdhci_ops = { 2023 .request = sdhci_request, 2024 .set_ios = sdhci_set_ios, 2025 .get_ro = sdhci_get_ro, 2026 .hw_reset = sdhci_hw_reset, 2027 .enable_sdio_irq = sdhci_enable_sdio_irq, 2028 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, 2029 .execute_tuning = sdhci_execute_tuning, 2030 .enable_preset_value = sdhci_enable_preset_value, 2031 .card_event = sdhci_card_event, 2032 }; 2033 2034 /*****************************************************************************\ 2035 * * 2036 * Tasklets * 2037 * * 2038 \*****************************************************************************/ 2039 2040 static void sdhci_tasklet_card(unsigned long param) 2041 { 2042 struct sdhci_host *host = (struct sdhci_host*)param; 2043 2044 sdhci_card_event(host->mmc); 2045 2046 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 2047 } 2048 2049 static void sdhci_tasklet_finish(unsigned long param) 2050 { 2051 struct sdhci_host *host; 2052 unsigned long flags; 2053 struct mmc_request *mrq; 2054 2055 host = (struct sdhci_host*)param; 2056 2057 spin_lock_irqsave(&host->lock, flags); 2058 2059 /* 2060 * If this tasklet gets rescheduled while running, it will 2061 * be run again afterwards but without any active request. 2062 */ 2063 if (!host->mrq) { 2064 spin_unlock_irqrestore(&host->lock, flags); 2065 return; 2066 } 2067 2068 del_timer(&host->timer); 2069 2070 mrq = host->mrq; 2071 2072 /* 2073 * The controller needs a reset of internal state machines 2074 * upon error conditions. 2075 */ 2076 if (!(host->flags & SDHCI_DEVICE_DEAD) && 2077 ((mrq->cmd && mrq->cmd->error) || 2078 (mrq->data && (mrq->data->error || 2079 (mrq->data->stop && mrq->data->stop->error))) || 2080 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { 2081 2082 /* Some controllers need this kick or reset won't work here */ 2083 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { 2084 unsigned int clock; 2085 2086 /* This is to force an update */ 2087 clock = host->clock; 2088 host->clock = 0; 2089 sdhci_set_clock(host, clock); 2090 } 2091 2092 /* Spec says we should do both at the same time, but Ricoh 2093 controllers do not like that. */ 2094 sdhci_reset(host, SDHCI_RESET_CMD); 2095 sdhci_reset(host, SDHCI_RESET_DATA); 2096 } 2097 2098 host->mrq = NULL; 2099 host->cmd = NULL; 2100 host->data = NULL; 2101 2102 #ifndef SDHCI_USE_LEDS_CLASS 2103 sdhci_deactivate_led(host); 2104 #endif 2105 2106 mmiowb(); 2107 spin_unlock_irqrestore(&host->lock, flags); 2108 2109 mmc_request_done(host->mmc, mrq); 2110 sdhci_runtime_pm_put(host); 2111 } 2112 2113 static void sdhci_timeout_timer(unsigned long data) 2114 { 2115 struct sdhci_host *host; 2116 unsigned long flags; 2117 2118 host = (struct sdhci_host*)data; 2119 2120 spin_lock_irqsave(&host->lock, flags); 2121 2122 if (host->mrq) { 2123 pr_err("%s: Timeout waiting for hardware " 2124 "interrupt.\n", mmc_hostname(host->mmc)); 2125 sdhci_dumpregs(host); 2126 2127 if (host->data) { 2128 host->data->error = -ETIMEDOUT; 2129 sdhci_finish_data(host); 2130 } else { 2131 if (host->cmd) 2132 host->cmd->error = -ETIMEDOUT; 2133 else 2134 host->mrq->cmd->error = -ETIMEDOUT; 2135 2136 tasklet_schedule(&host->finish_tasklet); 2137 } 2138 } 2139 2140 mmiowb(); 2141 spin_unlock_irqrestore(&host->lock, flags); 2142 } 2143 2144 static void sdhci_tuning_timer(unsigned long data) 2145 { 2146 struct sdhci_host *host; 2147 unsigned long flags; 2148 2149 host = (struct sdhci_host *)data; 2150 2151 spin_lock_irqsave(&host->lock, flags); 2152 2153 host->flags |= SDHCI_NEEDS_RETUNING; 2154 2155 spin_unlock_irqrestore(&host->lock, flags); 2156 } 2157 2158 /*****************************************************************************\ 2159 * * 2160 * Interrupt handling * 2161 * * 2162 \*****************************************************************************/ 2163 2164 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) 2165 { 2166 BUG_ON(intmask == 0); 2167 2168 if (!host->cmd) { 2169 pr_err("%s: Got command interrupt 0x%08x even " 2170 "though no command operation was in progress.\n", 2171 mmc_hostname(host->mmc), (unsigned)intmask); 2172 sdhci_dumpregs(host); 2173 return; 2174 } 2175 2176 if (intmask & SDHCI_INT_TIMEOUT) 2177 host->cmd->error = -ETIMEDOUT; 2178 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | 2179 SDHCI_INT_INDEX)) 2180 host->cmd->error = -EILSEQ; 2181 2182 if (host->cmd->error) { 2183 tasklet_schedule(&host->finish_tasklet); 2184 return; 2185 } 2186 2187 /* 2188 * The host can send and interrupt when the busy state has 2189 * ended, allowing us to wait without wasting CPU cycles. 2190 * Unfortunately this is overloaded on the "data complete" 2191 * interrupt, so we need to take some care when handling 2192 * it. 2193 * 2194 * Note: The 1.0 specification is a bit ambiguous about this 2195 * feature so there might be some problems with older 2196 * controllers. 2197 */ 2198 if (host->cmd->flags & MMC_RSP_BUSY) { 2199 if (host->cmd->data) 2200 DBG("Cannot wait for busy signal when also " 2201 "doing a data transfer"); 2202 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) 2203 return; 2204 2205 /* The controller does not support the end-of-busy IRQ, 2206 * fall through and take the SDHCI_INT_RESPONSE */ 2207 } 2208 2209 if (intmask & SDHCI_INT_RESPONSE) 2210 sdhci_finish_command(host); 2211 } 2212 2213 #ifdef CONFIG_MMC_DEBUG 2214 static void sdhci_show_adma_error(struct sdhci_host *host) 2215 { 2216 const char *name = mmc_hostname(host->mmc); 2217 u8 *desc = host->adma_desc; 2218 __le32 *dma; 2219 __le16 *len; 2220 u8 attr; 2221 2222 sdhci_dumpregs(host); 2223 2224 while (true) { 2225 dma = (__le32 *)(desc + 4); 2226 len = (__le16 *)(desc + 2); 2227 attr = *desc; 2228 2229 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", 2230 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); 2231 2232 desc += 8; 2233 2234 if (attr & 2) 2235 break; 2236 } 2237 } 2238 #else 2239 static void sdhci_show_adma_error(struct sdhci_host *host) { } 2240 #endif 2241 2242 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) 2243 { 2244 u32 command; 2245 BUG_ON(intmask == 0); 2246 2247 /* CMD19 generates _only_ Buffer Read Ready interrupt */ 2248 if (intmask & SDHCI_INT_DATA_AVAIL) { 2249 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); 2250 if (command == MMC_SEND_TUNING_BLOCK || 2251 command == MMC_SEND_TUNING_BLOCK_HS200) { 2252 host->tuning_done = 1; 2253 wake_up(&host->buf_ready_int); 2254 return; 2255 } 2256 } 2257 2258 if (!host->data) { 2259 /* 2260 * The "data complete" interrupt is also used to 2261 * indicate that a busy state has ended. See comment 2262 * above in sdhci_cmd_irq(). 2263 */ 2264 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { 2265 if (intmask & SDHCI_INT_DATA_END) { 2266 sdhci_finish_command(host); 2267 return; 2268 } 2269 } 2270 2271 pr_err("%s: Got data interrupt 0x%08x even " 2272 "though no data operation was in progress.\n", 2273 mmc_hostname(host->mmc), (unsigned)intmask); 2274 sdhci_dumpregs(host); 2275 2276 return; 2277 } 2278 2279 if (intmask & SDHCI_INT_DATA_TIMEOUT) 2280 host->data->error = -ETIMEDOUT; 2281 else if (intmask & SDHCI_INT_DATA_END_BIT) 2282 host->data->error = -EILSEQ; 2283 else if ((intmask & SDHCI_INT_DATA_CRC) && 2284 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) 2285 != MMC_BUS_TEST_R) 2286 host->data->error = -EILSEQ; 2287 else if (intmask & SDHCI_INT_ADMA_ERROR) { 2288 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); 2289 sdhci_show_adma_error(host); 2290 host->data->error = -EIO; 2291 if (host->ops->adma_workaround) 2292 host->ops->adma_workaround(host, intmask); 2293 } 2294 2295 if (host->data->error) 2296 sdhci_finish_data(host); 2297 else { 2298 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) 2299 sdhci_transfer_pio(host); 2300 2301 /* 2302 * We currently don't do anything fancy with DMA 2303 * boundaries, but as we can't disable the feature 2304 * we need to at least restart the transfer. 2305 * 2306 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) 2307 * should return a valid address to continue from, but as 2308 * some controllers are faulty, don't trust them. 2309 */ 2310 if (intmask & SDHCI_INT_DMA_END) { 2311 u32 dmastart, dmanow; 2312 dmastart = sg_dma_address(host->data->sg); 2313 dmanow = dmastart + host->data->bytes_xfered; 2314 /* 2315 * Force update to the next DMA block boundary. 2316 */ 2317 dmanow = (dmanow & 2318 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 2319 SDHCI_DEFAULT_BOUNDARY_SIZE; 2320 host->data->bytes_xfered = dmanow - dmastart; 2321 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," 2322 " next 0x%08x\n", 2323 mmc_hostname(host->mmc), dmastart, 2324 host->data->bytes_xfered, dmanow); 2325 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 2326 } 2327 2328 if (intmask & SDHCI_INT_DATA_END) { 2329 if (host->cmd) { 2330 /* 2331 * Data managed to finish before the 2332 * command completed. Make sure we do 2333 * things in the proper order. 2334 */ 2335 host->data_early = 1; 2336 } else { 2337 sdhci_finish_data(host); 2338 } 2339 } 2340 } 2341 } 2342 2343 static irqreturn_t sdhci_irq(int irq, void *dev_id) 2344 { 2345 irqreturn_t result; 2346 struct sdhci_host *host = dev_id; 2347 u32 intmask, unexpected = 0; 2348 int cardint = 0, max_loops = 16; 2349 2350 spin_lock(&host->lock); 2351 2352 if (host->runtime_suspended) { 2353 spin_unlock(&host->lock); 2354 pr_warning("%s: got irq while runtime suspended\n", 2355 mmc_hostname(host->mmc)); 2356 return IRQ_HANDLED; 2357 } 2358 2359 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2360 2361 if (!intmask || intmask == 0xffffffff) { 2362 result = IRQ_NONE; 2363 goto out; 2364 } 2365 2366 again: 2367 DBG("*** %s got interrupt: 0x%08x\n", 2368 mmc_hostname(host->mmc), intmask); 2369 2370 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { 2371 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & 2372 SDHCI_CARD_PRESENT; 2373 2374 /* 2375 * There is a observation on i.mx esdhc. INSERT bit will be 2376 * immediately set again when it gets cleared, if a card is 2377 * inserted. We have to mask the irq to prevent interrupt 2378 * storm which will freeze the system. And the REMOVE gets 2379 * the same situation. 2380 * 2381 * More testing are needed here to ensure it works for other 2382 * platforms though. 2383 */ 2384 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : 2385 SDHCI_INT_CARD_REMOVE); 2386 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : 2387 SDHCI_INT_CARD_INSERT); 2388 2389 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | 2390 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); 2391 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); 2392 tasklet_schedule(&host->card_tasklet); 2393 } 2394 2395 if (intmask & SDHCI_INT_CMD_MASK) { 2396 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, 2397 SDHCI_INT_STATUS); 2398 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); 2399 } 2400 2401 if (intmask & SDHCI_INT_DATA_MASK) { 2402 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, 2403 SDHCI_INT_STATUS); 2404 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); 2405 } 2406 2407 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); 2408 2409 intmask &= ~SDHCI_INT_ERROR; 2410 2411 if (intmask & SDHCI_INT_BUS_POWER) { 2412 pr_err("%s: Card is consuming too much power!\n", 2413 mmc_hostname(host->mmc)); 2414 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); 2415 } 2416 2417 intmask &= ~SDHCI_INT_BUS_POWER; 2418 2419 if (intmask & SDHCI_INT_CARD_INT) 2420 cardint = 1; 2421 2422 intmask &= ~SDHCI_INT_CARD_INT; 2423 2424 if (intmask) { 2425 unexpected |= intmask; 2426 sdhci_writel(host, intmask, SDHCI_INT_STATUS); 2427 } 2428 2429 result = IRQ_HANDLED; 2430 2431 intmask = sdhci_readl(host, SDHCI_INT_STATUS); 2432 if (intmask && --max_loops) 2433 goto again; 2434 out: 2435 spin_unlock(&host->lock); 2436 2437 if (unexpected) { 2438 pr_err("%s: Unexpected interrupt 0x%08x.\n", 2439 mmc_hostname(host->mmc), unexpected); 2440 sdhci_dumpregs(host); 2441 } 2442 /* 2443 * We have to delay this as it calls back into the driver. 2444 */ 2445 if (cardint) 2446 mmc_signal_sdio_irq(host->mmc); 2447 2448 return result; 2449 } 2450 2451 /*****************************************************************************\ 2452 * * 2453 * Suspend/resume * 2454 * * 2455 \*****************************************************************************/ 2456 2457 #ifdef CONFIG_PM 2458 2459 int sdhci_suspend_host(struct sdhci_host *host) 2460 { 2461 int ret; 2462 2463 if (host->ops->platform_suspend) 2464 host->ops->platform_suspend(host); 2465 2466 sdhci_disable_card_detection(host); 2467 2468 /* Disable tuning since we are suspending */ 2469 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2470 del_timer_sync(&host->tuning_timer); 2471 host->flags &= ~SDHCI_NEEDS_RETUNING; 2472 } 2473 2474 ret = mmc_suspend_host(host->mmc); 2475 if (ret) { 2476 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2477 host->flags |= SDHCI_NEEDS_RETUNING; 2478 mod_timer(&host->tuning_timer, jiffies + 2479 host->tuning_count * HZ); 2480 } 2481 2482 sdhci_enable_card_detection(host); 2483 2484 return ret; 2485 } 2486 2487 free_irq(host->irq, host); 2488 2489 return ret; 2490 } 2491 2492 EXPORT_SYMBOL_GPL(sdhci_suspend_host); 2493 2494 int sdhci_resume_host(struct sdhci_host *host) 2495 { 2496 int ret; 2497 2498 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2499 if (host->ops->enable_dma) 2500 host->ops->enable_dma(host); 2501 } 2502 2503 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 2504 mmc_hostname(host->mmc), host); 2505 if (ret) 2506 return ret; 2507 2508 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && 2509 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { 2510 /* Card keeps power but host controller does not */ 2511 sdhci_init(host, 0); 2512 host->pwr = 0; 2513 host->clock = 0; 2514 sdhci_do_set_ios(host, &host->mmc->ios); 2515 } else { 2516 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); 2517 mmiowb(); 2518 } 2519 2520 ret = mmc_resume_host(host->mmc); 2521 sdhci_enable_card_detection(host); 2522 2523 if (host->ops->platform_resume) 2524 host->ops->platform_resume(host); 2525 2526 /* Set the re-tuning expiration flag */ 2527 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2528 host->flags |= SDHCI_NEEDS_RETUNING; 2529 2530 return ret; 2531 } 2532 2533 EXPORT_SYMBOL_GPL(sdhci_resume_host); 2534 2535 void sdhci_enable_irq_wakeups(struct sdhci_host *host) 2536 { 2537 u8 val; 2538 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); 2539 val |= SDHCI_WAKE_ON_INT; 2540 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); 2541 } 2542 2543 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); 2544 2545 #endif /* CONFIG_PM */ 2546 2547 #ifdef CONFIG_PM_RUNTIME 2548 2549 static int sdhci_runtime_pm_get(struct sdhci_host *host) 2550 { 2551 return pm_runtime_get_sync(host->mmc->parent); 2552 } 2553 2554 static int sdhci_runtime_pm_put(struct sdhci_host *host) 2555 { 2556 pm_runtime_mark_last_busy(host->mmc->parent); 2557 return pm_runtime_put_autosuspend(host->mmc->parent); 2558 } 2559 2560 int sdhci_runtime_suspend_host(struct sdhci_host *host) 2561 { 2562 unsigned long flags; 2563 int ret = 0; 2564 2565 /* Disable tuning since we are suspending */ 2566 if (host->flags & SDHCI_USING_RETUNING_TIMER) { 2567 del_timer_sync(&host->tuning_timer); 2568 host->flags &= ~SDHCI_NEEDS_RETUNING; 2569 } 2570 2571 spin_lock_irqsave(&host->lock, flags); 2572 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); 2573 spin_unlock_irqrestore(&host->lock, flags); 2574 2575 synchronize_irq(host->irq); 2576 2577 spin_lock_irqsave(&host->lock, flags); 2578 host->runtime_suspended = true; 2579 spin_unlock_irqrestore(&host->lock, flags); 2580 2581 return ret; 2582 } 2583 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); 2584 2585 int sdhci_runtime_resume_host(struct sdhci_host *host) 2586 { 2587 unsigned long flags; 2588 int ret = 0, host_flags = host->flags; 2589 2590 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2591 if (host->ops->enable_dma) 2592 host->ops->enable_dma(host); 2593 } 2594 2595 sdhci_init(host, 0); 2596 2597 /* Force clock and power re-program */ 2598 host->pwr = 0; 2599 host->clock = 0; 2600 sdhci_do_set_ios(host, &host->mmc->ios); 2601 2602 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); 2603 if (host_flags & SDHCI_PV_ENABLED) 2604 sdhci_do_enable_preset_value(host, true); 2605 2606 /* Set the re-tuning expiration flag */ 2607 if (host->flags & SDHCI_USING_RETUNING_TIMER) 2608 host->flags |= SDHCI_NEEDS_RETUNING; 2609 2610 spin_lock_irqsave(&host->lock, flags); 2611 2612 host->runtime_suspended = false; 2613 2614 /* Enable SDIO IRQ */ 2615 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) 2616 sdhci_enable_sdio_irq_nolock(host, true); 2617 2618 /* Enable Card Detection */ 2619 sdhci_enable_card_detection(host); 2620 2621 spin_unlock_irqrestore(&host->lock, flags); 2622 2623 return ret; 2624 } 2625 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); 2626 2627 #endif 2628 2629 /*****************************************************************************\ 2630 * * 2631 * Device allocation/registration * 2632 * * 2633 \*****************************************************************************/ 2634 2635 struct sdhci_host *sdhci_alloc_host(struct device *dev, 2636 size_t priv_size) 2637 { 2638 struct mmc_host *mmc; 2639 struct sdhci_host *host; 2640 2641 WARN_ON(dev == NULL); 2642 2643 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); 2644 if (!mmc) 2645 return ERR_PTR(-ENOMEM); 2646 2647 host = mmc_priv(mmc); 2648 host->mmc = mmc; 2649 2650 return host; 2651 } 2652 2653 EXPORT_SYMBOL_GPL(sdhci_alloc_host); 2654 2655 int sdhci_add_host(struct sdhci_host *host) 2656 { 2657 struct mmc_host *mmc; 2658 u32 caps[2] = {0, 0}; 2659 u32 max_current_caps; 2660 unsigned int ocr_avail; 2661 int ret; 2662 2663 WARN_ON(host == NULL); 2664 if (host == NULL) 2665 return -EINVAL; 2666 2667 mmc = host->mmc; 2668 2669 if (debug_quirks) 2670 host->quirks = debug_quirks; 2671 if (debug_quirks2) 2672 host->quirks2 = debug_quirks2; 2673 2674 sdhci_reset(host, SDHCI_RESET_ALL); 2675 2676 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 2677 host->version = (host->version & SDHCI_SPEC_VER_MASK) 2678 >> SDHCI_SPEC_VER_SHIFT; 2679 if (host->version > SDHCI_SPEC_300) { 2680 pr_err("%s: Unknown controller version (%d). " 2681 "You may experience problems.\n", mmc_hostname(mmc), 2682 host->version); 2683 } 2684 2685 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : 2686 sdhci_readl(host, SDHCI_CAPABILITIES); 2687 2688 if (host->version >= SDHCI_SPEC_300) 2689 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? 2690 host->caps1 : 2691 sdhci_readl(host, SDHCI_CAPABILITIES_1); 2692 2693 if (host->quirks & SDHCI_QUIRK_FORCE_DMA) 2694 host->flags |= SDHCI_USE_SDMA; 2695 else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) 2696 DBG("Controller doesn't have SDMA capability\n"); 2697 else 2698 host->flags |= SDHCI_USE_SDMA; 2699 2700 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && 2701 (host->flags & SDHCI_USE_SDMA)) { 2702 DBG("Disabling DMA as it is marked broken\n"); 2703 host->flags &= ~SDHCI_USE_SDMA; 2704 } 2705 2706 if ((host->version >= SDHCI_SPEC_200) && 2707 (caps[0] & SDHCI_CAN_DO_ADMA2)) 2708 host->flags |= SDHCI_USE_ADMA; 2709 2710 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && 2711 (host->flags & SDHCI_USE_ADMA)) { 2712 DBG("Disabling ADMA as it is marked broken\n"); 2713 host->flags &= ~SDHCI_USE_ADMA; 2714 } 2715 2716 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { 2717 if (host->ops->enable_dma) { 2718 if (host->ops->enable_dma(host)) { 2719 pr_warning("%s: No suitable DMA " 2720 "available. Falling back to PIO.\n", 2721 mmc_hostname(mmc)); 2722 host->flags &= 2723 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); 2724 } 2725 } 2726 } 2727 2728 if (host->flags & SDHCI_USE_ADMA) { 2729 /* 2730 * We need to allocate descriptors for all sg entries 2731 * (128) and potentially one alignment transfer for 2732 * each of those entries. 2733 */ 2734 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); 2735 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); 2736 if (!host->adma_desc || !host->align_buffer) { 2737 kfree(host->adma_desc); 2738 kfree(host->align_buffer); 2739 pr_warning("%s: Unable to allocate ADMA " 2740 "buffers. Falling back to standard DMA.\n", 2741 mmc_hostname(mmc)); 2742 host->flags &= ~SDHCI_USE_ADMA; 2743 } 2744 } 2745 2746 /* 2747 * If we use DMA, then it's up to the caller to set the DMA 2748 * mask, but PIO does not need the hw shim so we set a new 2749 * mask here in that case. 2750 */ 2751 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { 2752 host->dma_mask = DMA_BIT_MASK(64); 2753 mmc_dev(host->mmc)->dma_mask = &host->dma_mask; 2754 } 2755 2756 if (host->version >= SDHCI_SPEC_300) 2757 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) 2758 >> SDHCI_CLOCK_BASE_SHIFT; 2759 else 2760 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) 2761 >> SDHCI_CLOCK_BASE_SHIFT; 2762 2763 host->max_clk *= 1000000; 2764 if (host->max_clk == 0 || host->quirks & 2765 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { 2766 if (!host->ops->get_max_clock) { 2767 pr_err("%s: Hardware doesn't specify base clock " 2768 "frequency.\n", mmc_hostname(mmc)); 2769 return -ENODEV; 2770 } 2771 host->max_clk = host->ops->get_max_clock(host); 2772 } 2773 2774 /* 2775 * In case of Host Controller v3.00, find out whether clock 2776 * multiplier is supported. 2777 */ 2778 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> 2779 SDHCI_CLOCK_MUL_SHIFT; 2780 2781 /* 2782 * In case the value in Clock Multiplier is 0, then programmable 2783 * clock mode is not supported, otherwise the actual clock 2784 * multiplier is one more than the value of Clock Multiplier 2785 * in the Capabilities Register. 2786 */ 2787 if (host->clk_mul) 2788 host->clk_mul += 1; 2789 2790 /* 2791 * Set host parameters. 2792 */ 2793 mmc->ops = &sdhci_ops; 2794 mmc->f_max = host->max_clk; 2795 if (host->ops->get_min_clock) 2796 mmc->f_min = host->ops->get_min_clock(host); 2797 else if (host->version >= SDHCI_SPEC_300) { 2798 if (host->clk_mul) { 2799 mmc->f_min = (host->max_clk * host->clk_mul) / 1024; 2800 mmc->f_max = host->max_clk * host->clk_mul; 2801 } else 2802 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; 2803 } else 2804 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; 2805 2806 host->timeout_clk = 2807 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; 2808 if (host->timeout_clk == 0) { 2809 if (host->ops->get_timeout_clock) { 2810 host->timeout_clk = host->ops->get_timeout_clock(host); 2811 } else if (!(host->quirks & 2812 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { 2813 pr_err("%s: Hardware doesn't specify timeout clock " 2814 "frequency.\n", mmc_hostname(mmc)); 2815 return -ENODEV; 2816 } 2817 } 2818 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) 2819 host->timeout_clk *= 1000; 2820 2821 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) 2822 host->timeout_clk = mmc->f_max / 1000; 2823 2824 mmc->max_discard_to = (1 << 27) / host->timeout_clk; 2825 2826 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; 2827 2828 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) 2829 host->flags |= SDHCI_AUTO_CMD12; 2830 2831 /* Auto-CMD23 stuff only works in ADMA or PIO. */ 2832 if ((host->version >= SDHCI_SPEC_300) && 2833 ((host->flags & SDHCI_USE_ADMA) || 2834 !(host->flags & SDHCI_USE_SDMA))) { 2835 host->flags |= SDHCI_AUTO_CMD23; 2836 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); 2837 } else { 2838 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); 2839 } 2840 2841 /* 2842 * A controller may support 8-bit width, but the board itself 2843 * might not have the pins brought out. Boards that support 2844 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in 2845 * their platform code before calling sdhci_add_host(), and we 2846 * won't assume 8-bit width for hosts without that CAP. 2847 */ 2848 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) 2849 mmc->caps |= MMC_CAP_4_BIT_DATA; 2850 2851 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) 2852 mmc->caps &= ~MMC_CAP_CMD23; 2853 2854 if (caps[0] & SDHCI_CAN_DO_HISPD) 2855 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 2856 2857 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && 2858 !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) 2859 mmc->caps |= MMC_CAP_NEEDS_POLL; 2860 2861 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ 2862 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc"); 2863 if (IS_ERR_OR_NULL(host->vqmmc)) { 2864 if (PTR_ERR(host->vqmmc) < 0) { 2865 pr_info("%s: no vqmmc regulator found\n", 2866 mmc_hostname(mmc)); 2867 host->vqmmc = NULL; 2868 } 2869 } else { 2870 regulator_enable(host->vqmmc); 2871 if (!regulator_is_supported_voltage(host->vqmmc, 1700000, 2872 1950000)) 2873 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | 2874 SDHCI_SUPPORT_SDR50 | 2875 SDHCI_SUPPORT_DDR50); 2876 } 2877 2878 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) 2879 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2880 SDHCI_SUPPORT_DDR50); 2881 2882 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ 2883 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | 2884 SDHCI_SUPPORT_DDR50)) 2885 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 2886 2887 /* SDR104 supports also implies SDR50 support */ 2888 if (caps[1] & SDHCI_SUPPORT_SDR104) 2889 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; 2890 else if (caps[1] & SDHCI_SUPPORT_SDR50) 2891 mmc->caps |= MMC_CAP_UHS_SDR50; 2892 2893 if (caps[1] & SDHCI_SUPPORT_DDR50) 2894 mmc->caps |= MMC_CAP_UHS_DDR50; 2895 2896 /* Does the host need tuning for SDR50? */ 2897 if (caps[1] & SDHCI_USE_SDR50_TUNING) 2898 host->flags |= SDHCI_SDR50_NEEDS_TUNING; 2899 2900 /* Does the host need tuning for HS200? */ 2901 if (mmc->caps2 & MMC_CAP2_HS200) 2902 host->flags |= SDHCI_HS200_NEEDS_TUNING; 2903 2904 /* Driver Type(s) (A, C, D) supported by the host */ 2905 if (caps[1] & SDHCI_DRIVER_TYPE_A) 2906 mmc->caps |= MMC_CAP_DRIVER_TYPE_A; 2907 if (caps[1] & SDHCI_DRIVER_TYPE_C) 2908 mmc->caps |= MMC_CAP_DRIVER_TYPE_C; 2909 if (caps[1] & SDHCI_DRIVER_TYPE_D) 2910 mmc->caps |= MMC_CAP_DRIVER_TYPE_D; 2911 2912 /* Initial value for re-tuning timer count */ 2913 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> 2914 SDHCI_RETUNING_TIMER_COUNT_SHIFT; 2915 2916 /* 2917 * In case Re-tuning Timer is not disabled, the actual value of 2918 * re-tuning timer will be 2 ^ (n - 1). 2919 */ 2920 if (host->tuning_count) 2921 host->tuning_count = 1 << (host->tuning_count - 1); 2922 2923 /* Re-tuning mode supported by the Host Controller */ 2924 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> 2925 SDHCI_RETUNING_MODE_SHIFT; 2926 2927 ocr_avail = 0; 2928 2929 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); 2930 if (IS_ERR_OR_NULL(host->vmmc)) { 2931 if (PTR_ERR(host->vmmc) < 0) { 2932 pr_info("%s: no vmmc regulator found\n", 2933 mmc_hostname(mmc)); 2934 host->vmmc = NULL; 2935 } 2936 } 2937 2938 #ifdef CONFIG_REGULATOR 2939 if (host->vmmc) { 2940 ret = regulator_is_supported_voltage(host->vmmc, 2700000, 2941 3600000); 2942 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) 2943 caps[0] &= ~SDHCI_CAN_VDD_330; 2944 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) 2945 caps[0] &= ~SDHCI_CAN_VDD_300; 2946 ret = regulator_is_supported_voltage(host->vmmc, 1700000, 2947 1950000); 2948 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) 2949 caps[0] &= ~SDHCI_CAN_VDD_180; 2950 } 2951 #endif /* CONFIG_REGULATOR */ 2952 2953 /* 2954 * According to SD Host Controller spec v3.00, if the Host System 2955 * can afford more than 150mA, Host Driver should set XPC to 1. Also 2956 * the value is meaningful only if Voltage Support in the Capabilities 2957 * register is set. The actual current value is 4 times the register 2958 * value. 2959 */ 2960 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); 2961 if (!max_current_caps && host->vmmc) { 2962 u32 curr = regulator_get_current_limit(host->vmmc); 2963 if (curr > 0) { 2964 2965 /* convert to SDHCI_MAX_CURRENT format */ 2966 curr = curr/1000; /* convert to mA */ 2967 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; 2968 2969 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); 2970 max_current_caps = 2971 (curr << SDHCI_MAX_CURRENT_330_SHIFT) | 2972 (curr << SDHCI_MAX_CURRENT_300_SHIFT) | 2973 (curr << SDHCI_MAX_CURRENT_180_SHIFT); 2974 } 2975 } 2976 2977 if (caps[0] & SDHCI_CAN_VDD_330) { 2978 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; 2979 2980 mmc->max_current_330 = ((max_current_caps & 2981 SDHCI_MAX_CURRENT_330_MASK) >> 2982 SDHCI_MAX_CURRENT_330_SHIFT) * 2983 SDHCI_MAX_CURRENT_MULTIPLIER; 2984 } 2985 if (caps[0] & SDHCI_CAN_VDD_300) { 2986 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; 2987 2988 mmc->max_current_300 = ((max_current_caps & 2989 SDHCI_MAX_CURRENT_300_MASK) >> 2990 SDHCI_MAX_CURRENT_300_SHIFT) * 2991 SDHCI_MAX_CURRENT_MULTIPLIER; 2992 } 2993 if (caps[0] & SDHCI_CAN_VDD_180) { 2994 ocr_avail |= MMC_VDD_165_195; 2995 2996 mmc->max_current_180 = ((max_current_caps & 2997 SDHCI_MAX_CURRENT_180_MASK) >> 2998 SDHCI_MAX_CURRENT_180_SHIFT) * 2999 SDHCI_MAX_CURRENT_MULTIPLIER; 3000 } 3001 3002 mmc->ocr_avail = ocr_avail; 3003 mmc->ocr_avail_sdio = ocr_avail; 3004 if (host->ocr_avail_sdio) 3005 mmc->ocr_avail_sdio &= host->ocr_avail_sdio; 3006 mmc->ocr_avail_sd = ocr_avail; 3007 if (host->ocr_avail_sd) 3008 mmc->ocr_avail_sd &= host->ocr_avail_sd; 3009 else /* normal SD controllers don't support 1.8V */ 3010 mmc->ocr_avail_sd &= ~MMC_VDD_165_195; 3011 mmc->ocr_avail_mmc = ocr_avail; 3012 if (host->ocr_avail_mmc) 3013 mmc->ocr_avail_mmc &= host->ocr_avail_mmc; 3014 3015 if (mmc->ocr_avail == 0) { 3016 pr_err("%s: Hardware doesn't report any " 3017 "support voltages.\n", mmc_hostname(mmc)); 3018 return -ENODEV; 3019 } 3020 3021 spin_lock_init(&host->lock); 3022 3023 /* 3024 * Maximum number of segments. Depends on if the hardware 3025 * can do scatter/gather or not. 3026 */ 3027 if (host->flags & SDHCI_USE_ADMA) 3028 mmc->max_segs = 128; 3029 else if (host->flags & SDHCI_USE_SDMA) 3030 mmc->max_segs = 1; 3031 else /* PIO */ 3032 mmc->max_segs = 128; 3033 3034 /* 3035 * Maximum number of sectors in one transfer. Limited by DMA boundary 3036 * size (512KiB). 3037 */ 3038 mmc->max_req_size = 524288; 3039 3040 /* 3041 * Maximum segment size. Could be one segment with the maximum number 3042 * of bytes. When doing hardware scatter/gather, each entry cannot 3043 * be larger than 64 KiB though. 3044 */ 3045 if (host->flags & SDHCI_USE_ADMA) { 3046 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) 3047 mmc->max_seg_size = 65535; 3048 else 3049 mmc->max_seg_size = 65536; 3050 } else { 3051 mmc->max_seg_size = mmc->max_req_size; 3052 } 3053 3054 /* 3055 * Maximum block size. This varies from controller to controller and 3056 * is specified in the capabilities register. 3057 */ 3058 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { 3059 mmc->max_blk_size = 2; 3060 } else { 3061 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> 3062 SDHCI_MAX_BLOCK_SHIFT; 3063 if (mmc->max_blk_size >= 3) { 3064 pr_warning("%s: Invalid maximum block size, " 3065 "assuming 512 bytes\n", mmc_hostname(mmc)); 3066 mmc->max_blk_size = 0; 3067 } 3068 } 3069 3070 mmc->max_blk_size = 512 << mmc->max_blk_size; 3071 3072 /* 3073 * Maximum block count. 3074 */ 3075 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; 3076 3077 /* 3078 * Init tasklets. 3079 */ 3080 tasklet_init(&host->card_tasklet, 3081 sdhci_tasklet_card, (unsigned long)host); 3082 tasklet_init(&host->finish_tasklet, 3083 sdhci_tasklet_finish, (unsigned long)host); 3084 3085 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); 3086 3087 if (host->version >= SDHCI_SPEC_300) { 3088 init_waitqueue_head(&host->buf_ready_int); 3089 3090 /* Initialize re-tuning timer */ 3091 init_timer(&host->tuning_timer); 3092 host->tuning_timer.data = (unsigned long)host; 3093 host->tuning_timer.function = sdhci_tuning_timer; 3094 } 3095 3096 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, 3097 mmc_hostname(mmc), host); 3098 if (ret) { 3099 pr_err("%s: Failed to request IRQ %d: %d\n", 3100 mmc_hostname(mmc), host->irq, ret); 3101 goto untasklet; 3102 } 3103 3104 sdhci_init(host, 0); 3105 3106 #ifdef CONFIG_MMC_DEBUG 3107 sdhci_dumpregs(host); 3108 #endif 3109 3110 #ifdef SDHCI_USE_LEDS_CLASS 3111 snprintf(host->led_name, sizeof(host->led_name), 3112 "%s::", mmc_hostname(mmc)); 3113 host->led.name = host->led_name; 3114 host->led.brightness = LED_OFF; 3115 host->led.default_trigger = mmc_hostname(mmc); 3116 host->led.brightness_set = sdhci_led_control; 3117 3118 ret = led_classdev_register(mmc_dev(mmc), &host->led); 3119 if (ret) { 3120 pr_err("%s: Failed to register LED device: %d\n", 3121 mmc_hostname(mmc), ret); 3122 goto reset; 3123 } 3124 #endif 3125 3126 mmiowb(); 3127 3128 mmc_add_host(mmc); 3129 3130 pr_info("%s: SDHCI controller on %s [%s] using %s\n", 3131 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), 3132 (host->flags & SDHCI_USE_ADMA) ? "ADMA" : 3133 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); 3134 3135 sdhci_enable_card_detection(host); 3136 3137 return 0; 3138 3139 #ifdef SDHCI_USE_LEDS_CLASS 3140 reset: 3141 sdhci_reset(host, SDHCI_RESET_ALL); 3142 free_irq(host->irq, host); 3143 #endif 3144 untasklet: 3145 tasklet_kill(&host->card_tasklet); 3146 tasklet_kill(&host->finish_tasklet); 3147 3148 return ret; 3149 } 3150 3151 EXPORT_SYMBOL_GPL(sdhci_add_host); 3152 3153 void sdhci_remove_host(struct sdhci_host *host, int dead) 3154 { 3155 unsigned long flags; 3156 3157 if (dead) { 3158 spin_lock_irqsave(&host->lock, flags); 3159 3160 host->flags |= SDHCI_DEVICE_DEAD; 3161 3162 if (host->mrq) { 3163 pr_err("%s: Controller removed during " 3164 " transfer!\n", mmc_hostname(host->mmc)); 3165 3166 host->mrq->cmd->error = -ENOMEDIUM; 3167 tasklet_schedule(&host->finish_tasklet); 3168 } 3169 3170 spin_unlock_irqrestore(&host->lock, flags); 3171 } 3172 3173 sdhci_disable_card_detection(host); 3174 3175 mmc_remove_host(host->mmc); 3176 3177 #ifdef SDHCI_USE_LEDS_CLASS 3178 led_classdev_unregister(&host->led); 3179 #endif 3180 3181 if (!dead) 3182 sdhci_reset(host, SDHCI_RESET_ALL); 3183 3184 free_irq(host->irq, host); 3185 3186 del_timer_sync(&host->timer); 3187 3188 tasklet_kill(&host->card_tasklet); 3189 tasklet_kill(&host->finish_tasklet); 3190 3191 if (host->vmmc) { 3192 regulator_disable(host->vmmc); 3193 regulator_put(host->vmmc); 3194 } 3195 3196 if (host->vqmmc) { 3197 regulator_disable(host->vqmmc); 3198 regulator_put(host->vqmmc); 3199 } 3200 3201 kfree(host->adma_desc); 3202 kfree(host->align_buffer); 3203 3204 host->adma_desc = NULL; 3205 host->align_buffer = NULL; 3206 } 3207 3208 EXPORT_SYMBOL_GPL(sdhci_remove_host); 3209 3210 void sdhci_free_host(struct sdhci_host *host) 3211 { 3212 mmc_free_host(host->mmc); 3213 } 3214 3215 EXPORT_SYMBOL_GPL(sdhci_free_host); 3216 3217 /*****************************************************************************\ 3218 * * 3219 * Driver init/exit * 3220 * * 3221 \*****************************************************************************/ 3222 3223 static int __init sdhci_drv_init(void) 3224 { 3225 pr_info(DRIVER_NAME 3226 ": Secure Digital Host Controller Interface driver\n"); 3227 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); 3228 3229 return 0; 3230 } 3231 3232 static void __exit sdhci_drv_exit(void) 3233 { 3234 } 3235 3236 module_init(sdhci_drv_init); 3237 module_exit(sdhci_drv_exit); 3238 3239 module_param(debug_quirks, uint, 0444); 3240 module_param(debug_quirks2, uint, 0444); 3241 3242 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 3243 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); 3244 MODULE_LICENSE("GPL"); 3245 3246 MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); 3247 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); 3248