1 /* 2 * Driver for Marvell Xenon SDHC as a platform device 3 * 4 * Copyright (C) 2016 Marvell, All Rights Reserved. 5 * 6 * Author: Hu Ziji <huziji@marvell.com> 7 * Date: 2016-8-24 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * Inspired by Jisheng Zhang <jszhang@marvell.com> 14 * Special thanks to Video BG4 project team. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/ktime.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 22 #include "sdhci-pltfm.h" 23 #include "sdhci-xenon.h" 24 25 static int xenon_enable_internal_clk(struct sdhci_host *host) 26 { 27 u32 reg; 28 ktime_t timeout; 29 30 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 31 reg |= SDHCI_CLOCK_INT_EN; 32 sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); 33 /* Wait max 20 ms */ 34 timeout = ktime_add_ms(ktime_get(), 20); 35 while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 36 & SDHCI_CLOCK_INT_STABLE)) { 37 if (ktime_after(ktime_get(), timeout)) { 38 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); 39 return -ETIMEDOUT; 40 } 41 usleep_range(900, 1100); 42 } 43 44 return 0; 45 } 46 47 /* Set SDCLK-off-while-idle */ 48 static void xenon_set_sdclk_off_idle(struct sdhci_host *host, 49 unsigned char sdhc_id, bool enable) 50 { 51 u32 reg; 52 u32 mask; 53 54 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); 55 /* Get the bit shift basing on the SDHC index */ 56 mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id)); 57 if (enable) 58 reg |= mask; 59 else 60 reg &= ~mask; 61 62 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); 63 } 64 65 /* Enable/Disable the Auto Clock Gating function */ 66 static void xenon_set_acg(struct sdhci_host *host, bool enable) 67 { 68 u32 reg; 69 70 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); 71 if (enable) 72 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK; 73 else 74 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK; 75 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); 76 } 77 78 /* Enable this SDHC */ 79 static void xenon_enable_sdhc(struct sdhci_host *host, 80 unsigned char sdhc_id) 81 { 82 u32 reg; 83 84 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); 85 reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); 86 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); 87 88 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 89 /* 90 * Force to clear BUS_TEST to 91 * skip bus_test_pre and bus_test_post 92 */ 93 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; 94 } 95 96 /* Disable this SDHC */ 97 static void xenon_disable_sdhc(struct sdhci_host *host, 98 unsigned char sdhc_id) 99 { 100 u32 reg; 101 102 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); 103 reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); 104 sdhci_writel(host, reg, XENON_SYS_OP_CTRL); 105 } 106 107 /* Enable Parallel Transfer Mode */ 108 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host, 109 unsigned char sdhc_id) 110 { 111 u32 reg; 112 113 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); 114 reg |= BIT(sdhc_id); 115 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); 116 } 117 118 /* Mask command conflict error */ 119 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host) 120 { 121 u32 reg; 122 123 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); 124 reg |= XENON_MASK_CMD_CONFLICT_ERR; 125 sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); 126 } 127 128 static void xenon_retune_setup(struct sdhci_host *host) 129 { 130 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 131 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 132 u32 reg; 133 134 /* Disable the Re-Tuning Request functionality */ 135 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); 136 reg &= ~XENON_RETUNING_COMPATIBLE; 137 sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL); 138 139 /* Disable the Re-tuning Interrupt */ 140 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); 141 reg &= ~SDHCI_INT_RETUNE; 142 sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); 143 reg = sdhci_readl(host, SDHCI_INT_ENABLE); 144 reg &= ~SDHCI_INT_RETUNE; 145 sdhci_writel(host, reg, SDHCI_INT_ENABLE); 146 147 /* Force to use Tuning Mode 1 */ 148 host->tuning_mode = SDHCI_TUNING_MODE_1; 149 /* Set re-tuning period */ 150 host->tuning_count = 1 << (priv->tuning_count - 1); 151 } 152 153 /* 154 * Operations inside struct sdhci_ops 155 */ 156 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */ 157 static void xenon_reset_exit(struct sdhci_host *host, 158 unsigned char sdhc_id, u8 mask) 159 { 160 /* Only SOFTWARE RESET ALL will clear the register setting */ 161 if (!(mask & SDHCI_RESET_ALL)) 162 return; 163 164 /* Disable tuning request and auto-retuning again */ 165 xenon_retune_setup(host); 166 167 xenon_set_acg(host, true); 168 169 xenon_set_sdclk_off_idle(host, sdhc_id, false); 170 171 xenon_mask_cmd_conflict_err(host); 172 } 173 174 static void xenon_reset(struct sdhci_host *host, u8 mask) 175 { 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 178 179 sdhci_reset(host, mask); 180 xenon_reset_exit(host, priv->sdhc_id, mask); 181 } 182 183 /* 184 * Xenon defines different values for HS200 and HS400 185 * in Host_Control_2 186 */ 187 static void xenon_set_uhs_signaling(struct sdhci_host *host, 188 unsigned int timing) 189 { 190 u16 ctrl_2; 191 192 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 193 /* Select Bus Speed Mode for host */ 194 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 195 if (timing == MMC_TIMING_MMC_HS200) 196 ctrl_2 |= XENON_CTRL_HS200; 197 else if (timing == MMC_TIMING_UHS_SDR104) 198 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 199 else if (timing == MMC_TIMING_UHS_SDR12) 200 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 201 else if (timing == MMC_TIMING_UHS_SDR25) 202 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 203 else if (timing == MMC_TIMING_UHS_SDR50) 204 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 205 else if ((timing == MMC_TIMING_UHS_DDR50) || 206 (timing == MMC_TIMING_MMC_DDR52)) 207 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 208 else if (timing == MMC_TIMING_MMC_HS400) 209 ctrl_2 |= XENON_CTRL_HS400; 210 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 211 } 212 213 static void xenon_set_power(struct sdhci_host *host, unsigned char mode, 214 unsigned short vdd) 215 { 216 struct mmc_host *mmc = host->mmc; 217 u8 pwr = host->pwr; 218 219 sdhci_set_power_noreg(host, mode, vdd); 220 221 if (host->pwr == pwr) 222 return; 223 224 if (host->pwr == 0) 225 vdd = 0; 226 227 if (!IS_ERR(mmc->supply.vmmc)) 228 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 229 } 230 231 static const struct sdhci_ops sdhci_xenon_ops = { 232 .set_clock = sdhci_set_clock, 233 .set_power = xenon_set_power, 234 .set_bus_width = sdhci_set_bus_width, 235 .reset = xenon_reset, 236 .set_uhs_signaling = xenon_set_uhs_signaling, 237 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 238 }; 239 240 static const struct sdhci_pltfm_data sdhci_xenon_pdata = { 241 .ops = &sdhci_xenon_ops, 242 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 243 SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 244 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 245 }; 246 247 /* 248 * Xenon Specific Operations in mmc_host_ops 249 */ 250 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 251 { 252 struct sdhci_host *host = mmc_priv(mmc); 253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 254 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 255 u32 reg; 256 257 /* 258 * HS400/HS200/eMMC HS doesn't have Preset Value register. 259 * However, sdhci_set_ios will read HS400/HS200 Preset register. 260 * Disable Preset Value register for HS400/HS200. 261 * eMMC HS with preset_enabled set will trigger a bug in 262 * get_preset_value(). 263 */ 264 if ((ios->timing == MMC_TIMING_MMC_HS400) || 265 (ios->timing == MMC_TIMING_MMC_HS200) || 266 (ios->timing == MMC_TIMING_MMC_HS)) { 267 host->preset_enabled = false; 268 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 269 host->flags &= ~SDHCI_PV_ENABLED; 270 271 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); 272 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 273 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); 274 } else { 275 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 276 } 277 278 sdhci_set_ios(mmc, ios); 279 xenon_phy_adj(host, ios); 280 281 if (host->clock > XENON_DEFAULT_SDCLK_FREQ) 282 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true); 283 } 284 285 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc, 286 struct mmc_ios *ios) 287 { 288 struct sdhci_host *host = mmc_priv(mmc); 289 290 /* 291 * Before SD/SDIO set signal voltage, SD bus clock should be 292 * disabled. However, sdhci_set_clock will also disable the Internal 293 * clock in mmc_set_signal_voltage(). 294 * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated. 295 * Thus here manually enable internal clock. 296 * 297 * After switch completes, it is unnecessary to disable internal clock, 298 * since keeping internal clock active obeys SD spec. 299 */ 300 xenon_enable_internal_clk(host); 301 302 xenon_soc_pad_ctrl(host, ios->signal_voltage); 303 304 /* 305 * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable. 306 * Thus SDHCI_CTRL_VDD_180 bit might not work then. 307 * Skip the standard voltage switch to avoid any issue. 308 */ 309 if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV) 310 return 0; 311 312 return sdhci_start_signal_voltage_switch(mmc, ios); 313 } 314 315 /* 316 * Update card type. 317 * priv->init_card_type will be used in PHY timing adjustment. 318 */ 319 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card) 320 { 321 struct sdhci_host *host = mmc_priv(mmc); 322 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 323 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 324 325 /* Update card type*/ 326 priv->init_card_type = card->type; 327 } 328 329 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode) 330 { 331 struct sdhci_host *host = mmc_priv(mmc); 332 333 if (host->timing == MMC_TIMING_UHS_DDR50) 334 return 0; 335 336 /* 337 * Currently force Xenon driver back to support mode 1 only, 338 * even though Xenon might claim to support mode 2 or mode 3. 339 * It requires more time to test mode 2/mode 3 on more platforms. 340 */ 341 if (host->tuning_mode != SDHCI_TUNING_MODE_1) 342 xenon_retune_setup(host); 343 344 return sdhci_execute_tuning(mmc, opcode); 345 } 346 347 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable) 348 { 349 struct sdhci_host *host = mmc_priv(mmc); 350 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 351 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 352 u32 reg; 353 u8 sdhc_id = priv->sdhc_id; 354 355 sdhci_enable_sdio_irq(mmc, enable); 356 357 if (enable) { 358 /* 359 * Set SDIO Card Inserted indication 360 * to enable detecting SDIO async irq. 361 */ 362 reg = sdhci_readl(host, XENON_SYS_CFG_INFO); 363 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); 364 sdhci_writel(host, reg, XENON_SYS_CFG_INFO); 365 } else { 366 /* Clear SDIO Card Inserted indication */ 367 reg = sdhci_readl(host, XENON_SYS_CFG_INFO); 368 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); 369 sdhci_writel(host, reg, XENON_SYS_CFG_INFO); 370 } 371 } 372 373 static void xenon_replace_mmc_host_ops(struct sdhci_host *host) 374 { 375 host->mmc_host_ops.set_ios = xenon_set_ios; 376 host->mmc_host_ops.start_signal_voltage_switch = 377 xenon_start_signal_voltage_switch; 378 host->mmc_host_ops.init_card = xenon_init_card; 379 host->mmc_host_ops.execute_tuning = xenon_execute_tuning; 380 host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq; 381 } 382 383 /* 384 * Parse Xenon specific DT properties: 385 * sdhc-id: the index of current SDHC. 386 * Refer to XENON_SYS_CFG_INFO register 387 * tun-count: the interval between re-tuning 388 */ 389 static int xenon_probe_dt(struct platform_device *pdev) 390 { 391 struct device_node *np = pdev->dev.of_node; 392 struct sdhci_host *host = platform_get_drvdata(pdev); 393 struct mmc_host *mmc = host->mmc; 394 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 395 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 396 u32 sdhc_id, nr_sdhc; 397 u32 tuning_count; 398 399 /* Disable HS200 on Armada AP806 */ 400 if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci")) 401 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 402 403 sdhc_id = 0x0; 404 if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) { 405 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO); 406 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK; 407 if (unlikely(sdhc_id > nr_sdhc)) { 408 dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n", 409 sdhc_id, nr_sdhc); 410 return -EINVAL; 411 } 412 } 413 priv->sdhc_id = sdhc_id; 414 415 tuning_count = XENON_DEF_TUNING_COUNT; 416 if (!of_property_read_u32(np, "marvell,xenon-tun-count", 417 &tuning_count)) { 418 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) { 419 dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n", 420 XENON_DEF_TUNING_COUNT); 421 tuning_count = XENON_DEF_TUNING_COUNT; 422 } 423 } 424 priv->tuning_count = tuning_count; 425 426 return xenon_phy_parse_dt(np, host); 427 } 428 429 static int xenon_sdhc_prepare(struct sdhci_host *host) 430 { 431 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 432 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 433 u8 sdhc_id = priv->sdhc_id; 434 435 /* Enable SDHC */ 436 xenon_enable_sdhc(host, sdhc_id); 437 438 /* Enable ACG */ 439 xenon_set_acg(host, true); 440 441 /* Enable Parallel Transfer Mode */ 442 xenon_enable_sdhc_parallel_tran(host, sdhc_id); 443 444 /* Disable SDCLK-Off-While-Idle before card init */ 445 xenon_set_sdclk_off_idle(host, sdhc_id, false); 446 447 xenon_mask_cmd_conflict_err(host); 448 449 return 0; 450 } 451 452 static void xenon_sdhc_unprepare(struct sdhci_host *host) 453 { 454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 456 u8 sdhc_id = priv->sdhc_id; 457 458 /* disable SDHC */ 459 xenon_disable_sdhc(host, sdhc_id); 460 } 461 462 static int xenon_probe(struct platform_device *pdev) 463 { 464 struct sdhci_pltfm_host *pltfm_host; 465 struct sdhci_host *host; 466 struct xenon_priv *priv; 467 int err; 468 469 host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata, 470 sizeof(struct xenon_priv)); 471 if (IS_ERR(host)) 472 return PTR_ERR(host); 473 474 pltfm_host = sdhci_priv(host); 475 priv = sdhci_pltfm_priv(pltfm_host); 476 477 /* 478 * Link Xenon specific mmc_host_ops function, 479 * to replace standard ones in sdhci_ops. 480 */ 481 xenon_replace_mmc_host_ops(host); 482 483 pltfm_host->clk = devm_clk_get(&pdev->dev, "core"); 484 if (IS_ERR(pltfm_host->clk)) { 485 err = PTR_ERR(pltfm_host->clk); 486 dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err); 487 goto free_pltfm; 488 } 489 err = clk_prepare_enable(pltfm_host->clk); 490 if (err) 491 goto free_pltfm; 492 493 err = mmc_of_parse(host->mmc); 494 if (err) 495 goto err_clk; 496 497 sdhci_get_of_property(pdev); 498 499 xenon_set_acg(host, false); 500 501 /* Xenon specific dt parse */ 502 err = xenon_probe_dt(pdev); 503 if (err) 504 goto err_clk; 505 506 err = xenon_sdhc_prepare(host); 507 if (err) 508 goto err_clk; 509 510 err = sdhci_add_host(host); 511 if (err) 512 goto remove_sdhc; 513 514 return 0; 515 516 remove_sdhc: 517 xenon_sdhc_unprepare(host); 518 err_clk: 519 clk_disable_unprepare(pltfm_host->clk); 520 free_pltfm: 521 sdhci_pltfm_free(pdev); 522 return err; 523 } 524 525 static int xenon_remove(struct platform_device *pdev) 526 { 527 struct sdhci_host *host = platform_get_drvdata(pdev); 528 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 529 530 sdhci_remove_host(host, 0); 531 532 xenon_sdhc_unprepare(host); 533 534 clk_disable_unprepare(pltfm_host->clk); 535 536 sdhci_pltfm_free(pdev); 537 538 return 0; 539 } 540 541 static const struct of_device_id sdhci_xenon_dt_ids[] = { 542 { .compatible = "marvell,armada-ap806-sdhci",}, 543 { .compatible = "marvell,armada-cp110-sdhci",}, 544 { .compatible = "marvell,armada-3700-sdhci",}, 545 {} 546 }; 547 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); 548 549 static struct platform_driver sdhci_xenon_driver = { 550 .driver = { 551 .name = "xenon-sdhci", 552 .of_match_table = sdhci_xenon_dt_ids, 553 .pm = &sdhci_pltfm_pmops, 554 }, 555 .probe = xenon_probe, 556 .remove = xenon_remove, 557 }; 558 559 module_platform_driver(sdhci_xenon_driver); 560 561 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC"); 562 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>"); 563 MODULE_LICENSE("GPL v2"); 564