1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PHY support for Xenon SDHC 4 * 5 * Copyright (C) 2016 Marvell, All Rights Reserved. 6 * 7 * Author: Hu Ziji <huziji@marvell.com> 8 * Date: 2016-8-24 9 */ 10 11 #include <linux/slab.h> 12 #include <linux/delay.h> 13 #include <linux/ktime.h> 14 #include <linux/iopoll.h> 15 #include <linux/of_address.h> 16 17 #include "sdhci-pltfm.h" 18 #include "sdhci-xenon.h" 19 20 /* Register base for eMMC PHY 5.0 Version */ 21 #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160 22 /* Register base for eMMC PHY 5.1 Version */ 23 #define XENON_EMMC_PHY_REG_BASE 0x0170 24 25 #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE 26 #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE 27 #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) 28 #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) 29 #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) 30 #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 31 #define XENON_PHY_INITIALIZAION BIT(31) 32 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF 33 #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12 34 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF 35 #define XENON_FC_SYNC_EN_DURATION_SHIFT 8 36 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF 37 #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4 38 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF 39 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0 40 41 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4) 42 #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \ 43 (XENON_EMMC_5_0_PHY_REG_BASE + 0x4) 44 #define XENON_ASYNC_DDRMODE_MASK BIT(23) 45 #define XENON_ASYNC_DDRMODE_SHIFT 23 46 #define XENON_CMD_DDR_MODE BIT(16) 47 #define XENON_DQ_DDR_MODE_SHIFT 8 48 #define XENON_DQ_DDR_MODE_MASK 0xFF 49 #define XENON_DQ_ASYNC_MODE BIT(4) 50 51 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8) 52 #define XENON_EMMC_5_0_PHY_PAD_CONTROL \ 53 (XENON_EMMC_5_0_PHY_REG_BASE + 0x8) 54 #define XENON_REC_EN_SHIFT 24 55 #define XENON_REC_EN_MASK 0xF 56 #define XENON_FC_DQ_RECEN BIT(24) 57 #define XENON_FC_CMD_RECEN BIT(25) 58 #define XENON_FC_QSP_RECEN BIT(26) 59 #define XENON_FC_QSN_RECEN BIT(27) 60 #define XENON_OEN_QSN BIT(28) 61 #define XENON_AUTO_RECEN_CTRL BIT(30) 62 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000 63 64 #define XENON_EMMC5_FC_QSP_PD BIT(18) 65 #define XENON_EMMC5_FC_QSP_PU BIT(22) 66 #define XENON_EMMC5_FC_CMD_PD BIT(17) 67 #define XENON_EMMC5_FC_CMD_PU BIT(21) 68 #define XENON_EMMC5_FC_DQ_PD BIT(16) 69 #define XENON_EMMC5_FC_DQ_PU BIT(20) 70 71 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC) 72 #define XENON_EMMC5_1_FC_QSP_PD BIT(9) 73 #define XENON_EMMC5_1_FC_QSP_PU BIT(25) 74 #define XENON_EMMC5_1_FC_CMD_PD BIT(8) 75 #define XENON_EMMC5_1_FC_CMD_PU BIT(24) 76 #define XENON_EMMC5_1_FC_DQ_PD 0xFF 77 #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16) 78 79 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10) 80 #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \ 81 (XENON_EMMC_5_0_PHY_REG_BASE + 0xC) 82 #define XENON_ZNR_MASK 0x1F 83 #define XENON_ZNR_SHIFT 8 84 #define XENON_ZPR_MASK 0x1F 85 /* Preferred ZNR and ZPR value vary between different boards. 86 * The specific ZNR and ZPR value should be defined here 87 * according to board actual timing. 88 */ 89 #define XENON_ZNR_DEF_VALUE 0xF 90 #define XENON_ZPR_DEF_VALUE 0xF 91 92 #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14) 93 #define XENON_EMMC_5_0_PHY_DLL_CONTROL \ 94 (XENON_EMMC_5_0_PHY_REG_BASE + 0x10) 95 #define XENON_DLL_ENABLE BIT(31) 96 #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) 97 #define XENON_DLL_REFCLK_SEL BIT(30) 98 #define XENON_DLL_UPDATE BIT(23) 99 #define XENON_DLL_PHSEL1_SHIFT 24 100 #define XENON_DLL_PHSEL0_SHIFT 16 101 #define XENON_DLL_PHASE_MASK 0x3F 102 #define XENON_DLL_PHASE_90_DEGREE 0x1F 103 #define XENON_DLL_FAST_LOCK BIT(5) 104 #define XENON_DLL_GAIN2X BIT(3) 105 #define XENON_DLL_BYPASS_EN BIT(0) 106 107 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \ 108 (XENON_EMMC_5_0_PHY_REG_BASE + 0x14) 109 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54 110 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) 111 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 112 113 /* 114 * List offset of PHY registers and some special register values 115 * in eMMC PHY 5.0 or eMMC PHY 5.1 116 */ 117 struct xenon_emmc_phy_regs { 118 /* Offset of Timing Adjust register */ 119 u16 timing_adj; 120 /* Offset of Func Control register */ 121 u16 func_ctrl; 122 /* Offset of Pad Control register */ 123 u16 pad_ctrl; 124 /* Offset of Pad Control register 2 */ 125 u16 pad_ctrl2; 126 /* Offset of DLL Control register */ 127 u16 dll_ctrl; 128 /* Offset of Logic Timing Adjust register */ 129 u16 logic_timing_adj; 130 /* DLL Update Enable bit */ 131 u32 dll_update; 132 /* value in Logic Timing Adjustment register */ 133 u32 logic_timing_val; 134 }; 135 136 static const char * const phy_types[] = { 137 "emmc 5.0 phy", 138 "emmc 5.1 phy" 139 }; 140 141 enum xenon_phy_type_enum { 142 EMMC_5_0_PHY, 143 EMMC_5_1_PHY, 144 NR_PHY_TYPES 145 }; 146 147 enum soc_pad_ctrl_type { 148 SOC_PAD_SD, 149 SOC_PAD_FIXED_1_8V, 150 }; 151 152 struct soc_pad_ctrl { 153 /* Register address of SoC PHY PAD ctrl */ 154 void __iomem *reg; 155 /* SoC PHY PAD ctrl type */ 156 enum soc_pad_ctrl_type pad_type; 157 /* SoC specific operation to set SoC PHY PAD */ 158 void (*set_soc_pad)(struct sdhci_host *host, 159 unsigned char signal_voltage); 160 }; 161 162 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = { 163 .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST, 164 .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL, 165 .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL, 166 .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2, 167 .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL, 168 .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST, 169 .dll_update = XENON_DLL_UPDATE_STROBE_5_0, 170 .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE, 171 }; 172 173 static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = { 174 .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST, 175 .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL, 176 .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL, 177 .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2, 178 .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL, 179 .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, 180 .dll_update = XENON_DLL_UPDATE, 181 .logic_timing_val = XENON_LOGIC_TIMING_VALUE, 182 }; 183 184 /* 185 * eMMC PHY configuration and operations 186 */ 187 struct xenon_emmc_phy_params { 188 bool slow_mode; 189 190 u8 znr; 191 u8 zpr; 192 193 /* Nr of consecutive Sampling Points of a Valid Sampling Window */ 194 u8 nr_tun_times; 195 /* Divider for calculating Tuning Step */ 196 u8 tun_step_divider; 197 198 struct soc_pad_ctrl pad_ctrl; 199 }; 200 201 static int xenon_alloc_emmc_phy(struct sdhci_host *host) 202 { 203 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 204 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 205 struct xenon_emmc_phy_params *params; 206 207 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); 208 if (!params) 209 return -ENOMEM; 210 211 priv->phy_params = params; 212 if (priv->phy_type == EMMC_5_0_PHY) 213 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; 214 else 215 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; 216 217 return 0; 218 } 219 220 static int xenon_check_stability_internal_clk(struct sdhci_host *host) 221 { 222 u32 reg; 223 int err; 224 225 err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE, 226 1100, 20000, false, host, SDHCI_CLOCK_CONTROL); 227 if (err) 228 dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); 229 230 return err; 231 } 232 233 /* 234 * eMMC 5.0/5.1 PHY init/re-init. 235 * eMMC PHY init should be executed after: 236 * 1. SDCLK frequency changes. 237 * 2. SDCLK is stopped and re-enabled. 238 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl 239 * are changed 240 */ 241 static int xenon_emmc_phy_init(struct sdhci_host *host) 242 { 243 u32 reg; 244 u32 wait, clock; 245 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 246 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 247 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 248 249 int ret = xenon_check_stability_internal_clk(host); 250 251 if (ret) 252 return ret; 253 254 reg = sdhci_readl(host, phy_regs->timing_adj); 255 reg |= XENON_PHY_INITIALIZAION; 256 sdhci_writel(host, reg, phy_regs->timing_adj); 257 258 /* Add duration of FC_SYNC_RST */ 259 wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) & 260 XENON_FC_SYNC_RST_DURATION_MASK); 261 /* Add interval between FC_SYNC_EN and FC_SYNC_RST */ 262 wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) & 263 XENON_FC_SYNC_RST_EN_DURATION_MASK); 264 /* Add duration of asserting FC_SYNC_EN */ 265 wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) & 266 XENON_FC_SYNC_EN_DURATION_MASK); 267 /* Add duration of waiting for PHY */ 268 wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) & 269 XENON_WAIT_CYCLE_BEFORE_USING_MASK); 270 /* 4 additional bus clock and 4 AXI bus clock are required */ 271 wait += 8; 272 wait <<= 20; 273 274 clock = host->clock; 275 if (!clock) 276 /* Use the possibly slowest bus frequency value */ 277 clock = XENON_LOWEST_SDCLK_FREQ; 278 /* get the wait time */ 279 wait /= clock; 280 wait++; 281 /* wait for host eMMC PHY init completes */ 282 udelay(wait); 283 284 reg = sdhci_readl(host, phy_regs->timing_adj); 285 reg &= XENON_PHY_INITIALIZAION; 286 if (reg) { 287 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", 288 wait); 289 return -ETIMEDOUT; 290 } 291 292 return 0; 293 } 294 295 #define ARMADA_3700_SOC_PAD_1_8V 0x1 296 #define ARMADA_3700_SOC_PAD_3_3V 0x0 297 298 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, 299 unsigned char signal_voltage) 300 { 301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 302 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 303 struct xenon_emmc_phy_params *params = priv->phy_params; 304 305 if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { 306 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 307 } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { 308 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) 309 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); 310 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 311 writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); 312 } 313 } 314 315 /* 316 * Set SoC PHY voltage PAD control register, 317 * according to the operation voltage on PAD. 318 * The detailed operation depends on SoC implementation. 319 */ 320 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, 321 unsigned char signal_voltage) 322 { 323 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 324 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 325 struct xenon_emmc_phy_params *params = priv->phy_params; 326 327 if (!params->pad_ctrl.reg) 328 return; 329 330 if (params->pad_ctrl.set_soc_pad) 331 params->pad_ctrl.set_soc_pad(host, signal_voltage); 332 } 333 334 /* 335 * Enable eMMC PHY HW DLL 336 * DLL should be enabled and stable before HS200/SDR104 tuning, 337 * and before HS400 data strobe setting. 338 */ 339 static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) 340 { 341 u32 reg; 342 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 343 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 344 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 345 ktime_t timeout; 346 347 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR)) 348 return -EINVAL; 349 350 reg = sdhci_readl(host, phy_regs->dll_ctrl); 351 if (reg & XENON_DLL_ENABLE) 352 return 0; 353 354 /* Enable DLL */ 355 reg = sdhci_readl(host, phy_regs->dll_ctrl); 356 reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); 357 358 /* 359 * Set Phase as 90 degree, which is most common value. 360 * Might set another value if necessary. 361 * The granularity is 1 degree. 362 */ 363 reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | 364 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT)); 365 reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | 366 (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT)); 367 368 reg &= ~XENON_DLL_BYPASS_EN; 369 reg |= phy_regs->dll_update; 370 if (priv->phy_type == EMMC_5_1_PHY) 371 reg &= ~XENON_DLL_REFCLK_SEL; 372 sdhci_writel(host, reg, phy_regs->dll_ctrl); 373 374 /* Wait max 32 ms */ 375 timeout = ktime_add_ms(ktime_get(), 32); 376 while (1) { 377 bool timedout = ktime_after(ktime_get(), timeout); 378 379 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & 380 XENON_DLL_LOCK_STATE) 381 break; 382 if (timedout) { 383 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); 384 return -ETIMEDOUT; 385 } 386 udelay(100); 387 } 388 return 0; 389 } 390 391 /* 392 * Config to eMMC PHY to prepare for tuning. 393 * Enable HW DLL and set the TUNING_STEP 394 */ 395 static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) 396 { 397 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 398 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 399 struct xenon_emmc_phy_params *params = priv->phy_params; 400 u32 reg, tuning_step; 401 int ret; 402 403 if (host->clock <= MMC_HIGH_52_MAX_DTR) 404 return -EINVAL; 405 406 ret = xenon_emmc_phy_enable_dll(host); 407 if (ret) 408 return ret; 409 410 /* Achieve TUNING_STEP with HW DLL help */ 411 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); 412 tuning_step = reg / params->tun_step_divider; 413 if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) { 414 dev_warn(mmc_dev(host->mmc), 415 "HS200 TUNING_STEP %d is larger than MAX value\n", 416 tuning_step); 417 tuning_step = XENON_TUNING_STEP_MASK; 418 } 419 420 /* Set TUNING_STEP for later tuning */ 421 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); 422 reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << 423 XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 424 reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); 425 reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); 426 reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); 427 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); 428 429 return 0; 430 } 431 432 static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host) 433 { 434 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 435 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 436 u32 reg; 437 438 /* Disable both SDHC Data Strobe and Enhanced Strobe */ 439 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 440 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); 441 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 442 443 /* Clear Strobe line Pull down or Pull up */ 444 if (priv->phy_type == EMMC_5_0_PHY) { 445 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 446 reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU); 447 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 448 } else { 449 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 450 reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU); 451 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 452 } 453 } 454 455 /* Set HS400 Data Strobe and Enhanced Strobe */ 456 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host) 457 { 458 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 459 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 460 u32 reg; 461 462 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) 463 return; 464 465 if (host->clock <= MMC_HIGH_52_MAX_DTR) 466 return; 467 468 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); 469 470 xenon_emmc_phy_enable_dll(host); 471 472 /* Enable SDHC Data Strobe */ 473 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); 474 reg |= XENON_ENABLE_DATA_STROBE; 475 /* 476 * Enable SDHC Enhanced Strobe if supported 477 * Xenon Enhanced Strobe should be enabled only when 478 * 1. card is in HS400 mode and 479 * 2. SDCLK is higher than 52MHz 480 * 3. DLL is enabled 481 */ 482 if (host->mmc->ios.enhanced_strobe) 483 reg |= XENON_ENABLE_RESP_STROBE; 484 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); 485 486 /* Set Data Strobe Pull down */ 487 if (priv->phy_type == EMMC_5_0_PHY) { 488 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 489 reg |= XENON_EMMC5_FC_QSP_PD; 490 reg &= ~XENON_EMMC5_FC_QSP_PU; 491 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 492 } else { 493 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 494 reg |= XENON_EMMC5_1_FC_QSP_PD; 495 reg &= ~XENON_EMMC5_1_FC_QSP_PU; 496 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 497 } 498 } 499 500 /* 501 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) 502 * in SDR mode, enable Slow Mode to bypass eMMC PHY. 503 * SDIO slower SDR mode also requires Slow Mode. 504 * 505 * If Slow Mode is enabled, return true. 506 * Otherwise, return false. 507 */ 508 static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host, 509 unsigned char timing) 510 { 511 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 512 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 513 struct xenon_emmc_phy_params *params = priv->phy_params; 514 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 515 u32 reg; 516 int ret; 517 518 if (host->clock > MMC_HIGH_52_MAX_DTR) 519 return false; 520 521 reg = sdhci_readl(host, phy_regs->timing_adj); 522 /* When in slower SDR mode, enable Slow Mode for SDIO 523 * or when Slow Mode flag is set 524 */ 525 switch (timing) { 526 case MMC_TIMING_LEGACY: 527 /* 528 * If Slow Mode is required, enable Slow Mode by default 529 * in early init phase to avoid any potential issue. 530 */ 531 if (params->slow_mode) { 532 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 533 ret = true; 534 } else { 535 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 536 ret = false; 537 } 538 break; 539 case MMC_TIMING_UHS_SDR25: 540 case MMC_TIMING_UHS_SDR12: 541 case MMC_TIMING_SD_HS: 542 case MMC_TIMING_MMC_HS: 543 if ((priv->init_card_type == MMC_TYPE_SDIO) || 544 params->slow_mode) { 545 reg |= XENON_TIMING_ADJUST_SLOW_MODE; 546 ret = true; 547 break; 548 } 549 fallthrough; 550 default: 551 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; 552 ret = false; 553 } 554 555 sdhci_writel(host, reg, phy_regs->timing_adj); 556 return ret; 557 } 558 559 /* 560 * Set-up eMMC 5.0/5.1 PHY. 561 * Specific configuration depends on the current speed mode in use. 562 */ 563 static void xenon_emmc_phy_set(struct sdhci_host *host, 564 unsigned char timing) 565 { 566 u32 reg; 567 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 568 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 569 struct xenon_emmc_phy_params *params = priv->phy_params; 570 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; 571 572 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n"); 573 574 /* Setup pad, set bit[28] and bits[26:24] */ 575 reg = sdhci_readl(host, phy_regs->pad_ctrl); 576 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | 577 XENON_FC_QSP_RECEN | XENON_OEN_QSN); 578 /* All FC_XX_RECEIVCE should be set as CMOS Type */ 579 reg |= XENON_FC_ALL_CMOS_RECEIVER; 580 sdhci_writel(host, reg, phy_regs->pad_ctrl); 581 582 /* Set CMD and DQ Pull Up */ 583 if (priv->phy_type == EMMC_5_0_PHY) { 584 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); 585 reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU); 586 reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD); 587 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); 588 } else { 589 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); 590 reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU); 591 reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD); 592 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); 593 } 594 595 if (timing == MMC_TIMING_LEGACY) { 596 xenon_emmc_phy_slow_mode(host, timing); 597 goto phy_init; 598 } 599 600 /* 601 * If SDIO card, set SDIO Mode 602 * Otherwise, clear SDIO Mode 603 */ 604 reg = sdhci_readl(host, phy_regs->timing_adj); 605 if (priv->init_card_type == MMC_TYPE_SDIO) 606 reg |= XENON_TIMING_ADJUST_SDIO_MODE; 607 else 608 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; 609 sdhci_writel(host, reg, phy_regs->timing_adj); 610 611 if (xenon_emmc_phy_slow_mode(host, timing)) 612 goto phy_init; 613 614 /* 615 * Set preferred ZNR and ZPR value 616 * The ZNR and ZPR value vary between different boards. 617 * Define them both in sdhci-xenon-emmc-phy.h. 618 */ 619 reg = sdhci_readl(host, phy_regs->pad_ctrl2); 620 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); 621 reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); 622 sdhci_writel(host, reg, phy_regs->pad_ctrl2); 623 624 /* 625 * When setting EMMC_PHY_FUNC_CONTROL register, 626 * SD clock should be disabled 627 */ 628 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 629 reg &= ~SDHCI_CLOCK_CARD_EN; 630 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 631 632 reg = sdhci_readl(host, phy_regs->func_ctrl); 633 switch (timing) { 634 case MMC_TIMING_MMC_HS400: 635 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 636 XENON_CMD_DDR_MODE; 637 reg &= ~XENON_DQ_ASYNC_MODE; 638 break; 639 case MMC_TIMING_UHS_DDR50: 640 case MMC_TIMING_MMC_DDR52: 641 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 642 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; 643 break; 644 default: 645 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | 646 XENON_CMD_DDR_MODE); 647 reg |= XENON_DQ_ASYNC_MODE; 648 } 649 sdhci_writel(host, reg, phy_regs->func_ctrl); 650 651 /* Enable bus clock */ 652 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 653 reg |= SDHCI_CLOCK_CARD_EN; 654 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); 655 656 if (timing == MMC_TIMING_MMC_HS400) 657 /* Hardware team recommend a value for HS400 */ 658 sdhci_writel(host, phy_regs->logic_timing_val, 659 phy_regs->logic_timing_adj); 660 else 661 xenon_emmc_phy_disable_strobe(host); 662 663 phy_init: 664 xenon_emmc_phy_init(host); 665 666 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); 667 } 668 669 static int get_dt_pad_ctrl_data(struct sdhci_host *host, 670 struct device_node *np, 671 struct xenon_emmc_phy_params *params) 672 { 673 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 674 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 675 int ret = 0; 676 const char *name; 677 struct resource iomem; 678 679 if (priv->hw_version == XENON_A3700) 680 params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; 681 else 682 return 0; 683 684 if (of_address_to_resource(np, 1, &iomem)) { 685 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n", 686 np); 687 return -EINVAL; 688 } 689 690 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), 691 &iomem); 692 if (IS_ERR(params->pad_ctrl.reg)) 693 return PTR_ERR(params->pad_ctrl.reg); 694 695 ret = of_property_read_string(np, "marvell,pad-type", &name); 696 if (ret) { 697 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); 698 return ret; 699 } 700 if (!strcmp(name, "sd")) { 701 params->pad_ctrl.pad_type = SOC_PAD_SD; 702 } else if (!strcmp(name, "fixed-1-8v")) { 703 params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; 704 } else { 705 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", 706 name); 707 return -EINVAL; 708 } 709 710 return ret; 711 } 712 713 static int xenon_emmc_phy_parse_params(struct sdhci_host *host, 714 struct device *dev, 715 struct xenon_emmc_phy_params *params) 716 { 717 u32 value; 718 719 params->slow_mode = false; 720 if (device_property_read_bool(dev, "marvell,xenon-phy-slow-mode")) 721 params->slow_mode = true; 722 723 params->znr = XENON_ZNR_DEF_VALUE; 724 if (!device_property_read_u32(dev, "marvell,xenon-phy-znr", &value)) 725 params->znr = value & XENON_ZNR_MASK; 726 727 params->zpr = XENON_ZPR_DEF_VALUE; 728 if (!device_property_read_u32(dev, "marvell,xenon-phy-zpr", &value)) 729 params->zpr = value & XENON_ZPR_MASK; 730 731 params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES; 732 if (!device_property_read_u32(dev, "marvell,xenon-phy-nr-success-tun", 733 &value)) 734 params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK; 735 736 params->tun_step_divider = XENON_TUNING_STEP_DIVIDER; 737 if (!device_property_read_u32(dev, "marvell,xenon-phy-tun-step-divider", 738 &value)) 739 params->tun_step_divider = value & 0xFF; 740 741 if (dev->of_node) 742 return get_dt_pad_ctrl_data(host, dev->of_node, params); 743 return 0; 744 } 745 746 /* Set SoC PHY Voltage PAD */ 747 void xenon_soc_pad_ctrl(struct sdhci_host *host, 748 unsigned char signal_voltage) 749 { 750 xenon_emmc_phy_set_soc_pad(host, signal_voltage); 751 } 752 753 /* 754 * Setting PHY when card is working in High Speed Mode. 755 * HS400 set Data Strobe and Enhanced Strobe if it is supported. 756 * HS200/SDR104 set tuning config to prepare for tuning. 757 */ 758 static int xenon_hs_delay_adj(struct sdhci_host *host) 759 { 760 int ret = 0; 761 762 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ)) 763 return -EINVAL; 764 765 switch (host->timing) { 766 case MMC_TIMING_MMC_HS400: 767 xenon_emmc_phy_strobe_delay_adj(host); 768 return 0; 769 case MMC_TIMING_MMC_HS200: 770 case MMC_TIMING_UHS_SDR104: 771 return xenon_emmc_phy_config_tuning(host); 772 case MMC_TIMING_MMC_DDR52: 773 case MMC_TIMING_UHS_DDR50: 774 /* 775 * DDR Mode requires driver to scan Sampling Fixed Delay Line, 776 * to find out a perfect operation sampling point. 777 * It is hard to implement such a scan in host driver 778 * since initiating commands by host driver is not safe. 779 * Thus so far just keep PHY Sampling Fixed Delay in 780 * default value of DDR mode. 781 * 782 * If any timing issue occurs in DDR mode on Marvell products, 783 * please contact maintainer for internal support in Marvell. 784 */ 785 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n"); 786 return 0; 787 } 788 789 return ret; 790 } 791 792 /* 793 * Adjust PHY setting. 794 * PHY setting should be adjusted when SDCLK frequency, Bus Width 795 * or Speed Mode is changed. 796 * Additional config are required when card is working in High Speed mode, 797 * after leaving Legacy Mode. 798 */ 799 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios) 800 { 801 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 802 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 803 int ret = 0; 804 805 if (!host->clock) { 806 priv->clock = 0; 807 return 0; 808 } 809 810 /* 811 * The timing, frequency or bus width is changed, 812 * better to set eMMC PHY based on current setting 813 * and adjust Xenon SDHC delay. 814 */ 815 if ((host->clock == priv->clock) && 816 (ios->bus_width == priv->bus_width) && 817 (ios->timing == priv->timing)) 818 return 0; 819 820 xenon_emmc_phy_set(host, ios->timing); 821 822 /* Update the record */ 823 priv->bus_width = ios->bus_width; 824 825 priv->timing = ios->timing; 826 priv->clock = host->clock; 827 828 /* Legacy mode is a special case */ 829 if (ios->timing == MMC_TIMING_LEGACY) 830 return 0; 831 832 if (host->clock > XENON_DEFAULT_SDCLK_FREQ) 833 ret = xenon_hs_delay_adj(host); 834 return ret; 835 } 836 837 static int xenon_add_phy(struct device *dev, struct sdhci_host *host, 838 const char *phy_name) 839 { 840 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 841 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); 842 int ret; 843 844 priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name); 845 if (priv->phy_type < 0) { 846 dev_err(mmc_dev(host->mmc), 847 "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n", 848 phy_name); 849 priv->phy_type = EMMC_5_1_PHY; 850 } 851 852 ret = xenon_alloc_emmc_phy(host); 853 if (ret) 854 return ret; 855 856 return xenon_emmc_phy_parse_params(host, dev, priv->phy_params); 857 } 858 859 int xenon_phy_parse_params(struct device *dev, struct sdhci_host *host) 860 { 861 const char *phy_type = NULL; 862 863 if (!device_property_read_string(dev, "marvell,xenon-phy-type", &phy_type)) 864 return xenon_add_phy(dev, host, phy_type); 865 866 return xenon_add_phy(dev, host, "emmc 5.1 phy"); 867 } 868