1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 Marvell International Ltd. 4 * Zhangfei Gao <zhangfei.gao@marvell.com> 5 * Kevin Wang <dwang4@marvell.com> 6 * Mingwei Wang <mwwang@marvell.com> 7 * Philip Rakity <prakity@marvell.com> 8 * Mark Brown <markb@marvell.com> 9 */ 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/io.h> 15 #include <linux/mmc/card.h> 16 #include <linux/mmc/host.h> 17 #include <linux/platform_data/pxa_sdhci.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/mbus.h> 27 #include <linux/units.h> 28 29 #include "sdhci.h" 30 #include "sdhci-pltfm.h" 31 32 #define PXAV3_RPM_DELAY_MS 50 33 34 #define SD_CLOCK_BURST_SIZE_SETUP 0x10A 35 #define SDCLK_SEL 0x100 36 #define SDCLK_DELAY_SHIFT 9 37 #define SDCLK_DELAY_MASK 0x1f 38 39 #define SD_CFG_FIFO_PARAM 0x100 40 #define SDCFG_GEN_PAD_CLK_ON (1<<6) 41 #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF 42 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 43 44 #define SD_SPI_MODE 0x108 45 #define SD_CE_ATA_1 0x10C 46 47 #define SD_CE_ATA_2 0x10E 48 #define SDCE_MISC_INT (1<<2) 49 #define SDCE_MISC_INT_EN (1<<1) 50 51 struct sdhci_pxa { 52 struct clk *clk_core; 53 struct clk *clk_io; 54 u8 power_mode; 55 void __iomem *sdio3_conf_reg; 56 struct pinctrl *pinctrl; 57 struct pinctrl_state *pins_default; 58 struct pinctrl_state *pins_uhs; 59 }; 60 61 /* 62 * These registers are relative to the second register region, for the 63 * MBus bridge. 64 */ 65 #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3)) 66 #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3)) 67 #define SDHCI_MAX_WIN_NUM 8 68 69 /* 70 * Fields below belong to SDIO3 Configuration Register (third register 71 * region for the Armada 38x flavor) 72 */ 73 74 #define SDIO3_CONF_CLK_INV BIT(0) 75 #define SDIO3_CONF_SD_FB_CLK BIT(2) 76 77 static int mv_conf_mbus_windows(struct platform_device *pdev, 78 const struct mbus_dram_target_info *dram) 79 { 80 int i; 81 void __iomem *regs; 82 struct resource *res; 83 84 if (!dram) { 85 dev_err(&pdev->dev, "no mbus dram info\n"); 86 return -EINVAL; 87 } 88 89 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 90 if (!res) { 91 dev_err(&pdev->dev, "cannot get mbus registers\n"); 92 return -EINVAL; 93 } 94 95 regs = ioremap(res->start, resource_size(res)); 96 if (!regs) { 97 dev_err(&pdev->dev, "cannot map mbus registers\n"); 98 return -ENOMEM; 99 } 100 101 for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) { 102 writel(0, regs + SDHCI_WINDOW_CTRL(i)); 103 writel(0, regs + SDHCI_WINDOW_BASE(i)); 104 } 105 106 for (i = 0; i < dram->num_cs; i++) { 107 const struct mbus_dram_window *cs = dram->cs + i; 108 109 /* Write size, attributes and target id to control register */ 110 writel(((cs->size - 1) & 0xffff0000) | 111 (cs->mbus_attr << 8) | 112 (dram->mbus_dram_target_id << 4) | 1, 113 regs + SDHCI_WINDOW_CTRL(i)); 114 /* Write base address to base register */ 115 writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); 116 } 117 118 iounmap(regs); 119 120 return 0; 121 } 122 123 static int armada_38x_quirks(struct platform_device *pdev, 124 struct sdhci_host *host) 125 { 126 struct device_node *np = pdev->dev.of_node; 127 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 128 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 129 struct resource *res; 130 131 host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; 132 133 sdhci_read_caps(host); 134 135 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 136 "conf-sdio3"); 137 if (res) { 138 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res); 139 if (IS_ERR(pxa->sdio3_conf_reg)) 140 return PTR_ERR(pxa->sdio3_conf_reg); 141 } else { 142 /* 143 * According to erratum 'FE-2946959' both SDR50 and DDR50 144 * modes require specific clock adjustments in SDIO3 145 * Configuration register, if the adjustment is not done, 146 * remove them from the capabilities. 147 */ 148 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 149 150 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n"); 151 } 152 153 /* 154 * According to erratum 'ERR-7878951' Armada 38x SDHCI 155 * controller has different capabilities than the ones shown 156 * in its registers 157 */ 158 if (of_property_read_bool(np, "no-1-8-v")) { 159 host->caps &= ~SDHCI_CAN_VDD_180; 160 host->mmc->caps &= ~MMC_CAP_1_8V_DDR; 161 } else { 162 host->caps &= ~SDHCI_CAN_VDD_330; 163 } 164 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING); 165 166 return 0; 167 } 168 169 static void pxav3_reset(struct sdhci_host *host, u8 mask) 170 { 171 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); 172 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 173 174 sdhci_reset(host, mask); 175 176 if (mask == SDHCI_RESET_ALL) { 177 /* 178 * tune timing of read data/command when crc error happen 179 * no performance impact 180 */ 181 if (pdata && 0 != pdata->clk_delay_cycles) { 182 u16 tmp; 183 184 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 185 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) 186 << SDCLK_DELAY_SHIFT; 187 tmp |= SDCLK_SEL; 188 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); 189 } 190 } 191 } 192 193 #define MAX_WAIT_COUNT 5 194 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) 195 { 196 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 197 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 198 u16 tmp; 199 int count; 200 201 if (pxa->power_mode == MMC_POWER_UP 202 && power_mode == MMC_POWER_ON) { 203 204 dev_dbg(mmc_dev(host->mmc), 205 "%s: slot->power_mode = %d," 206 "ios->power_mode = %d\n", 207 __func__, 208 pxa->power_mode, 209 power_mode); 210 211 /* set we want notice of when 74 clocks are sent */ 212 tmp = readw(host->ioaddr + SD_CE_ATA_2); 213 tmp |= SDCE_MISC_INT_EN; 214 writew(tmp, host->ioaddr + SD_CE_ATA_2); 215 216 /* start sending the 74 clocks */ 217 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); 218 tmp |= SDCFG_GEN_PAD_CLK_ON; 219 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); 220 221 /* slowest speed is about 100KHz or 10usec per clock */ 222 udelay(740); 223 count = 0; 224 225 while (count++ < MAX_WAIT_COUNT) { 226 if ((readw(host->ioaddr + SD_CE_ATA_2) 227 & SDCE_MISC_INT) == 0) 228 break; 229 udelay(10); 230 } 231 232 if (count == MAX_WAIT_COUNT) 233 dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); 234 235 /* clear the interrupt bit if posted */ 236 tmp = readw(host->ioaddr + SD_CE_ATA_2); 237 tmp |= SDCE_MISC_INT; 238 writew(tmp, host->ioaddr + SD_CE_ATA_2); 239 } 240 pxa->power_mode = power_mode; 241 } 242 243 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 244 { 245 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 246 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 247 u16 ctrl_2; 248 249 /* 250 * Set V18_EN -- UHS modes do not work without this. 251 * does not change signaling voltage 252 */ 253 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 254 255 /* Select Bus Speed Mode for host */ 256 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 257 switch (uhs) { 258 case MMC_TIMING_UHS_SDR12: 259 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 260 break; 261 case MMC_TIMING_UHS_SDR25: 262 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 263 break; 264 case MMC_TIMING_UHS_SDR50: 265 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; 266 break; 267 case MMC_TIMING_UHS_SDR104: 268 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; 269 break; 270 case MMC_TIMING_MMC_DDR52: 271 case MMC_TIMING_UHS_DDR50: 272 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; 273 break; 274 } 275 276 /* 277 * Update SDIO3 Configuration register according to erratum 278 * FE-2946959 279 */ 280 if (pxa->sdio3_conf_reg) { 281 u8 reg_val = readb(pxa->sdio3_conf_reg); 282 283 if (uhs == MMC_TIMING_UHS_SDR50 || 284 uhs == MMC_TIMING_UHS_DDR50) { 285 reg_val &= ~SDIO3_CONF_CLK_INV; 286 reg_val |= SDIO3_CONF_SD_FB_CLK; 287 } else if (uhs == MMC_TIMING_MMC_HS) { 288 reg_val &= ~SDIO3_CONF_CLK_INV; 289 reg_val &= ~SDIO3_CONF_SD_FB_CLK; 290 } else { 291 reg_val |= SDIO3_CONF_CLK_INV; 292 reg_val &= ~SDIO3_CONF_SD_FB_CLK; 293 } 294 writeb(reg_val, pxa->sdio3_conf_reg); 295 } 296 297 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 298 dev_dbg(mmc_dev(host->mmc), 299 "%s uhs = %d, ctrl_2 = %04X\n", 300 __func__, uhs, ctrl_2); 301 } 302 303 static void pxav3_set_power(struct sdhci_host *host, unsigned char mode, 304 unsigned short vdd) 305 { 306 struct mmc_host *mmc = host->mmc; 307 u8 pwr = host->pwr; 308 309 sdhci_set_power_noreg(host, mode, vdd); 310 311 if (host->pwr == pwr) 312 return; 313 314 if (host->pwr == 0) 315 vdd = 0; 316 317 if (!IS_ERR(mmc->supply.vmmc)) 318 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 319 } 320 321 static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) 322 { 323 struct sdhci_pltfm_host *phost = sdhci_priv(host); 324 struct sdhci_pxa *pxa = sdhci_pltfm_priv(phost); 325 struct pinctrl_state *pins = clock < 100 * HZ_PER_MHZ ? pxa->pins_default : pxa->pins_uhs; 326 327 if (pins) 328 pinctrl_select_state(pxa->pinctrl, pins); 329 330 sdhci_set_clock(host, clock); 331 } 332 333 static const struct sdhci_ops pxav3_sdhci_ops = { 334 .set_clock = pxav3_set_clock, 335 .set_power = pxav3_set_power, 336 .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, 337 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 338 .set_bus_width = sdhci_set_bus_width, 339 .reset = pxav3_reset, 340 .set_uhs_signaling = pxav3_set_uhs_signaling, 341 }; 342 343 static const struct sdhci_pltfm_data sdhci_pxav3_pdata = { 344 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 345 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 346 | SDHCI_QUIRK_32BIT_ADMA_SIZE 347 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 348 .ops = &pxav3_sdhci_ops, 349 }; 350 351 #ifdef CONFIG_OF 352 static const struct of_device_id sdhci_pxav3_of_match[] = { 353 { 354 .compatible = "mrvl,pxav3-mmc", 355 }, 356 { 357 .compatible = "marvell,armada-380-sdhci", 358 }, 359 {}, 360 }; 361 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); 362 363 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 364 { 365 struct sdhci_pxa_platdata *pdata; 366 struct device_node *np = dev->of_node; 367 u32 clk_delay_cycles; 368 369 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 370 if (!pdata) 371 return NULL; 372 373 if (!of_property_read_u32(np, "mrvl,clk-delay-cycles", 374 &clk_delay_cycles)) 375 pdata->clk_delay_cycles = clk_delay_cycles; 376 377 return pdata; 378 } 379 #else 380 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) 381 { 382 return NULL; 383 } 384 #endif 385 386 static struct pinctrl_state *pxav3_lookup_pinstate(struct device *dev, struct pinctrl *pinctrl, 387 const char *name) 388 { 389 struct pinctrl_state *pins = pinctrl_lookup_state(pinctrl, name); 390 391 if (IS_ERR(pins)) { 392 dev_dbg(dev, "could not get pinstate '%s': %ld\n", name, PTR_ERR(pins)); 393 return NULL; 394 } 395 396 return pins; 397 } 398 399 static int sdhci_pxav3_probe(struct platform_device *pdev) 400 { 401 struct sdhci_pltfm_host *pltfm_host; 402 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; 403 struct device *dev = &pdev->dev; 404 struct device_node *np = pdev->dev.of_node; 405 struct sdhci_host *host = NULL; 406 struct sdhci_pxa *pxa = NULL; 407 const struct of_device_id *match; 408 int ret; 409 410 host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa)); 411 if (IS_ERR(host)) 412 return PTR_ERR(host); 413 414 pltfm_host = sdhci_priv(host); 415 pxa = sdhci_pltfm_priv(pltfm_host); 416 417 pxa->clk_io = devm_clk_get(dev, "io"); 418 if (IS_ERR(pxa->clk_io)) 419 pxa->clk_io = devm_clk_get(dev, NULL); 420 if (IS_ERR(pxa->clk_io)) { 421 dev_err(dev, "failed to get io clock\n"); 422 return PTR_ERR(pxa->clk_io); 423 } 424 pltfm_host->clk = pxa->clk_io; 425 clk_prepare_enable(pxa->clk_io); 426 427 pxa->clk_core = devm_clk_get(dev, "core"); 428 if (!IS_ERR(pxa->clk_core)) 429 clk_prepare_enable(pxa->clk_core); 430 431 host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 432 /* enable 1/8V DDR capable */ 433 host->mmc->caps |= MMC_CAP_1_8V_DDR; 434 435 if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { 436 ret = armada_38x_quirks(pdev, host); 437 if (ret < 0) 438 goto err_mbus_win; 439 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); 440 if (ret < 0) 441 goto err_mbus_win; 442 } 443 444 match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); 445 if (match) { 446 ret = mmc_of_parse(host->mmc); 447 if (ret) 448 goto err_of_parse; 449 sdhci_get_of_property(pdev); 450 pdata = pxav3_get_mmc_pdata(dev); 451 pdev->dev.platform_data = pdata; 452 } else if (pdata) { 453 /* on-chip device */ 454 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) 455 host->mmc->caps |= MMC_CAP_NONREMOVABLE; 456 457 /* If slot design supports 8 bit data, indicate this to MMC. */ 458 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) 459 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 460 461 if (pdata->quirks) 462 host->quirks |= pdata->quirks; 463 if (pdata->quirks2) 464 host->quirks2 |= pdata->quirks2; 465 if (pdata->host_caps) 466 host->mmc->caps |= pdata->host_caps; 467 if (pdata->host_caps2) 468 host->mmc->caps2 |= pdata->host_caps2; 469 if (pdata->pm_caps) 470 host->mmc->pm_caps |= pdata->pm_caps; 471 } 472 473 pxa->pinctrl = devm_pinctrl_get(dev); 474 if (!IS_ERR(pxa->pinctrl)) { 475 pxa->pins_default = pxav3_lookup_pinstate(dev, pxa->pinctrl, "default"); 476 if (pxa->pins_default) 477 pxa->pins_uhs = pxav3_lookup_pinstate(dev, pxa->pinctrl, "state_uhs"); 478 } else { 479 dev_dbg(dev, "could not get pinctrl handle: %ld\n", PTR_ERR(pxa->pinctrl)); 480 } 481 482 pm_runtime_get_noresume(&pdev->dev); 483 pm_runtime_set_active(&pdev->dev); 484 pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); 485 pm_runtime_use_autosuspend(&pdev->dev); 486 pm_runtime_enable(&pdev->dev); 487 pm_suspend_ignore_children(&pdev->dev, 1); 488 489 ret = sdhci_add_host(host); 490 if (ret) 491 goto err_add_host; 492 493 if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) 494 device_init_wakeup(&pdev->dev, 1); 495 496 pm_runtime_put_autosuspend(&pdev->dev); 497 498 return 0; 499 500 err_add_host: 501 pm_runtime_disable(&pdev->dev); 502 pm_runtime_put_noidle(&pdev->dev); 503 err_of_parse: 504 err_mbus_win: 505 clk_disable_unprepare(pxa->clk_io); 506 clk_disable_unprepare(pxa->clk_core); 507 return ret; 508 } 509 510 static void sdhci_pxav3_remove(struct platform_device *pdev) 511 { 512 struct sdhci_host *host = platform_get_drvdata(pdev); 513 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 514 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 515 516 pm_runtime_get_sync(&pdev->dev); 517 pm_runtime_disable(&pdev->dev); 518 pm_runtime_put_noidle(&pdev->dev); 519 520 sdhci_remove_host(host, 1); 521 522 clk_disable_unprepare(pxa->clk_io); 523 clk_disable_unprepare(pxa->clk_core); 524 } 525 526 static int sdhci_pxav3_suspend(struct device *dev) 527 { 528 int ret; 529 struct sdhci_host *host = dev_get_drvdata(dev); 530 531 pm_runtime_get_sync(dev); 532 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 533 mmc_retune_needed(host->mmc); 534 ret = sdhci_suspend_host(host); 535 pm_runtime_put_autosuspend(dev); 536 537 return ret; 538 } 539 540 static int sdhci_pxav3_resume(struct device *dev) 541 { 542 int ret; 543 struct sdhci_host *host = dev_get_drvdata(dev); 544 545 pm_runtime_get_sync(dev); 546 ret = sdhci_resume_host(host); 547 pm_runtime_put_autosuspend(dev); 548 549 return ret; 550 } 551 552 static int sdhci_pxav3_runtime_suspend(struct device *dev) 553 { 554 struct sdhci_host *host = dev_get_drvdata(dev); 555 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 556 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 557 558 sdhci_runtime_suspend_host(host); 559 560 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 561 mmc_retune_needed(host->mmc); 562 563 clk_disable_unprepare(pxa->clk_io); 564 if (!IS_ERR(pxa->clk_core)) 565 clk_disable_unprepare(pxa->clk_core); 566 567 return 0; 568 } 569 570 static int sdhci_pxav3_runtime_resume(struct device *dev) 571 { 572 struct sdhci_host *host = dev_get_drvdata(dev); 573 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 574 struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host); 575 576 clk_prepare_enable(pxa->clk_io); 577 if (!IS_ERR(pxa->clk_core)) 578 clk_prepare_enable(pxa->clk_core); 579 580 sdhci_runtime_resume_host(host, 0); 581 return 0; 582 } 583 584 static const struct dev_pm_ops sdhci_pxav3_pmops = { 585 SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) 586 RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, sdhci_pxav3_runtime_resume, NULL) 587 }; 588 589 static struct platform_driver sdhci_pxav3_driver = { 590 .driver = { 591 .name = "sdhci-pxav3", 592 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 593 .of_match_table = of_match_ptr(sdhci_pxav3_of_match), 594 .pm = pm_ptr(&sdhci_pxav3_pmops), 595 }, 596 .probe = sdhci_pxav3_probe, 597 .remove = sdhci_pxav3_remove, 598 }; 599 600 module_platform_driver(sdhci_pxav3_driver); 601 602 MODULE_DESCRIPTION("SDHCI driver for pxav3"); 603 MODULE_AUTHOR("Marvell International Ltd."); 604 MODULE_LICENSE("GPL v2"); 605 606