1515033f9SAnton Vorontsov /* 2515033f9SAnton Vorontsov * Copyright 2010 MontaVista Software, LLC. 3515033f9SAnton Vorontsov * 4515033f9SAnton Vorontsov * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 5515033f9SAnton Vorontsov * 6515033f9SAnton Vorontsov * This program is free software; you can redistribute it and/or modify 7515033f9SAnton Vorontsov * it under the terms of the GNU General Public License version 2 as 8515033f9SAnton Vorontsov * published by the Free Software Foundation. 9515033f9SAnton Vorontsov */ 10515033f9SAnton Vorontsov 11515033f9SAnton Vorontsov #ifndef _DRIVERS_MMC_SDHCI_PLTFM_H 12515033f9SAnton Vorontsov #define _DRIVERS_MMC_SDHCI_PLTFM_H 13515033f9SAnton Vorontsov 144b711cb1SWolfram Sang #include <linux/clk.h> 1585d6509dSShawn Guo #include <linux/platform_device.h> 16f0de8369SShawn Guo #include "sdhci.h" 1720b1597bSAnton Vorontsov 1894cc6a86SShawn Guo struct sdhci_pltfm_data { 19ad1df8c2SLars-Peter Clausen const struct sdhci_ops *ops; 2094cc6a86SShawn Guo unsigned int quirks; 21ad82ab65SAl Cooper unsigned int quirks2; 2294cc6a86SShawn Guo }; 2394cc6a86SShawn Guo 244b711cb1SWolfram Sang struct sdhci_pltfm_host { 254b711cb1SWolfram Sang struct clk *clk; 26e307148fSShawn Guo 27e307148fSShawn Guo /* migrate from sdhci_of_host */ 28e307148fSShawn Guo unsigned int clock; 29e307148fSShawn Guo u16 xfer_mode_shadow; 300e748234SChristian Daudt 310e748234SChristian Daudt unsigned long private[0] ____cacheline_aligned; 324b711cb1SWolfram Sang }; 334b711cb1SWolfram Sang 3438576af1SShawn Guo #ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER 35f0de8369SShawn Guo /* 36f0de8369SShawn Guo * These accessors are designed for big endian hosts doing I/O to 37f0de8369SShawn Guo * little endian controllers incorporating a 32-bit hardware byte swapper. 38f0de8369SShawn Guo */ 39f0de8369SShawn Guo static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) 40f0de8369SShawn Guo { 41f0de8369SShawn Guo return in_be32(host->ioaddr + reg); 42f0de8369SShawn Guo } 43f0de8369SShawn Guo 44f0de8369SShawn Guo static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) 45f0de8369SShawn Guo { 46f0de8369SShawn Guo return in_be16(host->ioaddr + (reg ^ 0x2)); 47f0de8369SShawn Guo } 48f0de8369SShawn Guo 49f0de8369SShawn Guo static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) 50f0de8369SShawn Guo { 51f0de8369SShawn Guo return in_8(host->ioaddr + (reg ^ 0x3)); 52f0de8369SShawn Guo } 53f0de8369SShawn Guo 54f0de8369SShawn Guo static inline void sdhci_be32bs_writel(struct sdhci_host *host, 55f0de8369SShawn Guo u32 val, int reg) 56f0de8369SShawn Guo { 57f0de8369SShawn Guo out_be32(host->ioaddr + reg, val); 58f0de8369SShawn Guo } 59f0de8369SShawn Guo 60f0de8369SShawn Guo static inline void sdhci_be32bs_writew(struct sdhci_host *host, 61f0de8369SShawn Guo u16 val, int reg) 62f0de8369SShawn Guo { 63f0de8369SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 64f0de8369SShawn Guo int base = reg & ~0x3; 65f0de8369SShawn Guo int shift = (reg & 0x2) * 8; 66f0de8369SShawn Guo 67f0de8369SShawn Guo switch (reg) { 68f0de8369SShawn Guo case SDHCI_TRANSFER_MODE: 69f0de8369SShawn Guo /* 70f0de8369SShawn Guo * Postpone this write, we must do it together with a 71f0de8369SShawn Guo * command write that is down below. 72f0de8369SShawn Guo */ 73f0de8369SShawn Guo pltfm_host->xfer_mode_shadow = val; 74f0de8369SShawn Guo return; 75f0de8369SShawn Guo case SDHCI_COMMAND: 76f0de8369SShawn Guo sdhci_be32bs_writel(host, 77f0de8369SShawn Guo val << 16 | pltfm_host->xfer_mode_shadow, 78f0de8369SShawn Guo SDHCI_TRANSFER_MODE); 79f0de8369SShawn Guo return; 80f0de8369SShawn Guo } 81f0de8369SShawn Guo clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift); 82f0de8369SShawn Guo } 83f0de8369SShawn Guo 84f0de8369SShawn Guo static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) 85f0de8369SShawn Guo { 86f0de8369SShawn Guo int base = reg & ~0x3; 87f0de8369SShawn Guo int shift = (reg & 0x3) * 8; 88f0de8369SShawn Guo 89f0de8369SShawn Guo clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift); 90f0de8369SShawn Guo } 91f0de8369SShawn Guo #endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */ 9238576af1SShawn Guo 9338576af1SShawn Guo extern void sdhci_get_of_property(struct platform_device *pdev); 9438576af1SShawn Guo 9585d6509dSShawn Guo extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, 960e748234SChristian Daudt const struct sdhci_pltfm_data *pdata, 970e748234SChristian Daudt size_t priv_size); 9885d6509dSShawn Guo extern void sdhci_pltfm_free(struct platform_device *pdev); 9985d6509dSShawn Guo 10085d6509dSShawn Guo extern int sdhci_pltfm_register(struct platform_device *pdev, 1010e748234SChristian Daudt const struct sdhci_pltfm_data *pdata, 1020e748234SChristian Daudt size_t priv_size); 10385d6509dSShawn Guo extern int sdhci_pltfm_unregister(struct platform_device *pdev); 10485d6509dSShawn Guo 105d005d943SLars-Peter Clausen extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host); 106d005d943SLars-Peter Clausen 1070e748234SChristian Daudt static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host) 1080e748234SChristian Daudt { 109178b0fa0SMasahiro Yamada return host->private; 1100e748234SChristian Daudt } 1110e748234SChristian Daudt 112*83a7b32aSMasahiro Yamada int sdhci_pltfm_suspend(struct device *dev); 113*83a7b32aSMasahiro Yamada int sdhci_pltfm_resume(struct device *dev); 11429495aa0SManuel Lauss extern const struct dev_pm_ops sdhci_pltfm_pmops; 11520b1597bSAnton Vorontsov 116515033f9SAnton Vorontsov #endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */ 117